Semiconductor system

Abstract

This semiconductor system (1) comprises: a motherboard (10); a slave substrate (40) disposed above the motherboard (10) and including a package substrate (20) located on the motherboard (10) side and an interposer (30) laminated above the package substrate; a semiconductor device (50) disposed above the slave substrate (40); at least one first capacitor element (61) disposed on the motherboard (10); and at least one second capacitor element (62a, 62b, 62c, 63a, and 63b) disposed in a structure (20, 30, 50) above the motherboard (10). In a top view of the slave substrate (40), a range in which an outer edge of the slave substrate (40) is outwardly expanded to 5 mm is used as a reference surface, the reference surface being expanded in a thickness direction from a bottom portion of the semiconductor system (1) so as to include an upper portion thereof. When such region is defined as a reference region (A), the total capacitance value of the second capacitor elements (62a, 62b, 62c, 63a, and 63b) included in the reference region (A) is greater than the total capacitance value of the first capacitor element (61) included in the reference region (A).

Description

Semiconductor Systems

[0001] The present invention relates to semiconductor systems.

[0002] 2. Description of the Related Art A processor system for high-performance computing (HPC) is known in which a motherboard, a package substrate, an interposer, and a semiconductor chip are stacked in this order (Non-Patent Document 1).

[0003] "Development of high-performance 'interposer', an important component of next-generation semiconductor packages", paragraphs 2-3, [online], November 12, 2021, Dai Nippon Printing Co., Ltd., [Retrieved May 28, 2024], Internet<URL: https: / / www.dnp.co.jp / news / detail / 10161685_1587.html>

[0004] In a processor system such as that described in Non-Patent Document 1, capacitor elements are placed in each part for the purpose of supplying power and suppressing voltage fluctuations, and inductor elements are placed for the purpose of converting voltage and stabilizing current.

[0005] In a processor system such as that described in Non-Patent Document 1, when a large number of capacitor elements and inductor elements are arranged, there is a problem that the impedance in the processor system becomes high.

[0006] The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor system with sufficiently low impedance.

[0007] The semiconductor system of the present invention is a semiconductor system including a motherboard, a sub-board arranged on the motherboard and including a package substrate located on the motherboard side and an interposer stacked on top of it, a semiconductor device arranged on the sub-board, at least one first capacitor element arranged on the motherboard, and at least one second capacitor element arranged in a structure above the motherboard, wherein when the sub-board is viewed from above, the range obtained by extending the outer edge of the sub-board 5 mm outward is used as a reference plane, and the reference plane is extended in the thickness direction to include the bottom and top of the semiconductor system, and this area is used as a reference area, the total capacitance of the second capacitor elements included in the reference area is greater than the total capacitance of the first capacitor elements included in the reference area.

[0008] Another aspect of the present invention provides a semiconductor system including a motherboard, a daughter board disposed on the motherboard and including a package substrate located on the motherboard side and an interposer stacked thereon, a semiconductor device disposed on the daughter board, at least one first capacitor element disposed on the motherboard, and at least one second capacitor element disposed in a structure above the motherboard, wherein the second capacitor element is connected to at least one third capacitor element disposed in a structure above the package substrate, and and at least one fourth capacitor element placed on the substrate, and when the substrate is viewed from above and the range extending 5 mm outward from the outer edge of the substrate is used as a reference plane, and the reference plane is extended in the thickness direction to include the bottom and top of the semiconductor system, and this area is used as a reference area, the total capacitance of the third capacitor elements included in the reference area is less than or equal to the total capacitance of the fourth capacitor elements included in the reference area, and the total capacitance of the fourth capacitor elements included in the reference area is less than or equal to the total capacitance of the first capacitor elements included in the reference area.

[0009] According to the present invention, it is possible to provide a semiconductor system with a sufficiently low impedance.

[0010] 1 is a cross-sectional view schematically illustrating an example of a semiconductor system according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view schematically illustrating an example of a semiconductor system according to a second embodiment of the present invention.

[0011] The semiconductor system of the present invention will be described below. However, the present invention is not limited to the following embodiments, and can be appropriately modified and applied within the scope of the present invention. A combination of two or more of the individual desirable configurations of the present invention described in the following embodiments also constitutes the present invention.

[0012] The drawings shown below are schematic diagrams, and the dimensions, aspect ratio, scale, etc. may differ from those of the actual product.

[0013] Furthermore, the following embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. From the second embodiment onwards, a description of the matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0014] First Embodiment FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor system according to a first embodiment of the present invention.

[0015] 1 includes a motherboard 10, a daughter board 40 disposed on the motherboard 10 and including a package substrate 20 located on the motherboard 10 side and an interposer 30 stacked thereon, and a plurality of semiconductor devices 50 disposed on the daughter board 40. In this specification, "above" does not mean the upper side in the vertical direction, but rather the stacking direction (the direction indicated by arrow D1 in FIG. 1).

[0016] The motherboard 10 has wiring 11 extending inside and over its surface. A capacitor element 61, an inductor element 71, and a voltage regulator 81 connected to the motherboard 10 are arranged on the bottom surface of the motherboard 10.

[0017] The package substrate 20 includes an inner layer (core layer) 20a and outer layers 20b sandwiching the inner layer 20a.

[0018] The package substrate 20 has wiring 21 extending through the interior and surfaces of the inner layer 20a and the outer layer 20b.

[0019] A voltage regulator 82 is disposed inside the package substrate 20. Furthermore, a capacitor element 62c and an inductor element 72c are disposed inside the package substrate 20. A capacitor element 62a and an inductor element 72a connected to the package substrate 20 are disposed on the lower surface of the package substrate 20, and a capacitor element 62b and an inductor element 72b connected to the package substrate 20 are disposed on the upper surface of the package substrate 20.

[0020] The interposer 30 has wiring 31 extending inside and over its surface. The interposer 30 differs from the package substrate 20 in that it does not have an outer layer. Furthermore, a capacitor element 63a and an inductor element 73a are disposed inside the interposer 30.

[0021] The semiconductor device 50 includes a processor 51, a memory 52, and a high bandwidth memory (HBM) 53. In this specification, the term "semiconductor device" refers to integrated circuits such as processors and memories, and does not include power semiconductors used for power supply. Examples of the processor 51 include a CPU and a GPU.

[0022] The processor 51 also includes a capacitor element 63b and an inductor element 73b therein.

[0023] In the semiconductor system 1 , the wiring 11 of the motherboard 10 is connected to the wiring 21 of the package substrate 20 by solder 90 , and the wiring 21 of the package substrate 20 is connected to the wiring 31 of the interposer 30 .

[0024] In the semiconductor system 1, the motherboard 10, the package substrate 20, the interposer 30, the semiconductor device 50, the capacitor elements (61, 62a, 62b, 63), the inductor elements (71, 72a, 72b, 73), and the voltage regulators (81, 82) may be conventionally known. For example, the capacitor elements may be silicon-based capacitor elements, ceramic-based capacitor elements, metal-insulator-metal (MIM) capacitor elements, or aluminum electrolytic capacitors. For example, the inductor elements may be ferrite-based laminated inductor elements, metal composite inductor elements, or wire-wound inductor elements.

[0025] The semiconductor system 1 is connected to a power supply (not shown) via a connector 2 that connects to a motherboard 10 .

[0026] In the semiconductor system 1, when the daughter board 40 is viewed from above, the reference area is the area obtained by extending 5 mm outward from the outer edge of the daughter board 40. This reference area is then extended in the thickness direction to include the area from the bottom to the top of the semiconductor system 1, and this area is defined as the reference area (the area indicated by the dashed line A in FIG. 1 ). The bottom of the semiconductor system 1 refers to the bottom ends of the electronic components arranged on the underside of the motherboard 10. Note that these electronic components do not include the connector 2. The top of the semiconductor system 1 refers to the top end of the semiconductor device 50.

[0027] In the semiconductor system 1, the capacitor element 61 arranged on the motherboard 10 is defined as the first capacitor element, and the capacitor elements 62a, 62b, 62c, 63a, and 63b arranged in the structure above the motherboard 10 (i.e., the daughter board 40 and the semiconductor device 50) are defined as the second capacitor elements. The total capacitance of the second capacitor elements (capacitor elements 62a, 62b, 62c, 63a, and 63b) included in the reference area A is greater than the total capacitance of the first capacitor element (capacitor element 61) included in the reference area A. In other words, in the semiconductor system 1, large-capacity capacitor elements are arranged near the semiconductor device 50. With this configuration, power can be supplied to the semiconductor device 50 quickly, significantly reducing impedance, particularly at high frequencies (10 MHz or higher). Therefore, the semiconductor system 1 can be said to be a semiconductor system with sufficiently low impedance.

[0028] In this specification, "total capacitance of the capacitor elements" means the capacitance of the capacitor element when there is one capacitor element, and when there are multiple capacitor elements, means the sum of the capacitance values ​​of the individual capacitor elements.

[0029] Furthermore, when calculating the total capacitance of the capacitor elements included in the reference area A, there may be cases where the capacitor elements are arranged across the boundary of the reference area A (hereinafter, such capacitor elements will also be referred to as "boundary capacitor elements"). In this case, when calculating the "total capacitance of the capacitor elements", the numerical value of the capacitance of the boundary capacitor element is not used directly in the calculation, but rather a numerical value obtained by reducing the numerical value of the capacitance according to the volume proportion included in the reference area A is used in the calculation. More specifically, for a boundary capacitor element, the numerical value used to calculate the "total capacitance of the capacitor elements" is calculated as follows. First, the ratio (V2 / V1) of the volume V2 of the part of the boundary capacitor element included in the reference area A to the total volume V1 of the boundary capacitor element is calculated. Then, the numerical value obtained by multiplying the capacitance of the boundary capacitor element by the ratio (V2 / V1) is used as the numerical value for calculating the "total capacitance of the capacitor elements".

[0030] In the semiconductor system 1, when the capacitor elements 63a and 63b arranged in the structure above the package substrate 20 (i.e., the interposer 30 and the semiconductor device 50) are defined as third capacitor elements, and the capacitor elements 62a, 62b, and 62c arranged on the package substrate 20 are defined as fourth capacitor elements, it is preferable that the total capacitance value of the third capacitor elements (capacitor elements 63a and 63b) included in the reference area A is larger than the total capacitance value of the first capacitor elements (capacitor elements 61) included in the reference area A. With such a configuration, the impedance at high frequencies can be further reduced.

[0031] In the semiconductor system 1, the total capacitance of the first capacitor elements (capacitor elements 61) included in the reference area A is preferably less than 2000 μF, and more preferably 500 μF or less. In the semiconductor system 1, the total capacitance of the second capacitor elements (capacitor elements 62a, 62b, 62c, 63a, and 63b) included in the reference area A (i.e., the total capacitance of the third capacitor element and the fourth capacitor element) is preferably 500 μF or more, and more preferably 750 μF or more. In the semiconductor system 1, the total capacitance of the third capacitor elements (capacitor elements 63a and 63b) included in the reference area A is preferably 500 μF or more, and more preferably 750 μF or more. In the semiconductor system 1, the total capacitance of the fourth capacitor elements (capacitor elements 62a and 62b) included in the reference area A is preferably 0 μF or more and 50 μF or less.

[0032] In the semiconductor system 1, when the inductor element 71 placed on the motherboard 10 is defined as the first inductor element, and the inductor elements 72a, 72b, 72c, 73a, and 73b placed in the structure above the motherboard 10 (the daughter board 40 and the semiconductor device 50) are defined as the second inductor elements, the total inductance value of the second inductor elements (inductor elements 72a, 72b, 72c, 73a, and 73b) included in the reference area A may be greater than the total inductance value of the first inductor elements (inductor element 71) included in the reference area A.

[0033] Furthermore, in the semiconductor system 1, when the inductor elements 73a and 73b arranged in the structure above the package substrate 20 (i.e., the interposer 30 and the semiconductor device 50) are defined as third inductor elements, and the inductor elements 72a, 72b, and 72c arranged on the package substrate 20 are defined as fourth inductor elements, the total inductance value of the third inductor elements (inductor elements 73a and 73b) included in the reference area A may be greater than the total inductance value of the first inductor elements (inductor elements 71) included in the reference area A. With this configuration, the inductor elements 71 arranged on the motherboard 10 in the semiconductor system 1 can be made smaller. As a result, the space required for arranging the motherboard 10 is reduced. Therefore, the electronic device in which the motherboard 10 is arranged can be made smaller.

[0034] Furthermore, when calculating the total inductance value of the inductor elements included in the reference area A, there may be cases where the inductor elements are arranged across the boundary of the reference area A (hereinafter, such inductor elements will also be referred to as "boundary inductor elements"). In this case, when calculating the "total inductance value of the inductor elements," the inductance value of the boundary inductor element is not used directly in the calculation, but a value obtained by reducing the inductance value according to the volume ratio included in the reference area A is used. More specifically, for a boundary inductor element, the value used to calculate the "total inductance value of the inductor elements" is calculated as follows. First, the ratio (V4 / V3) of the volume V4 of the part of the boundary inductor element included in the reference area A to the entire volume V3 of the boundary inductor element is calculated. Then, the product of the inductance value of the boundary inductor element and the ratio (V4 / V3) is used as the value for calculating the "total inductance value of the inductor elements."

[0035] In the semiconductor system 1, the total inductance value of the first inductor elements (inductor elements 71) included in the reference region A is preferably less than 2000 nH, and more preferably 100 nH or less. In the semiconductor system 1, the total inductance value of the second inductor elements (inductor elements 72a, 72b, 72c, 73a, and 73b) included in the reference region A is preferably 20 nH or more, and more preferably 1010 nH or more. In the semiconductor system 1, the total inductance value of the third inductor elements (inductor elements 73a and 73b) included in the reference region A is preferably 10 nH or more, and more preferably 100 nH or less. In the semiconductor system 1, the total inductance value of the fourth inductor elements (inductor elements 72a, 72b, and 72c) included in the reference region A is preferably 10 nH or more, and more preferably 1000 nH or more.

[0036] In the semiconductor system 1, if the voltage regulator 81 disposed on the motherboard 10 is defined as the first voltage regulator and the voltage regulator disposed in a structure above the motherboard 10 (i.e., the voltage regulator 82 disposed on the package substrate 20) is defined as the second voltage regulator, the total inductance value of the second inductor elements (inductor elements 72a, 72b, and 72c) included in the reference area A used in the step-down circuit configuration of the second voltage regulator may be greater than the total inductance value of the first inductor element (inductor element 71) included in the reference area A used in the step-down circuit configuration of the first voltage regulator. In this case, the inductor element 71 disposed on the motherboard 10 in the semiconductor system 1 can be made smaller. As a result, the space required for arranging the motherboard 10 is reduced. This allows the electronic device in which the motherboard 10 is disposed to be made smaller.

[0037] In this case, the average thermal expansion coefficient in the planar direction of the second inductor elements (inductor elements 72a, 72b, and 72c) included in the reference area A used in the step-down circuit configuration of the second voltage regulator may be greater than the average thermal expansion coefficient in the planar direction of the first inductor element (inductor element 71) included in the reference area A.

[0038] Here, the average thermal expansion coefficient in the plane direction of the first inductor element and the second inductor element included in the reference area will be described. First, the thermal expansion coefficient in the plane direction of each inductor element at 200°C is measured. The arithmetic mean of the thermal expansion coefficients in the plane direction at 200°C of each inductor element classified as a first inductor element is the average thermal expansion coefficient of the first inductor element. Furthermore, the arithmetic mean of the thermal expansion coefficients in the plane direction at 200°C of each inductor element classified as a second inductor element is the average thermal expansion coefficient of the second inductor element. Note that even if an inductor element is a boundary inductor element arranged across the boundary of the reference area A, it is treated as a single inductor element when calculating the average thermal expansion coefficient in the plane direction of the first inductor element and the second inductor element.

[0039] (Modification of First Embodiment) Next, a semiconductor system according to a modification of the first embodiment of the present invention will be described. The semiconductor system according to the modification of the first embodiment of the present invention has the same configuration as the semiconductor system 1, except that inductor element 71, inductor element 72a, inductor element 72b, inductor element 72c, inductor element 73a, and inductor element 73b included in reference region A are different as follows.

[0040] In the semiconductor system according to the modified example of the first embodiment of the present invention, the inductance value of the third inductor elements (inductor elements 73a and 73b) included in the reference region A may be equal to or less than the inductance value of the fourth inductor elements (inductor elements 72a, 72b, and 72c) included in the reference region A, and the inductance value of the fourth inductor elements (inductor elements 72a, 72b, and 72c) included in the reference region A may be equal to or less than the inductance value of the first inductor element (inductor element 71) included in the reference region A. In this case, the inductance value of each inductor element can be optimized, and a small-sized voltage conversion module that can be placed in any position can be configured.

[0041] In the semiconductor system according to the modified example of the first embodiment of the present invention, the total inductance value of the second inductor elements (inductor elements 72a, 72b, and 72c) included in the reference region A used in the step-down circuit configuration of the second voltage regulator (voltage regulator 82) is preferably equal to or less than the total inductance value of the first inductor elements (inductor element 71) included in the reference region A used in the step-down circuit configuration of the first voltage regulator (voltage regulator 81). In this case, the inductance value of each inductor element can be more optimized.

[0042] In the semiconductor system according to the modification of the first embodiment of the present invention, the total inductance value of the first inductor elements (inductor elements 71) included in the reference region A is preferably 300 nH or more but less than 3100 nH, and more preferably 500 nH or more but 2600 nH or less. In the semiconductor system according to the modification of the first embodiment of the present invention, the total inductance value of the third inductor elements (inductor elements 73 a and 73 b) included in the reference region A is preferably 10 nH or more but 1000 nH or less, and more preferably 200 nH or more but 500 nH or less. In the semiconductor system according to the modification of the first embodiment of the present invention, the total inductance value of the fourth inductor elements (inductor elements 72 a, 72 b, and 72 c) included in the reference region A is preferably 100 nH or more but 3000 nH or less, and more preferably 1000 nH or more but 2500 nH or less.

[0043] When an inductor element functions, heat is generated, causing the inductor element itself to thermally expand. Thermal expansion of the inductor element has an effect such as pressing on surrounding components. The package substrate 20 is larger than the semiconductor device 50, and the motherboard 10 is larger than the package substrate 20. Therefore, it is easier to design the package substrate 20 to be less affected by the thermal expansion of the inductor element than the semiconductor device 50, and it is easier to design the motherboard 10 to be less affected by the thermal expansion of the inductor element than the package substrate 20. In other words, it is preferable that the inductor elements arranged on the package substrate 20 have a lower coefficient of thermal expansion than the inductor elements arranged on the motherboard 10, and it is preferable that the inductor elements arranged on the interposer 30 and the semiconductor device 50 have a lower coefficient of thermal expansion than the inductor elements arranged on the package substrate 20. For these reasons, in the semiconductor system according to the modified example of the first embodiment of the present invention, it is preferable that the average thermal expansion coefficient in the planar direction of the third inductor elements (inductor elements 73a and 73b) included in the reference region A is equal to or less than the average thermal expansion coefficient in the planar direction of the fourth inductor elements (inductor elements 72a, 72b, and 72c) included in the reference region A, and that the average thermal expansion coefficient in the planar direction of the fourth inductor elements (inductor elements 72a, 72b, and 72c) included in the reference region A is equal to or less than the average thermal expansion coefficient in the planar direction of the first inductor element (inductor element 71) included in the reference region A. Such a structure of the semiconductor system ensures a structure that is stable against thermal cycles.

[0044] Here, the average thermal expansion coefficients in the planar direction of the first inductor element, the third inductor element, and the fourth inductor element included in the reference area will be described. First, the thermal expansion coefficient in the planar direction of each inductor element at 200°C is measured. The arithmetic mean of the thermal expansion coefficients in the planar direction of each inductor element classified as the first inductor element at 200°C is the average thermal expansion coefficient of the first inductor element. Furthermore, the arithmetic mean of the thermal expansion coefficients in the planar direction of each inductor element classified as the third inductor element at 200°C is the average thermal expansion coefficient of the third inductor element. Furthermore, the arithmetic mean of the thermal expansion coefficients in the planar direction of each inductor element classified as the fourth inductor element at 200°C is the average thermal expansion coefficient of the fourth inductor element. Note that even if an inductor element is a boundary inductor element positioned across the boundary of the reference area A, it is treated as a single inductor element when calculating the average thermal expansion coefficient in the planar direction of the first inductor element, the third inductor element, and the fourth inductor element.

[0045] Second Embodiment Next, a semiconductor system according to a modified example of the second embodiment of the present invention will be described. Fig. 2 is a cross-sectional view schematically showing an example of the semiconductor system according to the second embodiment of the present invention.

[0046] The semiconductor system 101 shown in Figure 2 comprises a motherboard 110, a daughter board 140 arranged on the motherboard 110 and including a package substrate 120 located on the motherboard 110 side and an interposer 130 stacked on top of it, and a plurality of semiconductor devices 150 arranged on the daughter board 140.

[0047] The motherboard 110 has wiring 111 extending inside and over its surface. A capacitor element 161, an inductor element 171, and a voltage regulator 181 connected to the motherboard 110 are arranged on the bottom surface of the motherboard 110.

[0048] The package substrate 120 includes an inner layer (core layer) 120a and outer layers 120b sandwiching the inner layer 120a. The package substrate 120 has wiring 121 extending across the interior and surfaces of the inner layer 120a and the outer layer 120b. A voltage regulator 182 is disposed inside the package substrate 120. A capacitor element 162c and an inductor element 172c are also disposed inside the package substrate 120. A capacitor element 162a and an inductor element 172a connected to the package substrate 120 are disposed on the bottom surface of the package substrate 120, and a capacitor element 162b and an inductor element 172b connected to the package substrate 120 are disposed on the top surface of the package substrate 120.

[0049] The interposer 130 has wiring 131 extending inside and over the surface. Also, a capacitor element 163a and an inductor element 173a are disposed inside the interposer 130.

[0050] The semiconductor device 150 includes a processor 151, a memory 152, and a high bandwidth memory (HBM) 153. The processor 151 also includes therein a capacitor element 163b and an inductor element 173b.

[0051] In the semiconductor system 101 , the wiring 111 of the motherboard 110 is connected to the wiring 121 of the package substrate 120 by solder 190 , and the wiring 121 of the package substrate 120 is connected to the wiring 131 of the interposer 130 .

[0052] The semiconductor system 101 is connected to a power supply (not shown) via a connector 102 that connects to a motherboard 110 .

[0053] The preferred materials, etc. of the motherboard 110, package substrate 120, interposer 130, sub-board 140 and semiconductor device 150 in the semiconductor system 101 are the same as the preferred materials, etc. of the motherboard 10, package substrate 20, interposer 30, sub-board 40 and semiconductor device 50 in the semiconductor system 1 described above.

[0054] In the semiconductor system 101, when the substrate 140 is viewed from above, the reference area is the area obtained by extending 5 mm outward from the outer edge of the substrate 140. This reference area is then extended in the thickness direction to include the area from the bottom to the top of the semiconductor system 101, and this area is defined as the reference area (the area indicated by the dashed line A in FIG. 2 ).

[0055] In the semiconductor system 101, if the capacitor element 161 arranged on the motherboard 110 is defined as the first capacitor element, the capacitor elements 162a, 162b, and 162c arranged on the package substrate 120 are defined as fourth capacitor elements, and the capacitor elements 163a and 163b arranged in a structure above the package substrate (i.e., the interposer 130 and the semiconductor device 150) are defined as third capacitor elements, the total capacitance value of the third capacitor elements (capacitor elements 163a and 163b) included in the reference area A is less than or equal to the total capacitance value of the fourth capacitor elements (capacitor elements 162a, 162b, and 162c) included in the reference area A, and the total capacitance value of the fourth capacitor elements (capacitor elements 162a, 162b, and 162c) included in the reference area A is less than or equal to the total capacitance value of the first capacitor elements (capacitor elements 161) included in the reference area A. With this configuration, the capacitance can be optimized to suppress voltage fluctuations throughout the semiconductor system 101. This reduces impedance, particularly in the low to medium frequencies (less than 100 Hz). Therefore, the semiconductor system 101 can be said to be a semiconductor system with sufficiently low impedance.

[0056] In the semiconductor system 101, when calculating the total capacitance value of the capacitor elements included in the reference area A, if the capacitor elements are arranged across the boundary of the reference area A, the "total capacitance value of the capacitor elements" is calculated in the same manner as in the semiconductor system of the first embodiment described above.

[0057] In the semiconductor system 101, the total capacitance of the first capacitor elements (capacitor elements 161) included in the reference area A is preferably 5,000 μF or more and less than 15,000 μF. In the semiconductor system 1, the total capacitance of the third capacitor elements (capacitor elements 163a and 163b) included in the reference area A is preferably 5 μF or more and 200 μF or less. In the semiconductor system 1, the total capacitance of the fourth capacitor elements (capacitor elements 162a, 162b, and 162c) included in the reference area A is preferably 300 μF or more and 500 μF or less.

[0058] When a capacitor element functions, heat is generated, causing the capacitor element itself to thermally expand. Thermal expansion of the capacitor element has an effect such as pressing on surrounding components. The package substrate 120 is larger than the semiconductor device 150, and the motherboard 110 is larger than the package substrate 120. Therefore, it is easier to design the package substrate 120 to be less affected by the thermal expansion of the capacitor element than the semiconductor device 150, and it is easier to design the motherboard 110 to be less affected by the thermal expansion of the capacitor element than the package substrate 120. In other words, it is preferable that the capacitor element disposed on the package substrate 120 has a lower coefficient of thermal expansion than the capacitor element disposed on the motherboard 110, and it is preferable that the capacitor element disposed on the semiconductor device 150 has a lower coefficient of thermal expansion than the capacitor element disposed on the package substrate 120. For these reasons, in the semiconductor system 101, it is preferable that the average thermal expansion coefficient in the planar direction of the third capacitor elements (capacitor elements 163a and 163b) included in the reference region A is equal to or less than the average thermal expansion coefficient in the planar direction of the fourth capacitor elements (capacitor elements 162a, 162b, and 162c) included in the reference region A, and that the average thermal expansion coefficient in the planar direction of the fourth capacitor elements (capacitor elements 162a, 162b, and 162c) included in the reference region A is equal to or less than the average thermal expansion coefficient in the planar direction of the first capacitor element (capacitor element 161) included in the reference region A. Such a structure of the semiconductor system ensures a structure that is stable against thermal cycles.

[0059] Here, the average thermal expansion coefficient in the plane direction of the first capacitor element, the third capacitor element, and the fourth capacitor element included in the reference area will be described. First, the thermal expansion coefficient in the plane direction of each capacitor element at 200°C is measured. The arithmetic mean of the thermal expansion coefficient in the plane direction of each capacitor element classified as the first capacitor element at 200°C is the average thermal expansion coefficient of the first capacitor element. The arithmetic mean of the thermal expansion coefficient in the plane direction of each capacitor element classified as the third capacitor element at 200°C is the average thermal expansion coefficient of the third capacitor element. The arithmetic mean of the thermal expansion coefficient in the plane direction of each capacitor element classified as the fourth capacitor element at 200°C is the average thermal expansion coefficient of the fourth capacitor element. Note that even if a capacitor element is a boundary capacitor element arranged across the boundary of the reference area A, it is treated as a single capacitor element when calculating the average thermal expansion coefficient in the plane direction of the first capacitor element, the third capacitor element, and the fourth capacitor element.

[0060] In the semiconductor system 101, when the inductor element 171 placed on the motherboard 110 is defined as the first inductor element, and the inductor elements 172a, 172b, 172c, 173a, and 173b placed in the structure above the motherboard 110 (the daughter board 140 and the semiconductor device 150) are defined as the second inductor elements, the total inductance value of the second inductor elements (inductor elements 172a, 172b, 172c, 173a, and 173b) included in the reference area A may be greater than the total inductance value of the first inductance element (inductor element 171) included in the reference area A.

[0061] Furthermore, in the semiconductor system 101, when the inductor elements 173a and 173b arranged in the structure above the package substrate 120 (i.e., the interposer 130 and the semiconductor device 150) are defined as third inductor elements, and the inductor elements 172a, 172b, and 172c arranged on the package substrate 120 are defined as fourth inductor elements, the total inductance value of the third inductor elements (inductor elements 173a and 172b) included in the reference area A may be greater than the total inductance value of the first inductor elements (inductor elements 171) included in the reference area A. With this configuration, the inductor element 171 arranged on the motherboard 110 in the semiconductor system 1 can be made smaller. As a result, the space required for arranging the motherboard 110 is reduced. Therefore, the electronic device in which the motherboard 110 is arranged can be made smaller.

[0062] In the semiconductor system 101, when calculating the total capacitance value of the inductor elements included in the reference area A, if the inductor elements are arranged across the boundary of the reference area A, the "total capacitance value of the inductor elements" is calculated in the same manner as in the semiconductor system of the first embodiment described above.

[0063] In the semiconductor system 101, the total inductance value of the first inductor elements (inductor elements 171) included in the reference region A is preferably less than 2000 nH, and more preferably 100 nH or less. In the semiconductor system 101, the total inductance value of the second inductor elements (inductor elements 172a, 172b, 172c, 173a, and 173b) included in the reference region A is preferably 20 nH or more, and more preferably 1010 nH or more. In the semiconductor system 101, the total inductance value of the third inductor elements (inductor elements 173 and 173b) included in the reference region A is preferably 10 nH or more, and more preferably 100 nH or less. In the semiconductor system 101, the total inductance value of the fourth inductor elements (inductor elements 172a and 172b) included in the reference region A is preferably 10 nH or more, and more preferably 1000 nH or more.

[0064] In the semiconductor system 101, if the voltage regulator 181 disposed on the motherboard 110 is defined as the first voltage regulator and the voltage regulator disposed in a structure above the motherboard 110 (i.e., the voltage regulator 182 disposed on the package substrate 120) is defined as the second voltage regulator, the total inductance value of the second inductor elements (inductor elements 172a, 172b, and 172c) included in the reference area A used in the step-down circuit configuration of the second voltage regulator may be greater than the total inductance value of the first inductor element (inductor element 171) included in the reference area A used in the step-down circuit configuration of the first voltage regulator. In this case, the inductor element 171 disposed on the motherboard 110 in the semiconductor system 101 can be made smaller. As a result, the space required for arranging the motherboard 110 is reduced. This allows the electronic device in which the motherboard 110 is disposed to be made smaller.

[0065] In this case, the average thermal expansion coefficient in the planar direction of the second inductor elements (inductor elements 172a, 172b, and inductor element 172) included in reference region A may be greater than the average thermal expansion coefficient in the planar direction of the first inductor element (inductor element 171) included in reference region A.

[0066] The method for calculating the average thermal expansion coefficient in the planar direction of the first inductor element and the second inductor element included in the reference region in the semiconductor system 101 is the same as the method for calculating the average thermal expansion coefficient in the planar direction of the first inductor element and the second inductor element in the semiconductor system according to the first embodiment of the present invention.

[0067] (Variation of Second Embodiment) Next, a semiconductor system according to a variation of the second embodiment of the present invention will be described. The semiconductor system according to the variation of the second embodiment of the present invention has the same configuration as the semiconductor system 101, except that inductor element 171, inductor element 172a, inductor element 172b, inductor element 172c, inductor element 173a, and inductor element 173b included in reference region A are different as follows.

[0068] In the semiconductor system according to the modified example of the second embodiment of the present invention, the inductance value of the third inductor elements (inductor elements 173a and 173b) included in the reference region A may be equal to or less than the inductance value of the fourth inductor elements (inductor elements 172a, 172b, and 172c) included in the reference region A, and the inductance value of the fourth inductor elements (inductor elements 172a, 172b, and 172c) included in the reference region A may be equal to or less than the inductance value of the first inductor element (inductor element 171) included in the reference region A. In this case, the inductance value of each inductor element can be optimized, and a small-sized voltage conversion module that can be placed in any position can be configured.

[0069] In the semiconductor system according to the modified example of the second embodiment of the present invention, the total inductance value of the second inductor elements (inductor elements 172a, 172b, and 172c) included in the reference region A used in the step-down circuit configuration of the second voltage regulator (voltage regulator 82) is preferably equal to or less than the total inductance value of the first inductor elements (inductor elements 171) included in the reference region A used in the step-down circuit configuration of the first voltage regulator (voltage regulator 181). In this case, the inductance value of each inductor element can be more optimized.

[0070] In the semiconductor system according to the modification of the second embodiment of the present invention, the total inductance value of the first inductor elements (inductor elements 171) included in the reference region A is preferably 300 nH or more but less than 3100 nH, and more preferably 500 nH or more but 2600 nH or less. In the semiconductor system according to the modification of the second embodiment of the present invention, the total inductance value of the third inductor elements (inductor elements 173a and 173b) included in the reference region A is preferably 10 nH or more but 1000 nH or less, and more preferably 200 nH or more but 500 nH or less. In the semiconductor system according to the modification of the second embodiment of the present invention, the total inductance value of the fourth inductor elements (inductor elements 172a, 172b, and 172c) included in the reference region A is preferably 100 nH or more but 3000 nH or less, and more preferably 1000 nH or more but 2500 nH or less.

[0071] When an inductor element functions, heat is generated, causing the inductor element itself to thermally expand. Thermal expansion of the inductor element has an effect such as pressing on surrounding components. The package substrate 120 is larger than the semiconductor device 150, and the motherboard 110 is larger than the package substrate 120. Therefore, it is easier to design the package substrate 120 to be less affected by the thermal expansion of the inductor element than the semiconductor device 150, and it is easier to design the motherboard 110 to be less affected by the thermal expansion of the inductor element than the package substrate 120. In other words, it is preferable that the inductor element disposed on the package substrate 120 have a lower coefficient of thermal expansion than the inductor element disposed on the motherboard 110, and it is preferable that the inductor element disposed on the semiconductor device 150 have a lower coefficient of thermal expansion than the inductor element disposed on the package substrate 120. For these reasons, in the semiconductor system according to the modified example of the second embodiment of the present invention, it is preferable that the average thermal expansion coefficient in the planar direction of the third inductor elements (inductor elements 173a and 173b) included in the reference region A is equal to or less than the average thermal expansion coefficient in the planar direction of the fourth inductor elements (inductor elements 172a, 172b, and 172c) included in the reference region A, and that the average thermal expansion coefficient in the planar direction of the fourth inductor elements (inductor elements 172a, 172b, and 172c) included in the reference region A is equal to or less than the average thermal expansion coefficient in the planar direction of the first inductor element (inductor element 171) included in the reference region A. Such a structure of the semiconductor system ensures a structure that is stable against thermal cycles.

[0072] In a semiconductor system according to a modified example of the second embodiment of the present invention, the method for measuring the average thermal expansion coefficient in the planar direction of the first inductor element, the third inductor element, and the fourth inductor element included in the reference region is the same as the method for measuring the average thermal expansion coefficient in the planar direction of the first inductor element, the third inductor element, and the fourth inductor element included in the reference region in the semiconductor system according to the modified example of the first embodiment of the present invention described above.

[0073] (Other Embodiments) In the semiconductor systems of the above-described first embodiment, modified example of the first embodiment, second embodiment, and modified example of the second embodiment, the capacitor elements and inductor elements were arranged inside the interposer. In the semiconductor system of the present invention, the capacitor elements and inductor elements may be arranged on the surface of the interposer. Because the interposer is a structure above the motherboard, the capacitor elements and inductor elements arranged on the surface of the interposer are also second capacitor elements and second inductor elements. Moreover, because the interposer is a structure above the package substrate, the capacitor elements and inductor elements arranged on the surface of the interposer are also third capacitor elements and third inductor elements.

[0074] In the semiconductor systems of the first embodiment, the modified example of the first embodiment, the second embodiment, and the modified example of the second embodiment, the capacitor elements and the inductor elements are arranged on the underside of the motherboard. However, in the semiconductor system of the present invention, the capacitor elements and the inductor elements may be arranged on the upper surface of the motherboard.

[0075] In the semiconductor systems of the above-described first embodiment, the modified example of the first embodiment, the second embodiment, and the modified example of the second embodiment, a voltage regulator was arranged inside the package substrate, but in the semiconductor system of the present invention, a voltage regulator may be arranged on the surface of the package substrate, or a voltage regulator may be arranged inside and / or on the surface of the interposer. Because the package substrate and the interposer are structures above the motherboard, the voltage regulator arranged on the package substrate and the voltage regulator arranged on the interposer also serve as second voltage regulators.

[0076] In the semiconductor systems of the above-described first embodiment, the modified example of the first embodiment, the second embodiment, and the modified example of the second embodiment, the daughter board includes one package substrate and one interposer, but in the semiconductor system of the present invention, the daughter board may include multiple package substrates and multiple interposers.

[0077] This specification describes the following:

[0078] The present invention (1) is a semiconductor system including a motherboard, a sub-board arranged on the motherboard and including a package substrate located on the motherboard side and an interposer stacked on the package substrate, a semiconductor device arranged on the sub-board, at least one first capacitor element arranged on the motherboard, and at least one second capacitor element arranged in a structure above the motherboard, wherein when the sub-board is viewed from above, the range obtained by extending the outer edge of the sub-board 5 mm outward is used as a reference plane, and the reference plane is extended in the thickness direction to include the bottom and top of the semiconductor system, and this region is used as a reference region, the total capacitance of the second capacitor elements included in the reference region is greater than the total capacitance of the first capacitor elements included in the reference region.

[0079] The present invention (2) is a semiconductor system described in the present invention (1), wherein the second capacitor element includes at least one third capacitor element arranged in a structure above the package substrate, and the total capacitance value of the third capacitor elements included in the reference area is greater than the total capacitance value of the first capacitor elements included in the reference area.

[0080] The present invention (3) is a semiconductor system including a motherboard, a daughter board arranged on the motherboard and including a package substrate located on the motherboard side and an interposer stacked thereon, a semiconductor device arranged on the daughter board, at least one first capacitor element arranged on the motherboard, and at least one second capacitor element arranged in a structure above the motherboard, wherein the second capacitor element is at least one third capacitor element arranged in a structure above the package substrate, and at least one and fourth capacitor elements, wherein when the substrate is viewed from above, a range extending 5 mm outward from the outer edge of the substrate is used as a reference plane, the reference plane is extended in the thickness direction to include the bottom and top of the semiconductor system, and this region is used as a reference region, the total capacitance of the third capacitor elements included in the reference region is less than or equal to the total capacitance of the fourth capacitor elements included in the reference region, and the total capacitance of the fourth capacitor elements included in the reference region is less than or equal to the total capacitance of the first capacitor elements included in the reference region.

[0081] The present invention (4) is a semiconductor system described in the present invention (3), wherein the average thermal expansion coefficient in the planar direction of the third capacitor element included in the reference area is equal to or less than the average thermal expansion coefficient in the planar direction of the fourth capacitor element included in the reference area, and the average thermal expansion coefficient in the planar direction of the fourth capacitor element included in the reference area is equal to or less than the average thermal expansion coefficient in the planar direction of the first capacitor element included in the reference area.

[0082] The present invention (5) is a semiconductor system according to any one of the present inventions (1) to (4), including at least one first inductor element arranged on the motherboard and at least one second inductor element arranged in a structure above the motherboard.

[0083] The present invention (6) is a semiconductor system described in the present invention (5), wherein the sum of the inductance values ​​of the second inductor elements included in the reference region is greater than the sum of the inductance values ​​of the first inductor elements included in the reference region.

[0084] The present invention (7) is a semiconductor system described in the present invention (6), wherein the second inductor element includes at least one third inductor element arranged in a structure above the package substrate, and the sum of the inductance values ​​of the third inductor elements included in the reference area is greater than the sum of the inductance values ​​of the first inductor elements included in the reference area.

[0085] The present invention (8) is a semiconductor system according to the present invention (6) or (7), which includes a first voltage regulator arranged on the motherboard inside the reference area, and a second voltage regulator arranged in a structure above the motherboard, and the total inductance value of the second inductor elements used in the step-down circuit configuration of the second voltage regulator and included in the reference area is greater than the total inductance value of the first inductor elements used in the step-down circuit configuration of the first voltage regulator and included in the reference area.

[0086] The present invention (9) is a semiconductor system according to any one of the present inventions (8), wherein the average thermal expansion coefficient in the planar direction of the second inductor element used in the step-down circuit configuration of the second voltage regulator and included in the reference region is greater than the average thermal expansion coefficient in the planar direction of the first inductor element used in the step-down circuit configuration of the first voltage regulator and included in the reference region.

[0087] The present invention (10) is a semiconductor system described in the present invention (5), wherein the second inductor element includes at least one third inductor element arranged in a structure above the package substrate and at least one fourth inductor element arranged on the package substrate, and the inductance value of the third inductor element included in the reference area is less than or equal to the inductance value of the fourth inductor element included in the reference area, and the inductance value of the fourth inductor element included in the reference area is less than or equal to the inductance value of the first inductor element included in the reference area.

[0088] The present invention (11) is a semiconductor system according to the present invention (10), wherein the average thermal expansion coefficient in the planar direction of the third inductor element included in the reference region is equal to or less than the average thermal expansion coefficient in the planar direction of the fourth inductor element included in the reference region, and the average thermal expansion coefficient in the planar direction of the fourth inductor element included in the reference region is equal to or less than the average thermal expansion coefficient in the planar direction of the first inductor element included in the reference region.

[0089] The present invention (12) is a semiconductor system according to the present invention (10) or (11), which includes a first voltage regulator arranged on the motherboard inside the reference area, and a second voltage regulator arranged in a structure above the motherboard, and the total inductance value of the second inductor elements used in the step-down circuit configuration of the second voltage regulator and included in the reference area is less than or equal to the total inductance value of the first inductor elements used in the step-down circuit configuration of the first voltage regulator and included in the reference area.

[0090] REFERENCE SIGNS LIST 1, 101 Semiconductor system 2, 102 Connector 10, 110 Motherboard 11, 111 Wiring of motherboard 20, 120 Package substrate 20a, 120a Inner layer 20b, 120b Outer layer 21, 121 Wiring of package substrate 30, 130 Interposer 31, 131 Wiring of interposer 40, 140 Substrate 50, 150 Semiconductor device 51, 151 Processor 52, 152 Memory 53, 153 HBM 61, 161 Capacitor element (first capacitor element) 62a, 62b, 62c, 162a, 162b, 162c Capacitor elements (second capacitor element, fourth capacitor element) 63a, 63b, 163a, 163b Capacitor elements (second capacitor element, third capacitor element) 71, 171 inductor element (first inductor element) 72a, 72b, 72c, 172a, 172b, 172c inductor element (second inductor element, fourth inductor element) 73a, 73b, 173a, 173b inductor element (second inductor element, third inductor element) 81, 181 voltage regulator (first voltage regulator) 82, 182 voltage regulator (second voltage regulator) 90, 190 solder

Claims

1. A semiconductor system including: a motherboard; a daughter board arranged on the motherboard, including a package substrate located on the motherboard side and an interposer stacked on the package substrate; a semiconductor device arranged on the daughter board; at least one first capacitor element arranged on the motherboard; and at least one second capacitor element arranged in a structure above the motherboard, wherein, when viewed from above, the daughter board is extended 5 mm outward from the outer edge of the daughter board to form a reference plane, and the reference plane is extended in the thickness direction to include the bottom and top of the semiconductor system, and this region is defined as a reference region, the total capacitance of the second capacitor elements included in the reference region is greater than the total capacitance of the first capacitor elements included in the reference region.

2. The semiconductor system of claim 1, wherein the second capacitor element includes at least one third capacitor element arranged in a structure above the package substrate, and the total capacitance value of the third capacitor elements included in the reference area is greater than the total capacitance value of the first capacitor elements included in the reference area.

3. A semiconductor system comprising: a motherboard; a daughter board disposed on the motherboard, the daughter board including a package substrate located on the motherboard side and an interposer stacked on the package substrate; a semiconductor device disposed on the daughter board; at least one first capacitor element disposed on the motherboard; and at least one second capacitor element disposed in a structure above the motherboard, wherein the second capacitor element includes at least one third capacitor element disposed in a structure above the package substrate and at least one fourth capacitor element disposed on the package substrate, wherein, when viewed from above, the daughter board has a reference plane defined by an area extending 5 mm outward from the outer edge of the daughter board, and the reference plane is extended in the thickness direction to include the bottom and top of the semiconductor system, and the reference plane defines a reference region, the total capacitance of the third capacitor elements included in the reference region is less than or equal to the total capacitance of the fourth capacitor elements included in the reference region, and the total capacitance of the fourth capacitor elements included in the reference region is less than or equal to the total capacitance of the first capacitor elements included in the reference region.

4. The semiconductor system of claim 3, wherein the average thermal expansion coefficient in the planar direction of the third capacitor element included in the reference area is equal to or less than the average thermal expansion coefficient in the planar direction of the fourth capacitor element included in the reference area, and the average thermal expansion coefficient in the planar direction of the fourth capacitor element included in the reference area is equal to or less than the average thermal expansion coefficient in the planar direction of the first capacitor element included in the reference area.

5. A semiconductor system according to any one of claims 1 to 4, comprising: at least one first inductor element disposed on the motherboard; and at least one second inductor element disposed in a structure above the motherboard.

6. The semiconductor system according to claim 5, wherein the sum of the inductance values ​​of the second inductor elements included in the reference region is greater than the sum of the inductance values ​​of the first inductor elements included in the reference region.

7. The semiconductor system of claim 6, wherein the second inductor element includes at least one third inductor element arranged in a structure above the package substrate, and the sum of the inductance values ​​of the third inductor elements included in the reference region is greater than the sum of the inductance values ​​of the first inductor elements included in the reference region.

8. The semiconductor system according to claim 6 or 7, further comprising: a first voltage regulator disposed on the motherboard inside the reference area; and a second voltage regulator disposed in a structure above the motherboard, wherein the sum of the inductance values ​​of the second inductor elements used in the step-down circuit configuration of the second voltage regulator and included in the reference area is greater than the sum of the inductance values ​​of the first inductor elements used in the step-down circuit configuration of the first voltage regulator and included in the reference area.

9. The semiconductor system of claim 8, wherein the second inductor element used in the step-down circuit configuration of the second voltage regulator and included in the reference region has a larger average thermal expansion coefficient in the planar direction than the first inductor element used in the step-down circuit configuration of the first voltage regulator and included in the reference region.

10. The semiconductor system of claim 5, wherein the second inductor element includes at least one third inductor element arranged in a structure above the package substrate and at least one fourth inductor element arranged on the package substrate, and the inductance value of the third inductor element included in the reference region is less than or equal to the inductance value of the fourth inductor element included in the reference region, and the inductance value of the fourth inductor element included in the reference region is less than or equal to the inductance value of the first inductor element included in the reference region.

11. The semiconductor system of claim 10, wherein the average thermal expansion coefficient in the planar direction of the third inductor element included in the reference region is less than or equal to the average thermal expansion coefficient in the planar direction of the fourth inductor element included in the reference region, and the average thermal expansion coefficient in the planar direction of the fourth inductor element included in the reference region is less than or equal to the average thermal expansion coefficient in the planar direction of the first inductor element included in the reference region.

12. The semiconductor system of claim 10 or 11, further comprising: a first voltage regulator disposed on the motherboard inside the reference area; and a second voltage regulator disposed in a structure above the motherboard, wherein the sum of the inductance values ​​of the second inductor elements used in the step-down circuit configuration of the second voltage regulator and included in the reference area is less than or equal to the sum of the inductance values ​​of the first inductor elements used in the step-down circuit configuration of the first voltage regulator and included in the reference area.

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