Multilayer ceramic capacitor

Abstract

This multilayer ceramic capacitor (100) is provided with a laminate (110) and external electrodes (120, 130). The laminate (110) has an inner layer part (C) and an outer layer part (X). The inner layer part (C) has a layered structure in which a plurality of inner layer dielectric layers (140) and a plurality of inner electrode layers (150) are alternately stacked, wherein the inner layer dielectric layers (140) contain a plurality of grains that are mainly composed of BaTiO3. The inner layer part (C) has a central region (C1), an outer region (C2) in the stacking direction, and an outer region (C3) in a first direction. In the particle size distribution of the area equivalent circle diameter of the grains that are contained in the inner layer dielectric layers (140), if D50 is the particle diameter at which the cumulative amount reaches 50% on an area basis, D50 of the grains contained in the central region (C1) is 80 nm to 140 nm inclusive, and D50 of the grains contained in the outer region (C2) in the stacking direction and the outer region (C3) in the first direction is 90% to 120% inclusive of the D50 of the grains contained in the central region (C1).

Description

Multilayer ceramic capacitors

[0001] The present disclosure relates to multilayer ceramic capacitors.

[0002] As electronic devices become more sophisticated, there is a demand for higher capacitance and reliability in the multilayer ceramic capacitors mounted in the electronic devices. Patent Document 1 discloses a multilayer ceramic capacitor in which the reliability and capacitance per unit volume are improved by controlling the number of dielectric crystal grains in the dielectric layers.

[0003] Japanese Patent Application Laid-Open No. 2023-106279

[0004] The multilayer ceramic capacitor described in Patent Document 1 has a wide particle size distribution of the dielectric crystal grains contained in the dielectric layers, and is relatively prone to short circuits, so there is room for improvement in terms of reliability.

[0005] An object of the present disclosure is to provide a multilayer ceramic capacitor with improved reliability.

[0006] A multilayer ceramic capacitor according to an embodiment of the present disclosure includes a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, and an external electrode. The laminate has an internal layer portion and external layer portions arranged to sandwich the internal layer portion in the stacking direction. The internal layer portion has a laminate structure in which multiple internal dielectric layers and multiple internal electrode layers are alternately stacked. The multiple internal dielectric layers are made of BaTiO ３In a cross section of the laminate parallel to the stacking direction and the first direction, the inner layer portion has a central region, a stacking direction outer region, and a first direction outer region. In a particle size distribution of the area circle equivalent diameters of the plurality of grains contained in the plurality of inner dielectric layers, when the particle size at which a cumulative 50% diameter is obtained on an area basis is defined as D50, the D50 of the grains contained in the central region is 80 nm or more and 140 nm or less, the D50 of the grains contained in the stacking direction outer region is 90% or more and 120% or less of the D50 of the grains contained in the central region, and the D50 of the grains contained in the first direction outer region is 90% or more and 120% or less of the D50 of the grains contained in the central region.

[0007] According to the present disclosure, it is possible to provide a multilayer ceramic capacitor with improved reliability.

[0008] 1 is a perspective view showing the appearance of the multilayer ceramic capacitor according to the embodiment, and FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG.

[0009] The multilayer ceramic capacitor according to the embodiment will be described below.

[0010] [Multilayer Ceramic Capacitor] Fig. 1 is a perspective view showing the appearance of a multilayer ceramic capacitor according to an embodiment. Fig. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in Fig. 1. Fig. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in Fig. 1.

[0011] 1 to 3, the multilayer ceramic capacitor 100 of the embodiment includes a laminate 110 and external electrodes. The external electrodes of the multilayer ceramic capacitor 100 include a first external electrode 120 and a second external electrode 130.

[0012] The laminate 110 has a first surface 111 and a second surface 112 that face each other in the stacking direction, a third surface 113 and a fourth surface 114 that face each other in a first direction perpendicular to the stacking direction, and a fifth surface 115 and a sixth surface 116 that face each other in a second direction perpendicular to the stacking direction and the first direction. In FIGS. 1 to 3 , the stacking direction is denoted as T, the first direction is denoted as W, and the second direction is denoted as L. The first direction may be the width direction of the multilayer ceramic capacitor 100. The second direction may be the length direction of the multilayer ceramic capacitor 100.

[0013] The laminate 110 includes a plurality of ridges and a plurality of corners. A ridge is a portion where two of the first surface 111 to the sixth surface 116 intersect. A corner is a portion where three of the first surface 111 to the sixth surface 116 intersect. The plurality of ridges and the plurality of corners may all be rounded.

[0014] The laminate 110 is partitioned into an inner layer portion C, two outer layer portions X, two side gap portions S, and two end gap portions E. The outer layer portions X are arranged between the first surface 111 of the laminate 110 and the internal electrode layer 150 closest to the first surface 111, and between the second surface 112 and the internal electrode layer 150 closest to the second surface 112. The inner layer portion C is arranged in a region sandwiched between the two outer layer portions X. The side gap portions S are arranged between the inner layer portion C and the third surface 113 in the first direction, and between the inner layer portion C and the fourth surface 114 in the first direction. The two side gap portions S cover, along the ends in the first direction, of the multiple internal electrode layers 150 exposed on the third surface 113 and the fourth surface 114 of the laminate 110. The end gap portions E are arranged between the inner layer portion C and the fifth surface 115 in the second direction, and between the inner layer portion C and the sixth surface 116 in the second direction. As will be described later, external electrodes electrically connected to the internal electrode layers 150 are formed on the fifth surface 115 and the sixth surface 116. Therefore, the two end gap portions E are regions between the inner layer portions C and the surfaces to which the internal electrode layers 150 and the external electrodes are electrically connected.

[0015] The inner layer portion C has a laminated structure in which a plurality of inner dielectric layers 140 and a plurality of internal electrode layers 150 are alternately laminated.

[0016] The multiple internal electrode layers 150 include a first internal electrode layer 151 and a second internal electrode layer 152. The first internal electrode layer 151 has a counter electrode portion facing the second internal electrode layer 152 via the internal dielectric layer 140, and a lead electrode portion extending from the counter electrode portion to the fifth surface 115 of the laminate 110. The second internal electrode layer 152 has a counter electrode portion facing the first internal electrode layer 151 via the internal dielectric layer 140, and a lead electrode portion extending from the counter electrode portion to the sixth surface 116 of the laminate 110. The multiple internal electrode layers 150 included in the internal layer portion C include multiple pairs of electrode layers each consisting of the first internal electrode layer 151 and the second internal electrode layer 152.

[0017] A single capacitor is formed by the first internal electrode layer 151 and the second internal electrode layer 152 facing each other via the internal dielectric layer 140. The multilayer ceramic capacitor 100 can be said to be a plurality of capacitors connected in parallel via first external electrodes 120 and second external electrodes 130, which will be described later.

[0018] The inner layer portion C preferably includes 100 to 1000, more preferably 300 to 400, of the internal electrode layers 150 .

[0019] The thickness of each of the plurality of internal electrode layers 150 may be, for example, 0.01 μm or more and 0.5 μm or less, and preferably 0.2 μm or more and 0.5 μm or less. The thickness of the internal electrode layer 150 is measured in a scanning electron microscope (hereinafter sometimes abbreviated as SEM) observation image of a cross section of the laminate 110 in the stacking direction.

[0020] Of the ends of the plurality of internal electrode layers 150 on the third surface 113 side, the amount of deviation between the outermost end in the first direction and the innermost end in the first direction is preferably 1.0 μm or less. Also, of the ends of the plurality of internal electrode layers 150 on the fourth surface 114 side, the amount of deviation between the outermost end in the first direction and the innermost end in the first direction is preferably 1.0 μm or less. That is, it is preferable that both ends of the plurality of internal electrode layers 150 in the first direction are aligned in the stacking direction.

[0021] The internal electrode layer 150 includes a conductive material. Examples of the conductive material include at least one metal selected from nickel (Ni), copper (Cu), silver (Ag), gold (Au), palladium (Pd), etc., or an alloy containing such a metal. In this embodiment, the internal electrode layer 150 includes Ni as a main component. The main component refers to the component with the largest content in terms of mass among the constituent components. The internal electrode layer 150 may further include dielectric particles called a common material. The common material may include magnesium (Mg).

[0022] The internal electrode layer 150 preferably further contains tin (Sn). Sn is preferably present at the interfaces between the first internal electrode layer 151 and the second internal electrode layer 152 and the internal dielectric layer 140.

[0023] A part of Ni in the internal electrode layer 150 may segregate to the end of the internal electrode layer 150 in the first direction. Also, a part of Mg in the laminate 110 may segregate to the end of the internal electrode layer 150 in the first direction. A part of the segregated Ni and a part of Mg form Ni-Mg oxide. That is, Ni-Mg oxide may segregate to the end of some internal electrode layers 150 in the first direction (at least one of the two end portions; the same applies hereinafter) of the plurality of internal electrode layers 150. The total number of internal electrode layers 150 having segregation of Ni-Mg oxide at the end in the first direction is preferably 10% or less of the total number of internal electrode layers 150. By setting the ratio of the internal electrode layers 150 having Ni-Mg oxide segregation at the ends in the first direction within the above range, it is possible to reduce electric field concentration on the internal electrode layers 150 due to the segregation of Ni-Mg oxide, and more effectively suppress conduction between adjacent internal electrode layers 150.

[0024] The thickness of each of the plurality of inner dielectric layers 140 is preferably 0.3 μm or more and 1.0 μm or less, more preferably 0.4 μm or more and 0.6 μm or less. The thickness of the inner dielectric layer 140 is measured in an SEM observation image of a cross section of the laminate 110 in the stacking direction.

[0025] The inner dielectric layer 140 is made of barium titanate (BaTiO ３ The inner dielectric layer 140 is made of a ceramic material mainly composed of BaTiO ３ The content of may be, for example, 90 mass % or more, 95 mass % or more, or 99 mass % or more based on the total mass of the inner dielectric layer 140 .

[0026] BaTiO ３ The molar ratio of the A-site component to the B-site component, i.e., the molar ratio of Ba to Ti, Ba / Ti, is preferably 1.004 to 1.010. By having Ba / Ti within the above range, grain growth during firing can be suppressed, and the generation of coarse particles can be suppressed.

[0027] The inner dielectric layer 140 is made of BaTiO ３ The perovskite-type compounds of the BaTiO ３The perovskite-type compound in this system is, for example, BaTiO ３ , and BaTiO ３ Ba ２＋ and Ti ４＋ At least one of the ２＋ and Zr ４＋ and perovskite-type compounds substituted with other ions such as ZnO.

[0028] The inner dielectric layer 140 may further contain a rare earth element. The content of the rare earth element in the inner dielectric layer 140 is BaTiO ３ The rare earth element content may be 0.5 mol % or more and 3.0 mol % or less, preferably 1.0 mol % or more and 2.5 mol % or less, and more preferably 1.3 mol % or more and 2.0 mol % or less, relative to 100 mol %. By having the rare earth element content within the above range, it is possible to improve the effective capacity and reliability.

[0029] When the inner dielectric layer 140 further contains a rare earth element, BaTiO ３ The perovskite compounds of this system have Ba in the crystal lattice. ２＋ A part of the rare earth element ions Re ３＋ The compound may be a perovskite-type compound substituted by

[0030] The rare earth element may include at least one selected from the group consisting of scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). The rare earth element preferably includes at least one selected from the group consisting of Dy, Y, Gd, Tb, Ho, and Er, and more preferably includes Dy.

[0031] The inner dielectric layer 140 may further contain at least one element selected from the group consisting of silicon (Si), aluminum (Al), Mg, manganese (Mn), Ni, iron (Fe), Cu, and vanadium (V) as other elements. By including these elements, the density of the inner dielectric layer 140 in the firing step can be controlled.

[0032] The plurality of inner dielectric layers 140 preferably contain Mn. The content of Mn in the inner dielectric layers 140 is set to BaTiO ３ The content is preferably 0.1 mol % or more and 0.2 mol % or less relative to 100 mol %.

[0033] The plurality of inner dielectric layers 140 preferably contain Dy and Mn from the viewpoint of improving the effective capacity and reliability. The content of Dy in the inner dielectric layers 140 is preferably 0.01 to 0.1% by weight of BaTiO ３ The Mn content in the inner dielectric layer 140 is preferably 1.3 mol % or more and 2.0 mol % or less relative to 100 mol %, and the ... ３ The content is preferably 0.1 mol % or more and 0.2 mol % or less relative to 100 mol %.

[0034] The contents of rare earth elements and other elements in the inner dielectric layer 140 can be determined from the compounding ratios of the starting materials. The contents of rare earth elements and other elements in the inner dielectric layer 140 can be quantified by, for example, X-ray fluorescence analysis (XRF), inductively coupled plasma atomic emission spectroscopy (ICP-AES), energy dispersive X-ray spectroscopy (EDX), etc. When the contents of rare earth elements and other elements in the inner dielectric layer 140 are quantified by EDX, the measurements can be made using, for example, images observed at a magnification of 150,000 times using a scanning transmission electron microscope (STEM / EDX).

[0035] The inner dielectric layer 140 includes a plurality of grains. A grain is a particle surrounded by a grain boundary, and is also called a crystal grain.

[0036] In this specification, the particle size of a single grain refers to the diameter of a circle having an area equal to the area of ​​the cross section of the grain in an SEM image of a cross section of the laminate 110 parallel to the stacking direction and the first direction (hereinafter also referred to as the equivalent circle diameter). Furthermore, in the particle size distribution of the equivalent circle diameters measured from the SEM image of the cross section of the laminate 110, the particle size at which the cumulative 50% is measured on an area basis is defined as D50. The SEM image of the cross section of the laminate 110 may be, for example, an SEM image observed at 50,000x magnification. The cumulative particle size distribution of the particle sizes of multiple grains is determined from the particle sizes of 200 or more grains. It is not necessary for one SEM image to contain 200 or more grains; it is sufficient that the total number of grains contained in multiple SEM images is 200 or more.

[0037] The grain size is determined by, for example, the starting material (e.g., BaTiO ３ The content can be controlled by selecting the particle size and composition of the ceramic powder, adjusting the rare earth content and other element contents, and adjusting the firing temperature and temperature rise rate in the firing step of the method for producing a multilayer ceramic capacitor, which will be described later.

[0038] The inner layer portion C has a central region C1, a stacking direction outer region C2, and a first direction outer region C3 in a cross section parallel to the stacking direction and the first direction. The central region C1, stacking direction outer region C2, and first direction outer region C3 will be described using FIG. 3 . The central region C1 is a 3.0 μm × 3.0 μm square region of the inner dielectric layer 140, centered on the intersection of a center line that bisects the inner layer portion C in the stacking direction and a center line that bisects the inner layer portion C in the first direction. The stacking direction outer region C2 is a region of the inner dielectric layer 140 closest to the outer layer portion X, located in the center in the first direction. The center in the first direction is a region 1.5 μm on both sides of the center line that bisects the inner layer portion C in the first direction (a total width of 3.0 μm). The first direction outer region C3 is a 3.0 μm × 3.0 μm square region centered on the intersection of a center line dividing the inner layer portion C in half in the stacking direction and a line indicating a position 1.5 μm inward from the end of the internal electrode layer 150 in the first direction. While only the stacking direction outer region C2 on the first surface 111 side is shown in FIG. 3 , the stacking direction outer region C2 also exists on the second surface 112 side. The grain size of the grains contained in the stacking direction outer region C2 may be measured from an SEM observation image of either of the two stacking direction outer regions C2. Furthermore, while only the first direction outer region C3 on the fourth surface 114 side is shown in FIG. 3 , the first direction outer region C3 also exists on the third surface 113 side. The grain size of the grains contained in the first direction outer region C3 may be measured from an SEM observation image of either of the two first direction outer regions C3.

[0039] In the inner layer portion C, the central region C1, the stacking direction outer region C2, and the first direction outer region C3 exhibit different sintering behaviors during the firing process, and therefore the grain size in each region may differ. If the grain size differs depending on the region of the inner layer portion C, the grain size distribution of the grains contained in the inner layer portion C becomes broader, which tends to reduce the reliability of the multilayer ceramic capacitor.

[0040] The grains contained in the central region C1 have a D50 of 80 nm or more and 140 nm or less, preferably 80 nm or more and 120 nm or less, and more preferably 90 nm or more and 110 nm or less. By having the D50 of the grains contained in the central region C1 within the above range, the rate of change in DC bias characteristics can be reduced. Specifically, the rate of change in DC bias characteristics when a voltage of 3.15 V is applied to the multilayer ceramic capacitor of this embodiment can be reduced to 60% or less.

[0041] The D50 of the grains included in the outer region C2 in the stacking direction is 90% to 120% of the D50 of the grains included in the central region C1, preferably 95% to 115%, and more preferably 95% to 110%. The D50 of the grains included in the outer region C3 in the first direction is 90% to 120% of the D50 of the grains included in the central region C1, preferably 95% to 115%, and more preferably 95% to 110%.

[0042] When the D50 of the grains contained in each region of the inner layer portion C is within the above range, the grain size distribution becomes narrow, thereby making it possible to obtain a multilayer ceramic capacitor with improved reliability. Furthermore, because the grain size distribution becomes narrow, it is possible to obtain a multilayer ceramic capacitor with a small rate of change in DC bias characteristics while maintaining effective capacitance.

[0043] The outer layer portions X are arranged to sandwich the inner layer portion C in the stacking direction. The outer layer portions X include one or more outer dielectric layers. The outer dielectric layers are made of BaTiO ３ The ceramic material constituting the outer dielectric layer may be the same as or different from the ceramic material constituting the inner dielectric layer 140.

[0044] The multilayer ceramic capacitor 100 further includes a first external electrode 120 and a second external electrode 130. The first external electrode 120 is formed on a fifth surface 115 of the laminate 110 so as to be electrically connected to the first internal electrode layer 151. The first external electrode 120 extends from the fifth surface 115 to the first surface 111, the second surface 112, the third surface 113, and the fourth surface 114. The second external electrode 130 is formed on a sixth surface 116 of the laminate 110 so as to be electrically connected to the second internal electrode layer 152. The second external electrode 130 extends from the sixth surface 116 to the first surface 111, the second surface 112, the third surface 113, and the fourth surface 114.

[0045] The first external electrode 120 and the second external electrode 130 each have, for example, a base electrode layer and a plating layer disposed on the base electrode layer. The base electrode layer includes, for example, at least one selected from a sintered body layer, a conductive resin layer, and a metal thin film layer.

[0046] The sintered body layer is formed by baking a paste containing glass powder and metal powder, and includes a glass portion and a metal portion. ２ O ３ -SiO ２ Examples of the metal that constitutes the metal portion include at least one selected from Ni, Cu, Ag, etc., or an alloy containing such a metal. The sintered body layer may be formed of multiple layers made of different components. In addition, in the manufacturing method described below, the sintered body layer may be fired simultaneously with the laminate 110, or may be baked after the laminate 110 has been fired.

[0047] The conductive resin layer includes conductive particles such as metal fine particles and a resin portion. The metal fine particles may be made of at least one metal selected from Ni, Cu, Ag, etc., or an alloy containing such a metal. The resin portion may be made of an epoxy-based thermosetting resin, etc. The conductive resin layer may be formed of multiple layers made of different components.

[0048] The metal thin film layer is a layer of metal fine particles deposited to a thickness of 1 μm or less, formed by a thin film formation method such as sputtering or vapor deposition. The metal constituting the metal thin film layer may be at least one selected from Ni, Cu, Ag, Au, etc., or an alloy containing such a metal. The metal thin film layer may be formed of multiple layers made of different components.

[0049] Examples of the metal constituting the plating layer include at least one selected from Ni, Cu, Ag, Au, Sn, etc., or an alloy containing such a metal. The plating layer may be formed of a plurality of layers made of different components.

[0050] The first external electrode 120 and the second external electrode 130 may each be a plated layer that is provided directly on the laminate 110 and directly connected to the corresponding internal electrode layer described above.

[0051] From the viewpoint of improving reliability, the multilayer ceramic capacitor 100 of this embodiment preferably has a dimension in the stacking direction of 0.2 mm or more and 0.8 mm or less, a dimension in the first direction of 0.2 mm or more and 0.8 mm or less, and a dimension in the second direction of 0.4 mm or more and 1.0 mm or less, and more preferably has a dimension in the stacking direction of 0.25 mm or more and 0.35 mm or less, a dimension in the first direction of 0.25 mm or more and 0.35 mm or less, and a dimension in the second direction of 0.55 mm or more and 0.65 mm or less.

[0052] From the viewpoint of improving reliability, the multilayer ceramic capacitor 100 of this embodiment preferably has a dimension in the stacking direction of 0.2 mm or more and 0.8 mm or less, a dimension in the first direction of 0.2 mm or more and 0.8 mm or less, and a dimension in the second direction of 0.4 mm or more and 1.0 mm or less, the inner layer portion C includes 100 to 1000 internal electrode layers, and each of the plurality of inner dielectric layers preferably has a thickness of 0.3 μm or more and 1.0 μm or less.

[0053] From the viewpoint of improving reliability, it is more preferable that the multilayer ceramic capacitor 100 of this embodiment has a dimension in the stacking direction of 0.25 mm or more and 0.35 mm or less, a dimension in the first direction of 0.25 mm or more and 0.35 mm or less, and a dimension in the second direction of 0.55 mm or more and 0.65 mm or less, the inner layer portion C includes 300 or more and 400 or less internal electrode layers, and each of the plurality of inner dielectric layers has a thickness of 0.4 μm or more and 0.6 μm or less.

[0054] The multilayer ceramic capacitor 100 of this embodiment may be a two-terminal capacitor as shown in Fig. 1 . Alternatively, the multilayer ceramic capacitor 100 of this embodiment may be a three-terminal capacitor. A two-terminal capacitor has a configuration in which the first internal electrode layer 151 is exposed on the fifth surface 115 and the second internal electrode layer 152 is exposed on the sixth surface 116, whereas a three-terminal capacitor has a configuration in which the first internal electrode layer 151 is exposed on the fifth surface 115 and the sixth surface 116 and the second internal electrode layer 152 is exposed on the third surface 113 and the fourth surface 114, and further, a third external electrode and a fourth external electrode are provided on the third surface 113 and the fourth surface 114 of the laminate 110.

[0055] [Method for Manufacturing Multilayer Ceramic Capacitor] The method for manufacturing the multilayer ceramic capacitor 100 includes a step of stacking a plurality of pre-fired dielectric sheets, including a pre-fired dielectric sheet on which an internal electrode pattern is formed, to obtain a pre-fired laminate (hereinafter also referred to as a lamination step), a step of forming a side gap portion in the pre-fired laminate, and a step of sintering the pre-fired laminate to obtain a laminate in which a plurality of inner dielectric layers and a plurality of internal electrode layers are stacked (hereinafter also referred to as a firing step).

[0056] The pre-fired dielectric sheet used in the lamination process can be produced as follows: First, a slurry for forming the dielectric layer is prepared. Specifically, BaTiO ３ The powder containing the additives, binder, solvent, etc. are mixed in a predetermined blending ratio to prepare a slurry for forming the dielectric layer.

[0057] Next, the dielectric layer forming slurry is formed into a sheet on a carrier film using a die coater, gravure coater, microgravure coater, or the like, to form a pre-fired dielectric sheet.

[0058] Next, a mother sheet is formed. Specifically, a conductive paste is printed in a predetermined pattern on the pre-fired dielectric sheet using a screen printing method, a gravure printing method, or the like, to form a mother sheet having the predetermined conductive pattern on the pre-fired dielectric sheet.

[0059] As the mother sheet, a pre-fired dielectric sheet on which no conductive pattern is formed is also prepared.

[0060] Next, the mother sheets are stacked. Specifically, a predetermined number of mother sheets that do not have a conductive pattern and that form the outer layer portion are stacked, and then a plurality of mother sheets that have a conductive pattern and that form the inner layer portion are stacked in order on top of these, and then a predetermined number of mother sheets that do not have a conductive pattern are stacked on top of these, thereby forming a mother sheet group.

[0061] Next, the mother sheets are pressed together by a hydrostatic press or a rigid press in the stacking direction to form a mother laminate.

[0062] Next, the mother laminate is divided. Specifically, the mother laminate is divided into a matrix by press-cutting, dicing, or laser cutting, and is divided into a plurality of pre-fired laminates. The pre-fired laminates may be barrel-polished.

[0063] Next, a side gap portion is formed in the pre-fired laminate. First, a ceramic slurry is prepared. Specifically, BaTiO ３ The powder containing the additives, the binder, the solvent, etc. are mixed in a predetermined blending ratio to prepare a ceramic slurry. The ceramic slurry may be the same as or different from the above-mentioned slurry for forming the dielectric layer.

[0064] Next, a ceramic slurry is applied to the resin film and dried to form a pre-fired dielectric sheet for the side gap portion. The pre-fired dielectric sheet for the side gap portion may be a single layer or multiple layers. Next, the side gap portion is formed by attaching the pre-fired dielectric sheet for the side gap portion to both sides of the pre-fired laminate where the internal electrode layers are exposed. This results in a pre-fired laminate with a side gap portion formed therein.

[0065] The side gap portion is not limited to a configuration in which the side gap portion is attached to both side surfaces of the pre-fired laminate after the pre-fired laminate is manufactured, and the side gap portion may be manufactured simultaneously with the manufacturing of the pre-fired laminate.

[0066] Next, in the firing step, the pre-fired laminate is fired. Specifically, the pre-fired laminate is degreased under predetermined conditions, and then heated to a predetermined temperature at a predetermined heating rate to form a laminate. In the firing step, the grain diameter can be controlled by setting an appropriate firing temperature and heating rate, etc. The firing temperature is appropriately set depending on the type of starting material and the size of the multilayer ceramic capacitor to be manufactured, and may be, for example, 900°C or higher and 1300°C or lower. The heating rate is appropriately set depending on the type of starting material and the size of the multilayer ceramic capacitor to be manufactured, but is preferably 15°C / min or higher. A temperature rise rate of 15°C / min or more tends to result in a multilayer ceramic capacitor in which the D50 of the grains contained in the central region C1 is 80 nm or more and 140 nm or less, the D50 of the grains contained in the stacking direction outer region C2 is 90% or more and 120% or less of the D50 of the grains contained in the central region C1, and the D50 of the grains contained in the first direction outer region C3 is 90% or more and 120% or less of the D50 of the grains contained in the central region C1. Heat treatment (annealing) may be performed after firing. The annealing temperature may be, for example, 900°C or more and 1100°C or less. The annealing temperature is preferably lower than the maximum temperature in the firing process. Annealing is preferably performed in a weakly reducing atmosphere.

[0067] Next, external electrodes are formed on the laminate. For example, after a base electrode layer is formed on the surface of the laminate, a plating layer is formed by electroplating so as to cover the base electrode layer.

[0068] The multilayer ceramic capacitor 100 can be manufactured through the above series of steps.

[0069] Hereinafter, the present disclosure will be described in more detail with reference to examples and comparative examples, but the present disclosure is not limited to these.

[0070] Example 1 A multilayer ceramic capacitor was fabricated in the following manner. First, a pre-fired dielectric sheet was fabricated using a dielectric raw material powder. The dielectric raw material powder contained BaTiO 4 in which the molar ratio of Ba to Ti (Ba / Ti) was 1.004 or more and 1.010 or less. ３ The powder (average particle size: 100 nm) was used as the main component, and Dy and Mn were further added. The Dy content in the dielectric raw material powder was BaTiO ３ The Mn content in the dielectric raw material powder was 1.3 mol % or more and 2.0 mol % or less relative to 100 mol %. ３ It was blended in an amount of 0.1 mol % or more and 0.2 mol % or less relative to 100 mol %. ３ The powder prepared had a narrow particle size distribution.

[0071] Next, an internal electrode pattern was formed on the pre-fired dielectric sheet by printing a Ni-based conductive paste for the internal electrodes in a predetermined pattern. A predetermined number of pre-fired dielectric sheets for the outer layer portion, on which no internal electrode pattern was printed, were stacked, and then 300 pre-fired dielectric sheets on which the internal electrode pattern was printed were stacked on top of these, and a predetermined number of pre-fired dielectric sheets for the outer layer portion were stacked on top of these to produce a pre-fired laminate. The pre-fired laminate was pressed in the stacking direction using an isostatic press to produce a laminate block. The laminate block was cut to a predetermined size, and a laminate chip was cut out. Pre-fired dielectric sheets for the side gap, on which no internal electrode pattern was printed, were attached to both sides of the laminate chip. At this time, the corners and ridges of the laminate chip were rounded by barrel polishing. The laminate chip was sintered to produce a laminate. The sintering temperature was 1200°C, and the heating rate from the start of sintering to the sintering temperature was 15°C / min. A conductive paste primarily composed of Cu for the external electrodes was applied to both end surfaces of the laminated chip and baked to form baked layers for the external electrodes. Ni and Sn plating were applied to the surface of the baked layer to obtain a multilayer ceramic capacitor. The dimensions of the multilayer ceramic capacitor in the lamination direction were 0.3 mm, the dimensions in the first direction were 0.3 mm, and the dimensions in the second direction were 0.6 mm. The thicknesses of the inner dielectric layers were each 0.5 μm. A reliability test was conducted on the resulting multilayer ceramic capacitor. The results are shown in Table 1.

[0072] (Examples 2 to 12) Dielectric raw material powder (BaTiO ３ By adjusting the Ba / Ti ratio and average particle size of the ceramic powder, the Dy and Mn contents, and the firing temperature and heating rate in the firing step, multilayer ceramic capacitors with different grain D50 were obtained. Reliability tests were conducted on the resulting multilayer ceramic capacitors. The results are shown in Table 1.

[0073] Comparative Example 1: A dielectric raw material powder containing BaTiO 4 with a molar ratio of Ba to Ti (Ba / Ti) of less than 1.004 was used. ３A multilayer ceramic capacitor was obtained in the same manner as in Example 1, except that the powder was used as the main component and the temperature rise rate in the firing step was set to 10°C / min. The obtained multilayer ceramic capacitor was subjected to a reliability test. The results are shown in Table 1.

[0074] (Comparative Examples 2 to 6) Dielectric raw material powder (BaTiO ３ By adjusting the Ba / Ti ratio and average particle size of the ceramic powder, the Dy and Mn contents, and the firing temperature and heating rate in the firing step, multilayer ceramic capacitors with different grain D50 were obtained. Reliability tests were conducted on the resulting multilayer ceramic capacitors. The results are shown in Table 1.

[0075] [Reliability Test] A reliability test was performed by preparing 100 multilayer ceramic capacitors and applying a voltage of 9.5 V for 10 hours at 120° C. After the test, if the number of short-circuited multilayer ceramic capacitors was 0, it was marked as "○", and if the number was 1 or more, it was marked as "×".

[0076] [Grain Diameter Measurement] A multilayer ceramic capacitor was cross-sectioned to expose a cross section parallel to the stacking direction and the first direction, and the cross section was polished to 1 / 2 in the second direction. The polished cross section was observed at 50,000x magnification using an SEM (Hitachi, SU8230), and the equivalent circle diameter of each of 200 or more grains was calculated by image analysis. The grain diameter at 50% cumulative area was defined as D50. The cross section was observed and D50 was calculated for the central region, the outer region in the stacking direction, and the outer region in the first direction. The results are shown in Table 1.

[0077]

[0078] The multilayer ceramic capacitors of Examples 1 to 12 had excellent reliability because the D50 of the grains included in the outer region in the stacking direction and the outer region in the first direction was 90% or more and 120% or less of the D50 of the grains included in the central region. The multilayer ceramic capacitors of Comparative Examples 1, 3, and 5 had small D50 of the grains included in the outer region in the stacking direction and the outer region in the first direction, resulting in short circuits. This is presumably due to insufficient solid solution of the additive (e.g., Dy) in the inner dielectric layer in the grains included in the outer region in the stacking direction and the outer region in the first direction. In Comparative Examples 2, 4, and 6, the D50 of the grains included in the outer region in the stacking direction and the outer region in the first direction was large, resulting in short circuits. This is thought to be due to the fact that the number of grains included in the inner dielectric layer arranged between adjacent internal electrode layers was reduced, resulting in an increase in the electric field strength per grain.

[0079] In the above-described embodiments, configurations that can be combined may be combined with each other.

[0080] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0081] It will be appreciated by those skilled in the art that the exemplary embodiments described above are examples of the following aspects.

[0082] (Item 1) A multilayer ceramic capacitor according to one embodiment of the present disclosure includes a laminate having a first surface and a second surface that face each other in a stacking direction, a third surface and a fourth surface that face each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface that face each other in a second direction perpendicular to the stacking direction and the first direction, and an external electrode. The laminate has an internal layer portion and external layer portions that are arranged to sandwich the internal layer portion in the stacking direction. The internal layer portion has a laminate structure in which multiple internal dielectric layers and multiple internal electrode layers are alternately stacked. The multiple internal dielectric layers are made of BaTiO ３The laminate includes a plurality of grains whose main component is BaTiO. In a cross section of the laminate parallel to the stacking direction and the first direction, the inner layer portion has a central region, an outer region in the stacking direction, and an outer region in the first direction. In a particle size distribution of the area circle equivalent diameters of the plurality of grains included in the plurality of inner dielectric layers, when the particle size at which the cumulative 50% on an area basis is D50, the D50 of the grains included in the central region is 80 nm or more and 140 nm or less, the D50 of the grains included in the outer region in the stacking direction is 90% or more and 120% or less of the D50 of the grains included in the central region, and the D50 of the grains included in the outer region in the first direction is 90% or more and 120% or less of the D50 of the grains included in the central region. (Item 2) In the multilayer ceramic capacitor described in item 1, the plurality of inner dielectric layers include Dy and Mn. The Dy content is BaTiO ３ The Mn content is 1.3 mol% or more and 2.0 mol% or less relative to 100 mol%, and the Mn content is BaTiO ３The molar ratio of Ba to Ti contained in the plurality of inner dielectric layers is 0.1 mol % or more and 0.2 mol % or less, relative to 100 mol %. (Item 3) In the multilayer ceramic capacitor described in items 1 or 2, the molar ratio of Ba to Ti contained in the plurality of inner dielectric layers is 1.004 or more and 1.010 or less. (Item 4) In the multilayer ceramic capacitor described in any one of items 1 to 3, the plurality of internal electrode layers contain Ni as a main component. The plurality of internal electrode layers include internal electrode layers having segregation of Ni—Mg oxide at their ends in the first direction. The total number of internal electrode layers having segregation of Ni—Mg oxide is 10% or less of the total number of the plurality of internal electrode layers. (5) The multilayer ceramic capacitor according to any one of paragraphs 1 to 4 has a dimension in the stacking direction of 0.2 mm to 0.8 mm, a dimension in the first direction of 0.2 mm to 0.8 mm, and a dimension in the second direction of 0.4 mm to 1.0 mm, the inner layer portion includes 100 to 1000 internal electrode layers, and each of the plurality of inner dielectric layers has a thickness of 0.3 μm to 1.0 μm. (6) The multilayer ceramic capacitor according to any one of paragraphs 1 to 4 has a dimension in the stacking direction of 0.25 mm to 0.35 mm, a dimension in the first direction of 0.25 mm to 0.35 mm, and a dimension in the second direction of 0.55 mm to 0.65 mm, the inner layer portion includes 300 to 400 internal electrode layers, and each of the plurality of inner dielectric layers has a thickness of 0.4 μm to 0.6 μm.

[0083] 100 multilayer ceramic capacitor, 110 laminate, 111 first surface, 112 second surface, 113 third surface, 114 fourth surface, 115 fifth surface, 116 sixth surface, 120 first external electrode, 130 second external electrode, 140 inner dielectric layer, 150 internal electrode layer, 151 first internal electrode layer, 152 second internal electrode layer, C inner layer portion, C1 central region, C2 outer region in stacking direction, C3 outer region in first direction, E end gap portion, L second direction, S side gap portion, T stacking direction, W first direction, X outer layer portion.

Claims

1. A multilayer ceramic capacitor comprising: a laminate having a first surface and a second surface opposed to each other in a lamination direction, a third surface and a fourth surface opposed to each other in a first direction perpendicular to the lamination direction, and a fifth surface and a sixth surface opposed to each other in a second direction perpendicular to the lamination direction and the first direction; and an external electrode, wherein the laminate has an internal layer portion and external layer portions arranged to sandwich the internal layer portion in the lamination direction, the internal layer portion having a laminate structure in which a plurality of internal dielectric layers and a plurality of internal electrode layers are alternately laminated, and the plurality of internal dielectric layers are made of BaTiO ３ a multilayer ceramic capacitor comprising a plurality of grains each having a principal component of the above-mentioned, wherein in a cross section of the laminate parallel to the stacking direction and the first direction, the inner layer portion has a central region, a stacking direction outer region, and a first direction outer region, wherein, in a particle size distribution of area circle equivalent diameters of the plurality of grains contained in the plurality of inner dielectric layers, when a particle size at which a cumulative 50% particle size on an area basis is D50, the D50 of the grains contained in the central region is 80 nm or more and 140 nm or less, the D50 of the grains contained in the stacking direction outer region is 90% or more and 120% or less of the D50 of the grains contained in the central region, and the D50 of the grains contained in the first direction outer region is 90% or more and 120% or less of the D50 of the grains contained in the central region.

2. The plurality of inner dielectric layers contain Dy and Mn, and the Dy content is BaTiO ３ The Mn content is 1.3 mol% or more and 2.0 mol% or less relative to 100 mol%, and BaTiO ３ 2. The multilayer ceramic capacitor according to claim 1, wherein the content is 0.1 mol % or more and 0.2 mol % or less relative to 100 mol %.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the molar ratio of Ba to Ti contained in said plurality of inner dielectric layers is 1.004 or more and 1.010 or less.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the plurality of internal electrode layers contain Ni as a main component, the plurality of internal electrode layers include internal electrode layers having segregation of Ni-Mg oxide at ends in the first direction, and the total number of the internal electrode layers having segregation of Ni-Mg oxide is 10% or less of the total number of the plurality of internal electrode layers.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the dimension in the lamination direction is 0.2 mm or more and 0.8 mm or less, the dimension in the first direction is 0.2 mm or more and 0.8 mm or less, and the dimension in the second direction is 0.4 mm or more and 1.0 mm or less, the inner layer portion includes 100 to 1000 of the internal electrode layers, and each of the plurality of inner dielectric layers has a thickness of 0.3 μm or more and 1.0 μm or less.

6. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the dimension in the lamination direction is 0.25 mm or more and 0.35 mm or less, the dimension in the first direction is 0.25 mm or more and 0.35 mm or less, and the dimension in the second direction is 0.55 mm or more and 0.65 mm or less, the inner layer portion includes 300 to 400 of the internal electrode layers, and each of the plurality of inner dielectric layers has a thickness of 0.4 μm or more and 0.6 μm or less.

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