Devices and methods involving thermally-conductive devices using substrate

Abstract

In certain examples, methods and semiconductor structures are directed to managing heat in integrated circuits (ICs) by way of a substrate-based matrix of IC-directed pathways including those that conduct electricity and that conduct heat. For example, a semiconductor apparatus includes a substrate, characterized as predominantly including highly thermal- conductive materials (e.g., diamond and / or AIN), in proximity to an active region of an integrated circuit (IC) of a semiconductor device. The substrate includes a matrix of pathways that conduct electricity to and / or from the IC and the sides of the substrate, further including thermal vias that conduct and disperse heat through the bulk of the substrate and away from the active region.

Description

[0001] STFD.465PCT (S24-245) 1      DEVICES AND INVOLVING THERMALLY-CONDUCTIVE DEVICES USING SUBSTRATE BACKGROUND The present disclosure generally relates to improving thermal management in integrated circuits (ICs). More specifically, the present disclosure relates to reducing the self- heating issues including those which can occur from hot spots of transistors such as used in high-power and / or fast switching transistors and more generally in highly densified ICs such as individual chip and chip sets. In response to the ever-increasing demand for speed, power and functionality of integrated circuits, aggressive scaling of feature sizes according to Moore’s law has enabled enhanced device and circuit capabilities. In tandem with this pursuit, a large reduction of interconnect metal pitch, metallization levels, and overall interconnect density within packaging architecture has been achieved with state-of-the-art linewidths and spacings of ~0.6 um in silicon substrates. The primary driver for advanced 2D and 3D packaging technologies is the need for increased interconnect densities to deliver increasing bandwidth in a power-efficient manner while enabling efficient power delivery. These aggressive efforts to densify integrated-circuits technology are being pushed even further by suggestions of using double-sided package substrates. While double- sided package substrates can offer improved performance, they also introduce new thermal challenges that need to be addressed to ensure the reliability and longevity of chips, chipsets, chiplets and interconnects. Maintaining low thermal resistances with effective thermal management strategies in place can help mitigate these issues. The resulting increase in current density through the interconnects in advanced substrates leads to increasing thermal issues. The self-heating or Joule heating that occurs from high current densities in shrinking interconnects can lead to severe reliability issues that mainly stem from electromigration (EM) of the interconnect material, commonly copper. The time to failure, t, of a Cu line may be described by using Black’s equation. EM can cause issues in the interconnects both by the formation of voids, causing an interconnect to first increase in resistance, and eventually become open, and by the formation of metal extrusions, causing unwanted shorts with neighboring lines. Recent efforts have recognized that low-K SiO2 based dielectric materials, which are needed to minimize the RC delay, exacerbate this effect due to their particularly low thermal conductivity. Thus, overheating can cause signal integrity issues, and higher losses, especially in the power distribution network and lowered performance. Furthermore, STFD.465PCT (S24-245) 2      at the die and / or chiplet level, severe cases high thermal resistance can lead to a phenomenon known as thermal runaway, where an increase in temperature causes further heating, leading to a destructive cycle that causes irreversible damage to a device. With ongoing studies of device-level thermal engineering, a thermally conductive substrate and bonding design can offer an additional pathway to promote heat spreading away from active regions and reduce the thermal resistance. SUMMARY OF VARIOUS ASPECTS AND EXAMPLES Various examples / embodiments presented by the present disclosure are directed to issues such as those addressed above and / or others which may become apparent from the following disclosure (“present disclosure”). For example, certain aspects of the present disclosure are directed to apparatuses and methods involving thermally-conductive dielectric substrate, being proximal active region(s) of a semiconductor die, including a three- dimensional distribution (e.g., as a matrix or network) of pathways of electrically conductive pathways that electrically connect or couple to circuitry in the die (e.g., connecting through contacts along the substrate-facing die surface and thermal pathways (aka vias) that conduct and disperse heat from the active regions through the bulk of the substrate and away from the active region. In one specific example embodiment, the present disclosure is directed to an apparatus which includes a substrate, characterized as predominantly including thermally conductive materials (e.g., highly thermal conductive such as by using diamond and / or AlN), that is in proximity to an active region of an integrated circuit (IC) of a semiconductor device. The substrate includes a matrix of pathways that conduct electricity between the active region of the IC and the sides of the substrate, further including thermal vias that conduct and disperse heat through the bulk of the substrate and away from the active region. In other example embodiments, the present disclosure is directed to a method involving use of a semiconductor device that include an integrated-circuit (IC) die. The method includes at least the following steps or actions: causing heat to be generated at one or more active regions of the IC die adjacent a substrate, secured to the IC die, that predominantly includes one or more highly thermally-conductive materials, and to be drawn into thermally-conductive dielectric vias of a matrix of pathways spread throughout a portion of the substrate that is secured to the IC die, wherein the matrix of pathways includes electrically-conductive routing paths and the thermally-conductive dielectric vias; and passing electricity through the electrically-conductive routing paths for the IC die (e.g., such STFD.465PCT (S24-245) 3      as between contacts of the IC die and locations located along at least one external surface of the substrate). In certain other examples which may also build on the above-discussed aspects, such apparatuses (e.g., the above-characterized devices) include additional sections to form a double-sided integrated package that includes the substrate and the IC die. In this context, a double-sided package substrate permits scaling down and improving communication between dies (e.g., between chiplets), and permits use of through-substrate conductive vias. The additional sections include: a thermally-conductive dielectric layer that is integrated with and on a side of the substrate that faces away from the inner facing side, another IC die including a substrate-facing and, adjacent to or along the inner side, an active region and die contacts, and another substrate. The other substrate is situated between the other IC die and the thermally-conductive dielectric layer, and its material composition consists predominantly of a set of one or more highly thermal- conductive materials. The other substrate also includes a matrix of pathways, spread throughout the other substrate, including routing paths to conduct electricity to and / or from the die contacts and including thermally-conductive dielectric vias to direct heat away from the active region(s) of the other (more-proximal) IC die. In more specific examples related to, and / or useful as aspects for building onto, the above methodology and / or devices, the semiconductor device includes a plurality of IC dies and a plurality of similarly-characterized substrates (e.g., each as characterized above). For example, a first IC die is secured to a first substrate (as in the above examples), and the semiconductor device also includes a second IC die secured to a second substrate (as in a stack), with the first and second substrates being on the inside and the IC dies being on the outside. In certain other application-specific and / or experimental example embodiments, the present disclosure is directed to a substrate design to address the thermal issues discussed above, by use of a substrate material or structure in sufficient proximity to the die surface(s) to draw heat from the active regions into the substrate, wherein the material composition of the substrate is one or more highly thermally-conductive materials such as AlN, diamond, or their composites. The substrate material set is deposited near the surface of the substrate in a matrix with low-k dielectrics for interconnect routing, and with fan-out and through-substrate design which may be implemented using stacked layers. Thermal vias may be included (e.g., added) in dense current flow areas to dissipate heat into the substrate. STFD.465PCT (S24-245) 4      Advantageously and also in with the present disclosure, another important aspect of this substrate technology involves the integration and specialized growth technique of thermally conductive material, such as afforded by use of AlN and / or diamond. The above discussion is not intended to describe each aspect, embodiment or every implementation of the present disclosure. The figures and detailed description that follow also exemplify various embodiments.

[0002] STFD.465PCT (S24-245) 5      BRIEF OF FIGURES Various example embodiments, including experimental examples, may be more completely understood in consideration of the following detailed description in connection with the accompanying drawings, each in accordance with the present disclosure, in which: FIG.1A illustrates a packaged substrate structure according to certain exemplary aspects of the present disclosure; FIG.1B is a side view of another packaged substrate structure according to certain exemplary aspects of the present disclosure; FIGs.2A-2E show aspects of diamond used in the substrate structure that is shown in FIG.1B, also according to certain exemplary aspects of the present disclosure, wherein FIG.2A is an example of the relationship between diamond thickness and thermal conductivity, and FIGs.2B - 2E are cross-sectional and top-view SEM images showing different isotropic diamond layers of varying thicknesses which are 7 µm (FIG.2B), 12 µm (FIG.2c), 23 µm (FIG.2D) and 23 µm (FIG.2e); FIGs.3A-3H show aspects for a chip (SRAM), also according to certain exemplary aspects of the present disclosure, wherein: FIG.3A is an example layout or floorplan, FIG.3B is a side view of the chip showing a stacked systolic array and SRAM blocks in the particular example of FIG.3A, FIG.3C is a bar graph showing lateral thermal conductivity yields for the particular example of FIG.3A, FIGs.3D and 3G are tables showing material properties used for thermal simulation for the particular example of FIG. 3A, FIG.3E is an example flip-chip configuration consistent with aspects shown in FIG.3A, FIG.3F is a sideview also consistent with aspects shown in FIG.3A and also showing backside power delivery, and FIG.3H is another bar graph showing benefits of diamond heat spreading in both scenarios leading to roughly 10 K (20%) reduction in temperature rise; and FIG.4 is a partial cross-section schematic of the design, according to certain exemplary aspects of the present disclosure, which shows the heat removal path through misaligned interlevel diamond vias assisted by diamond interlayers. While various embodiments discussed herein are amenable to modifications and alternative forms, aspects thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure including aspects defined in the claims. In addition, the term “example” as used throughout this application is only by way of illustration, and not limitation. STFD.465PCT (S24-245) 6      Aspects of the present disclosure are believed to be applicable to a variety of different types of apparatuses, systems and methods involving devices characterized at least in part by a thermally-conductive dielectric substrate, being proximal active region(s) of a semiconductor (IC) die, including a three-dimensional distribution (e.g., as a matrix) of pathways of electrically conductive pathways connecting to die contacts and thermal pathways (aka vias) that conduct and disperse heat from the active regions through the bulk of the substrate and away from the active region. While the present disclosure is not necessarily limited to such aspects, an understanding of specific examples in the following description may be understood from discussion in such specific contexts. In certain specific example embodiments, the present disclosure is directed to methods and / or apparatuses (e.g., systems, semiconductor devices, chips, etc.) involving a matrix of pathways that conduct electricity between the active region of the IC and the sides of the substrate, further including thermal vias that conduct and disperse heat through the bulk of the substrate and away from the active region. Accordingly, in the following description various specific details are set forth to describe specific examples presented herein. It should be apparent to one skilled in the art, however, that one or more other examples and / or variations of these examples may be practiced without all the specific details given below. In other instances, well-known features have not been described in detail so as not to obscure the description of the examples herein. For ease of illustration, the same connotation and / or reference numerals may be used in different diagrams to refer to the same elements or additional instances of the same element. Also, although aspects and features may in some cases be described in individual figures, it will be appreciated that features from one figure or embodiment can be combined with features of another figure or embodiment even though the combination is not explicitly shown or explicitly described as a combination. Consistent with the above aspects, such a manufactured device or method of such manufacture may involve aspects presented and claimed in U.S. Provisional Application Serial No.63 / 668,700 filed on July 8, 2024 (STFD.465P1 / S24-245) with an Appendix, to which priority is claimed and in which common aspects are disclosed as should be apparent even if different terminology is used (e.g., in the present disclosure and in the U.S. Provisional Application, contacts may be referred to as die contacts, IC die contacts, and solder bumps). To the extent permitted, such subject matter is incorporated by reference in its STFD.465PCT (S24-245) 7      entirety generally and to the extent that aspects and examples (such as experimental and / more-detailed embodiments) may be useful to supplement and / or clarify. Consistent with the present disclosure, such devices and / or methods may be used for producing (among other examples) more complex integrated circuits. In one such example, there are multiple of the IC dies and multiple of the substrates. Each of the substrates includes one or more highly thermal-conductive materials and a matrix or three- dimensional network of pathways such as described in the one or more above embodiments. Additionally, a heat sink is thermally coupled to a side of one of the IC dies that is opposite the inner-facing side. This embodiment further includes a highly thermal-conductive material layer, predominantly composed of diamond and / or AlN. Multiple electrically-conductive arteries run through the material layer to connect the respective circuitries of the IC dies. A dielectric silicon-based layer is located between the highly thermal-conductive material layer and each of the substrates. This dielectric layer includes extensions of the electrically- conductive arteries and further thermally-conductive dielectric vias to pass the heat into the thermally-conductive material layer. As noted above, certain exemplary aspects of the present disclosure involve methodology and structures directed to use of a matrix of highly thermal-conductive pathways and electrically conductive routing pathways spread throughout a portion of a substrate. FIG.1A illustrates a specific type of example embodiment according to the present disclosure, in which such a substrate 100 has a matrix of pathways, which include thermal vias 111 used to draw heat away from hot spots 101 (generated at active regions) within the die 102, and draw heat into the substrate 100 and away from the hot spots 101, and ideally, eventually out of the substrate by exposed sidewall portions of the substrate 100 and at the ends of the thermal vias 111. The matrix of pathways also includes electrical conductors 110 for passing connections (e.g., signal and / or power conductors) from die contacts 103 at a substrate-facing side of the die (e.g., to one or more external surfaces of the substrate and / or another contacts along the same substrate-facing side of the die). The dashed lines in FIG.1A are used to identify aspects that would not typically be included in more general examples of the present disclosure but, rather, are associated with specific examples and aspects that would be more-commonly present in specific applications. For one example associated with the dashed lines, another substrate 100” may be secured to another region of the die 102 such as along another surface of the die 102 or, as depicted in FIG.1A, along the same surface at which the substrate 100 is attached. In one example, the die 102 may include one section over the substrate 100” which includes high- STFD.465PCT (S24-245) 8      power fast-switching FET-type circuits that significantly more heat than the other portions of the die 102, and for this example the substrate 100” may be composed of one or more materials that have a higher thermal conductivity rating (e.g., all diamond) than one or more materials used to implement the thermal vias 111. As another example associated with the dashed lines, a thermal field plate 104 may be used to facilitate transfer of large amounts of heat away from the die 102 (e.g., as shown between the die 102 and the adjacent substrate 100”. Similarly, a thermally conductive lateral field plate 105 (or section as in FIG.1A) may be located between the substrate 100 and the adjacent substrate 100” and also used to facilitate transfer of large amounts of heat away from the die 102, through the substrate 100. As with the above example involving the high-power fast-switching FET-type circuits, one or both plates may be implemented using material(s) having a higher thermal conductivity rating than used elsewhere (e.g., in the thermal vias 111 and / or the material in the substrate surrounding the thermal vias 111). This type of approach permits for individual ones of such thermal conductive elements to be manufactured separately and implemented in selective stages of the IC packaging process. In specific methods of manufacturing examples, also consistent with the present disclosure, such approaches facilitate assembly and save costs by permitting for some of the thermally- conductive elements to be manufactured without diamond which can reduce expenses considerably; in certain examples, little if any diamond is used with the substrate and / or thermal vias being composed at least primarily of one or a combination from: SiC (crystalline and amorphous), AlN (crystalline and polycrystalline), Boron Nitride, and Graphene. In further specific examples which build on the above-discussed aspects, the diamond material and / or such other thermally-conductive elements (e.g., the thermal field plate 104) may have particular characteristics as appropriate for a given application. For example, the IC die 102 may have a thickness greater than a thickness of the substrate 100, and the polycrystalline-grown diamond may be characterized by an average diamond grain width dimension which is closer to the average thickness dimension than to twice an average diamond grain thickness dimension. In experimental implementations consistent with the structure of FIG.1A, efforts in connection with the present disclosure have realized a thermally managed package substrate that lowers the hot spot thermal resistance in the die area by at least factor of two and reduces the temperature in the substrate generated from high density interconnects carrying high current densities. This approach first consists of shifting towards replacing the bulk of traditional glass or silicon substrates through use of thermally conductive STFD.465PCT (S24-245) 9      semiconductor material in the substrate(s) as AlN, diamond, or their composites. Such thermally conductive materials, as implemented in a matrix (e.g., 3D network of pathways), may use low-k dielectrics in the region near the surface of the substrate as may be needed for interconnect signal / power routing may be implemented, and this signal / power routing may be implemented both in a fan-out and through-substrate design (e.g., fanning out laterally along a plane parallel to an interfacial surface where the die is secured to the substrate) and vertically (or orthogonally relative to such a plane). In these regions where there is extremely dense current flow, thermal vias may be added to dissipate heat into the bulk of the thermally conductive matrix-based substrate. FIG.1B is a side-view schematic of another IC die structure for a package including a plurality of dies (e.g., 102’ and 102”), according to the present disclosure. In this example, more than half of the substrate is all diamond or an AlN / diamond composite, with copper through-substrate vias (CTSVs) connecting the chips on both sides of the package substrate, wherein diamond through silicon vias (DTSVs) are used to lower the overall thermal resistance, and polycrystalline diamond is grown between the two bonded wafers. The dimensions of the DTSVs, in certain experimental examples, vary between 10 µm and 100 µm depending on the thermal budget. Such efforts in connection with these experimental examples have shown the temperature of the hot spots can be dropped 20-50% when using diamond thermal dielectric (with further benefits by growing more isotropic diamond grains as shown in FIGs.2B-2E, wherein the average grain width dimension and the average thickness dimension characterize the polycrystalline-diamond grains as being more isotropic than columnar. The illustrated structure includes matrix-based substrates 200 and 200’ secured therein to (e.g., bonded by) silicon-based wafers 201, and with an AlN or diamond layer 202 between them. Each of the plurality of IC dies 102’ is bonded to each of the substrates via contacts 103’ (depicted as solder bumps in FIG.1B). Each of the matrix-based substrates 200 and 200’ is a three-dimensional network of electrically conductive pathways and (e.g., highly) thermal conductive pathways is routed from the contacts 103’ of each die 102’ through each of the substrates, as described in the one or more above embodiments. Certain specific experimental embodiments have realized impressive thermal conductivity targets. For example, with 50-100% of the Si substrate being replaced by AlN / Diamond or all-Diamond (TCdiamond= 2200 W / m / K) composite substrate, using highly thermally-conductive dielectric (e.g., including a set of one or more materials characterized as being thermally conductive with a lower limit of 20 w / m / k), and using the two thinned Si STFD.465PCT (S24-245) 10      wafers bonded on both sides of the substrate (or polycrystalline diamond being grown between the two Si substrates), the target thermal conductivity of the composite substrate is between 1500-2200 W / m / K, which is ~10 times higher than the Si substrate (TCSi: 130-150 W / m / K). More specifically, the structure depicted in FIG.1B may be viewed and / or manufactured as a stack of layers, with each of the layers secured to the nearest adjacent layer. In this example, these layers, from top and bottom to the center of the stack, are: upper heat sink and lower heat sink, upper die 102’ and lower die 102”, upper substrate 200 and lower substrate 200’ (each being matrix-based – meaning including a matrix of pathways), upper Si-based wafer 201 and lower silicon-based wafers 201’, and with a thick thermal conductive spacer (e.g., highly thermally conductive such as AlN and / or diamond) separating the Si-based wafers 201 and 201’. As exemplified in FIGs.1A and 1B, apostrophes or quotation marks after common numerals denote a similarly-constructed element, such as 102, 102’ and 102”. In the example embodiment of FIG.1B, electrically conductive pathways may be implemented as copper-through-substrate vias 110’ (CSTVs) and may be developed by etching both Si and composite substrates, followed by Cu electroplating to connect the IC dies 102’ on both sides of the package substrate. The highly thermally-conductive pathways in this embodiment, are depicted in FIG.1B as AlN / Diamond Interlayer Thermal Vias 111’ (DTSVs), and are used to lower the Si substrate overall thermal resistance and connect the composite substrate to diamond interlayer dielectrics and vias with a lower thermal resistance. In many specific examples, the dimensions of DTSVs may vary between 10 µm and 100 µm depending on the thermal budget. FIG.2A is a chart depicting thermal conductivity (W / m / K) relative to material thickness (µm). The chart illustrates a comparison of diamond as implemented in the illustrated device to that of other diamond works and different competing material options for heat spreading. The chart shows that the thermal conductivity of diamond can be enhanced one order of magnitude by growing more isotropic diamond grains. FIGs.2B-2E are cross-sectional and top-view SEM images showing different isotropic diamond layers of varying thicknesses. FIG.2B shows a layer with a thickness of 7 µm, and FIG.2C shows a layer with a thickness of 12 µm. FIG.2D shows only the cross- sectional view of a diamond layer with a thickness of 23 µm, and FIG.2C shows a top-view of the same diamond layer thickness of 23 µm. STFD.465PCT (S24-245) 11      FIGs.3A-3H show aspects for (SRAM), also according to certain exemplary aspects of the present disclosure. FIG.3A is an example layout or floorplan for this chip. More particularly, FIG.3B is a side view of the chip showing a stacked systolic array and SRAM blocks in the example of FIG.3A, wherein diamond dielectric is used in the conductor (power pathways) delivery network on each tier. FIG.3C is a bar graph showing lateral thermal conductivity yields for the particular example of FIG.3A. As indicated in FIG.3C, inclusion of diamond with excellent lateral thermal conductivity yields 3.4x reduction in temperature rise. FIGs.3D and 3G are tables showing material properties used for thermal simulation for the particular example of FIG.3A. FIG.3E is an example flip-chip configuration consistent with aspects shown in FIG.3A, wherein the flip-chip configuration uses 2 μm diamond integrated into the power delivery network. The top tier in FIG.3E has a 200x200 μm2200 W / cm2hotspot, while the rest of the chip dissipates 50 W / cm2. FIGs.3F-3H illustrate further benefits of above-disclosed aspects of the present disclosure. FIG.3F is a sideview of a chip also consistent with aspects shown in FIG.3A and also showing backside power delivery. With diamond integrated into the backside power delivery network, there is a 200x200 μm2200 W / cm2hotspot, while the rest of the chip dissipates 50 W / cm2. FIG.3H is another bar graph showing benefits of diamond heat spreading in both scenarios leading to roughly 10 K (20%) reduction in temperature rise. For the signal / power routings, a mixture of diamond interlayers and current technology low dielectric constant porous SiCOH is used. Diamond interlayers replace 10- 30% of the interlayer dielectric (ILD), which enhances heat spreading laterally from the interconnects (wires) due to their high in-plane TC of 100-1000 W / m / K. The ILD layer can be implemented by using a low dielectric constant (2-3) diamond therein after the development of porous diamond. Adding air gaps into the diamond structure can reduce the dielectric constant to values as low as 2-3 at the cost of lowering its TC (however, compared with recent developments of ILD TC measurements, the porous diamond TC is >500x larger). In further more-specific examples related to and / or building on the above- discussed examples, the matrix is completed by using diamond-type interlevel vias between diamond interlayers to remove the heat generated in the die area and to spread the heat generated by the interconnects. The diamond thermal vias between the two tiers do not need to be precisely aligned as the diamond interlayer provides lateral heat transport as shown in FIG.4. STFD.465PCT (S24-245) 12      The interfaces between Si or and diamond can be engineered to lower the thermal boundary resistance. It has been previously shown (published by one or more inventors of the present disclosure) that by using a proper dielectric (e.g., a thin thermal field plate as in FIG.1A) between diamond and Si, the TBR can be reduced to below 3 m2K / GW, thereby approaching theoretical prediction. This technology approach can be used for the thermally managed package substrate at the interfaces between Die / diamond, Cu / diamond, SiCOH / diamond, and Si / diamond. FIG.4 is a partial cross-section schematic of an embodiment of the device, which shows heat being removed from the hot spot 101’ and dispersing through the substrate along the heat removal path 403. The diamond interlevel vias 111’ (thermal vias) are used between diamond interlayers 410 to remove the heat generated in the hot spots 101’, and to spread the heat carried into and / or through the matrix of thermal vias and electrically conductive pathways, and in some examples, also interconnects (the latter not shown in FIG.4). Thermal issues caused by any non-alignment of the thermal vias (from one stacked layer to the next) may be mitigated by using the thermal vias 111’ between diamond interlayers 410, thereby providing lateral heat transport as shown by the heat removal path 403. In certain of the above-noted experimental examples, certain design metrics were used. These metrics include the following examples. (i) Through substrate via diameter: Using deep RIE through substrate trenches is made and is filled with copper electroplating for substrate thicknesses between 200-600 µm. The maximum diameter is set to 100 µm to meet the target. (ii) Max number of Layers (hierarchical): 3+3, to 15+15 layers for both glass / composite / glass and Si / composite / Si substrates is used. (iii) Effective CTE of the multilayer stack: since composite diamond-based substrates are being used, the effective CTE drops significantly compared to Si or glass substrates (CTEdiamond: 1.1 ppm), which provides more room for increasing the number of layers and adding materials with higher CTEs. Through these efforts, the thermal residual stress in the diamond layer after growth on GaN and Si substrates has been measured and verified as being mitigated. (iv) Max substrate size: the size of the package substrate can be extended to 8”. (v) Maximum thickness: The overall thickness includes 2x Si wafers (10-100 µm), composite substrate (200-400 µm), and signal and power routing layers (200-400 µm). Accordingly, many different types of processes and devices using such aspects of the present disclosure may be advantaged in terms of a compact and / or densified IC-based design and also importantly, with appropriate thermal relief for proper operation of the circuitries inside the die(s). STFD.465PCT (S24-245) 13      It is recognized and appreciated as specific examples, the above- characterized figures and discussion are provided to help illustrate certain aspects (and advantages in some instances) which may be used in the manufacture of such structures and devices. These structures and devices include the exemplary structures and devices described in connection with each of the figures as well as other devices, as each such described embodiment has one or more related aspects which may be modified and / or combined with the other such devices and examples as described hereinabove may also be found in the Appendix of the above-referenced Provisional. The skilled artisan would also recognize various terminology as used in the present disclosure by way of their plain meaning. As examples, the Specification may describe and / or illustrate aspects useful for implementing the examples by way of various semiconductor materials / circuits which may be illustrated as or using terms such as layers, blocks, modules, device, system, unit, controller, and / or other circuit-type depictions. Also, in connection with such descriptions, such semiconductor and / or semiconductive materials (including portions of semiconductor structure) and circuit elements and / or related circuitry may be used together with other elements to exemplify how certain examples may be carried out in the form or structures, steps, functions, operations, activities, etc. It would also be appreciated that terms to exemplify orientation, such as upper / lower, left / right, top / bottom and above / below, may be used herein to refer to relative positions of elements as shown in the figures. It should be understood that the terminology is used for notational convenience only and that in actual use the disclosed structures may be oriented differently from the orientation shown in the figures. As other examples, reference to a noun in the singular refers to one from among one or more of, unless otherwise indicated (e.g., “an element” in various contexts is the same as referring to “at least one element”), and reference to “example” is not intended to be limiting (e.g., “example” and “non-limiting example” are synonymous). Also, forms of the words “include” and “comprise” are synonymous with one another. Such aspects and circuit elements and / or related circuitry may be used together with other aspects to exemplify how certain examples may be carried out in the form or structures, steps, functions, operations, activities, etc. It should be understood that the terminology is used for notational convenience only and that in actual use the disclosed structures may be oriented and / or ordered different from the orientation or ordering shown in the figures. Thus, the terms should not be construed in a limiting manner. Based upon the above discussion and illustrations, those skilled in the art will readily recognize that various modifications and changes may be made to the various STFD.465PCT (S24-245) 14      embodiments without strictly following the embodiments and applications illustrated and described herein. For example, methods as exemplified in the Figures may involve steps carried out in various orders, with one or more aspects of the embodiments herein retained, or may involve fewer or more steps. Such modifications do not depart from the true spirit and scope of various aspects of the disclosure, including aspects set forth in the claims.

Claims

STFD.465PCT (S24-245) 15      What is Claimed:

1. A semiconductor device comprising: an integrated-circuit (IC) die including one or more active regions and including die contacts located along an inner-facing side of the IC die; a substrate, secured to the inner-facing side of the IC die, including one or more highly thermally conductive materials and including a matrix of pathways spread throughout a portion of the substrate that is secured to the IC die; and the matrix of pathways including electrically-conductive routing paths to pass electricity between the IC die and through the substrate to selected locations of at least one external surface of the substrate, and thermally-conductive dielectric vias to draw heat from the inner-facing side of the one or more active regions, into the thermally-conductive dielectric vias and out of the substrate.

2. The semiconductor device of claim 1, wherein the thermally-conductive dielectric vias are: composed of one or more highly-thermal conductive materials, at least one of which includes diamond; and formed as a plurality of dielectric layers.

3. The semiconductor device of claim 2, wherein the plurality of dielectric layers include a plurality of successively-stacked layers, each including one or more respective ones of the thermally-conductive dielectric vias, and wherein the one or more respective ones of the thermally-conductive dielectric are not aligned for passing the heat successively among the successively-stacked layers.

4. The semiconductor device of claim 1, wherein the thermally-conductive dielectric vias include interlevel thermal vias, each including at least one of AlN and diamond, extending from one level of the substrate, that is proximal to the IC die, to another level of the substrate that is distal to the IC die.

5. The semiconductor device of claim 1, further including diamond, in each of the thermally-conductive dielectric vias, to facilitate thermal conductivity of the substrate.STFD.465PCT (S24-245) 16      6. The semiconductor device of claim the thermally-conductive dielectric vias refer to or include a set of one or more materials characterized as being highly-thermally conductive with a lower limit of 20 w / m / k, and the one or more materials being from the following: diamond, SiC (crystalline and amorphous), AlN (crystalline and polycrystalline), Boron Nitride, and Graphene.

7. The semiconductor device of claim 1, wherein the substrate is not predominantly composed of glass, silicon, or a combination of glass and silicon.

8. The semiconductor device of claim 1, wherein the electrically-conductive routing paths are to conduct electricity in the form of at least one of: electrical signals to connect with circuits in the IC die, and operating power to operate circuits in the IC die and cause the one or more active regions to generate heat.

9. The semiconductor device of claim 1, wherein the substrate includes a layer of polycrystalline-diamond grains with an average grain width dimension in a range from 100 nm to 10 microns and an average thickness dimension in a range from 100 nm to 10 microns, wherein the average grain width dimension and the average thickness dimension characterize the polycrystalline-diamond grains as being more isotropic than columnar.

10. The semiconductor device of claim 1, further including a thermal field plate that has an average thickness greater than an average thickness of the substrate and that is composed of one or more materials dominated by at least one of: polycrystalline-grown diamond and AlN.

11. The semiconductor device of claim 1, further including a thermal field plate, located adjacent to the substrate on a side opposite of the IC die or a side orthogonal to the IC die, having a thickness greater than a thickness of the substrate and having polycrystalline-grown diamond characterized by an average diamond grain width dimension which is closer to the average thickness dimension than to twice an average diamond grain thickness dimension.

12. The semiconductor device of claim 1, further including an interface layer, including Silicon, immediately adjacent and arranged opposite the inner facing side of the substrate.STFD.465PCT (S24-245) 17      13. The semiconductor device of claim the substrate is composed of one or more materials dominated by at least one of: polycrystalline-grown diamond and AlN.

14. The semiconductor device of claim 1, further including diamond in the substrate, wherein the diamond has a phase purity in a range from 90% to 99% and thermal conductivity in a range from 100 W / m / K up to 2000 W / m / K.

15. The semiconductor device of claim 1, wherein the one or more highly thermally- conductive materials includes diamond in areas of the substrate surrounding most of the matrix of pathways including the thermally conductive thermal vias.

16. The semiconductor device of claim 1, wherein the pathways of the matrix include pathways which are composed of copper and are to provide interconnection signal routing in directions corresponding to a fan-out design of the pathways.

17. The semiconductor device of claim 1, further including additional IC sections to form a double-sided integrated package that includes the substrate and the IC die, the additional sections including: a thermally-conductive dielectric layer that is integrated with and on a side of the substrate that faces away from the inner facing side, another IC die including an active region, die contacts and a substrate facing side, the substrate facing side facing the inner facing side, and another substrate, between the other IC die and the thermally-conductive dielectric layer, characterized as predominantly composed of one or more highly thermal-conductive materials and including a matrix of pathways, spread throughout the other substrate, the matrix of pathways including routing paths to conduct electricity and including thermal vias to direct heat away from the active region of the other IC die.

18. The semiconductor device of claim 1, wherein the IC die corresponds to a first of a plurality of IC dies, the substrate corresponds to a first of a plurality of the substrates, wherein each of the plurality of the substrates includes a respective set of one or more highly thermally-conductive materials and includes a respective matrix of pathways as recited for the first of the plurality of the substrates; andSTFD.465PCT (S24-245) 18      wherein the semiconductor device includes a heat sink thermally coupled to a side of one of the plurality of IC dies, located opposite to the inner-facing side, a highly thermally-conductive material layer, predominantly composed of at least one of diamond and AlN, including a plurality of electrically-conductive arteries to electrically connect respective circuitries of the plurality of IC dies, and a dielectric silicon-based layer, located between the highly thermally conductive material layer and the first of a plurality of the substrates, including further thermally-conductive dielectric vias to pass the heat into the highly thermal- conductive material layer and including extensions of the plurality of electrically- conductive arteries.

19. A semiconductor device for use with an integrated-circuit (IC) die, the semiconductor device comprising: a dielectric substrate including an inner-facing side to be directed towards the IC die, at least one external surface which faces away from the IC die, and a matrix of pathways, spread in three-dimensions of the substrate, including electrically-conductive routing paths to pass electricity between die contacts of the IC die and selected locations of the at least one external surface, and thermally-conductive dielectric vias, and a surrounding substrate portion surrounding at least the highly- conductive-thermal vias, and the thermally-conductive dielectric vias and the surrounding substrate portion being at least predominantly composed of one or more highly-thermal materials and being cooperatively arranged to direct heat away from active regions of the IC die, through the three-dimensions of the substrate, and towards the at least one external surface.STFD.465PCT (S24-245) 19      20. A method involving use of a device including an integrated-circuit (IC) die, the method comprising: causing heat to be generated at one or more active regions of the IC die adjacent a substrate that is secured to the IC die, that predominantly includes one or more highly thermal-conductive materials, and to be drawn into thermally-conductive dielectric vias of a matrix of pathways spread throughout a portion of the substrate that is secured to the IC die, wherein the matrix of pathways includes electrically-conductive routing paths and the thermally-conductive dielectric vias; and passing electricity through the electrically-conductive routing paths between IC die contacts of the IC die for connecting to circuitry that is part of or coupled to the semiconductor device.

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