Methods for die-to-wafer and wafer-to-wafer bonding

The method addresses precision and yield issues in die-to-wafer and wafer-to-wafer bonding by using alignment marks and optical metrology to correct overlay errors, enhancing precision and reducing voids for improved bonding efficiency.

WO2026015698A1PCT designated stage Publication Date: 2026-01-15BOARD OF RGT THE UNIV OF TEXAS SYST
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Patent Information

Application Number
PCT/US2025/037088
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-07-10
Filing Date
2025-07-10
Publication Date
2026-01-15

AI Technical Summary

Technical Problem

Current die-to-wafer and wafer-to-wafer bonding techniques face challenges with high-speed, sub-micron accuracy placement, overlay accuracy, voids, non-uniform bonding, and high complexity, leading to limited yield and increased costs.

Method used

A method for bonding substrates using alignment marks to determine bonding overlay errors and implement corrections during the bonding process, utilizing in-situ optical alignment moire metrology and fluid drop evaporation control for precise alignment.

Benefits of technology

Enhances bonding yield and throughput by achieving sub-nanometer precision and reducing voids and non-uniform bonding, thereby improving the efficiency and reliability of die-to-wafer and wafer-to-wafer bonding processes.

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Abstract

A method for bonding a first substrate to a second substrate, where the first substrate has a set of alignment marks, and the second substrate has a set of complementary alignment marks. The set of alignment marks on the first substrate and the set of complementary alignment marks on the second substrate are utilized to determine a bonding overlay error between the first and second substrates prior to bonding. Corrections are then implemented during bonding of the first substrate to the second substrate based on the determined bonding overlay error.
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Description

METHODS FOR DIE-TO-WAFER AND WAFER-TO-WAFER BONDINGCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 669,620 entitled “Methods for D2W and W2W Bonding,” filed on July 10, 2024, which is incorporated by reference herein in its entirety.TECHNICAL FIELD

[0002] The present disclosure relates generally to die-to-wafer and wafer-to-wafer bonding, and more particularly to process control techniques for die-to-wafer and wafer-to-wafer bonding with high bonding yield.BACKGROUND

[0003] Die-to-wafer bonding (D2W) is a technique where individual dies (silicon chips) are bonded to a substrate wafer. This process is used to create multi-chip modules or integrate different die functionalities onto a single substrate. It is a crucial technology in enabling nextgeneration high-performance computing and memory systems.

[0004] Wafer-to-wafer (W2W) bonding is a technique used in microfabrication to permanently join two or more wafers together thereby creating a single, larger structure with enhanced functionality or performance. This process is crucial for applications, such as 3D integration, MEMS, and SOI (Silicon on Insulator) wafers. It allows for the stacking of multiple chips or the creation of complex devices with high interconnect density.

[0005] Both die-to-wafer (D2W) and wafer-to-wafer (W2W) bonding have unique challenges. D2W faces issues with high-speed, sub-micron accuracy placement, and multi-die handling. W2W struggles with overlay accuracy, wafer stress, and the need for identical die sizes. Additionally, both methods can suffer from voids, non-uniform bonding, and difficulties with cleaning and surface preparation.

[0006] Some deficiencies involving D2W bonding include requiring precise and rapid placement of individual dies onto a wafer, which can be challenging to achieve with sub-micron accuracy, especially at high throughput. In another example, D2W processes must accommodate varying die sizes and potentially multiple dies on a single package, requiring flexible and adaptableequipment. In a further example, D2W involves thin dies (e.g., below 50 pm), which can be prone to cracking or damage during the pick-and-placc process. In another example, incomplete cleaning of the die backside after dicing can lead to voids or bonding defects. In a further example, maintaining strong bonds and reliable interconnects (especially at fine pitches) between the die and wafer is crucial, and can be affected by surface cleanliness and other factors. In another example, die-to-wafer bonding often requires extreme alignment accuracy, and variations in the die size and shape can impact the overall yield.

[0007] Examples of W2W bonding deficiencies include overlay accuracy. Precise overlay alignment between the two wafers is critical for proper interconnect formation and can be affected by wafer thickness variations and surface roughness. In another example, the bonding process can introduce stress into the wafers, potentially leading to warping or other issues, especially with larger wafers. In a further example, W2W bonding typically requires that the dies on both wafers are the same size, which can limit flexibility in chiplet integration. In another example, voids can occur at the bonding interface due to trapped air or contaminants, leading to reduced yield and potential reliability issues. In a further example, both wafers must have clean, flat surfaces for proper bonding. Contamination or surface imperfections can result in voids or weak bonds. In another example, variations in wafer edges can affect bonding uniformity and alignment, especially in the peripheral areas.

[0008] General deficiencies for both D2W and W2W include yield, cost, process complexity, and throughput. Both D2W and W2W bonding can experience yield losses due to various factors, including voids, alignment errors, and surface contamination. Furthermore, the equipment and materials required for both processes can be expensive, and the complexity of the processes can contribute to overall cost. Additionally, both D2W and W2W bonding involve multiple process steps, including cleaning, surface preparation, alignment, bonding, and potential annealing, which require careful control and expertise. Furthermore, achieving high throughput (the number of bonded wafers or die per unit time) is an ongoing challenge for both D2W and W2W.

[0009] Hence, there are numerous deficiencies and challenges to D2W and W2W bonding resulting in a limited yield. That is, die-to-wafer and wafer-to-wafer bonding using current process control techniques is deficient.SUMMARY

[0010] In one embodiment of the present disclosure, a method for bonding a first substrate to a second substrate, where the first substrate has a set of alignment marks, where the second substrate has a set of complementary alignment marks, the method comprises utilizing the set of alignment marks on the first substrate and the set of complementary alignment marks on the second substrate to determine a bonding overlay error between the first and second substrates prior to bonding. The method further comprises implementing corrections during bonding of the first substate to the second substrate based on the determined bonding overlay error.

[0011] The foregoing has outlined rather generally the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the present invention that follows may be better understood. Additional features and advantages of the present invention will be described hereinafter which may form the subject of the claims of the present invention.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A better understanding of the present invention can be obtained when the following detailed description is considered in conjunction with the following drawings, in which:

[0013] Figure 1 illustrates an exemplary image unit for in-situ optical alignment moire metrology for bonding of two substrates in accordance with an embodiment of the present disclosure;

[0014] Figures 2A-2C illustrate an exemplary imaging technique with one imaging unit per alignment mark with a coaxial light source for illumination in accordance with an embodiment of the present disclosure;

[0015] Figure 3 illustrates the static dual moire imaging technique in accordance with an embodiment of the present disclosure;

[0016] Figure 4 illustrates the scanning dual moire imaging technique in accordance with an embodiment of the present disclosure;

[0017] Figure 5 illustrates the static overhead moire imaging technique in accordance with an embodiment of the present disclosure;

[0018] Figure 6 illustrates the scanning overhead moire imaging technique in accordance with an embodiment of the present disclosure;

[0019] Figure 7 illustrates the off-axis moire imaging technique in accordance with an embodiment of the present disclosure;

[0020] Figure 8A illustrates the top view of the exemplary convergent moire imaging technique in accordance with an embodiment of the present disclosure;

[0021] Figure 8B illustrates the front view of the exemplary convergent moire imaging technique in accordance with an embodiment of the present disclosure;

[0022] Figure 9A illustrates the top view of an alternative exemplary convergent moire imaging technique in accordance with an embodiment of the present disclosure;

[0023] Figure 9B illustrates the front view of the alternative exemplary convergent moire imaging technique in accordance with an embodiment of the present disclosure;

[0024] Figures 10A-10D illustrate an exemplary mechanism for substrate bowing and bond wave control in accordance with an embodiment of the present disclosure;

[0025] Figure 11 illustrates an exemplary mechanism and structure for fluid drop evaporation control for in-liquid alignment using the shroud in accordance with an embodiment of the present disclosure;

[0026] Figures 12A-12B illustrate an exemplary mechanism for dispensed fluid evaporation control with heat exchangers in accordance with an embodiment of the present disclosure;

[0027] Figure 13 illustrates an exemplary mechanism for dispensing fluid for in-liquid alignment in accordance with an embodiment of the present disclosure;

[0028] Figures 14A-14B illustrate an exemplary mechanism for in-liquid alignment between the upper and lower substrates in accordance with an embodiment of the present disclosure;

[0029] Figure 15A illustrates an exemplary method of bonding dies on a wafer during the first pass in accordance with an embodiment of the present disclosure;

[0030] Figure 15B illustrates an exemplary method of bonding dies on a wafer during the second pass in accordance with an embodiment of the present disclosure;

[0031] Figure 16A illustrates the ZTT stage 2 being retracted, and in-liquid pads being actuated to establish contact with the dispensed fluid on the lower substrate during the second pass in accordance with an embodiment of the present disclosure;

[0032] Figure 16B illustrates the ZTT stage 2 being actuated for establishing contact between the top and bottom substrates and in-liquid pads being actuated to establish contact with the dispensed fluid on the previously bonded dies during the second pass in accordance with an embodiment of the present disclosure; and

[0033] Figures 17A-17B illustrate an exemplary mechanism for in-liquid alignment between the upper and lower substrates with in-liquid pads being rigidly attached to the ZTT stage 1 in accordance with an embodiment of the present disclosure.DETAILED DESCRIPTION

[0034] As stated above, die-to-wafer bonding (D2W) is a technique where individual dies (silicon chips) are bonded to a substrate wafer. This process is used to create multi-chip modules or integrate different die functionalities onto a single substrate. It is a crucial technology in enabling next-generation high-performance computing and memory systems.

[0035] Wafer-to-wafer (W2W) bonding is a technique used in microfabrication to permanently join two or more wafers together thereby creating a single, larger structure with enhanced functionality or performance. This process is crucial for applications, such as 3D integration, MEMS, and SOI (Silicon on Insulator) wafers. It allows for the stacking of multiple chips or the creation of complex devices with high interconnect density.

[0036] Both die-to-wafer (D2W) and wafer-to-wafer (W2W) bonding have unique challenges. D2W faces issues with high-speed, sub-micron accuracy placement, and multi-die handling. W2W struggles with overlay accuracy, wafer stress, and the need for identical die sizes. Additionally, both methods can suffer from voids, non-uniform bonding, and difficulties with cleaning and surface preparation.

[0037] Some deficiencies involving D2W bonding include requiring precise and rapid placement of individual dies onto a wafer, which can be challenging to achieve with sub-micron accuracy, especially at high throughput. In another example, D2W processes must accommodate varying die sizes and potentially multiple dies on a single package, requiring flexible and adaptable equipment. In a further example, D2W involves thin dies (e.g., below 50 pm), which can be prone to cracking or damage during the pick-and-place process. In another example, incomplete cleaning of the die backside after dicing can lead to voids or bonding defects. In a further example, maintaining strong bonds and reliable interconnects (especially at fine pitches) between the die and wafer is crucial, and can be affected by surface cleanliness and other factors. In another example, die-to-wafer bonding often requires extreme alignment accuracy, and variations in the die size and shape can impact the overall yield.

[0038] Examples of W2W bonding deficiencies include overlay accuracy. Precise overlay alignment between the two wafers is critical for proper interconnect formation and can be affected by wafer thickness variations and surface roughness. In another example, the bonding process can introduce stress into the wafers, potentially leading to warping or other issues, especially withlarger wafers. In a further example, W2W bonding typically requires that the dies on both wafers arc the same size, which can limit flexibility in chiplct integration. In another example, voids can occur at the bonding interface due to trapped air or contaminants, leading to reduced yield and potential reliability issues. In a further example, both wafers must have clean, flat surfaces for proper bonding. Contamination or surface imperfections can result in voids or weak bonds. In another example, variations in wafer edges can affect bonding uniformity and alignment, especially in the peripheral areas.

[0039] General deficiencies for both D2W and W2W include yield, cost, process complexity, and throughput. Both D2W and W2W bonding can experience yield losses due to various factors, including voids, alignment errors, and surface contamination. Furthermore, the equipment and materials required for both processes can be expensive, and the complexity of the processes can contribute to overall cost. Additionally, both D2W and W2W bonding involve multiple process steps, including cleaning, surface preparation, alignment, bonding, and potential annealing, which require careful control and expertise. Furthermore, achieving high throughput (the number of bonded wafers or die per unit time) is an ongoing challenge for both D2W and W2W.

[0040] Hence, there are numerous deficiencies and challenges to D2W and W2W bonding resulting in a limited yield. That is, die-to-wafer and wafer-to-wafer bonding using current process control techniques is deficient.

[0041] As discussed herein, process control techniques have been developed for die-to-wafer and wafer-to-wafer bonding with high bonding yield.

[0042] The following published references are incorporated by reference herein in their entirety.

[0043] International Publication No. WO / 2018 / 119451 entitled “Heterogeneous Integration of Components Onto Compact Devices Using Moire Based Metrology and Vacuum Based Pick-and- Place,” is incorporated by reference herein in its entirety.

[0044] International Publication No. WO / 2019 / 126769 entitled “Nanoscale-Aligned Three- Dimensional Stacked Integrated Circuit,” is incorporated by reference herein in its entirety.

[0045] International Publication No. WO / 2020 / 051410 entitled “Nanofabrication and Design Techniques for 3D ICS and Configurable ASICS,” is incorporated by reference herein in its entirety.

[0046] International Publication No. WO / 2022 / 212260 entitled “Processes and Applications for Catalyst Influenced Chemical Etching,” is incorporated by reference herein in its entirety.

[0047] International Publication No. WO / 2023 / 056068 entitled “Tool and Processes for Pick-and- Place Assembly,” is incorporated by reference herein in its entirety.

[0048] International Publication No. WO / 2023 / 056072 entitled “Tool and Processes for Pick-and- Place Assembly, is incorporated by reference herein in its entirety.

[0049] International Publication No. WO / 2023 / 137181 entitled “High-Precision Heterogeneous Integration,” is incorporated by reference herein in its entirety.

[0050] International Publication No. WO / 2024 / 182712 entitled “Designs of Nano-Precise Short Stroke Stages for Actuation,” is incorporated by reference herein in its entirety.

[0051] International Publication No. WO / 2024 / 249853 entitled “Area- Specific Cleaning Methods for Bonding Applications,” is incorporated by reference herein in its entirety.

[0052] International Publication No. WO / 2023 / 164251 entitled “Programmable Precision Etching,” is incorporated by reference herein in its entirety.

[0053] The following terms as used in the present disclosure have the following meanings.

[0054] D2W: Die to Wafer.

[0055] Multi D2W Bonding: D2W bonding, where more than one die is bonded onto a product substrate simultaneously or in short time intervals between each other (for instance, sub-1 seconds, sub-0.5, 0.2, 0.1, 0.05, 0.02, 0.01 second time intervals).

[0056] W2W: Wafer to Wafer.

[0057] RW: Reconstituted Wafer, where a reconstituted wafer contains only known good dies that have been diced, picked and placed, and bonded onto a carrier.

[0058] HB: Hybrid Bonding.

[0059] FB: Fusion Bonding.

[0060] Bonding: A method for attaching a substrate (wafer, silicon wafer, SiC, GaAs, GaN on Si, GaN, GaSb, CdTe, polymeric substrate, a III-V substrate, glass, SiOi, fused silica, a crystalline material, an amorphous material, tape, tape on frame, back-grinding tape), or a portion of asubstrate (die, chip, chiplet, dielet), to a second substrate or a portion of a substrate, where the attachment could be performed using one or more of the following methods: Cu-Cu hybrid bonding, hybrid bonding, oxide-oxide fusion bonding, BCB based bonding, SU-8 based bonding, adhesive bonding (where the adhesive could be a UV-curable adhesive, a UV-release adhesive, for instance: https: / / www.sekisui.co.jp / electronics / en / device / semicon / Fabrication / SELFA / , a light-to- heat-conversion LTHC adhesive, etc.), anodic bonding, eutectic bonding, thermal compression bonding (TCB), C4 bump bonding, indium bump bonding, glass frit bonding, etc.

[0061] Substrate: A substrate refers to a wafer or a portion of a wafer (die, chip, chiplet, dielet).

[0062] Source Substrate: The source substrate is the substrate that is either directly bonded to a product substrate or is the source for dies that are subsequently bonded to the product substrate. The source substrate could include one or more of the following: a wafer, a silicon wafer, a reconstituted wafer, a wafer comprised of SiC, GaAs, GaN on Si, GaN, GaSb, CdTe, polymeric substrate, a III-V substrate, glass, SiC>2, fused silica, a crystalline material, an amorphous material, tape, tape on frame, back-grinding tape, dies on a carrier, where the carrier could be one or more of the following: a tape, a tape on a frame, a glass wafer, a silicon wafer, etc.

[0063] Product Wafer: The product wafer is the substrate onto which bonding of a source substrate, or dies from a source substrate, is performed. The product wafer could include one or more of the following: a wafer, a silicon wafer, a reconstituted wafer, a wafer comprised of SiC, GaAs, GaN on Si, GaN, GaSb, CdTe, polymeric substrate, a III-V substrate, glass, SiCL, fused silica, a crystalline material, an amorphous material, tape, tape on frame, back-grinding tape, dies on a carrier, where the carrier could be one or more of the following: a tape, a tape on a frame, a glass wafer, a silicon wafer, etc. The product wafer, after having undergone bonding, could be used to create System-in-Package (SiPs) of one or more of the following types: stacked logic, logic-on-memory stack, logic-on-SRAM stack, logic-on-DRAM stack, SRAM memory, DRAM memory, flash memory, high bandwidth memory (HBM), imagers, photonics devices, augmented reality devices, biomedical devices, quantum computing devices, thermal management devices, RF devices, and power devices, which could further be utilized for applications including: high performance computing, consumer devices, mobile computing, edge computing, cloud Al, energy, defense, medicine, telecommunication, transport, and automotive applications.

[0064] Face-Up Orientation: Face-up orientation is the orientation in which the bonding surface of a substrate to be bonded (die or a wafer) faces away from the item in relation to which the faceup orientation is being defined (for instance, a carrier substrate or a product substrate). In one embodiment, the item is an equipment (for instance, a bonding equipment), in which case the faceup orientation is defined to be one where the bonding surface of the substrate of interest faces the upward direction.

[0065] Face-Down Orientation: Face-down orientation is the orientation in which the bonding surface of a substrate to be bonded (die or a wafer) faces towards the item in relation to which the face-down orientation is being defined (for instance, a earner substrate or a product substrate). In one embodiment, the item is an equipment (for instance, a bonding equipment), in which case the face-down orientation is defined to be one where the bonding surface of the substrate of interest faces the downward direction.

[0066] Chuck: The chuck is a system for holding a substrate (a die or a wafer) against the forces of gravity and / or acceleration and / or internal stresses in a substrate. Chucks can be fabricated out of one or more of the following materials; aluminum (with optionally a coating of alumina), steel, alumina (or sapphire), silicon carbide (which could be in amorphous or crystalline form), polymers (such as PTFE, polycarbonate, Delrin, PFA, etc.). The chuck could additionally be used to maintain stability of a mechanical nature (against vibration, distortion, slippage) or thermal nature (against high temperature excursions, and localized temperature hot-spots). Chucks can maintain contact with the chucked substrate using one or more of the following mechanisms: vacuum, electrostatic, electromagnetic, and mechanical clamping.

[0067] Bonding overlay error: This is the offset in alignment between the bond pads in a first substrate (e.g., die, wafer), and the corresponding bond pads in a second substrate (e.g., wafer), where the first and the second substrates are bonded to each other using the bond pads.

[0068] In one embodiment, the first substrate has a set of alignment marks and the second substrate has a set of complementary alignment marks. In one embodiment, the set of alignment marks on the first substrate and the set of complementary alignment marks on the second substrate are utilized to determine a bonding overlay error between the first and second substrates prior to bonding, in one embodiment, corrections are implemented during bonding of the first substate to the second substrate based on the determined bonding overlay error.

[0069] In one embodiment, one or more of the following components of the bonding overlay error arc determined: rigid body errors, magnification distortion, skew distortion, orthogonality distortion, trapezoidal distortion, and higher-order distortions than the prior distortions.

[0070] In one embodiment, the bonding overlay error is determined in one of the following times prior to bonding: 1 second prior to bonding, 10 seconds prior to bonding, 100 seconds prior to bonding, and 1,000 seconds prior to bonding.

[0071] In one embodiment, the bonding overlay error is utilized to correct bonding overlay errors in real-time by feeding back the bonding overlay error to a set of actuators.

[0072] In one embodiment, the bonding overlay error is utilized to correct bonding overlay errors in a fccd-forward manner.

[0073] Alignment marks: Patterned features in a substrate that can be utilized to measure the misalignment along one or more of the X, Y, and rotation axes between the mark in a first substrate and a complementary mark in a second substrate. Either optical or non-optical techniques can be utilized to determine the misalignment.

[0074] In one embodiment, a misalignment between the set of alignment marks on the first substrate and the set of complementary alignment marks on the second substrate is measured utilizing one or more of the following techniques: moire-based metrology, infrared metrology, in- situ metrology, off-axis metrology, diffraction gratings, lst-order diffraction, and 0th-order diffraction.

[0075] Overlay error and substrates proximity: In a bonded state, the proximity between a first substrate and a second substrate is defined to be zero. This is a state where the Z coordinate of bond pads on a first substrate coincides with the Z coordinate of complementary pads on the second substrate, and also where the X and Y coordinates of the prior bond pads are within a prespecified error (for instance, less than 200 nm, 1 pm, 10 pm, 100 pm, etc.). In one embodiment, overlay error measurement is performed prior to bonding between the two substrates in states of the following proximity: (1) the X and Y misalignment between the two substrates is less than 1 pm each, and the proximity in the Z direction is less than 1 pm, (2) the X and Y misalignment between the two substrates is less than 1 pm each, and the proximity in the Z direction is less than 10 pm, (3) the X and Y misalignment between the two substrates is less than 10 pm each, and theproximity in the Z direction is less than 100 pm, (4) and the X and Y misalignment between the two substrates is less than 500 mm, and the proximity in the Z direction is less than 2 mm.

[0076] Feedforward vs Feedback Control: In feedforward control, errors between a first substrate and the second substrate are determined ahead of time, and during the bonding, a suitable model is used to predict the error state during and after bonding, and a suitable correction mechanism is implemented. In feedback control, errors are determined as the bonding is taking place and corrections are implemented in real time during the bonding as the bonding is proceeding.

[0077] In one embodiment, a first substrate carries primary alignment marks and a second substrate carries complementary marks. The substrates are approached towards each other, where, in one case, a controlled gap of < 1 pm — preferably 10 nm - 500 nm — is established. Furthermore, the gap is created using an intermediary liquid between the first substrate and the second substrate, where the liquid is one of the following: aqueous solution, water, citric acid, an acid, a solution of water and an acid, hydrofluoric acid, and a fluorine-based acid.

[0078] In one embodiment, mark pair is illuminated using broadband IR or a narrowband diffraction source. In one embodiment, super-posed mark images are acquired via a microscope objective. In one embodiment, overlay vectors Ax, Ay and higher-order distortion coefficients (e.g., magnification, skew, orthogonality, trapezoidal, >3rd-order) are computed. In one embodiment, corrections are applied either (a) in real time — <1 s latency — via nano-positioning actuators beneath a substrate chuck, or (b) in a feed-forward table for the subsequent bonding. In one embodiment, overlay may be re-evaluated at programmable intervals (1 s, 10 s, 100 s, 1000 s) to track drift. In one embodiment, the intermediary liquid is de-ionized water, weak citric acid, or dilute HF, chosen to promote surface activation and gap uniformity.

[0079] It is noted that the method of the present disclosure is equally applicable to die-to-wafer bonding, and wafer-to- wafer bonding, where both stages receive coordinated commands.

[0080] Referring now to the Figures, Figure 1 illustrates an exemplary image unit 100 for in-situ optical alignment moire metrology for bonding of two substrates in accordance with an embodiment of the present disclosure.

[0081] As shown in Figure 1 , Figure 1 illustrates an exemplary image unit 100 for in-situ optical moire metrology with sub-1 nm measurement resolution for bonding applications. In one embodiment, exemplary image unit (also referred to as “imaging unit”) 100 includes a light source 101, and an imaging lens and sensor 102. Furthermore, Figures 1 illustrates an upper (top) substrate 103 consisting of grating patterns (alignment marks) 104, whereas, the lower (bottom) substrate 105 consists of complementary checkerboard patterns (alignment marks) 106. In one embodiment, when upper substrate 103 is overlaid with lower substrate 105, they form moire patterns, which are used to align the two substrates with each other to nanometer precision (example precision values could be sub- 10 nm with mean +3 sigma, sub-5 nm, sub-4 nm, sub-3 nm, sub-2 nm, sub-1 nm, sub-0.5 nm, sub-0.2 nm, sub-0.1 nm). It is noted that in Figure 1, the incident light from light source 101 is oriented such that the 1storder diffraction from the checkerboard pattern (see 106) on bottom substrate 105 is reflected normally towards imaging lens and sensor 102. Further details regarding the moire metrology (including moire mark architecture) is discussed in Moon, Euclid E., et al. "Interferometric-spatial-phase imaging for six-axis mask control," loumal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, Vol. 21, No. 6, 2023, pp. 3112-3115, which is incorporated by reference herein in its entirety.

[0082] Referring now to Figures 2A-2C, Figures 2A-2C illustrate an exemplary imaging technique with one imaging unit per alignment mark with a coaxial light source for illumination in accordance with an embodiment of the present disclosure.

[0083] As shown in Figure 2A, Figure 2A illustrates the top view 200 of a top substrate 103, which illustrates moire alignment marks 201.

[0084] Furthermore, as shown in Figure 2B, Figure 2B illustrates the top view 202 of imaging units 100 with coaxial illumination, which illustrates light source 101 and imaging lens and sensor 102 consisting of imaging lens 203 and imaging sensor 204.

[0085] Additionally, as shown in Figure 2C, Figure 2C illustrates the front view 205 of imaging units 100 with coaxial illumination, which illustrates Littrow angle 206.

[0086] Furthermore, as shown in Figures 2A-2C, in one embodiment, there are two or more moire alignment marks 201 on the top and bottom substrates 103, 105, and there is one imaging unit 100 per alignment mark 201. In one embodiment, imaging unit 100 has coaxial illumination, i.e., theaxes of coincident light and diffracted of light coincide. In one embodiment, imaging units 100 arc placed at a Littrow angle 206 (for the checkerboard gratings, as defined in the Moon reference above).

[0087] Referring to Figure 3, Figure 3 illustrates the static dual moire imaging technique in accordance with an embodiment of the present disclosure. In such a technique, the diffracted light 301 (reflected from reflective surface 302) from two moire marks 201 on the same edge of a die (such as the top substrate 103) is routed to an optical tubular arrangement which collects this diffracted light 301 and converges it to a single imaging lens 203 and camera (imaging sensor 204). In one embodiment, two or more imaging units 100 are used to gather the signal from moire marks 201 . In one embodiment, light source 101 is coaxial with the light routing optical tube 303. In one embodiment, light source 101 is non-coaxial. In one embodiment, imaging lens 203 and camera (imaging sensor 204) are placed at the Littrow angle 206 (where the light path 304 is of the back-diffracted light rays from the two moire marks that lie in a plane that is also at the Littrow angle 206 from a vector that points in the vertical direction).

[0088] Referring to Figure 4, Figure 4 illustrates the scanning dual moire imaging technique in accordance with an embodiment of the present disclosure. In such a technique, an imaging unit 100 moves back and forth between two moire alignment marks 201 on the same edge to get the signal from both moire marks. In one embodiment, light sources 101 are coaxial. In one embodiment, light sources 101 are non-coaxial. In one embodiment, light sources 101 are any combination of coaxial and non-coaxial. In one embodiment, there are two or more imaging units 100 used for moire alignment. In one embodiment, imaging units 100 are mounted on direct drive stages. In one embodiment, imaging units 100 are mounted on screw driven stages. In one embodiment, imaging units 100 are mounted on piezo-electric actuator driven stages. In one embodiment, imaging units 100 are mounted on pneumatically driven stages. In one embodiment, imaging units 100 are mounted on any combination of direct drive, screw drive, piezo-electric driven, and pneumatically driven stages.

[0089] Furthermore, Figure 4 illustrates the direction of motion 401 of imaging unit 100. Additionally, Figure 4 illustrates imaging unit 100 with a telecentric lens tube 402, which is a specialized optical lens designed to minimize or eliminate perspective distortion in images, making objects appear the same size regardless of their distance from the lens.

[0090] Referring now to Figure 5, Figure 5 illustrates the static overhead moire imaging technique in accordance with an embodiment of the present disclosure.

[0091] As shown in Figure 5, light source 101 is non-coaxial. In one embodiment, light source 101 is placed in such a way that the diffracted light coming from the moire marks 201 is directly normal to the surface of upper substrate 103. In one embodiment, two or more imaging units 100 are used for moire imaging.

[0092] Referring now to Figure 6, Figure 6 illustrates the scanning overhead moire imaging technique in accordance with an embodiment of the present disclosure. In such a technique, in one embodiment, light source 101 is non-coaxial and is placed in such a way that the diffracted light is normal to the surface of upper substrate 103. In one embodiment, one or more imaging units 100 move over a part or the entirety of the surface of upper substrate 103 to scan over the moire alignment marks 201. In one embodiment, imaging units 100 are mounted on direct drive stages. In one embodiment, imaging units 100 are mounted on screw driven stages. In one embodiment, imaging units 100 are mounted on piezo-electric actuator driven stages. In one embodiment, imaging units 100 are mounted on pneumatically driven stages. In one embodiment, imaging units 100 are mounted on any combination of direct drive, screw drive, piezo-electric driven, and pneumatically driven stages.

[0093] Figure 6 further illustrates the exemplary path 601 of the light from light source 101.

[0094] Referring now to Figure 7, Figure 7 illustrates the off-axis moire imaging technique in accordance with an embodiment of the present disclosure.

[0095] As shown in Figure 7, in one embodiment, light source 101 is coaxial. Furthermore, Figure 7 illustrates the incident light path 701 which includes incident light 702 being routed to the substrates by reflective surfaces 1 and 2 (703, 704). Additionally, Figure 7 illustrates the defracted light path 705, which includes the diffracted light 706 being routed back to imaging unit 100 by reflective surfaces 3 and 1 (707, 703). In one embodiment, light source 101 is non-coaxial. In one embodiment, two or more imaging units 100 are used for moire imaging. In one embodiment, light sources 101 are a combination of coaxial and non-coaxial.

[0096] Referring now to Figures 8A-8B, Figure 8A illustrates the top view of the exemplary convergent moire imaging technique in accordance with an embodiment of the present disclosure.Figure 8B illustrates the front view of the exemplary convergent moire imaging technique in accordance with an embodiment of the present disclosure.

[0097] As shown in Figures 8A-8B, in one embodiment, light source 101 is non-coaxial. In one embodiment, imaging unit 100 consists of one imaging sensor and imaging lens 102, but two or more light sources 101. In one emboidment, the diffracted light is routed to the imaging lens 203 through reflective surfaces 1, 2, and 3 (703, 704, 707). As a result, the diffracted light path from the substrates to the imaging lens 203 is divided into 4 segments (segment 1 801, segment 2 802, segment 3 803, and segment 4 804). Reflective surfaces 1 703 route the light towards reflective surfaces 2 704, and the reflective surfaces 2 704 route the light towards reflective surface 3 707. Reflective surface 3 707 gathers light from all directions and routes it to imaging lens 203. In one embodiment, light sources 101 are placed at such an angle that the diffracted light is normal to the surface of upper substrate 103.

[0098] Referring now to Figures 9A-9B, Figure 9A illustrates the top view of an alternative exemplary convergent moire imaging technique in accordance with an embodiment of the present disclosure. Figure 9B illustrates the front view of the alternative exemplary convergent moire imaging technique in accordance with an embodiment of the present disclosure.

[0099] As shown in Figures 9A-9B, in conjunction with Figure 7, in one embodiment, light source 101 is non-coaxial. In one embodiment, imaging unit 100 consists of one imaging sensor 204 and imaging lens 203 (collectively shown as 102), but two or more light sources 101. In one embodiment, the diffracted light is routed to imaging lens 203 through reflective surfaces 1 and 2 (703, 704). As a result, diffracted light path 705 from the substrates to imaging lens 203 is divided into 3 segments. Reflective surfaces 1 (703) route the light towards reflective surfaces 2 (704), which gathers light from all directions and routes it to imaging lens 203.

[0100] Referring now to Figures 10A- 10D, Figures 10A- 10D illustrate an exemplary mechanism for substrate bowing and bond wave control in accordance with an embodiment of the present disclosure.

[0101] As shown in Figure 10A, Figure 10A illustrates an actuatable pin 1001 of high co-efficient of thermal expansion (GTE) material that is actuated at some position between home and the end of the limit such that there is some bend in the substrate (chucked substrate 1002) as shown in Figure 10B.

[0102] Figure 10C illustrates actuatable pins 1001 actuated at the end of the limit such that there is a maximum bend in the substrate (chucked substrate 1002) as shown in Figure 10D.

[0103] In one embodiment, a chuck used to chuck a substrate (“chucked substrate”) 1002 has an outer vacuum zone 1003. Vacuum zone 1003 chucks the substrate (chucked substrate 1002) at all times. In one embodiment, the substrate chuck has an inner vacuum zone and pressure zone 1004. When chucked substrate 1002 is flat, inner zone 1004 functions as a vacuum zone. In one embodiment, when chucked substrate 1002 needs to be bent, inner zone 1004 becomes a pressure zone.

[0104] Furthermore, as illustrated in Figures 10A-10B, pins 1001 are actuated via an actuator 1006 thereby resulting in a mechanical displacement or actuation of pins 1001 corresponding to a pin stroke 1007.

[0105] In one embodiment, there are two or more actuatable pins 1001 located between inner vacuum zone 1004 and outer vacuum zone 1003 on the chuck. These actuatable pins 1001 are sub-flushed or flushed with the chuck-substrate interface such that the substrate (chucked substrate 1002) is flat. When the substrate (chucked substrate 1002) needs to be bent, these pins 1001 actuate beyond the chuck-substrate interface towards the substrate (chucked substrate 1002) so that the substrate (chucked substrate 1002) could bend in the center as shown in Figures 10C-10D.

[0106] As can be seen in Figures 10C-10D, variable actuation of pins 1001 can give variable bend profiles on the substrate (chucked substrate 1002), which can be used for point contact initialization as well as precise bond wave control. In one embodiment, actuator 1006 of actuatable pins 1001 is piezo-electric. In one embodiment, the actuation mechanism of actuatable pins 1001 is thermal.

[0107] In one embodiment, actuatable pins 1001 are made of a material with a co-efficient of thermal expansion (CTE).

[0108] Referring now to Figure 11, Figure 11 illustrates an exemplary mechanism and structure for fluid drop evaporation control for in-liquid alignment using the shroud in accordance with an embodiment of the present disclosure.

[0109] In particular, Figure 11 shows an exemplary mechanism for evaporation control of dispensed fluid drops 1101 on lower substrate 105 for in-liquid alignment of top (upper) andbottom (lower) substrates 103, 105 with each other. In one embodiment, a fluid drop dispenser 1102 is placed at some distance away from the upper substrate holder (holds upper substrate 103) 1103, where fluid drop dispenser 1102 dispenses fluid drops 1101 in a fluid dispense region 1104 on lower substrate 105. In one embodiment, the volume of fluid drops 1101 is precisely controlled.

[0110] In one embodiment, there is a shroud structure 1105 covering the open space above lower substrate 105 and extends from fluid drop dispenser 1102 to upper substrate holder 1103. In one embodiment, shroud structure 1105 is configured to manage the evaporation rate. In one embodiment, shroud structure 1105 creates a local environment which remains largely unaffected by the surrounding environment. In one embodiment, shroud structure 1105 is actuatable in the Z-tip-tilt directions 1106. In one embodiment, fluid drop dispenser 1 102 is a collection of one or more single-jet dispensers. In one embodiment, fluid drop dispenser 1102 is a collection of one or more multi-jet dispensers.

[0111] Furthermore, Figure 11 illustrates a lower substrate holder 1107 configured to hold lower substrate 105. Figure 11 further illustrates the direction of movement 1108 of lower substrate holder 1107.

[0112] Referring now to Figures 12A-12B, Figures 12A-12B illustrate an exemplary mechanism for dispensed fluid evaporation control with heat exchangers in accordance with an embodiment of the present disclosure.

[0113] In particular, Figures 12A-12B illustrate an exemplary mechanism for dispensing fluid evaporation control using heat exchangers for in-liquid alignment of top and bottom substrates 103, 105 with respect to each other. In one embodiment, there is a collection of one or more heat exchangers 1201 embedded in lower substrate holder 1107. When the fluid is dispensed from fluid drop dispenser 1102 on lower substrate 105, heat exchangers 1201 instantly freeze the dispensed drops (see 1202) as shown in Figure 12A. In one embodiment, lower substrate holder 1107 moves underneath upper substrate 103, and upper substrate 103 moves towards lower substrate 105 and contacts the dispensed drops on lower substrate 105. Heat exchangers 1201 melt the frozen drops (see 1203) and in-liquid alignment can be instantly performed as shown in Figure 12B. In one embodiment, the lowering of upper substrate 103 happens before the melting of the drops (1203). In one embodiment, the lowering of upper substrate 103 happens after the melting of the drops (1203). In one embodiment, the lowering of upper substrate 103 and the melting of the drops(1203) happen simultaneously. In one embodiment, fluid drop dispenser 1102 performs precise volume control of the dispensed fluid (sec 1101 of Figure 11).

[0114] Referring now to Figure 13, Figure 13 illustrates an exemplary mechanism for dispensing fluid for in-liquid alignment in accordance with an embodiment of the present disclosure.

[0115] In particular, Figure 13 illustrates a mechanism for dispensing fluid for in-liquid alignment of upper and lower substrates 103, 105 with respect to each other. In one embodiment, one or more fluid drop dispensers 1102 are integrated with upper substrate holder 1103 in such a way that fluid drop dispensers 1102 surround upper substrate 103. In one embodiment, lower substrate 105 is placed underneath upper substrate 103 and the fluid dispensing (dispensing drops 1101 by fluid drop dispensers 1102) is performed. In one embodiment, as shown in Figure 13, one or more fluid drop dispensers 1102 are placed at an angle 0 1301 with respect to the normal to upper substrate holder 1103. The value of angle 0 1301 is such that the dispensed drop 1101 is deposited on a region on lower substrate 105 which is underneath upper substrate 103. This allows instantaneous drop dispense and in-liquid alignment. In one embodiment, one or more fluid drop dispensers 1102 are used to create the desired drop patterns for in-liquid alignment. In one embodiment, one or more fluid drop dispensers 1102 perform precise drop volume control. In one embodiment, one or more mechanisms for fluid dispensing mentioned in Figures 11, 12A-12B and 13 are used with one or more evaporation control mechanisms mentioned in Figures 11, 12A-12B and 13.

[0116] Referring now to Figures 14A-14B, Figures 14A-14B illustrate an exemplary mechanism for in-liquid alignment between upper and lower substrates 103, 105 in accordance with an embodiment of the present disclosure.

[0117] In one embodiment, upper substrate holder 1103 consists of a Z-tip-tilt (ZTT) stage. This can be seen in Figures 14A-14B (ZTT stage 1 1401) which is actuated by actuator set 1 1402. In one embodiment, ZTT stage 1 1401 has a ZTT stage 2 1403 that carries upper substrate 103.

[0118] Figure 14A shows ZTT stage 2 1403 (actuated by actuator set 2 1404) is at such a position that upper substrate 103 is held closely to lower substrate 105 but is not making contact with lower substrate 105. In one embodiment, ZTT stage 1 1401 also carries one or more in-liquid pads 1405 which can be actuated using actuator set 3 1406. These pads 1405 establish contact with the dispensed fluid 1407 on lower substrate 105 so that in-liquid alignment can be performed betweenupper and lower substrates 103, 105. That is, Figure 14A illustrates ZTT stage 2 1403 being retracted, and in-liquid pads 1405 being actuated to establish contact with dispensed fluid 1407 on lower substrate 105. After the in-liquid alignment has been performed, ZTT stage 2 1403 actuates and establishes contact with ZTT stage 2 1403 so that the upper and lower substrates 103, 105 can be bonded as shown in Figure 14B. That is, Figure 14B illustrates ZTT stage 2 1403 being actuated for establishing contact between top and bottom substrates 103, 105, and in-liquid pads 1405 being actuated to establish contact with dispensed fluid 1407 on lower substrate 105.

[0119] In one embodiment, one or more actuators are present in actuator set 1 1402. In one embodiment, one or more actuators are present in actuator set 2 1404. In one embodiment, one or more actuators are present in actuator set 3 1406. In one embodiment, one or more actuators in actuator sets 1, 2 and 3 1402, 1404, 1406 are piezo-electric actuators. In one embodiment, one or more actuators in actuator sets 1, 2 and 3 1402, 1404, 1406 are electromagnetic actuators. In one embodiment, one or more actuators in actuator sets 1, 2 and 3 1402, 1404, 1406 are screw-type actuators. In one embodiment, one or more actuators in actuator sets 1, 2 and 3 1402, 1404, 1406 are thermal actuators.

[0120] In die-to-wafer bonding, such a method requires jetting fluid on the neighboring bond locations on a wafer for bonding at a particular location. Hence, this method requires 2 passes of bonding dies on a wafer as shown in Figures 15A-15B.

[0121] Figure 15 A illustrates an exemplary method of bonding dies 1501 on a wafer 1502 during the first pass in accordance with an embodiment of the present disclosure. Figure 15B illustrates an exemplary method of bonding dies 1501 on a wafer 1502 during the second pass in accordance with an embodiment of the present disclosure.

[0122] As illustrated in Figures 15A-15B, such a die-to-wafer bonding method requires jetting fluid in regions 1503 (regions of fluid dispense) resulting in bonding dies 1501 to wafer 1502 in regions 1504 (regions of bonding).

[0123] In one embodiment, the fluid is dispensed on neighboring bonding locations (regions 1503) on wafer 1502 as shown in Figure 15 A to run the first pass of bonding. In one embodiment, the fluid is dispensed on already bonded dies on the wafer from the first pass, and the bond locations are the fluid dispense locations from the first pass where the dies are not bonded.

[0124] Referring now to Figures 16A-16B, Figure 16A illustrates ZTT stage 2 1403 being retracted, and in-liquid pads 1405 being actuated to establish contact with dispensed fluid 1407 on lower substrate 105 during the second pass in accordance with an embodiment of the present disclosure. Figure 16B illustrates ZTT stage 2 1403 being actuated for establishing contact between top and bottom substrates 103, 105, and in-liquid pads 1405 being actuated to establish contact with dispensed fluid 1407 on previously bonded dies 1601 during the second pass in accordance with an embodiment of the present disclosure.

[0125] As shown in Figure 16A, ZTT stage 2 1403 is retracted so that upper substrate 103 is not in contact with lower substrate 105 but very close to lower substrate 105. Fluid is dispensed (1407) on previously bonded dies 1601 . Furthermore, in-liquid alignment happens at this stage.

[0126] As shown in Figure 16B, ZTT stage 2 1403 is actuated to establish contact between the upper and lower substrates 103, 105.

[0127] As previously discussed, Figures 16A-16B illustrate the second pass of an exemplary mechanism for in-liquid alignment between upper and lower substrates 103, 105. In one embodiment, upper substrate holder 1103 consists of a Z-tip-tilt (ZTT) stage as illustrated in Figures 16A-16B (ZTT stage 1 1401) which is actuated by actuator set 1 1402. In one embodiment, ZTT stage 1 1401 has a ZTT stage 2 1403 that carries upper substrate 103.

[0128] Figure 16A illustrates that ZTT stage 2 1403 (actuated by actuator set 2 1404) is at such a position that upper substrate 103 is held closely to lower substrate 105 but is not making contact with lower substrate 105. In one embodiment, ZTT stage 1 1401 also carries one or more in-liquid pads 1405 which can be actuated using actuator set 3 1406. In-liquid pads 1405 are retracted to a higher position than the same in the first pass so as to establish contact with dispensed fluid 1407 on the previously bonded dies 1601 so that in-liquid alignment can be performed between the upper and lower substrates 103, 105.

[0129] After the in-liquid alignment has been performed, ZTT stage 2 1403 actuates so that the upper and lower substrates 103, 105 can be bonded as shown in Figure 16B.

[0130] In one embodiment, one or more actuators are present in actuator set 1 1402. In one embodiment, one or more actuators are present in actuator set 2 1404. In one embodiment, one or more actuators are present in actuator set 3 1406. In one embodiment, one or more actuators inactuator sets 1 , 2 and 3 1402, 1404, 1406 are piezo-electric actuators. Tn one embodiment, one or more actuators in actuator sets 1, 2 and 3 1402, 1404, 1406 arc electromagnetic actuators. In one embodiment, one or more actuators in actuator sets 1, 2 and 3 1402, 1404, 1406 are screw-type actuators. In one embodiment, one or more actuators in actuator sets 1, 2 and 3 1402, 1404, 1406 are thermal actuators.

[0131] In one embodiment, in- liquid pads 1405 are rigidly attached to ZTT stage 1 1401 as shown in Figures 17A-17B.

[0132] Figures 17A-17B illustrate an exemplary mechanism for in-liquid alignment between upper and lower substrates 103, 105 with in-liquid pads 1405 rigidly attached to ZTT stage 1 1401 in accordance with an embodiment of the present disclosure.

[0133] Referring to Figure 17 A, Figure 17 A illustrates that ZTT stage 2 1403 is retracted so that upper substrate 103 is not in contact with lower substrate 105 but very close to lower substrate 105. Fluid is dispensed on the previously bonded dies (see 1601 in Figures 16A-16B). Furthermore, in-liquid alignment happens at this stage. Additionally, Figure 17A illustrates that in-liquid pads 1405 are in contact with dispensed fluid 1407 on lower substrate 105.

[0134] Figure 17B illustrates that ZTT stage 2 1403 is actuated to establish contact between the upper and lower substrates 103, 105. Furthermore, Figure 17B illustrates that in-liquid pads 1405 are in contact with dispensed fluid 1407 on the previously bonded dies (see 1601 in Figures 16A- 16B).

[0135] As a result of the foregoing, process control techniques have been developed for die-to- wafer and wafer-to-wafer bonding with high bonding yield.

[0136] The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

CLAIMS:

1. A method for bonding a first substrate to a second substrate, wherein said first substrate has a set of alignment marks, wherein said second substrate has a set of complementary alignment marks, the method comprising: utilizing said set of alignment marks on said first substrate and said set of complementary alignment marks on said second substrate to determine a bonding overlay error between said first and second substrates prior to bonding; and implementing corrections during bonding of said first substate to said second substrate based on said determined bonding overlay error.

2. The method as recited in claim 1 further comprising: measuring a misalignment between said set of alignment marks on said first substrate and said set of complementary alignment marks on said second substrate utilizing one or more of the following techniques: moire-based metrology, infrared metrology, in-situ metrology, off-axis metrology, diffraction gratings, lst-order diffraction, and Oth-order diffraction.

3. The method as recited in claim 1 , wherein said set of alignment marks on said first substrate and said set of complementary alignment marks on said second substrate are utilized to determine said bonding overlay error between said first and second substrates prior to bonding in response to a gap between said first and second substrates being less than 1 pm.

4. The method as recited in claim 3, wherein said gap is created using an intermediary liquid between said first and second substrates.

5. The method as recited in claim 4, wherein said intermediary liquid comprises one or more of the following: an aqueous solution, water, citric acid, an acid, a solution of water and an acid, hydrofluoric acid, and a fluorine-based acid.

6. The method as recited in claim 1 further comprising: determining one or more of the following components of said bonding overlay error: rigid body errors, magnification distortion, skew distortion, orthogonality distortion, trapezoidal distortion, and higher-order distortions than the prior distortions.

7. The method as recited in claim 1, wherein said bonding overlay error is determined in the following times prior to bonding: 1 second prior to bonding, 10 seconds prior to bonding, 100 seconds prior to bonding, and 1,000 seconds prior to bonding.

8. The method as recited in claim 1, wherein said determined bonding overlay error is utilized to correct overlay errors in real-time by feeding back said bonding overlay error to a set of actuators.

9. The method as recited in claim 1 , wherein said determined bonding overlay error is utilized to correct overlay errors in a feed-forward manner.

10. The method as recited in claim 1, wherein said first substrate is a die and said second substrate is a wafer.

11. The method as recited in claim 1, wherein said first substrate is a wafer and said second substrate is a wafer.

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