CXL memory module, memory repair method, control chip, medium, and system

Abstract

A CXL memory module, a memory repair method, a control chip, a medium, and a system. The CXL memory module comprises a control chip and one or more memory chips managed by the control chip. Available storage spaces of the one or more memory chips comprise a plurality of regions. The control chip is configured to: during operation, sequentially use each of the plurality of regions as a region to be detected, so as to determine whether there is an unreliable memory cell in the region to be detected; when the region to be detected is in an idle state, directly perform failure detection on the region to be detected; when the region to be detected is in a use state, copy to a target region data in the region to be detected, record an address mapping relationship between the region to be detected and the target region, and then re-perform failure detection on the region to be detected; and when there is an unreliable memory cell, replace the unreliable memory cell with a predetermined redundant memory cell and perform recording.

Description

CXL memory module, memory repair method, control chip, medium and system

[0001] The present application claims priority from the Chinese patent application No. 2024109468148, filed on July 15, 2024, and entitled "CXL memory module, memory repair method, control chip, medium and system", the contents of which are understood to be incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, the technical field of data access, and in particular to a CXL memory module, a memory repair method, a control chip, a medium and a system. BACKGROUND

[0003] CXL (Compute Express Link) is a memory interface protocol based on the PCIe (Peripheral Component Interconnect Express) physical layer. Based on the CXL protocol, a CXL memory module can expand the memory of a computer.

[0004] How to repair the memory in the running state of the server is an urgent problem to be solved.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. Embodiments of the present disclosure provide a CXL memory module, a memory repair method, a control chip, a medium and a system.

[0007] In a first aspect, the embodiments of the present disclosure provide a CXL memory module, comprising a control chip and one or more memory chips managed by the control chip, the available storage space of the one or more memory chips comprising a plurality of regions; the control chip is configured to: in a working project, sequentially take each region in the plurality of regions as a to-be-detected region to determine whether there is an unreliable storage unit in the to-be-detected region; in the case that the to-be-detected region is in an idle state, directly performing failure detection on the to-be-detected region; in the case that the to-be-detected region is in a use state, copying data in the to-be-detected region to a target sub-region, and recording the address mapping relationship between the to-be-detected region and the target region, and then performing failure detection on the to-be-detected region; in the case that there is an unreliable storage unit in the to-be-detected region, replacing the unreliable storage unit with a pre-determined redundant storage unit and recording.

[0008] Secondly, this disclosure provides a memory repair method applied to a CXL memory module. The CXL memory module includes a control chip and one or more memory chips managed by the control chip. The available storage space of the one or more memory chips includes multiple regions. The method includes: during the operation of the CXL memory module, sequentially taking each sub-region of the multiple regions as a region to be tested to determine whether there are unreliable storage units in the region to be tested; when the region to be tested is in an idle state, directly performing failure detection on the region to be tested; when the region to be tested is in a used state, copying the data in the region to be tested to a target region and recording the address mapping relationship between the region to be tested and the target region, and then performing failure detection on the region to be tested; when there are unreliable storage units in the region to be tested, replacing the unreliable storage units with predetermined redundant storage units and recording the results.

[0009] Thirdly, this disclosure provides a control chip applied to a CXL memory module. The CXL memory module further includes one or more memory chips managed by the control chip, and the processor of the control chip is configured to execute the memory repair method in the above embodiments.

[0010] Fourthly, this disclosure provides a non-transient computer storage medium, which stores a computer program that, when executed by a processor, implements the memory repair method described in the above embodiments.

[0011] Fifthly, this disclosure provides a computer system including a host and the CXL memory module in the above embodiments. The host communicates with the CXL memory module through the CXL interface to realize the discovery, configuration and data transmission of the CXL memory module. The CXL memory module is configured to repair unreliable storage units in the memory chip during runtime.

[0012] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0013] Overview of the attached figures

[0014] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0015] Figure 1 is a schematic diagram of the structure of an embodiment of the CXL memory module disclosed herein;

[0016] Figure 2 is a structural schematic diagram of another embodiment of the CXL memory module disclosed herein;

[0017] Figure 3 is a flowchart illustrating an embodiment of the memory repair method disclosed herein;

[0018] Figure 4 is a flowchart illustrating another embodiment of the memory repair method disclosed herein;

[0019] Figure 5 is a schematic diagram of the structure of a control chip according to an embodiment of the present disclosure;

[0020] Figure 6 is a schematic diagram of the structure of an embodiment of the computer system disclosed herein.

[0021] Detailed Explanation

[0022] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined arbitrarily.

[0023] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0024] The ordinal numbers such as "first" and "second" in this disclosure are used to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0025] This disclosure describes several embodiments, but these descriptions are exemplary and not restrictive, and many more embodiments and implementations are possible within the scope of the embodiments described herein, which will be apparent to those skilled in the art. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with or in lieu of any other feature or element in any other embodiment.

[0026] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form the scheme defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other disclosed schemes to form another scheme defined by the claims. Therefore, it should be understood that any feature shown and discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0027] Furthermore, in describing representative embodiments, the specification may have presented methods and processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described in this disclosure to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and process should not be limited to performing the steps in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this disclosure.

[0028] In the description of this disclosure, unless otherwise stated, "a plurality of" means two or more. When a memory chip is manufactured, there may be unreliable memory cells within it. The memory chip needs to be tested before leaving the factory to detect unreliable memory cells and replace them with pre-determined redundant memory cells. The replacement information is then programmed into the on-chip eFuse (one-time programmable memory).

[0029] However, because the stress accumulated inside the chip during the integrated circuit manufacturing process takes a long time to release, the first six months after a memory chip leaves the factory are a high-risk period for failures, and these hidden dangers cannot be detected on the production line. For applications such as data centers that have high requirements for data storage reliability, memory chip failures during use are a major problem. Furthermore, since data center servers need to run continuously, often for years without being shut down, how to repair memory while the server is running is an urgent issue that needs to be addressed.

[0030] As shown in Figure 1, this embodiment of the disclosure provides a CXL memory module, which may include a control chip 110 and one or more memory chips 120 managed by it. The control chip 110, also known as a CXL controller, may be equipped with a CXL interface based on the CXL protocol, allowing the host CPU to interact with the control chip 110 via the CXL interface. For example, based on the CXL.io protocol, the host CPU can send instructions to the control chip 110; based on the CXL.mem protocol, the host CPU can read data from the memory chip 120 and write external data to the memory chip 120. The control chip 110 may also be equipped with a DDR (Double Data Rate) controller, enabling the CPU of the control chip 110 to manage the memory chips 120.

[0031] The memory chip 120 may be, for example, a DRAM (Dynamic Random Access Memory) chip. The available storage space of one or more memory chips 120 may be configured to include multiple regions, each region corresponding to a segment of physical storage addresses. An unreliable storage cell refers to a storage cell in the memory chip 120 that cannot function properly.

[0032] The control chip 110 can be configured to: during operation, sequentially use each of the multiple regions as the region to be detected to determine whether there are unreliable storage units in the region to be detected; when the region to be detected is in an idle state, directly perform failure detection on the region to be detected; when the region to be detected is in a used state, copy the data in the region to be detected to the target region, record the address mapping relationship between the region to be detected and the target region, and then perform failure detection on the region to be detected; if there are unreliable storage units in the region to be detected, replace the unreliable storage units with pre-determined redundant storage units and record the results.

[0033] In this embodiment, the control chip 110 may be pre-loaded with a failure detection algorithm, which may include, for example, repeated write and read tests. When the processor of the control chip 110 runs the failure detection algorithm, it can test the parameters of the storage cells in the memory chip 120 (such as data retention time, read / write timing, etc.) to determine whether the storage cell is unreliable. For example, when some parameters of the storage cell do not have sufficient redundancy, the storage cell can be determined to be unreliable.

[0034] When the CXL memory module is in operation, i.e., providing services to the host (such as data access, collaborative computing, etc.), the control chip 110 can determine one region as the region to be detected from multiple regions at a time, and use a failure detection algorithm to detect the region to determine whether there are unreliable memory cells in the region to be detected. If unreliable memory cells are stored in the region to be detected, redundant memory cells are used to replace the unreliable memory cells, thereby repairing the region to be detected. Then, new regions to be detected are determined from the remaining sub-regions, and the failure detection and repair operation is performed again until all regions are detected.

[0035] In some optional embodiments of this example, the control chip 110 may also be configured to: sequentially determine each sub-region of the plurality of sub-regions as the region to be detected at preset intervals, so as to periodically perform failure detection and repair on the available storage space of the chip 120. In this way, the control chip can periodically perform failure detection and repair on the memory chip.

[0036] In some optional implementations of this embodiment, the control chip may determine the area to be detected in the following way: preferentially determine the sub-regions that are in an idle state among multiple sub-regions as the area to be detected.

[0037] As an example, the control chip 110 can first detect whether all areas are in use. For instance, the control chip 110 can determine whether an area is in use based on its access records. Areas without access operations within a predetermined time period can be considered idle sub-areas, while areas accessed (including writing or reading data) within the predetermined time period can be considered sub-areas in use. Then, one of the idle sub-areas is randomly selected as the area to be detected. After the current area to be detected is repaired, the next area to be detected is selected from the remaining idle sub-areas, and so on, until there are no more idle sub-areas. Then, an area to be detected is selected from the sub-areas in use, until all areas have been detected and repaired.

[0038] In this embodiment, the control chip 110 can adopt different detection methods depending on whether the area to be detected is in use.

[0039] When the area to be detected is in an idle state (i.e., unused state), the control chip 110 can directly perform failure detection on the area to be detected to determine whether there are unreliable memory cells in the area to be detected.

[0040] When the area to be detected is in use, to avoid data loss in the area due to failure detection, the control chip 110 can first copy the data in the area to be detected to the target area, and then perform failure detection on the area to be detected. Here, the target area refers to the area used to store the data in the area to be detected. An unused area can be pre-determined from multiple areas as the target area before starting the detection, or it can be selected from areas that have already been detected during the detection process.

[0041] After copying the data from the area to be detected to the target area, the control chip 110 can record the address mapping relationship between the area to be detected and the target area. For example, it can be the mapping relationship between the physical storage address of the area to be detected in the memory chip 120 and the physical storage address of the target area in the memory chip 120. When repairing the area to be detected later, if an instruction to access the area to be detected is received, the control chip 110 can map the physical address carried in the instruction to the target area based on the address mapping relationship, and then access the data in the target area. In this way, repairing the memory chip 120 will not affect the normal operation of the CXL memory module.

[0042] In some embodiments, each memory chip 120 is provided with a redundant storage area and a replacement relationship table; the CXL memory module can implement the replacement process of unreliable storage cells in the following manner: the control chip 110 sends a replacement instruction to the memory chip 120 where the unreliable storage cell is located, and the replacement instruction carries the address information of the unreliable storage cell; the memory chip 120 is configured to: in response to the replacement instruction, replace the unreliable storage cell with a redundant storage cell in the redundant storage area, and record the address correspondence between the redundant storage cell and the unreliable storage cell in the replacement relationship table.

[0043] In this embodiment, under the control of the control chip, the memory chip itself can complete the replacement process of unreliable storage units, which helps to improve the repair efficiency of the CXL memory module.

[0044] In other embodiments, the multiple memory chips 120 may also be provided with a first storage space in addition to the available storage space; the control chip 110 may replace unreliable storage cells by using redundant storage cells in the first storage space to replace unreliable storage cells and recording the address correspondence between the redundant storage cells and the unreliable storage cells.

[0045] As an example, after the control chip 110 detects an unreliable storage unit in the area to be detected, it can replace the unreliable storage unit with a redundant storage unit in the first storage space. Then, it records the address correspondence between the unreliable and redundant storage units as a replacement relationship and stores it in eFuse or flash memory. When accessing an unreliable storage unit subsequently, the control chip 110 can access the corresponding redundant storage unit based on the replacement relationship, thereby achieving the repair processing of the area to be detected.

[0046] In this embodiment, the redundant storage units in the first storage space are shared by multiple memory chips 120. In this way, the control chip 110 can replace unreliable storage units among the multiple memory chips 120 with redundant storage units in the first storage space, which facilitates centralized management and control of the redundant storage units.

[0047] In some optional implementations of this embodiment, a first storage space can be set in the CXL memory module, and each memory chip 120 can also be provided with a redundant storage area. The control chip 110 can replace unreliable storage units through either of the above two methods. As an example, the control chip 110 can preferentially replace unreliable storage units by using the self-repair method of the memory chip 120. When the redundant storage area in the memory chip 120 is insufficient, redundant storage units in the first storage space can be used for replacement. This helps to improve the flexibility of memory repair in the CXL memory module.

[0048] In one example, when replacing unreliable memory cells in the area to be detected with redundant memory cells, the control chip 110 or the memory chip 120 can replace the row or column containing the unreliable memory cells with the row or column containing the redundant memory cells, and record the address correspondence between the row or column containing the unreliable memory cells and the row or column containing the redundant memory cells as the replacement relationship. This way, when accessing the row or column containing the unreliable memory cells later, the row or column containing the redundant memory cells can be accessed according to the replacement relationship, thereby achieving the repair of unreliable memory cells in the memory chip 120 by row or column.

[0049] In another example, the smallest unit for reading and writing data in the CXL memory module is a word (i.e., containing multiple bytes). The control chip 110 or the memory chip 120 can replace the word containing an unreliable storage unit with a word composed of redundant storage units in units of words. In this case, the replacement relationship can be the address correspondence between the word containing the unreliable storage unit and the word composed of redundant storage units.

[0050] The CXL memory module of this disclosure, during its operation, sequentially identifies each of the multiple regions comprising the available storage space of the memory chip as a region to be tested to determine whether any unreliable storage cells exist within that region. When the region to be tested is idle, failure detection is performed directly. When the region to be tested is in use, the data within it is copied to a predetermined target region, and the address mapping relationship between the region to be tested and the target region is recorded. Then, failure detection is performed on the region to be tested. If unreliable storage cells are found within the region to be tested, pre-determined redundant storage cells are used to replace the unreliable storage cells, and the replacement relationship between the redundant and unreliable storage cells is recorded. This allows for the repair of the memory chip during CXL memory module operation, contributing to improved reliability of data processing by the CXL memory module.

[0051] In some embodiments, after copying the data in the area to be detected to a predetermined target area and recording the address mapping relationship between the area to be detected and the target area, the control chip is further configured to: when receiving an access instruction to access the area to be detected, access the target area based on the address mapping relationship.

[0052] In this embodiment, after determining the address mapping relationship between the region to be detected and the target region, when the control chip 110 receives an access instruction to access the region to be detected, it can convert the address to be accessed carried in the access instruction into the corresponding address in the target region according to the address mapping relationship, and then access the target region according to the converted address. Before replacing the unreliable storage unit in the region to be detected with a redundant storage unit, the parallel processing of memory chip repair and memory access can be realized.

[0053] As an example, the address mapping relationship can include the correspondence between the memory addresses of the region to be detected and the memory addresses of the target region. The access instruction can be a read or write instruction sent by the host, carrying the external physical address to be accessed (i.e., the address carried in the instruction sent by the host CPU to the CXL module via the address bus). The control chip of the CXL module can extract the external physical address from the access instruction and convert it into a memory address (i.e., the physical address of a storage unit in the memory chip) using proprietary hardware (e.g., an address translator). Here, the converted memory address points to the region to be detected. Then, the control chip can look up the corresponding memory address in the address mapping relationship. Here, the corresponding memory address points to the target region, and the control chip can access the corresponding memory address to perform access processing for the region to be detected.

[0054] In some embodiments, the CXL memory module can also utilize virtual memory to manage the memory usage of various tasks. In this case, the address information carried in the memory access instruction on the host side is a virtual address. The control chip can translate the virtual address into a physical address and then access the corresponding memory unit. As shown in Figure 2, the control chip 210 has a virtual address translation table 211, which can include the correspondence between virtual addresses and physical addresses. The control chip 210 can access multiple memory chips 220 according to the virtual address carried in the access instruction through translation hardware 212 (e.g., a virtual address manager).

[0055] In this embodiment, after copying the data in the area to be detected to a predetermined target area and recording the address mapping relationship between the area to be detected and the target area, the control chip 210 is further configured to: modify the physical address of the area to be detected in the address translation table to the physical address of the target area based on the address mapping relationship.

[0056] In one example, the physical address in the virtual address translation table 211 can be an external physical address. After the control chip 110 translates the virtual address in the access instruction into an external physical address, it converts the external physical address into a memory address and then accesses the memory chip 220 based on the memory address. At this time, the control chip 210 can modify the external physical address corresponding to the region to be detected in the virtual address translation table to the external physical address of the target region. In this way, during the repair of the region to be detected and after the repair is completed, when an access instruction for the region to be detected is received, the control chip 210 can translate the virtual address carried in the access instruction into the external physical address of the target region based on the virtual address translation table, thereby mapping the memory access processing (e.g., writing data or reading data) for the region to be detected to the target region.

[0057] In another example, the physical address in the virtual address translation table 211 can be a memory address. The control chip 210 can directly translate the virtual address in the access instruction into a memory address to access the memory chip 220. In this case, the control chip 210 can modify the memory address of the region to be detected in the virtual address translation table 211 to the memory address of the target region. Thus, during the repair of the region to be detected and after the repair is completed, when an access instruction for the region to be detected is received, the control chip 210 can translate the virtual address carried in the access instruction into the memory address of the target region according to the virtual address translation table, and then map the memory access processing for the region to be detected to the target region.

[0058] In this embodiment, a virtual address translation table is stored in the control chip. Before repairing the area to be detected, the physical address of the area to be detected in the virtual address translation table is modified to the physical address of the target area. The virtual address can be used to switch and map the area to be detected and the target area. Then, the memory access processing of the area to be detected during and after the repair is mapped to the target area, which helps to improve the memory access efficiency during the memory repair process.

[0059] In some optional implementations of any of the above embodiments, after copying the data from the region to be detected to the target region, once the failure detection or repair of the region to be detected is completed, the data may not be copied back to the region to be detected. Instead, the target region can be used as the data storage location, and subsequent access operations to that data will be mapped to the target region. At this time, a new target region can be redefined for other regions, thereby reducing the number of times data is copied in the memory chip and helping to reduce the power consumption of the CXL memory module.

[0060] In this embodiment, the control chip is also configured to reserve one or more free areas in the available storage space as the initial target area for failure detection during operation.

[0061] Here, the initial target area can be predetermined. In the initial stage of failure detection, the control chip 211 can first store the data in the initial target area, and then determine a new target area during the subsequent detection process.

[0062] In an optional example, the control chip 211 is configured to, when sequentially using each of the multiple regions as the region to be detected, first use the initial target region as the region to be detected; if there are no unreliable storage units in the initial target region, use the initial target region as the target region for subsequent failure detection of other regions.

[0063] In this example, failure detection can be performed on the initial target area first, and the reliable initial target area that passes the detection can be used as the target area when other areas are tested for failure. This can avoid storing data in an unreliable initial target area and help to further improve the reliability of the data.

[0064] In another optional example, the control chip 211 is also configured to use the area to be detected as the target area for subsequent failure detection of other areas if there are no unreliable storage units in the area to be detected.

[0065] In this example, the reliable regions that have been detected (i.e., regions where there are no unreliable storage units) can be used as target regions for subsequent detection of other regions.

[0066] In some alternative implementations of any of the above embodiments, after replacing the unreliable storage unit with a redundant storage unit, the control chip can copy the data in the target area back to the area to be detected to clear the target area. In this way, the data stored in the target area can still be used when detecting other areas in the future.

[0067] In one example of the implementation, after replacing the unreliable storage unit with a predetermined redundant storage unit, the control chip 211 is further configured to copy the data in the target area back to the area to be detected and delete the address mapping relationship.

[0068] In this embodiment, to repair the memory chip during the operation of the CXL memory module, the memory access processing for the area to be tested is mapped to the target area during the repair process. After the repair of the area to be tested is completed, the data in the target area is copied to the area to be tested, which can ensure the timeliness of the data in the area to be tested and avoid data loss caused by repairing the memory chip. In another example of this embodiment, when the CXL memory module uses virtual addresses, after replacing unreliable storage units with predetermined redundant storage units, the control chip 211 can also be configured to: copy the data in the target area back to the area to be tested; and modify the physical address of the target area in the virtual address translation table to the physical address of the area to be tested based on the address mapping relationship.

[0069] In this embodiment, after the repair is completed (i.e., the unreliable storage unit is replaced), the control chip can modify the physical address of the target area of ​​the virtual address translation table to the physical address of the area to be detected, so that the repaired area to be detected can be directly accessed according to the virtual address.

[0070] This disclosure also provides a memory repair method applied to a CXL memory module. The CXL memory module includes a control chip and one or more memory chips managed by the control chip. The available storage space of the one or more memory chips includes multiple regions. As shown in Figure 3, the method includes steps 310 to 340.

[0071] Step 310: During the operation of the CXL memory module, each of the multiple regions is taken as the region to be tested in turn to determine whether there are unreliable storage units in the region to be tested.

[0072] In some optional implementations of this embodiment, step 310 can determine the area to be detected in the following way: preferentially determine the area that is in an idle state among multiple areas as the area to be detected.

[0073] Step 320: When the area to be tested is in an idle state (i.e., in an unused state), perform failure detection directly on the area to be tested.

[0074] Step 330: When the area to be tested is in use, copy the data in the area to be tested to the predetermined target area, record the address mapping relationship between the area to be tested and the target area, and then perform failure detection on the area to be tested.

[0075] Step 340: If there are unreliable storage units in the area to be detected, replace the unreliable storage units with pre-determined redundant storage units and record the results.

[0076] The memory repair method of this disclosure, during the operation of the CXL memory module, sequentially identifies each of the multiple regions included in the available storage space as a region to be tested to determine whether there are unreliable storage units in the region to be tested. When the region to be tested is idle, failure detection is directly performed on the region to be tested. When the region to be tested is in use, the data in the region to be tested is first copied to the target region, and the address mapping relationship between the region to be tested and the target region is recorded. Then, failure detection is performed on the region to be tested. If unreliable storage units are found in the region to be tested, the unreliable storage units are replaced with pre-determined redundant storage units, and this is recorded. This method allows for the repair of memory chips during the operation of the CXL memory module, helping to improve the reliability of data processing by the CXL memory module.

[0077] In some optional embodiments of this example, step 310 may further include: sequentially selecting each region in the plurality of regions as the region to be detected at preset intervals. This achieves periodic detection and repair of the memory chip.

[0078] In some optional embodiments of this example, each of the multiple memory chips is provided with a redundant storage area and a replacement relationship table; the above step 340 includes: sending a replacement instruction to the memory chip where the unreliable storage cell is located, so as to instruct the memory chip where the unreliable storage cell is located to replace the unreliable storage cell with a redundant storage cell in the redundant storage area, and recording the address correspondence between the redundant storage cell and the unreliable storage cell in the replacement relationship table; the replacement instruction carries the address information of the unreliable storage cell.

[0079] In some optional embodiments of this example, the multiple memory chips also include a first storage space in addition to the available storage space; the above step 340 includes: replacing unreliable storage cells with redundant storage cells in the first storage space, and recording the address correspondence between the redundant storage cells and the unreliable storage cells.

[0080] In some alternative implementations, the CXL memory module includes a first storage space, and each memory chip 120 may also have a redundant storage area. Step 340 can employ either of the two methods described above to replace unreliable storage units. For example, the memory chip 120 can preferentially replace unreliable storage units through its own repair mechanism. When the redundant storage area in the memory chip 120 is insufficient, redundant storage units in the first storage space can be used for replacement. This helps improve the flexibility of memory repair in the CXL memory module.

[0081] In some embodiments, after step 320 above, the method may further include: upon receiving an access instruction to access the region to be detected, accessing the target region based on the address mapping relationship. In this embodiment, the address to be accessed carried in the access instruction can be converted into a corresponding address in the target region according to the address mapping relationship, and then the target region can be accessed according to the converted address, thereby achieving parallel processing of memory chip repair and memory access. In some optional embodiments of this embodiment, after copying the data in the region to be detected to the target region, once the failure detection or repair of the region to be detected is completed, the data may not be copied back to the region to be detected. Instead, the target region can be used as the data storage location, and subsequent access operations for the data will be mapped to the target region. At this time, a new target region can be redefined for other subsequent regions, thereby reducing the number of times data is copied in the memory chip and helping to reduce the power consumption of the CXL memory module.

[0082] In this embodiment, the method may further include: during operation, reserving one or more free areas in the available storage space as the initial target area for failure detection.

[0083] Here, the initial target area can be predetermined. In the initial stage of failure detection, the data can be stored in the initial target area, and a new target area can be determined later during the detection process.

[0084] In an optional example, step 310 above may include: first, using the initial target area as the area to be detected; and if there are no unreliable storage units in the initial target area, using the initial target area as the target area for subsequent failure detection of other areas.

[0085] In this example, failure detection can be performed on the initial target area first, and the reliable initial target area that passes the detection can be used as the target area when other areas are tested for failure. This can avoid storing data in an unreliable initial target area and help to further improve the reliability of the data.

[0086] In another alternative example, after step 330 above, the method may further include: if there are no unreliable storage units in the area to be detected, using the area to be detected as the target area for subsequent failure detection of other areas.

[0087] In this example, the reliable regions that have been detected (i.e., regions where there are no unreliable storage units) can be used as target regions for subsequent detection of other regions.

[0088] In some other embodiments of this example, after step 340 above, the method may further include: copying data in the target area to the area to be detected, and deleting the address mapping relationship.

[0089] In this embodiment, in order to repair the memory chip during the operation of the CXL memory module, the memory access processing of the area to be tested during the repair process is mapped to the target area. After the repair of the area to be tested is completed, the data in the target area is copied to the area to be tested, which can ensure the timeliness of the data in the area to be tested and avoid data loss caused by repairing the memory chip.

[0090] Figure 4 shows a flowchart of an embodiment of the memory repair method of this disclosure. As shown in Figure 4, the process includes steps 410 to 450.

[0091] Step 410: During the operation of the CXL memory module, each of the multiple regions is taken as the region to be detected in turn.

[0092] In this embodiment, the control chip stores a virtual address translation table so that the control chip can access multiple memory chips according to the virtual address carried in the access instruction. The virtual address translation table includes the correspondence between virtual addresses and physical addresses, and the physical address represents the storage address of data in multiple memory chips.

[0093] Step 420: When the area to be detected is in use, copy the data in the area to be detected to the predetermined target area, and record the address mapping relationship between the area to be detected and the target area.

[0094] Step 430: Based on the address mapping relationship, modify the physical address of the area to be detected in the address translation table to the physical address of the target area.

[0095] Step 440: Perform failure detection on the area to be tested.

[0096] Step 450: If there are unreliable storage units in the area to be detected, replace the unreliable storage units with pre-determined redundant storage units and record the results.

[0097] In this embodiment, before repairing the region to be detected, the physical address of the region to be detected in the virtual address translation table is modified to the physical address of the target region. The virtual address can be used to switch and map the region to be detected and the target region. Then, the memory access processing for the region to be detected during and after the repair is mapped to the target region, which helps to improve the memory access efficiency during the memory repair process.

[0098] In some optional implementations of this embodiment, after step 450, the above process may further include: step 460, copying the data in the target area back to the area to be detected.

[0099] Step 470: Based on the address mapping relationship, modify the physical address of the target region in the virtual address translation table to the physical address of the region to be detected.

[0100] This disclosure also provides a control chip applied to a CXL memory module. As shown in FIG5, the CXL memory module further includes multiple memory chips 520 managed by the control chip. The processor 511 of the control chip 510 is configured to execute the memory repair method in the above embodiments.

[0101] This disclosure also provides a non-transient computer storage medium, which stores a computer program that, when executed by a processor, implements the memory repair method described in the above embodiments.

[0102] This disclosure also provides a computer system, as shown in FIG6. The computer system includes a host 610 and a CXL memory module 620 in any of the above embodiments. The host 610 communicates with the CXL memory module 620 through the CXL interface to realize one or more of the following: discovery, configuration and data transmission of the CXL memory module 620. The CXL memory module 620 is configured to repair unreliable storage units in the memory chip during runtime.

[0103] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0104] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A CXL memory module, comprising a control chip and one or more memory chips managed by the control chip, available storage space of the one or more memory chips comprising a plurality of regions; the control chip is configured to: in the working process, sequentially take each region in the plurality of regions as a to-be-detected region to determine whether there is an unreliable storage unit in the to-be-detected region; when the to-be-detected region is in an idle state, directly performing failure detection on the to-be-detected region; when the to-be-detected region is in a used state, copying data in the to-be-detected region to a target region, recording address mapping relationship between the to-be-detected region and the target region, and then performing failure detection on the to-be-detected region; in the case that there is the unreliable storage unit in the to-be-detected region, replacing the unreliable storage unit with a predetermined redundant storage unit. The control chip is configured to sequentially take each region in the plurality of regions as a to-be-detected region, comprising: every preset period, the control chip sequentially takes each region in the plurality of regions as a to-be-detected region. The control chip is configured to sequentially take each region in the plurality of regions as a to-be-detected region, comprising: the control chip preferentially determines a region in the idle state in the plurality of regions as the to-be-detected region.

2. The CXL memory module of claim 1, wherein, The control chip is further configured to: after copying data in the to-be-detected region to a target region and recording address mapping relationship between the to-be-detected region and the target region, when an access instruction for accessing the to-be-detected region is received, accessing the target region based on the address mapping relationship.

3. The CXL memory module of claim 1, wherein, The control chip stores a virtual address translation table, so that the control chip accesses the plurality of memory chips according to a virtual address carried in an access instruction, the virtual address translation table comprising a correspondence between a virtual address and a physical address; and 4. The CXL memory module of claim 1, wherein, The control chip is further configured to: after copying data in the to-be-detected region to a target region and recording address mapping relationship between the to-be-detected region and the target region, modifying a physical address of the to-be-detected region in the address translation table to a physical address of the target region based on the address mapping relationship.

5. The CXL memory module of claim 1, wherein, The control chip is further configured to: after replacing the unreliable storage unit with a predetermined redundant storage unit, copying data in the target region to the to-be-detected region; modifying a physical address of the target region in the virtual address translation table to a physical address of the to-be-detected region based on the address mapping relationship. The control chip is further configured to: after replacing the unreliable storage unit with a predetermined redundant storage unit, copying data in the target region to the to-be-detected region and deleting the address mapping relationship.

6. The CXL memory module of claim 5, wherein, The control chip is further configured to: in the working process, always reserve one or more idle regions in the available storage space as initial target regions for failure detection.

7. The CXL memory module of one of claims 1 to 5, wherein, ​ 8. The CXL memory module of one of claims 1 to 5, wherein, ​ 9. The CXL memory module of claim 8, wherein, The control chip is configured to sequentially take each of the plurality of regions as a to-be-detected region, including that the control chip first takes the initial target region as a to-be-detected region; and in the case that the initial target region does not exist the unreliable storage unit, taking the initial target region as a target region for subsequent invalidity detection on other regions.

10. The CXL memory module of claim 1 or 9, wherein, The control chip is further configured to, in the case that the to-be-detected region does not exist the unreliable storage unit, take the to-be-detected region as a target region for subsequent invalidity detection on other regions.

11. The CXL memory module of claim 1, wherein, Each of the one or more memory chips is provided with a redundant storage region and a replacement relationship table. The control chip is configured to replace the unreliable storage unit with a predetermined redundant storage unit, including that the control chip sends a replacement instruction to the memory chip where the unreliable storage unit is located, and the replacement instruction carries address information of the unreliable storage unit. Each of the one or more memory chips is configured to, in response to the replacement instruction, replace the unreliable storage unit with a redundant storage unit in the redundant storage region, and record the address correspondence relationship between the redundant storage unit and the unreliable storage unit in the replacement relationship table.

12. The CXL memory module of claim 1 or 11, wherein, The storage space of the one or more memory chips further includes a first storage space outside the available storage space. The control chip is configured to replace the unreliable storage unit with a predetermined redundant storage unit, including that the control chip replaces the unreliable storage unit with a redundant storage unit in the first storage space, and records the address correspondence relationship between the redundant storage unit and the unreliable storage unit.

13. A memory repair method applied to a CXL memory module, the CXL memory module including a control chip and one or more memory chips managed by the control chip, and available storage space of the one or more memory chips including a plurality of regions; the method comprising: In the working process of the CXL memory module, sequentially taking each of the plurality of regions as a to-be-detected region to determine whether there is an unreliable storage unit in the to-be-detected region; When the to-be-detected region is in an idle state, directly performing invalidity detection on the to-be-detected region; When the to-be-detected region is in a use state, copying data in the to-be-detected region to a predetermined target region, recording address mapping relationship between the to-be-detected region and the target region, and then performing invalidity detection on the to-be-detected region; In the case that the to-be-detected region exists the unreliable storage unit, replacing the unreliable storage unit with a predetermined redundant storage unit and recording.

14. The method of claim 13, wherein, The sequentially taking each of the plurality of regions as a to-be-detected region includes that every preset period, sequentially taking each of the plurality of regions as the to-be-detected region.

15. The method of claim 13, wherein, The sequentially taking each sub-region in the plurality of regions as a to-be-detected region comprises: preferentially taking a region in the plurality of regions in an idle state as the to-be-detected region.

16. The method of claim 13, after the copying data in the to-be-detected region into a target region and recording an address mapping relationship between the to-be-detected region and the target region, the method further comprises: Upon receiving an access instruction for accessing the to-be-detected region, accessing the target region based on the address mapping relationship.

17. The method of claim 13, wherein, The control chip stores a virtual address translation table, so that the control chip accesses the plurality of memory chips according to a virtual address carried in an access instruction, and the virtual address translation table comprises a corresponding relationship between a virtual address and a physical address; and After the copying data in the to-be-detected region into a target region and recording an address mapping relationship between the to-be-detected region and the target region, the method further comprises: modifying a physical address of the to-be-detected region in the address translation table to a physical address of the target region based on the address mapping relationship. Copying data in the target region into the to-be-detected region; 18. The method of claim 17, after said replacing said unreliable memory cell with a predetermined redundant memory cell, said method further comprising: Modifying a physical address of the target region in the virtual address translation table to a physical address of the to-be-detected region based on the address mapping relationship. Copying data in the target region into the to-be-detected region and deleting the address mapping relationship.

19. The method of one of claims 13 to 17, after said replacing of said unreliable memory cell by said predetermined redundant memory cell, said method further comprising: During operation, one or more idle regions are always reserved in the available storage space as initial target regions for failure detection.

20. The method of one of claims 13 to 17, further comprising: The sequentially taking each region in the plurality of regions as a to-be-detected region comprises: first taking the initial target region as a to-be-detected region; and in a case where the initial target region does not have the unreliable storage unit, taking the initial target region as a target region for subsequent failure detection on other regions.

21. The method of claim 20, wherein, In a case where the to-be-detected region does not have the unreliable storage unit, taking the to-be-detected region as a target region for subsequent failure detection on other regions.

22. The method of claim 21, further comprising: Each of the one or more memory chips is provided with a redundant storage region and a replacement relationship table; 23. The method of claim 13, wherein, The replacing the unreliable storage unit with a predetermined redundant storage unit comprises: sending a replacement instruction to a memory chip where the unreliable storage unit is located, to instruct the memory chip where the unreliable storage unit is located to replace the unreliable storage unit with a redundant storage unit in the redundant storage region, and recording an address corresponding relationship between the redundant storage unit and the unreliable storage unit in the replacement relationship table; the replacement instruction carries address information of the unreliable storage unit. The storage space of the plurality of memory chips further comprises a first storage space outside the available storage space; 24. The method of claim 13 or 23, wherein, ​ The replacing the unreliable storage unit with the predetermined redundant storage unit comprises: replacing the unreliable storage unit with a redundant storage unit in the first storage space, and recording an address correspondence relationship between the redundant storage unit and the unreliable storage unit. 25.A control chip applied to a CXL memory module, the CXL memory module further comprising one or more memory chips managed by the control chip, and a processor of the control chip is configured to execute the memory repair method of any one of claims 13 to 24. 26.A non-transitory computer storage medium, the computer storage medium storing a computer program, the computer program being executed by a processor to implement the memory repair method of any one of claims 13 to 24. 27.A computer system comprising a host and a CXL memory module of any one of claims 1 to 12, the host communicating with the CXL memory module through a CXL interface to implement one or more of discovery, configuration and data transmission of the CXL memory module, and the CXL memory module is configured to repair an unreliable storage unit in a memory chip at runtime.

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