Trench-structured depletion-type mosfet and manufacturing method therefor

Abstract

The present invention provides a trench-structured depletion-type MOSFET and a manufacturing method therefor. The manufacturing method comprises: providing a substrate; forming a well region of a first conductivity type in the substrate; forming a trench in the substrate, wherein the trench passes through the well region; and depositing an inversion layer of a second conductivity type in the trench, wherein the inversion layer covers the inner surface of the trench, and the second conductivity type is opposite to the first conductivity type. Forming the inversion layer by means of deposition avoids the mode of forming the inversion layer by multiple angled implantations, thereby reducing the risk of pinch-off of the inversion layer, and reducing the process difficulty of the trench-structured depletion-type MOSFET. In addition, in the manufacturing method, a grid-type cell structure can be used, which further reduces the on-resistance of a device. The trench-structured depletion-type MOSFET may be manufactured by using the manufacturing method for the trench-structured depletion-type MOSFET.

Description

Trench structure depletion-type MOSFET and its manufacturing method

[0001] Cross-references to related applications

[0002] This application claims priority to application number 202410954175.X, filed on July 16, 2024, entitled "Trench Structure Depletion-Type MOSFET and Manufacturing Method Thereof", the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] This invention relates to the field of semiconductor device technology, and in particular to a trench structure depletion-type MOSFET and its manufacturing method. Background Technology

[0004] Depletion-type metal-oxide-semiconductor field-effect transistors (MOSFETs) are normally on devices. When the gate voltage is 0V, the device is in the on state. To turn it off, a certain negative voltage must be applied to the gate. Depletion-type MOSFETs are used in chargers, LEDs, industrial control, electric vehicles, communication circuits, and the Internet of Things (IoT).

[0005] Figure 1 is a cross-sectional view of a planar depletion-type MOSFET. As shown in Figure 1, an inversion layer 102, an N+ doped region 103, and a P-well 101 are formed in the substrate of the planar depletion-type MOSFET. The inversion layer 102 and the N+ doped region 103 are formed above the P-well 101, and the N+ doped region 103 is located on the side of the inversion layer 102. However, the on-resistance (R) of the planar depletion-type MOSFET is... SP (It is relatively large.)

[0006] Trench-structured depletion-mode MOSFETs can significantly reduce the on-resistance of devices. However, the manufacturing process of trench-structured depletion-mode MOSFETs is more difficult, requiring multiple implantations of N-type dopant at angles to form the inversion layer, and the implantation angle of the N-type dopant is also critical. Figure 2 is a cross-sectional schematic diagram of a trench-structured depletion-mode MOSFET. Referring to Figure 2, when the N-type dopant implantation angle is too large, the N-type dopant cannot be implanted to the bottom of the trench 104 due to the obstruction of the other sidewall. The implantation depth of the inversion layer 102 is shallower than that of the P-well 101, which easily leads to the inversion layer 102 being pinched off at the junction of the bottom of the P-well 101 and the trench 104 (see the position shown by the dashed box in Figure 2), failing to meet the requirement of the device being normally on. Figure 3 is a cross-sectional schematic diagram of another trench-structured depletion-mode MOSFET. Referring to Figure 3, if the N-type dopant implantation angle is too small, the inversion layer 102 thickness will be insufficient. After the contact hole is formed and P-type dopant is implanted at the bottom of the contact hole, the inversion layer 102 at the junction of the N+ doped region 103 and the P-well 101, near the trench 104 (see the position shown in the dashed box in Figure 3), is at risk of being pinched off. Furthermore, due to the obstruction of the other sidewall of the trench 104, the inversion layer 102 cannot be formed at the bottom of the trench 104, which will also fail to meet the normally-on requirement of the device. In addition, since inversion layers need to be formed on all trench sidewalls, strip trench cells require two implantations of N-type dopant with angles, while grid trench cells require even more implantations of N-type dopant with angles to form an inversion layer. This increases the difficulty of the process, and the depth dose of the inversion layer is unstable.

[0007] Therefore, the manufacturing process of trench structure depletion-type MOSFETs urgently needs improvement. Summary of the Invention

[0008] One of the objectives of this invention is to provide a trench structure depletion MOSFET and its manufacturing method, which can avoid the method of forming an inversion layer by multiple angled injections, reduce the process difficulty of trench structure depletion MOSFET, and has high process stability.

[0009] To achieve the above objectives, the present invention provides a method for manufacturing a trench-structured depletion-type MOSFET. The method includes: providing a substrate; forming a well region of a first conductivity type in the substrate; forming a trench in the substrate, the trench penetrating the well region; and depositing an inversion layer of a second conductivity type within the trench, the inversion layer covering the inner surface of the trench, wherein the second conductivity type is opposite to the first conductivity type.

[0010] Optionally, in the step of depositing an inversion layer of the second conductivity type in the trench, the inversion layer is formed by an epitaxial growth process or a chemical vapor deposition process.

[0011] Optionally, the method of forming a second conductivity type inversion layer within the trench includes: depositing a second conductivity type inversion layer on the substrate, the inversion layer covering the top surface of the substrate and the inner surface of the trench; and removing the inversion layer on the top surface of the substrate while retaining the inversion layer within the trench.

[0012] Optionally, the method for manufacturing the trench structure depletion-type MOSFET further includes: after forming an inversion layer of a second conductivity type in the trench, forming a gate oxide layer on the substrate, the gate oxide layer covering the top surface of the inversion layer and the substrate; and forming a gate electrode in the trench.

[0013] Optionally, the width of the trench is D1, the thickness of the gate oxide layer is D2, and the thickness of the inversion layer is D3.

[0014] Optionally, in the step of forming the gate oxide layer on the substrate, the process temperature for forming the gate oxide layer is less than or equal to 1000°C.

[0015] Optionally, the method for manufacturing the trench structure depletion-type MOSFET further includes: forming a gate electrode in the trench, and then forming a second conductivity type doped region on top of the substrate; forming a dielectric layer on the substrate, the dielectric layer covering the top surface of the substrate and the gate electrode; etching the dielectric layer and the substrate to form a contact hole, the bottom surface of the contact hole being located in the well region; and forming a metal layer on the substrate, the metal layer filling the contact hole and at least partially covering the dielectric layer.

[0016] Optionally, after etching the dielectric layer and the substrate to form a contact hole and before forming a metal layer on the substrate, contact hole implantation is performed, and a dopant of a first conductivity type is implanted at the bottom of the contact hole.

[0017] Optionally, the width of the groove is greater than or equal to 0.3 μm.

[0018] Optionally, the method of forming a well region of a first conductivity type in the substrate includes: implanting a dopant of the first conductivity type on the top of the substrate; and performing a heat treatment to cause the dopant of the first conductivity type to diffuse toward the bottom of the substrate to form a well region of the first conductivity type.

[0019] In another aspect, the present invention provides a trench structure depletion MOSFET, which is manufactured using the above-described method for manufacturing a trench structure depletion MOSFET.

[0020] In the trench structure depletion MOSFET and its manufacturing method of the present invention, a second conductivity type inversion layer is deposited in the trench, avoiding the method of multiple angled injections to form the inversion layer, reducing the risk of pinch-off of the inversion layer, and the thickness and doping concentration of the inversion layer are easy to control, which helps to reduce the process difficulty of trench structure depletion MOSFET, improve the process stability of the device, and improve the reliability of the device; in addition, the manufacturing method of trench structure depletion MOSFET of the present application has no limitation on the cell structure of the device, and both strip trench cells and grid trench cells are applicable. Attached Figure Description

[0021] Figure 1 is a cross-sectional schematic diagram of a planar depletion-type MOSFET.

[0022] Figure 2 is a cross-sectional schematic diagram of a trench structure depletion-type MOSFET.

[0023] Figure 3 is a cross-sectional schematic diagram of another type of trench structure depletion-type MOSFET.

[0024] Figure 4 is a schematic flowchart of a method for manufacturing a trench structure depletion-type MOSFET according to an embodiment of the present invention.

[0025] Figures 5 to 15 are schematic diagrams of the step-by-step structure of a method for manufacturing a trench structure depletion-type MOSFET according to an embodiment of the present invention.

[0026] Figure reference numerals: (Figures 1 to 3) 101-P-well; 102-inversion layer; 103-N+ doped region; 104-trench; (Figures 5 to 15) 200-substrate; 201-substrate; 202-epitaxy layer; 203-well region; 204-hard mask layer; 205-trench; 206-inversion layer; 207-gate oxide layer; 208-gate electrode; 209-second conductivity type doped region; 210-dielectric layer; 211-contact hole; 212-metal layer. Detailed Implementation

[0027] The trench structure depletion-type MOSFET and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0028] Figure 4 is a schematic flowchart of a method for manufacturing a trench structure depletion-type MOSFET according to an embodiment of the present invention. As shown in Figure 4, the method for manufacturing the trench structure depletion-type MOSFET includes:

[0029] Step S1, provide the substrate;

[0030] Step S2, forming a well region of a first conductivity type in the substrate;

[0031] Step S3, forming a trench in the substrate, the trench penetrating the well region; and

[0032] Step S4: A second conductivity type inversion layer is deposited in the trench, the inversion layer covering the inner surface of the trench, the second conductivity type being the opposite of the first conductivity type.

[0033] Figures 5 to 15 are schematic diagrams illustrating the step-by-step structure of a trench structure depletion-type MOSFET manufacturing method according to an embodiment of the present invention. The manufacturing method of the trench structure depletion-type MOSFET of this application will be described below with reference to Figures 4, 5 to 15.

[0034] Referring to Figure 5, the substrate 200 provided in step S1 includes a substrate 201 and an epitaxial layer 202 located on the substrate 201. Since the epitaxial layer 202 is formed on the substrate 201 through an epitaxial process, the material composition and thickness of the epitaxial layer 202 can be precisely controlled, and the epitaxial layer 202 has fewer lattice defects. Subsequent fabrication of devices on the epitaxial layer 202 can improve device performance. In other embodiments, the substrate 200 may consist only of a substrate.

[0035] For example, in this embodiment, both the substrate 201 and the epitaxial layer 202 are made of silicon. In other embodiments, the substrate 200 may be made of semiconductor materials such as germanium, silicon-germanium alloy, silicon-carbon alloy, silicon-germanium-carbon alloy, gallium arsenide, indium arsenide, or indium phosphide.

[0036] As shown in Figure 6, step S2 is performed to form a well region 203 of the first conductivity type in the substrate 200.

[0037] For example, a method of forming a well region 203 of a first conductivity type in a substrate 200 may include: implanting a dopant of the first conductivity type on the top of the substrate 200; performing a heat treatment to cause the dopant of the first conductivity type to diffuse toward the bottom of the substrate to form a well region 203 of the first conductivity type.

[0038] In this embodiment, a well region 203 is formed on the epitaxial layer 202. The well region 203 extends from the top surface of the epitaxial layer 202 to the bottom surface of the epitaxial layer 202, but is not limited thereto.

[0039] It should be noted that in this embodiment, the injection of the well region 203 and the push-in junction completed by heat treatment are completed before the formation of the inversion layer, which can reduce the thermal process after the formation of the inversion layer.

[0040] As shown in Figure 7, step S3 is performed to form a trench 205 in the substrate 200. The trench 205 penetrates the well region 203, meaning that the depth of the trench 205 is greater than the depth of the well region 203.

[0041] Referring to Figure 7, the trench 205 is formed in the epitaxial layer 202, that is, the trench 205 does not penetrate the epitaxial layer 202.

[0042] For example, referring to FIG7, a method for forming a trench 205 in a substrate 200 may include: forming a hard mask layer 204 on the substrate 200, the hard mask layer 204 covering the top surface of the substrate 200; forming a patterned photoresist layer (not shown in the figure) on the hard mask layer 204, the patterned photoresist layer defining the formation area of ​​the trench 205; using the patterned photoresist layer as a mask, etching the hard mask layer 204 to expose the surface of the substrate 200; and then using the hard mask layer 204 as a mask, etching the substrate 200 to form the trench 205.

[0043] As shown in Figures 8 and 9, step S4 is performed to deposit an inversion layer 206 of a second conductivity type in the trench 205. The inversion layer 206 covers the inner surface of the trench 205, and the second conductivity type is opposite to the first conductivity type.

[0044] Specifically, the method for forming a second conductivity type inversion layer 206 in trench 205 may include: as shown in FIG8, depositing and forming a second conductivity type inversion layer 206 on substrate 200, wherein the inversion layer 206 covers the top surface of substrate 200 and covers the inner surface of trench 205; as shown in FIG9, removing the inversion layer 206 on the top surface of substrate 200 while retaining the inversion layer 206 in trench 205.

[0045] In this embodiment, the inversion layer 206 on the top surface of the substrate 200 is removed and only the inversion layer 206 in the trench 205 is retained, so as not to affect the chip terminal structure.

[0046] In this embodiment, referring to FIG8, when the inversion layer 206 is formed, the hard mask layer 204 can still remain on the substrate 200, that is, the original inversion layer 206 can cover the hard mask layer 204. When removing the inversion layer 206 on the top surface of the substrate 200, the hard mask layer 204 on the top surface of the substrate 200 can be removed simultaneously. Exemplarily, a chemical mechanical polishing (CMP) process can be used to remove the inversion layer 206 and the hard mask layer 204 on the top surface of the substrate 200, with the CMP stopping at the top surface of the substrate 200. In other embodiments, the hard mask layer 204 can also be removed after the trench 205 is formed and before the inversion layer 206 is formed.

[0047] In this embodiment, the first conductivity type is P-type and the second conductivity type is N-type. In other embodiments, the first conductivity type can be N-type and the second conductivity type can be P-type.

[0048] It is important to emphasize that in step S4, a new semiconductor material layer is deposited within trench 205 as an inversion layer 206. The material of the inversion layer 206 includes, but is not limited to, silicon. The inversion layer 206 contains an N-type dopant, meaning it is a doped semiconductor material layer. For example, the N-type dopant in the inversion layer 206 can be As. As diffuses slowly and is easily controlled; using an As-doped semiconductor material layer as the inversion layer can improve its reliability and thus enhance device reliability. In other embodiments, the dopant in the inversion layer 206 can be P or Sb, etc.

[0049] In this embodiment, the doping concentration of the inversion layer 206 is greater than that of the well region 203. The concentration and thickness of the inversion layer 206 can be adjusted according to the design of the trench structure depletion MOSFET to enable the trench structure depletion MOSFET to achieve the designed threshold voltage (Vth). The well region 203 can serve as the body region of the trench structure depletion MOSFET, for example, a P-type well region can serve as the P-type body region (P Body) of the trench structure depletion MOSFET.

[0050] In this embodiment, the inversion layer 206 can be formed by epitaxial growth (EPI) or chemical vapor deposition (CVD). Examples of epitaxial growth processes include vapor phase epitaxy (VPE), solid phase epitaxy (SPE), liquid phase epitaxy (LPE), or molecular beam epitaxy (MBE). Examples of chemical vapor deposition (CVD) processes include plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), and low pressure chemical vapor deposition (LPCVD).

[0051] In the process of depositing the inversion layer 206, the thickness and doping concentration of the inversion layer 206 can be controlled by controlling the process conditions of the deposition process.

[0052] After the inversion layer 206 is formed in the trench 205, as shown in FIG10, a gate oxide layer 207 is formed on the substrate 200, and the gate oxide layer 207 covers the inversion layer 206 and the top surface of the substrate 200.

[0053] For example, the material of the gate oxide layer 207 includes, but is not limited to, silicon oxide. The gate oxide layer 207 can be formed using a chemical vapor deposition process.

[0054] In this embodiment, in the step of forming the gate oxide layer 207, the process temperature used to form the gate oxide layer 207 is less than or equal to 1000°C, which can reduce the impact of the process thermal process on the inversion layer 206.

[0055] Referring to Figure 10, in this embodiment, the inversion layer 206 and the gate oxide layer 207 will not fill the trench 205. That is, after the inversion layer 206 and the gate oxide layer 207 are formed, the trench 205 still retains space for the formation of the gate electrode.

[0056] For example, referring to Figure 10, the width (i.e., feature size CD) of the trench 205 is D1, the thickness of the gate oxide layer 207 is D2, and the thickness of the inversion layer 206 is D3. This is to ensure sufficient formation space for the gate electrode. The 0.1μm is the reserved width, which can be adjusted according to the actual situation.

[0057] To prevent the inversion layer 206 and the gate oxide layer 207 from completely filling the trench 205, the width of the trench 205 should not be too small. For example, the width of the trench 205 is greater than or equal to 0.3 μm, but is not limited thereto.

[0058] As shown in Figure 11, a gate electrode 208 is formed within a trench 205. The gate electrode 208 covers the interior of the trench 205 and the gate oxide layer 207 within the trench 205. Exemplarily, the material of the gate electrode 208 includes, but is not limited to, polycrystalline silicon.

[0059] An exemplary method for forming a gate electrode 208 within a trench 205 includes: forming a gate material layer on a substrate 200, the gate material layer covering the top surface of the substrate 200 and filling the trench 205; performing back etching on the gate material layer to remove the gate material layer on the top surface of the substrate 200, while retaining at least a portion of the gate material layer within the trench 205 as the gate electrode 208.

[0060] Referring to Figure 11, in this embodiment, the top surface of the gate electrode 208 may be slightly lower than the top surface of the gate oxide layer 207 on the top surface of the substrate, but is not limited thereto.

[0061] As shown in Figure 12, a second conductivity type doped region 209 is formed on the top of the substrate 200. For example, the second conductivity type doped region 209 is an N+ doped region, but it is not limited thereto.

[0062] In this embodiment, in the step of forming a well region 203 of the first conductivity type in the substrate 200, the well region 203 extends from the top surface of the epitaxial layer 202 to the bottom surface of the epitaxial layer 202, and a doped region 209 of the second conductivity type is formed on the top of the well region 203. In other embodiments, in the step of forming a well region 203 of the first conductivity type in the substrate 200, the well region 203 may be formed within the epitaxial layer 202, that is, there is a gap greater than 0 between the top surface of the well region 203 and the top surface of the epitaxial layer 202; subsequently, the doped region 209 of the second conductivity type is directly formed on the top of the substrate 200, and the bottom surface of the doped region 209 is in contact with the top surface of the well region 203.

[0063] As shown in FIG13, a dielectric layer 210 is formed on a substrate 200, the dielectric layer 210 covering the top surface of the substrate 200, the gate electrode 208 and the gate oxide layer 207.

[0064] For example, the material of the dielectric layer 210 includes, but is not limited to, silicon oxide.

[0065] As shown in Figure 14, the etching medium layer 210 and the substrate 200 form a contact hole 211, and the bottom surface of the contact hole 211 is located in the well region 203.

[0066] After the contact hole 211 is formed, contact hole injection can be performed to inject a dopant of a first conductivity type, such as a P-type dopant, into the bottom of the contact hole 211 to increase the concentration of the P-type dopant at the bottom of the contact hole 211, thereby reducing the conduction resistance between the metal material subsequently filled in the contact hole 211 and the substrate 200.

[0067] As shown in Figure 15, a metal layer 212 is formed on the substrate 200. The metal layer 212 fills the contact hole 211 and covers the inner surface of the contact hole 211. The metal layer 212 also covers at least part of the dielectric layer 210.

[0068] In one embodiment, the cell of the trench structure depletion-type MOSFET is a strip trench cell. Specifically, the trench 205 can be an elongated trench, and multiple gate electrodes 208 are formed within the trench 205, with the multiple gate electrodes 208 spaced apart along the elongation direction of the trench 205. In another embodiment, the cell of the trench structure depletion-type MOSFET is a grid trench cell. Specifically, in the step of forming the trench 205 in the substrate 200, multiple trenches 205 are formed in the substrate 200, and the multiple trenches 205 are connected in a grid pattern; in the step of forming the gate electrode 208 within the trench 205, one gate electrode 208 is formed within each trench 205. It should be noted that the manufacturing method of the trench structure depletion-type MOSFET of this application is not limited to the cell structure of the device; both strip trench cells and grid trench cells are applicable.

[0069] This embodiment also provides a trench structure depletion-type MOSFET. Referring to FIG15, the trench structure depletion-type MOSFET includes a substrate 200 and an inversion layer 206 of a second conductivity type.

[0070] Specifically, the substrate 200 may include a substrate 201 and an epitaxial layer 202, but is not limited thereto.

[0071] A well region 203 of a first conductivity type is formed in the substrate 200. A doped region 209 of a second conductivity type is also formed on the top of the substrate 200, the second conductivity type doped region 209 being located above and connected to the well region 203. For example, the first conductivity type is P-type and the second conductivity type is N-type. For example, the second conductivity type doped region 209 is an N+ doped region.

[0072] A trench 205 is formed in the substrate 200, and the trench 205 penetrates the second conductivity type doped region 209 and the well region 203.

[0073] An inversion layer 206 is deposited within the trench 205, covering the inner surface of the trench 205.

[0074] A gate oxide layer 207 is formed on the substrate 200, which covers the inversion layer 206 and at least covers a portion of the substrate surface on the side of the trench 205.

[0075] A gate electrode 208 is also formed within the trench 205. Specifically, the gate electrode 208 is located within the space defined by the gate oxide layer 207 within the trench 205.

[0076] A dielectric layer 210 is also formed on the substrate 200, which covers part of the top surface of the substrate 200, the gate electrode 208, and the gate oxide layer 207. A contact hole 211 is formed in the dielectric layer 210, and the bottom surface of the contact hole 211 is located in the well region 203.

[0077] A metal layer 212 is also formed on the dielectric layer 210. The metal layer 212 fills the contact hole 211 and covers the inner surface of the contact hole 211. The metal layer 212 is electrically connected to the well region 203.

[0078] In the trench structure depletion MOSFET and its manufacturing method of the present invention, by depositing an inversion layer 206 of the second conductivity type in the trench 205, the method of forming the inversion layer by multiple angled injections is avoided, which reduces the risk of pinch-off of the inversion layer 206. Moreover, the thickness and doping concentration of the inversion layer 206 are easy to control, which helps to reduce the process difficulty of the trench structure depletion MOSFET, improve the process stability of the device, and improve the reliability of the device. In addition, the manufacturing method of the trench structure depletion MOSFET of the present application has no limitation on the cell structure of the device, and both strip trench cells and grid trench cells are applicable.

[0079] It should be noted that this instruction manual uses a progressive approach, with later descriptions focusing on the differences from earlier descriptions. Similarities and similarities between different sections can be found by referring to each other.

[0080] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A manufacturing method of a trench structure depletion mode MOSFET, characterized by, The method comprises: providing a substrate; forming a well region of a first conductivity type in the substrate; forming a trench in the substrate, the trench penetrating the well region; and depositing a gate oxide layer on the substrate, the gate oxide layer covering the trench and a top surface of the substrate; and forming a gate electrode in the trench.

2. The trench-structured depletion-mode MOSFET manufacturing method according to claim 1, wherein In the step of depositing a gate oxide layer on the substrate, a process temperature for forming the gate oxide layer is less than or equal to 1000℃.

3. The trench-structured depletion-mode MOSFET manufacturing method according to claim 1, wherein The method further comprises: after forming the gate electrode in the trench, forming a doped region of a second conductivity type on a top portion of the substrate; forming a dielectric layer on the substrate, the dielectric layer covering a top surface of the substrate and the gate electrode; 4. The trench-structured depletion-mode MOSFET manufacturing method according to claim 1, wherein etching the dielectric layer and the substrate to form a contact hole, a bottom surface of the contact hole being located in the well region; and forming a metal layer on the substrate, the metal layer filling the contact hole and covering at least a portion of the dielectric layer. After etching the dielectric layer and the substrate to form the contact hole, and before forming the metal layer on the substrate, a contact hole implantation is performed, a doped substance of a first conductivity type being implanted at a bottom portion of the contact hole. The trench has a width greater than or equal to 0.3μm.

5. The trench-structured depletion-mode MOSFET manufacturing method according to claim 4, wherein The width of the trench is D1, the thickness of the gate oxide layer is D2, the thickness of the inversion layer is D3, 6. The trench-structured depletion-mode MOSFET manufacturing method according to claim 4, wherein The method of forming a well region of a first conductivity type in a substrate comprises:

7. The trench-structured depletion-mode MOSFET manufacturing method according to claim 4, wherein implanting a doped substance of a first conductivity type on a top portion of the substrate; and performing a heat treatment so that the doped substance of the first conductivity type diffuses toward a bottom portion of the substrate to form a well region of the first conductivity type. The trench is a long strip-shaped trench, and a plurality of gate electrodes are formed in the trench and are arranged at intervals along a direction in which the trench is elongated. In the step of forming a trench in a substrate, a plurality of trenches are formed in the substrate, and the plurality of trenches are connected to form a grid pattern; and in the step of forming a gate electrode in the trench, one gate electrode is formed in each of the trenches. The doped concentration of the gate oxide layer is greater than the concentration of the well region. The substrate comprises a substrate and an epitaxial layer on the substrate, and the well region is formed on the epitaxial layer and extends from a top surface of the epitaxial layer to a bottom surface of the epitaxial layer.

8. The trench-structured depletion-mode MOSFET manufacturing method according to claim 7, wherein The trench-structured depletion-mode MOSFET is manufactured by the method of manufacturing a trench-structured depletion-mode MOSFET according to any one of claims 1 to 14, and comprises:

9. The trench-structured depletion-mode MOSFET manufacturing method according to claim 1, wherein a substrate in which a well region of a first conductivity type is formed; 10. The trench-structured depletion-mode MOSFET manufacturing method according to Claim 1, wherein ​ ​ ​ 11. The trench-structured depletion-mode MOSFET manufacturing method according to claim 4, wherein ​ 12. The trench-structured depletion-mode MOSFET manufacturing method according to claim 4, wherein ​ 13. The trench-structured depletion-mode MOSFET manufacturing method according to claim 1, wherein ​ 14. The trench-structured depletion-mode MOSFET manufacturing method according to claim 1, wherein ​ 15. A trench-structured depletion-mode MOSFET, characterized by, ​ ​ A trench is formed in the substrate, the trench penetrating the well region; and A second-conductivity-type inversion layer is formed in the trench, the inversion layer covering an inner surface of the trench, the second conductivity type being opposite to the first conductivity type.

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