Packaged chip, circuit board assembly, and electronic device

Abstract

A packaged chip, a circuit board assembly, and an electronic device, related to the technical field of chips, and solving the problem that existing chips using jet cooling are prone to surface corrosion. A packaged chip (20S) comprises a substrate (1), a bare die (2), and a first anti-corrosion layer (3). The bare die is disposed on the substrate. A surface on a side of the bare die distant from the substrate can be used for contacting cooling liquid sprayed by a jet cooling apparatus (30S), so as to cool the bare die during operation. The first anti-corrosion layer at least covers the surface on the side of the bare die distant from the substrate. The first anti-corrosion layer can protect the bare die, preventing the problem of surface corrosion of the bare die caused by long-term flushing by a coolant, and improving long-term use reliability of the bare die. The thermal conductivity of the first anti-corrosion layer is greater than 10w / m·k, ensuring that the first anti-corrosion layer does not affect heat dissipation performance of the bare die.

Description

A packaged chip, circuit board assembly and electronic device

[0001] This application claims priority to Chinese Patent Application No. 202410947090.9, filed on July 15, 2024, entitled "A packaged chip, circuit board assembly and electronic device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and in particular to a packaged chip, circuit board assembly, and electronic device. Background Technology

[0003] As the power consumption and power density of chips in communication equipment continue to increase, the thermal resistance of packaged chips accounts for 30% to 40% of the total thermal resistance of communication equipment. In order to reduce the thermal resistance of packaged chips, jet cooling can be used to cool the chips.

[0004] Coolant is sprayed at high speed onto the chip surface to dissipate heat and improve heat dissipation performance, resulting in good heat dissipation for the chip. Therefore, it can solve the problem of thermal interface material (TIM) delamination caused by bending at different temperatures due to differences in the coefficient of thermal expansion (CTE) of various film layers in various packaged chips.

[0005] However, the chip surface is prone to surface corrosion due to long-term exposure to coolant, which reduces the airtightness between the chip and the jet cooling device and makes the coolant prone to leakage. Summary of the Invention

[0006] This application provides a packaged chip, circuit board assembly, and electronic device, which solves the problem of surface corrosion that easily occurs when using jet cooling for existing chips.

[0007] To achieve the above objectives, this application adopts the following technical solution:

[0008] Firstly, embodiments of this application provide a packaged chip, specifically a lidless package. The packaged chip includes a substrate, a bare die, and a first anti-corrosion layer. The bare die is disposed on the substrate. The surface of the bare die away from the substrate can be used to contact the coolant sprayed by the jet cooling device to cool the bare die during operation. The first anti-corrosion layer covers at least the surface of the bare die away from the substrate. The first anti-corrosion layer protects the surface of the bare die that is washed by the coolant, preventing surface corrosion caused by long-term exposure to the coolant and improving the long-term reliability of the bare die. This ensures good airtightness between the bare die and the jet cooling device, reducing the likelihood of coolant leakage. Furthermore, the thermal conductivity of the first anti-corrosion layer is greater than 10 W / m·K, ensuring that the first anti-corrosion layer does not affect the heat dissipation performance of the bare die.

[0009] Therefore, in some embodiments of this application, the material of the first anti-corrosion layer includes any one of aluminum oxide, nickel, and chromium. These materials have good anti-corrosion properties and high thermal conductivity, which can meet the heat dissipation requirements of the bare chip.

[0010] In other embodiments of this application, the first anti-corrosion layer includes a first silicon oxide layer and a first metal layer stacked together, with the first metal layer located between the bare die and the first silicon oxide layer. The first silicon oxide layer has good anti-corrosion performance, and the first metal layer has high thermal conductivity, which can meet the heat dissipation requirements of the bare die.

[0011] Furthermore, in some embodiments of this application, the thickness of the area of ​​the first anti-corrosion layer covering the surface of the bare chip away from the substrate is 200 nm, so as to ensure the anti-corrosion effect on the surface of the bare chip, while the heat dissipation effect of the bare chip is good.

[0012] It is important to note that if the jet cooling device is directly and sealed to the side of the packaged chip furthest from the substrate, only the surface of the bare chip furthest from the substrate will come into contact with the coolant. In this case, the first anti-corrosion layer only needs to cover this side of the chip. However, if the jet cooling device is directly mounted on the outside of the packaged chip, the coolant may also come into contact with the outer perimeter of the packaged chip. Therefore, the first anti-corrosion layer also needs to cover the outer perimeter of the packaged chip.

[0013] In some embodiments of this application, the packaged chip further includes a molding compound, which is also disposed on the substrate. Furthermore, the molding compound is diffracted and filled around the outer periphery of the bare chip.

[0014] For applications where the jet cooling device is directly sealed and connected above the packaged chip, the aforementioned first anti-corrosion layer also covers the surface of the molding compound away from the substrate.

[0015] For applications where the jet cooling device is directly covered on the outside of the packaged chip, the aforementioned first anti-corrosion layer also covers the surface of the molding compound away from the substrate, the outer wall of the molding compound, and the outer wall of the substrate.

[0016] In this context, compared to the coolant erosion rate of the surface of the molding compound and the bare die away from the substrate, the coolant erosion rate of the outer walls of the molding compound and the substrate is lower. Therefore, the thickness of the area of ​​the first anti-corrosion layer covering the outer walls of the molding compound and the substrate can be less than the thickness of the area covering the surface of the molding compound and the bare die away from the substrate. The thickness of the area of ​​the first anti-corrosion layer covering the surface of the molding compound away from the substrate can also be 200 nm to ensure anti-corrosion effect on the surface of the molding compound without affecting its heat dissipation.

[0017] Therefore, in some embodiments of this application, the thickness of the area of ​​the first anti-corrosion layer covering the outer wall of the molding compound and the outer wall of the substrate is 10 nm, which not only ensures the protection effect on the outer wall of the molding compound and the outer wall of the substrate, but also improves the heat dissipation performance of the outer wall of the molding compound and the outer wall of the substrate.

[0018] In some application scenarios, the packaged chip in this application embodiment also includes a protective ring, which is disposed on the substrate and located on the outside of the molding compound.

[0019] For jet cooling devices that are directly and sealed above the packaged chip, the aforementioned first anti-corrosion layer also covers the surface of the protective ring away from the substrate.

[0020] For applications where the jet cooling device is directly covered on the outside of the packaged chip, the first anti-corrosion layer also covers the surface of the protective ring away from the substrate, the outer wall of the protective ring, and the outer wall of the substrate.

[0021] Similarly, in some embodiments of this application, the thickness of the area of ​​the first anti-corrosion layer covering the outer wall of the protective ring and the outer wall of the substrate is 10 nm, which not only ensures the protection effect on the outer wall of the protective ring and the outer wall of the substrate, but also does not affect the heat dissipation performance of the protective ring and the substrate.

[0022] Secondly, embodiments of this application also include a circuit board assembly, comprising a circuit board, a packaged chip as described in the above embodiments, and a jet cooling device. The packaged chip is disposed on the circuit board. The jet cooling device is sealed and connected to the side of the packaged chip away from the circuit board. Alternatively, the jet cooling device is sealed and covered outside the packaged chip. Furthermore, a coolant channel is formed within the jet cooling device. At least the surface of the packaged chip away from the circuit board is located within the coolant channel. Since the packaged chip in the circuit board assembly of this application has the same structure as the packaged chip described in the above embodiments, both can solve the same technical problems and achieve the same technical effects, further details are omitted here.

[0023] Based on this, in some embodiments of this application, the aforementioned jet cooling device includes a jet cooling device body and a second anti-corrosion layer. The coolant flow channel is formed within the jet cooling device body. The second anti-corrosion layer covers a portion of the inner wall of the jet cooling device body on which the coolant flow channel is formed. This further avoids corrosion caused by prolonged contact between the coolant and the jet cooling device, preventing a decrease in the hermeticity between the jet cooling device and the bare chip, and preventing coolant leakage.

[0024] Furthermore, in some embodiments of this application, the material of the second anti-corrosion layer includes any one of alumina, nickel, and chromium. These materials have good anti-corrosion properties and high thermal conductivity.

[0025] In other embodiments of this application, the second anti-corrosion layer comprises a second silicon oxide layer and a second metal layer stacked together, with the second metal layer located between the jet cooling device body and the second silicon oxide layer. The second silicon oxide layer has good anti-corrosion properties, the second metal layer has high thermal conductivity, and the jet cooling device body has good heat dissipation performance.

[0026] Based on the aforementioned second anti-corrosion layer, in some embodiments of this application, the thickness of the second anti-corrosion layer is 10 nm, which not only ensures the anti-corrosion effect on the inner wall of the jet cooling device body, but also ensures good heat dissipation performance of the jet cooling device body.

[0027] Thirdly, embodiments of this application also include an electronic device, comprising a housing and the circuit board assembly described in the above embodiments. The circuit board assembly is disposed within the housing. Since the circuit board assembly in the electronic device of this application has the same structure as the circuit board assembly described in the above embodiments, and both can solve the same technical problems and achieve the same technical effects, further details are omitted here. Attached Figure Description

[0028] To illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be described below.

[0029] Figure 1 is a three-dimensional structural diagram of an electronic device, specifically a laptop computer, according to an embodiment of this application.

[0030] Figure 2 is a schematic diagram of the circuit board assembly according to an embodiment of this application;

[0031] Figure 3 is a partial cross-sectional schematic diagram of the circuit board assembly according to an embodiment of this application;

[0032] Figure 4 is a cross-sectional schematic diagram of the packaged chip according to an embodiment of this application;

[0033] Figure 5 is a cross-sectional schematic diagram of the jet cooling device according to an embodiment of this application;

[0034] Figure 6 is a cross-sectional schematic diagram of the packaged chip and jet cooling device assembled according to an embodiment of this application;

[0035] Figure 7 is a cross-sectional schematic diagram of a jet cooling device according to an embodiment of this application, which is disposed on a packaged chip with molding compound and assembled with a motherboard;

[0036] Figure 8 is a cross-sectional schematic diagram of the jet cooling device of this application, which is covered by a packaged chip with molding compound and assembled with a motherboard.

[0037] Figure 9 is a cross-sectional schematic diagram of a jet cooling device according to an embodiment of this application, which is mounted on a packaged chip with a protective ring and assembled with a motherboard.

[0038] Figure 10 is a cross-sectional schematic diagram of the jet cooling device of this application being covered by a plastic encapsulation chip with a protective ring and assembled with a motherboard.

[0039] Figure 11 is a schematic diagram of the assembly structure of a bare chip and a first anti-corrosion layer having a first silicon oxide layer and a first metal layer according to an embodiment of this application;

[0040] Figure 12 is one of the thickness marking diagrams of the bare chip, molding compound and first anti-corrosion layer assembly in an embodiment of this application;

[0041] Figure 13 is one of the thickness marking diagrams of the bare chip, molding compound, protective ring and first anti-corrosion layer assembly in an embodiment of this application;

[0042] Figure 14 is a second thickness diagram of the bare chip, molding compound and first anti-corrosion layer assembly according to an embodiment of this application;

[0043] Figure 15 is a second thickness diagram showing the assembly of the bare chip, molding compound, protective ring, and first anti-corrosion layer in an embodiment of this application.

[0044] Figure 16 is a cross-sectional schematic diagram of the packaged chip and the jet cooling device with a second anti-corrosion layer according to an embodiment of this application.

[0045] Figure 17 is a schematic cross-sectional view of the assembly of the jet cooling device body and the second anti-corrosion layer in the jet cooling device of the embodiment of this application.

[0046] Reference numerals: 1000-Notebook computer; 100-Display screen; 200-Chassis; 300-Keyboard; 400-Circuit board assembly; 10-Motherboard; 20-Chip; 20S-Packaged chip; 1-Substrate; 1a-Outer wall of substrate; 2-Bare chip; 2a-Upper surface of bare chip; 3-First anti-corrosion layer; 31-First silicon oxide layer; 32-First metal layer; 4-Molding material; 4a-Upper surface of molding material; 4b-Outer wall of molding material; 5-Protective ring; 5a-Upper surface of protective ring; 5b-Outer wall of protective ring; 30-Heat sink; 30S-Jet cooling device; 301-Jet cooling device body; 301A-Coolant channel; 3011-Nozzle; 302-Second anti-corrosion layer; 3021-Second silicon oxide layer; 3022-Second metal layer. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0048] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0049] Furthermore, in this application, directional terms such as "upper," "lower," "left," "right," "horizontal," and "vertical" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0050] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can refer to a mechanical or physical connection. It can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. It can also be understood as the physical contact and electrical conduction of components, or as the form of connection between different components in a circuit structure through physical lines capable of transmitting electrical signals, such as PCB copper foil or wires.

[0051] This application provides an electronic device that may include a mobile phone, tablet computer, laptop computer, personal digital assistant (PDA), camera, personal computer, laptop computer, in-vehicle equipment, wearable device, augmented reality (AR) glasses, AR headset, virtual reality (VR) glasses, VR headset, router, server, switch, and other devices. The embodiments of this application do not impose special limitations on the specific form of the above-mentioned electronic device. For ease of explanation, the following description uses the laptop computer shown in Figure 1 as an example.

[0052] Please refer to Figures 1 and 2. Figure 1 is a perspective view of a laptop computer provided in some embodiments of this application. Figure 2 is a schematic diagram of the circuit board assembly in the electronic device according to an embodiment of this application. As can be seen from the above, the laptop computer 1000 may include components such as a display screen 100, a chassis 200, a keyboard 300, a circuit board assembly 400, and a battery.

[0053] The display screen 100 and the chassis 200 can be connected in a rotatable manner (e.g., hinged). The keyboard 300 can be embedded in the chassis 200. The circuit board assembly 400 and the battery are disposed within the chassis 200. As shown in Figures 2 and 3, the circuit board assembly 400 includes a motherboard 10 (specifically a printed circuit board), and various electronic components disposed on the motherboard 10, such as chips 20, heat sinks 30, hard drives, memory, various interfaces, expansion slots, sound cards, and power supplies.

[0054] It is understood that Figures 1 and 2 only schematically show some of the components included in the electronic device 1000, and the actual shape, size, location and construction of these components are not limited by Figures 1 and 2.

[0055] The circuit board assembly 400 contains various chips in different package types. For example, these chips may include those with lidded packages and those with lidless packages (as shown in Figure 3). As shown in Figure 3, a heat sink 30 can be disposed on the high-power chip 20 to dissipate heat. This heat sink 30 can be either an air-cooled or liquid-cooled device. In the embodiments of this application, the heat sink 30 is a jet cooling device, which uses high-speed jets of coolant to cool the lidless packaged chip 20.

[0056] However, the chip 20 is prone to surface corrosion due to long-term exposure to coolant, which reduces the airtightness between the chip 20 and the jet cooling device 30S, leading to coolant leakage. Therefore, this application provides a structurally improved packaged chip 20S. Specifically, the packaged chip 20S employs a lidless package. Referring to FIG4, the packaged chip 20S includes a substrate 1, a bare die 2, and a first anti-corrosion layer 3. The bare die 2 is disposed on the substrate 1.

[0057] The aforementioned first anti-corrosion layer 3 has a thermal conductivity greater than 10 W / m·K, indicating a relatively fast heat conduction rate. Depending on the jet cooling device 30S used in the packaged chip 20S, the first anti-corrosion layer 3 covers different areas of the bare chip 2.

[0058] It should be noted that, referring to Figure 5, the jet cooling device 30S includes a jet cooling device body 301, within which a coolant flow channel 301A is formed. A nozzle 3011 is disposed within the coolant flow channel 301A, which can spray coolant onto the surface of the bare chip 2. The coolant used in the jet cooling device 30S can be deionized water or a mixture of deionized water and anhydrous ethanol; this application does not impose any limitations on this.

[0059] If the jet cooling device 30S is directly and sealed above the packaged chip 20S, and only the surface of the bare chip 2 away from the substrate 1 (the upper surface 2a of the bare chip 2 shown in FIG. 6) is located within the coolant flow channel 301A, then in some embodiments of this application, the upper surface 2a of the bare chip 2 can be used to contact the coolant sprayed by the jet cooling device 30S to cool the bare chip 2 during operation.

[0060] The first anti-corrosion layer 3 protects the bare chip 2, preventing surface corrosion caused by long-term exposure to coolant and improving its long-term reliability. This ensures good airtightness between the bare chip 2 and the jet cooling device 30S, minimizing coolant leakage. Furthermore, the first anti-corrosion layer 3 has high thermal conductivity and does not affect the heat dissipation performance of the jet cooling device 30S on the bare chip 2. It should be noted that the top layer material of the bare chip 2 can include any of silicon, epoxy resin, stainless steel, aluminum, or copper, which can increase the adhesion of the first anti-corrosion layer 3 to the bare chip 2.

[0061] If the jet cooling device 30S is directly mounted on the outside of the packaged chip 20S (the jet cooling device 30S can be directly installed on the aforementioned motherboard 10) and is sealed to the packaged chip 20S, then a portion of the outer peripheral wall and upper surface of the packaged chip 20S are located within the coolant flow channel 301A, and the outlet of the nozzle 3011 can face the upper surface 2a of the bare chip 2. Therefore, in some other embodiments of this application, the first anti-corrosion layer 3 covers a portion of the outer peripheral wall and upper surface of the packaged chip 20S.

[0062] Based on the above structure, in some embodiments of this application, the packaged chip 20S further includes molding compound 4 as shown in FIG. 7, which is also disposed on the substrate 1. Furthermore, the molding compound 4 diffracts and fills the outer periphery of the bare chip 2, providing advantages such as environmental isolation, protection of the bare chip 2, good electrical insulation, and convenient installation of other components.

[0063] For applications where the jet cooling device 30S is directly and sealed above the packaged chip 20S, the jet cooling device 30S can be sealed onto the molding compound 4. The first anti-corrosion layer 3 can also cover the surface of the molding compound 4 away from the substrate 1 (the upper surface 4a of the molding compound 4 shown in FIG. 7).

[0064] In the application scenario where the jet cooling device 30S is directly covered outside the packaged chip 20S, as shown in Figure 8, the first anti-corrosion layer 3 also covers the upper surface 4a and the outer side wall 4b of the molding compound 4, as well as the outer side wall 1a of the substrate 1.

[0065] In other embodiments of this application, the packaged chip 20S further includes a guard ring 5 as shown in FIG. 9. The guard ring 5 is disposed on the substrate 1 and located outside the molding compound 4. The guard ring 5 serves both as the bulk end of various devices in the bare chip 2 and as isolation between devices in the integrated circuit (IP) to prevent noise from affecting the devices in the integrated circuit.

[0066] Similarly, for the jet cooling device 30S directly sealed and connected above the packaged chip 20S, the first anti-corrosion layer 3 also covers the side surface of the protective ring 5 away from the substrate 1 (the upper surface 5a of the protective ring 5 shown in FIG9).

[0067] In the application scenario where the jet cooling device 30S is directly covered on the outside of the packaged chip 20S, as shown in Figure 10, the first anti-corrosion layer 3 also covers the upper surface 5a and outer wall 5b of the protective ring 5, as well as the outer wall 1a of the substrate 1.

[0068] The first anti-corrosion layer 3 can be made of various materials. In some embodiments of this application, the material of the first anti-corrosion layer 3 includes any one of alumina, nickel, and chromium. These materials have good anti-corrosion properties and high thermal conductivity, which can meet the heat dissipation requirements of the bare chip 2.

[0069] In other embodiments of this application, as shown in FIG11, the first anti-corrosion layer 3 includes a first silicon oxide layer 31 and a first metal layer 32 stacked together, with the first metal layer 32 located between the bare chip 2 and the first silicon oxide layer 31. The first metal layer 32 can be made of any material selected from copper, stainless steel, and aluminum. The first silicon oxide layer 31 has good anti-corrosion performance, and the first metal layer 32 has high thermal conductivity, which can meet the heat dissipation requirements of the bare chip 2.

[0070] Furthermore, the thickness of the first anti-corrosion layer 3 varies in different areas to meet different waterproofing requirements. Since the upper surface 2a of the bare chip 2, the upper surface 4a of the molding compound 4, and the upper surface 5a of the protective ring 5 are directly opposite the nozzle 3011, the coolant exerts a significant impact on these surfaces. Therefore, a higher level of waterproofing is required.

[0071] Based on this, in some embodiments of this application, referring to FIG12, the thickness T1 of the first anti-corrosion layer 3 covering the area of ​​the upper surface 2a of the bare chip 2 is 200 nm, ensuring good heat dissipation of the bare chip 2 while guaranteeing its protective effect. For the packaged chip 20S with molding compound 4, the thickness T2 of the first anti-corrosion layer 3 covering the area of ​​the upper surface 4a of the molding compound 4 is also 200 nm, ensuring good protection of the molding compound 4 without affecting its heat dissipation. For the packaged chip 20S with protective ring 5, referring to FIG13, the thickness T3 of the first anti-corrosion layer 3 covering the area of ​​the upper surface 4a of the protective ring 5 is also 200 nm, ensuring good protection of the protective ring 5 without affecting its heat dissipation.

[0072] The coolant flows at a low velocity along the outer wall of the packaged chip 20S, so a high waterproof rating is not required. Based on this, in some embodiments of this application, referring to FIG14, the thickness T4 of the first anti-corrosion layer 3 covering the area of ​​the outer wall 4b of the molding compound 4 and the thickness T5 covering the area of ​​the outer wall 1a of the substrate 1 are both 10 nm. This not only ensures protection for the outer wall 4b of the molding compound 4 and the outer wall 1a of the substrate 1, but also does not affect the heat dissipation of the molding compound 4. For the packaged chip 20S with a protective ring 5, referring to FIG15, the thickness T6 of the first anti-corrosion layer 3 covering the area of ​​the outer wall 5b of the protective ring 5 is also 10 nm. This not only ensures protection for the outer wall 5b of the protective ring 5, but also does not affect the heat dissipation performance of the protective ring 5.

[0073] Considering that the wall surface of the coolant flow channel 301A formed on the body of the jet cooling device 30S may also suffer from surface corrosion due to long-term erosion, in some embodiments of this application, the jet cooling device 30S further includes a second anti-corrosion layer 302 as shown in FIG16. The second anti-corrosion layer 302 covers part of the inner wall of the jet cooling device body 301 that forms the coolant flow channel 301A. The second anti-corrosion layer 302 can protect the inner wall of the jet cooling device body 301, avoiding corrosion caused by long-term contact between the coolant and the inner wall of the jet cooling device body 301, which would lead to a decrease in the airtightness of the jet cooling device 30S and the packaged chip 20S, or even the problem of coolant leakage.

[0074] It should be noted that in this application, the jet cooling device body 301 is a general term for all structures of the jet cooling device 30S except for the second anti-corrosion layer 302. In some embodiments of this application, the material used for the inner wall of the portion forming the coolant flow channel 301A of the jet cooling device body 301 is any one of stainless steel, copper, or aluminum, which can increase the adhesion of the second anti-corrosion layer 302 to the inner wall of the coolant flow channel 301A.

[0075] The second anti-corrosion layer 302 described above can also be made of various materials. In some embodiments of this application, the material of the second anti-corrosion layer 302 includes any one of alumina, nickel, and chromium. These materials have good anti-corrosion properties and high thermal conductivity, and will not affect the heat dissipation of the packaged chip 20S.

[0076] In other embodiments of this application, as shown in FIG17, the aforementioned second anti-corrosion layer 302 includes a second silicon oxide layer 3021 and a second metal layer 3022 stacked together, with the second metal layer 3022 located between the jet cooling device body 301 and the second silicon oxide layer 3021. The second metal layer 3022 can be made of any material selected from copper, stainless steel, and aluminum. The second silicon oxide layer 3021 has good anti-corrosion performance, and the second metal layer 3022 has a high thermal conductivity, resulting in good heat dissipation performance of the jet cooling device body 301.

[0077] The flow velocity of the coolant is relatively low in most areas of the inner wall of the jet cooling device body 301, where the coolant flow channel 301A is formed. Therefore, in some embodiments of this application, the thickness T7 of the second anti-corrosion layer 302 is 10 nm, which not only ensures the anti-corrosion effect on the inner wall of the jet cooling device body 301, but also ensures good heat dissipation performance of the jet cooling device body 301.

[0078] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A packaged chip, comprising: The package chip comprises: a substrate; a bare chip disposed on the substrate; a first anticorrosion layer covering at least a side surface of the bare chip away from the substrate; a thermal conductivity of the first anticorrosion layer is greater than 10 w / m·k.

2. The chip package of claim 1, wherein a material of the first anticorrosion layer comprises any one of aluminum oxide, nickel, and chromium; alternatively, the first anticorrosion layer comprises a first silicon oxide layer and a first metal layer stacked together, and the first metal layer is located between the bare chip and the first silicon oxide layer.

3. The packaged chip of claim 1 or 2, wherein, a thickness of the first anticorrosion layer in a region covering the side surface of the bare chip away from the substrate is 200 nm.

4. The packaged chip of claim 2 or 3, wherein, The package chip further comprises: a plastic encapsulation disposed on the substrate and filling a periphery of the bare chip; the first anticorrosion layer further covers a side surface of the plastic encapsulation away from the substrate; or the first anticorrosion layer further covers the side surface of the plastic encapsulation away from the substrate, an outer sidewall of the plastic encapsulation, and an outer sidewall of the substrate.

5. The chip package of claim 4, wherein a thickness of the first anticorrosion layer in a region covering the outer sidewall of the plastic encapsulation and the outer sidewall of the substrate is 10 nm.

6. The chip package of claim 4, wherein The package chip further comprises: a protection ring disposed on the substrate and located outside the plastic encapsulation; the first anticorrosion layer further covers a side surface of the protection ring away from the substrate; or the first anticorrosion layer further covers the side surface and an outer sidewall of the protection ring away from the substrate, and an outer sidewall of the substrate.

7. The chip package of claim 6, wherein a thickness of the first anticorrosion layer in a region covering the outer sidewall of the protection ring and the outer sidewall of the substrate is 10 nm.

8. A circuit board assembly, characterized by The circuit board assembly comprises: a circuit board; the package chip according to any one of claims 1-7 is disposed on the circuit board; a jet cooling device is sealingly connected to a side of the package chip away from the circuit board, or is sealingly covered outside the package chip; a cooling liquid flow channel is formed in the jet cooling device; at least a surface of the package chip away from the circuit board is located in the cooling liquid flow channel.

9. The circuit board assembly of claim 8, wherein, The jet cooling device comprises: a jet cooling device body, and the cooling liquid flow channel is formed in the jet cooling device body; a second anticorrosion layer covering an inner wall of a portion of the jet cooling device body in which the cooling liquid flow channel is formed.

10. The circuit board assembly of claim 9, wherein, a material of the second anticorrosion layer comprises any one of aluminum oxide, nickel, and chromium; alternatively, the second anticorrosion layer comprises a second silicon oxide layer and a second metal layer stacked together, and the second metal layer is located between the jet cooling device body and the second silicon oxide layer.

11. The circuit board assembly of claim 9 or 10, wherein, a thickness of the second anticorrosion layer is 10 nm.

12. An electronic device, comprising: The circuit board assembly comprises: a housing; the circuit board assembly according to any one of claims 8-11 is disposed in the housing.

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