Lateral power semiconductor device, chip and electronic device

Abstract

This application relates to the technical field of semiconductors. Disclosed are a lateral power semiconductor device, a chip, and an electronic device. The lateral power semiconductor device comprises a substrate, and a first source electrode, a first drain electrode, a first gate electrode, a second gate electrode, a first isolation layer, and a second isolation layer that are disposed above the substrate, wherein the first source electrode, the first gate electrode, the second gate electrode and the first drain electrode are sequentially arranged; the second gate electrode comprises a first gate region and a second gate region, the second gate region being closer to the first drain electrode than the first gate region; and the first isolation layer is located between the first gate region and the substrate, and the second isolation layer is located between the second gate region and the substrate, the thickness of the first isolation layer being less than the thickness of the second isolation layer. Therefore, the lateral power semiconductor device can reduce losses caused by gate charge and specific on-resistance, and can also increase the breakdown voltage of the device.

Description

Lateral power semiconductor device, chip and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410970503.5 filed on July 18, 2024, and entitled "Lateral power semiconductor device, chip and electronic device", the whole content of the above application is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor, in particular to a lateral power semiconductor device, chip and electronic device. BACKGROUND

[0003] The lateral power semiconductor device is a kind of semiconductor device with internal current flowing in a lateral direction, and can control and convert electric energy in electronic devices, including frequency conversion, voltage conversion, current conversion and control switching, etc.

[0004] In the working process of the lateral power semiconductor device, the loss includes the loss caused by the specific on-resistance. The specific on-resistance is related to the on-state performance of the device, the larger the specific on-resistance, the greater the on-state loss of the device, and the worse the on-state performance. In the working process of the device, in order to prevent the device from being broken down and failing, a corresponding insulation structure needs to be provided in the device to prevent breakdown, and when the insulation structure is provided in the area that can originally conduct electricity, it will increase the specific on-resistance, thereby increasing the on-state loss of the device and reducing the on-state performance of the device.

[0005] Therefore, in the lateral power semiconductor device, how to reduce the specific on-resistance loss while ensuring that the device is not broken down and fails is a problem to be solved. SUMMARY

[0006] The present application provides a lateral power semiconductor device, chip and electronic device, which is used to optimize the trade-off relationship between the specific on-resistance and the breakdown voltage, so as to ensure that the lateral power semiconductor device is not broken down and fails and reduce the loss.

[0007] In a first aspect, the present application provides a lateral power semiconductor device, which includes a substrate and a first source electrode, a first drain electrode, a first gate electrode, a second gate electrode, a first isolation layer and a second isolation layer arranged above the substrate; wherein the first source electrode, the first gate electrode, the second gate electrode and the first drain electrode are arranged in sequence; the second gate electrode includes a first gate electrode region and a second gate electrode region, wherein the second gate electrode region is closer to the first drain electrode than the first gate electrode region; and the first isolation layer is located between the first gate electrode region and the substrate, and the second isolation layer is located between the second gate electrode region and the substrate; and the thickness of the first isolation layer is less than the thickness of the second isolation layer.

[0008] According to the embodiments of the present application, the gate electrode close to the drain electrode is provided as two laterally connected gate regions, and an insulating isolation layer is provided between the gate electrode and the substrate. Since the isolation layer is provided above the substrate, it does not occupy the area of the carrier activity region in the drift region of the substrate, thereby reducing the specific on-resistance and further reducing the loss caused by the specific on-resistance. Therefore, the lateral power semiconductor device provided by the present application can reduce the loss of the lateral power semiconductor device while not being broken down.

[0009] In some embodiments of the first aspect, a bottom surface of the first gate region is closer to the substrate than a bottom surface of the second gate region; and / or a top surface of the first gate region is closer to the substrate than a top surface of the second gate region.

[0010] In this way, the second gate as a whole forms a stepped profile. Since the top surface of the drift region below the second gate region is the peak of the electric field, the stepped second gate can prevent the drift region below the second gate from being broken down. Moreover, the first isolation layer and the second isolation layer are both provided above the substrate. For example, the second isolation layer can be formed above the substrate through deposition, etching and other steps, and its formation process and position will not affect the distribution of the doped ions in the substrate. Therefore, the isolation layer does not occupy the area of the conduction channel in the drift region, which helps to widen the conduction channel of the drift region to increase the carrier distribution area, thereby reducing the specific on-resistance and reducing the on-state loss of the lateral power semiconductor device.

[0011] In some embodiments of the first aspect, the material of the first isolation layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbon nitride; and / or the material of the second isolation layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbon nitride.

[0012] In this way, the first isolation layer and the second isolation layer can isolate the gate electrode from the substrate to prevent the surface of the substrate from being broken down. By providing the insulating isolation layer between the gate electrode and the substrate, the lateral power semiconductor device can be protected from being broken down while reducing the loss of the lateral power semiconductor device.

[0013] In some embodiments of the first aspect, the semiconductor device further comprises a first barrier layer; wherein the first barrier layer is located above the substrate and between the second gate region and the first drain electrode, and the first barrier layer is also located above a part of the surface of the second gate region close to the first drain electrode.

[0014] In this way, the first barrier layer is located above and beside the part of the surface of the second gate region close to the first drain electrode and does not contact the second gate region. Therefore, the first barrier layer is used to protect the surface of the second gate region, so that the second gate region is electrically isolated from the first drain electrode. In this way, the first barrier layer is located above and beside the part of the surface of the second gate region close to the first drain electrode and does not contact the second gate region. Therefore, the first barrier layer is used to protect the surface of the second gate region, so that the second gate region is electrically isolated from the first drain electrode.

[0015] In some embodiments of the first aspect, the semiconductor device further comprises a first field plate; wherein the first field plate is located above and connected with the first blocking layer.

[0016] In this way, the first field plate is used to modulate the electric field of the surface of the substrate, and by controlling the voltage of the first field plate, the carrier distribution of the surface of the substrate under the second gate can be controlled, thereby accelerating the turn-on or turn-off of the lateral power semiconductor device, so that the gate charge can be further reduced. Moreover, the setting of the first field plate can not only further improve the breakdown voltage, but also further reduce the specific on-resistance by adjusting the electric field of the surface of the substrate, thereby optimizing the trade-off relationship between the specific on-resistance and the breakdown voltage of the lateral power semiconductor device, while ensuring that the lateral power semiconductor device is not broken down, the loss of the lateral power semiconductor device is reduced.

[0017] In some embodiments of the first aspect, the semiconductor device further comprises a gate electrode; wherein the gate electrode is located above the substrate and connected with the second gate, and the gate electrode is used to provide a bias voltage for the second gate.

[0018] In this way, by setting the gate electrode connected with the second gate, the voltage of the second gate can be controlled separately, and by adjusting the size or bias time of the bias voltage, the carrier distribution of the surface of the well region and the drift region under the second gate can be controlled, thereby accelerating the turn-on or turn-off of the lateral power semiconductor device, so that the gate charge can be further reduced to further reduce the loss.

[0019] In some embodiments of the first aspect, the semiconductor device further comprises a second field plate and a second blocking layer; wherein the second field plate is located above the gap between the first gate and the second gate, and the second blocking layer is located between the second field plate and the substrate and connected with the second field plate.

[0020] In this way, the second field plate can improve the problem of excessively high surface electric field of the substrate at the right lower corner of the first gate. The second blocking layer is used to electrically isolate the second field plate from the first gate and the second gate. By adjusting the potential of the second field plate, the electric field strength at the position close to the first gate can be reduced, thereby preventing the right lower corner of the first gate from being broken down too early. The voltage of the second field plate can be the same as the voltage of the first source electrode, at this time, the second field plate and the first source electrode can be provided with voltage by the same electrode or different electrodes respectively. When the voltage of the second field plate is the same as the voltage of the first source electrode, the problem of electric field concentration caused by the dense distribution of potential lines at the edge of the first gate can be alleviated, and the gate charge can be further reduced.

[0021] In some embodiments of the first aspect, the substrate further comprises a second source contact region; wherein the second source contact region is located within the first well region; and a projection of the second source contact region on the first plane is tangent to or partially overlaps with a projection of the first gate on the first plane and is tangent to or partially overlaps with a projection of the second gate on the first plane.

[0022] In some embodiments of the first aspect, the substrate further comprises a second source contact region; wherein the second source contact region is located within the first well region; and a projection of the second source contact region on the first plane is tangent to or partially overlaps with a projection of the first gate on the first plane and is tangent to or partially overlaps with a projection of the second gate on the first plane.

[0023] In some embodiments of the first aspect, the substrate further comprises a second source contact region; wherein the second source contact region is located within the first well region; and a projection of the second source contact region on the first plane is tangent to or partially overlaps with a projection of the first gate on the first plane and is tangent to or partially overlaps with a projection of the second gate on the first plane.

[0024] In some embodiments of the first aspect, the substrate further comprises a second source contact region; wherein the second source contact region is located within the first well region; and a projection of the second source contact region on the first plane is tangent to or partially overlaps with a projection of the first gate on the first plane and is tangent to or partially overlaps with a projection of the second gate on the first plane.

[0025] In some embodiments of the first aspect, the substrate further comprises a second source contact region and a third well region; wherein the third well region is located in the first drift region, the second source contact region is located in the third well region, and the third well region is tangent to the second well region; a projection of the third well region on the first plane partially overlaps with a projection of the first gate on the first plane and partially overlaps with a projection of the second gate on the first plane; a projection of the second source contact region on the first plane is tangent to or partially overlaps with a projection of the first gate on the first plane and is tangent to or partially overlaps with a projection of the second gate on the first plane.

[0026] In some embodiments of the first aspect, the substrate further comprises a second body contact region; wherein the second body contact region is located in the first drift region, and a projection of the second body contact region on the first plane is tangent to a projection of the first gate on the first plane and is tangent to a projection of the second gate on the first plane.

[0027] In some embodiments of the first aspect, the semiconductor device further comprises a second source; wherein the second source is located above the substrate and is connected to the second body contact region.

[0028] In a second aspect, the present application provides a chip, characterized by comprising the semiconductor device according to any one of the embodiments of the present application.

[0029] In a third aspect, the present application provides an electronic device, characterized by comprising the semiconductor device according to any one of the embodiments of the present application.

[0030] The beneficial effects of the second aspect to the third aspect can refer to the related description of the first aspect and various embodiments of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the present application, the drawings used in the embodiments will be briefly introduced as follows.

[0032] FIG. 1 shows a schematic diagram of a cross-sectional structure of a semiconductor device 20 according to some embodiments of the present application;

[0033] FIG. 2 shows a schematic diagram of a cross-sectional structure of a semiconductor device 40a according to some embodiments of the present application;

[0034] FIG. 3 shows a line graph of the first gate voltage and the second gate voltage changing with time in a semiconductor device 40a according to some embodiments of the present application;

[0035] FIG. 4 shows a line graph of the voltage of a single-gate semiconductor device and the first gate voltage changing with time in a semiconductor device 40a according to some embodiments of the present application;

[0036] FIG. 5 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40b, according to some embodiments of the application;

[0037] FIG. 6 illustrates a line graph of first gate voltage, second gate voltage versus time in a semiconductor device 40b, according to some embodiments of the application;

[0038] FIG. 7 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40c, according to some embodiments of the application;

[0039] FIG. 8 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40d, according to some embodiments of the application;

[0040] FIG. 9 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40e, according to some embodiments of the application;

[0041] FIG. 10 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40f, according to some embodiments of the application;

[0042] FIG. 11 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40g, according to some embodiments of the application;

[0043] FIG. 12 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40h, according to some embodiments of the application;

[0044] FIG. 13 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40i, according to some embodiments of the application;

[0045] FIG. 14 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40j, according to some embodiments of the application;

[0046] FIG. 15 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40k, according to some embodiments of the application;

[0047] FIG. 16 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40l, according to some embodiments of the application;

[0048] FIG. 17 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40m, according to some embodiments of the application;

[0049] FIG. 18 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40n, according to some embodiments of the application;

[0050] FIG. 19 illustrates a cross-sectional structure schematic diagram of a semiconductor device 40o, according to some embodiments of the application;

[0051] FIG. 20 shows a schematic view of a cross-sectional structure of a semiconductor device 40p, according to some embodiments of the application;

[0052] FIG. 21 shows a schematic view of a cross-sectional structure of a semiconductor device 40q, according to some embodiments of the application;

[0053] FIG. 22 shows a schematic view of a cross-sectional structure of a semiconductor device 40r, according to some embodiments of the application;

[0054] FIG. 23 shows a schematic view of a cross-sectional structure of a semiconductor device 40s, according to some embodiments of the application;

[0055] FIG. 24 shows a schematic view of a cross-sectional structure of a semiconductor device 40t, according to some embodiments of the application;

[0056] FIG. 25 shows a schematic view of a cross-sectional structure of a semiconductor device 40u, according to some embodiments of the application;

[0057] FIG. 26 shows a schematic view of a cross-sectional structure of a semiconductor device 40v, according to some embodiments of the application;

[0058] FIG. 27 shows a schematic view of a cross-sectional structure of a semiconductor device 40w, according to some embodiments of the application;

[0059] FIG. 28 shows a schematic view of a structure of an electronic device 100, according to some embodiments of the application. DETAILED DESCRIPTION

[0060] Illustrative embodiments of the present application include, but are not limited to, lateral power semiconductor devices, chips, and electronic devices.

[0061] It should be noted that the orientation terms such as "upper", "lower", "left", "right" and the like used herein are exemplary orientations of the semiconductor device, and do not indicate or imply that the referenced part must have a particular orientation, which can be changed according to actual use, and should not be construed as a limitation of the present application. In addition, the length direction described in the embodiments of the present application can be the x direction in the drawing, and the thickness direction can be the y direction in the drawing.

[0062] It can be understood that the lateral power semiconductor device mentioned in the embodiments of the present application or the chip containing the lateral power semiconductor device can be applied to any electronic device. Among them, the electronic device includes but is not limited to mobile phones, tablets, personal computers, electronic watches, electronic bracelets, cameras, wearable devices, augmented reality (AR) devices, telecommunications machine rooms, data centers, routers, switches, servers and the like, and the type and form of the electronic device are not limited by the embodiments of the present application. It should be noted that the semiconductor device or chip mentioned in the embodiments of the present application can also be applied to other types of electronic devices, which are not limited here.

[0063] In addition, the semiconductor device mentioned in the embodiments of the present application can also be used in Bipolar-CMOS-DMOS (BCD) platform development, artificial intelligence (AI) chips, vehicle-mounted chips and the like platforms or products.

[0064] It should be noted that the lateral power semiconductor device in the present application can include but is not limited to laterally diffused metal oxide semiconductor (LDMOS), modulation-doped FET (MODFET), organic field-effect transistor (OFET), insulate-gate bipolar transistor (IGBT) and dual gate MOSFET (DGMOSFET).

[0065] As mentioned earlier, the loss of the lateral power semiconductor device includes the loss caused by the specific on-resistance, and the greater the specific on-resistance, the greater the loss. At present, when the device is guaranteed not to be broken down and fail, the specific on-resistance of the device will increase, which is described as follows.

[0066] FIG. 1 shows a cross-sectional structure schematic diagram of a semiconductor device 20 according to some embodiments of the present application. The semiconductor device 20 is a lateral power semiconductor device with a dual gate structure, in which a shallow trench isolation (STI) region 206 is provided to prevent the gate G2 from being broken down, but the existence of the STI region 206 will cause the increase of the specific on-resistance.

[0067] Specifically, the semiconductor device 20 comprises a substrate 201 and a source S, a gate G1, a gate G2, a drain D disposed directly on the top surface of the substrate 201, and a gate oxide layer 207 between the substrate 201 and the gate G1, the gate G2. The substrate 201 comprises a well region 202 and a well region 203 connected in the x direction, the well region 202 is provided with a source contact region 204 connected with the source S, the well region 203 is provided with a drain contact region 205 connected with the drain D, and the well region 203 is further provided with an STI region 206 connected with the gate G2.

[0068] When the semiconductor device 20 is turned on or off, there is an electric field peak on the surface of the substrate 201 (the well region 203) directly below a part of the gate G2 close to the drain D, and the electric field intensity is high, which can easily cause premature breakdown of the semiconductor device 20. Therefore, the STI region 206 is provided in the substrate 201 below the gate G2 to prevent the gate G2 from being broken down. In addition, for a lateral power semiconductor device with the STI region 206, the purpose of providing the gate G2 is also to adjust the potential distribution inside the device to avoid premature breakdown and reliability problems caused by the high electric field at the corner of the STI region 206 close to the source.

[0069] However, when the semiconductor device 20 is turned on between the source S and the drain D, that is, the source contact region 204 and the drain contact region 205 are turned on, the carriers in the well region 202 and the well region 203 must move, thereby forming a lateral conduction channel in the well region 202 and the well region 203. Due to the presence of the STI region 206, the distribution area of the carriers in the well region 203 is occupied, so that the carrier movement area in the well region 203 is reduced, and the conduction channel is narrowed. The specific on-resistance refers to the ratio of the resistance of the lateral power semiconductor device when turned on to the channel width of the device, therefore, the smaller the channel width of the device, the larger the specific on-resistance. Therefore, the presence of the STI region 206 increases the specific on-resistance of the semiconductor device 20, and the increase of the specific on-resistance leads to the increase of the on-state loss of the semiconductor device 20.

[0070] In other lateral semiconductor power device structures, in order to prevent the gate G2 from being broken down, a local oxidation of silicon (LOCOS) technology is also used to form an isolation region at the same position as the STI region 206.

[0071] However, the isolation region formed by the LOCOS technology and the above-mentioned STI region 206 are both insulating regions, and are both provided in the well region 203, which will also cause the specific on-resistance of the semiconductor device to increase, increase the on-state loss of the device, and affect the on-state performance of the device. Therefore, in order to ensure that the semiconductor device 20 is not broken down prematurely, the total loss of the semiconductor device 20 will be increased.

[0072] To solve the above problems, embodiments of the present application provide a lateral power semiconductor device, a chip and an electronic device. In the lateral power semiconductor device of the present application, the gate close to the drain is provided as two laterally connected gate regions, and an insulating isolation layer is provided between the gate and the substrate. Wherein, a thicker isolation layer is provided below the gate region closer to the drain than below the other gate region, that is, the thickness of the isolation layer below the two laterally connected gate regions is different, so that the gate close to the drain as a whole forms a stepped cross-sectional morphology, thereby specifically protecting the substrate below the gate region closer to the drain (at the electric field peak), so that it is not easy to be broken down in advance. Since the isolation layer is provided above the substrate, it does not occupy the area of the carrier activity region of the well region (drift region) in the substrate, thereby reducing the specific on-resistance, and further reducing the loss generated by the specific on-resistance. Therefore, the lateral power semiconductor device provided by the present application can reduce the loss of the lateral power semiconductor device while not being broken down.

[0073] For example, according to some embodiments of the present application, FIG. 2 shows a lateral power semiconductor device 40a which, based on the above-mentioned manner, provides an insulating isolation layer between the gate and the substrate to reduce the loss of the lateral power semiconductor device while protecting the lateral power semiconductor device from being broken down.

[0074] Specifically, as shown in FIG. 2, the lateral power semiconductor device 40a is provided with a gate 410 (an example of the first gate of the present application) and a gate 411 (an example of the second gate of the present application), the gate 410 is close to a source 412 (an example of the first source of the present application), and the gate 411 is close to a drain 413 (an example of the first drain of the present application). Wherein, the gate 411 includes a gate region 4111 (an example of the first gate region of the present application) and a gate region 4112 (an example of the second gate region of the present application) connected along the x direction. The gate region 4111 and the drift region 402 (an example of the first drift region of the present application) are provided with an isolation layer 408 (an example of the first isolation layer of the present application), and the gate region 4112 and the drift region 402 are provided with an isolation layer 409 (an example of the second isolation layer of the present application), and the thickness of the isolation layer 409 is greater than the thickness of the isolation layer 408, so that the distance between the bottom surface of the gate region 4112 and the top surface of the drift region 402 is greater than the distance between the bottom surface of the gate region 4111 and the top surface of the drift region 402. Thus, the gate region 4112 and the top surface of the drift region 402 below are not easy to be broken down, and also do not occupy the area of the conductive channel in the drift region 402, which helps to widen the conductive channel of the drift region 402 to increase the carrier distribution area, thereby reducing the specific on-resistance and reducing the on-state loss of the lateral power semiconductor device 40a.

[0075] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0076] It should be noted that the first type of doping ions in various embodiments of the present application can be P-type, and the second type can be N-type, or the first type can be N-type, and the second type can be P-type. Among them, the P-type doping ions can include but are not limited to any one or several of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions and other ions; the N-type doping ions can include but are not limited to one or several of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions and other ions.

[0077] The first embodiment of the lateral power semiconductor device of the present application will be described in detail below with reference to FIGS. 2-4. Among them, FIG. 3 shows a line graph of the first gate voltage and the second gate voltage changing with time in a lateral power semiconductor device 40a; and FIG. 4 shows a line graph of the voltage of a single-gate lateral power semiconductor device (not shown) and the first gate voltage changing with time in the lateral power semiconductor device 40a.

[0078] Continuing as shown in FIG. 2, the lateral power semiconductor device 40a includes a substrate 401, which includes a base 4011 and a drift region 402 stacked along the y direction, a well region 403 (an example of a first well region of the present application) and a drain contact region 407 (an example of a first drain contact region of the present application) are formed in the drift region 402, and a body contact region 404 (an example of a first body contact region of the present application), a source contact region 405 (an example of a first source contact region of the present application), and a source contact region 406 (an example of a second source contact region of the present application) are sequentially arranged in the well region 403. Among them, the top surface of the drift region 402 exposes the top surfaces of the well region 403, the body contact region 404, the source contact region 405, the source contact region 406, and the drain contact region 407; and the body contact region 404 and the source contact region 405 are tangent.

[0079] In some embodiments, the doping ions of the drift region 402, the source contact region 405, the source contact region 406, and the drain contact region 407 are of a first type, and the doping ions of the base 4011, the well region 403, and the body contact region 404 are of a second type.

[0080] In addition, the top surface of the substrate 401 is also provided with an isolation layer 408 and an isolation layer 409 connected along the x direction. Among them, the isolation layer 408 covers the top surface of the well region 403, the top surface of the drain contact region 407, and part of the top surface of the drift region 402 close to the well region 403, and the isolation layer 409 covers part of the top surface of the drift region 402. And the thickness of the isolation layer 409 is greater than the thickness of the isolation layer 408.

[0081] In some embodiments, the orthogonal projection of the isolation layer 409 on a plane perpendicular to the y direction (an example of the first plane of the present application) is tangent to the orthogonal projection of the drain contact region 407 on the plane perpendicular to the y direction.

[0082] In some embodiments, the side surface of the isolation layer 409 connected with the isolation layer 408 is at an acute angle with the bottom surface of the isolation layer 409, or the side surface of the isolation layer 409 connected with the isolation layer 408 is perpendicular to the bottom surface of the isolation layer 409. Thus, by setting a height difference between the isolation layer 409 and the isolation layer 408, the isolation layer 409 near the drain 413 is thicker, so as to protect the substrate 401 directly below the gate region 4112 near the drain from being broken down, i.e., to improve the breakdown voltage of the device.

[0083] In some embodiments, the material of the isolation layer 408 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride.

[0084] In some embodiments, the material of the isolation layer 409 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride.

[0085] Continuing to refer to FIG. 2, the substrate 401 further has a source 412 and a drain 413 arranged in sequence on the top surface of the substrate 401.

[0086] The source 412 is located above the body contact region 404 and the source contact region 405, and connects with the top surface of the body contact region 404 and the top surface of the source contact region 405 along the y direction. The drain 413 is located directly above the drain contact region 407, and connects with the top surface of the drain contact region 407 along the y direction.

[0087] The gate 410 is located above the isolation layer 408 directly above the well region 403, and is connected with the isolation layer 408. Specifically, the orthogonal projection of the gate 410 on a plane perpendicular to the y direction is tangent to the orthogonal projection of the source contact region 405 on the plane perpendicular to the y direction, and is tangent to or partially overlaps with the orthogonal projection of the source contact region 406 on the plane perpendicular to the y direction.

[0088] The gate region 4111 in the gate 411 is located above the isolation layer 408 above part of the top surface of the well region 403 and part of the top surface of the drift region 402, and is connected with the isolation layer 408. The gate region 4112 in the gate 411 is located above the isolation layer 409 and is connected with the isolation layer 409. Specifically, the orthogonal projection of the gate region 4111 on a plane perpendicular to the y direction is tangent to or partially overlaps with the orthogonal projection of the source contact region 406 on the plane perpendicular to the y direction.

[0089] Continuing to refer to FIG. 2, the orthogonal projection of the gate 410 on a plane perpendicular to the y direction is located within the orthogonal projection of the well region 403 on a plane perpendicular to the y direction, and the orthogonal projection of the gate 411 on a plane perpendicular to the y direction partially overlaps with the orthogonal projection of the well region 403 on a plane perpendicular to the y direction.

[0090] In some embodiments, the lateral power semiconductor device 40a further comprises a barrier layer 414 (an example of the first barrier layer of the present disclosure) located above and beside a part of the surface of the gate region 4112 close to the drain 413 and not in contact with the gate region 4112. The barrier layer 414 is used to protect the surface of the gate region 4112 so that the gate region 4112 is electrically isolated from the drain 413.

[0091] In some embodiments, the lateral power semiconductor device 40a further comprises a dielectric layer 415 filling the gaps between the structures above the substrate 401 and located above the isolation layer 408 and the isolation layer 409. For example, the dielectric layer 415 is located in the gaps between the source 412, the gate 410, the gate 411, the drain 413, and the barrier layer 414, thereby electrically isolating the source 412, the gate 410, the gate 411, and the drain 413.

[0092] In the above-described lateral power semiconductor device 40a, the thickness of the isolation layer 409 is greater than the thickness of the isolation layer 408, i.e., the isolation layer 409 and the isolation layer 408 form a stepped isolation layer topography, and the gate region 4111 is located above the isolation layer 408 and the gate region 4112 is located above the isolation layer 409. Therefore, the bottom surface of the gate region 4112 is higher than the bottom surface of the gate region 4111, i.e., the bottom surface of the gate 411 forms a stepped topography.

[0093] In addition, since the thickness of the gate region 4112 is the same as that of the gate region 4111, the top surface of the gate region 4112 is also higher than the top surface of the gate region 4111, thereby making the entire gate 411 form a stepped topography. Since the top surface of the drift region 402 below the gate region 4112 is at the electric field peak, the stepped gate 411 can prevent the drift region 402 below the gate 411 from being easily broken down. In addition, the isolation layer 408 and the isolation layer 409 are both disposed above the substrate 401. For example, the isolation layer 409 can be formed above the substrate 401 through deposition etching steps, and the formation process and position thereof will not affect the distribution of the doping ions in the substrate 401. Therefore, the isolation layer 409 will not occupy the region of the conduction channel in the drift region 402, which helps to widen the conduction channel of the drift region 402 to increase the carrier distribution area, thereby reducing the specific on-resistance and reducing the on-state loss of the lateral power semiconductor device 40a.

[0094] In some embodiments, the specific on-resistance can be further reduced by increasing the concentration of the doping ions in the drift region 402, so as to further reduce the loss caused by the specific on-resistance.

[0095] With continuous reference to FIG. 2, in some embodiments, the gate 411 can also be connected with an electrode (not shown) capable of providing a bias voltage for the gate 411, the bias voltage being a fixed value, and the electrode provides the fixed value of the voltage regardless of whether the lateral power semiconductor device 40a is on or off, and the size of the bias voltage does not need to be changed through the electrode. Specifically, the value of the bias voltage is greater than the voltage when the source 412 is working, and less than the voltage when the drain 413 is working, and the value of the bias voltage needs to ensure that the conductive channel under the gate 411 in the drift region 402 is inversely on.

[0096] The working principle of the lateral power semiconductor device 40a is described below in combination with FIG. 2 and FIG. 3. FIG. 3 shows the relationship between the first gate voltage and the second gate voltage over time. The first gate voltage represents the bias voltage of the gate 410, and the first gate voltage changes over time; the second gate voltage represents the bias voltage of the gate 411, and the second gate voltage does not change over time.

[0097] Specifically, the gate 410 is the main control gate in the lateral power semiconductor device 40a, and the voltage of the gate 410 changes over time as shown in FIG. 3. At t0, when the voltage of the gate 410 rises to a fixed voltage Vg, an inverse layer is formed on the surface of the well region 403, thereby turning on the channel. And at t0, since the gate 411 is biased to a fixed voltage Vg' (the size of the Vg' voltage can be equal to or different from Vg), the well region 403 and the drift region 402 directly below the gate 411 form a conductive channel and an accumulation layer, respectively. When the gate 410 rises to the fixed voltage Vg, at this time, adding a bias voltage on the drain 413, the electrons will move from the source 412 to the drain 413 along the x direction through the source contact region 405, the well region 403, the source contact region 406, the well region 403, the drift region 402 and the drain contact region 407 in turn, thereby forming a lateral current from the source 412 to the drain 413.

[0098] When the voltage of the gate 410 is not enough to generate the above-mentioned inverse channel (for example, the voltage is less than the fixed voltage Vg), adding a bias voltage on the drain 413, the lateral power semiconductor device 40a is equivalent to a diode, at this time, the electrons pass through the drift region 402 and the well region 403 to reach the source 412, that is, the diode is in a reverse bias state.

[0099] The following describes other aspects of performance that can be improved by employing the lateral power semiconductor device 40a provided by the present application compared to a single-gate lateral power semiconductor device in combination with FIG. 2 and FIG. 4. FIG. 4 shows the voltage of a single-gate (not shown) lateral power semiconductor device and the voltage of the first gate (gate 410) in the lateral power semiconductor device 40a over time.

[0100] In the working process of a single-gate lateral power semiconductor device, the loss generated includes the loss of gate charge in addition to the loss of specific on-resistance described above. The gate charge refers to the charge injected into the gate of the device by an external gate driver in order to turn on or turn off the lateral power semiconductor device. The speed of injecting the charge affects the speed of turning on or turning off the lateral power semiconductor power device. The slower the speed of turning on, the greater the loss of the lateral power semiconductor power device.

[0101] The gate charge mainly includes gate-drain charge and gate-source charge, which are used to charge the gate-drain capacitance and the gate-source capacitance, respectively. The gate-source capacitance is the capacitance between the gate and the source, and the gate-drain capacitance is the capacitance between the gate and the drain. The loss of the gate charge refers to the loss of the gate-drain charge and the loss of the gate-source charge, wherein the loss generated by the gate-drain charge charging the gate-drain capacitance accounts for the majority. Specifically, the gate-drain capacitance mainly includes the isolation layer capacitance, the depletion layer capacitance, and the dielectric capacitance between the gate and the drain, wherein the isolation layer capacitance and the depletion layer capacitance can be collectively referred to as gate-drain overlap capacitance.

[0102] The reason for the loss of the gate-drain capacitance is that when the single-gate lateral power semiconductor power device is turned on and turned off, a Miller platform (the broken line corresponding to the single gate in FIG. 4) appears in the gate voltage, which delays the rising or falling of the gate voltage, thereby generating a large loss. After the lateral power semiconductor device with a double-gate structure, such as the lateral power semiconductor device 40a in the present application, is employed, the gate-drain capacitance between the gate 410 and the drain 413 can be reduced due to the shielding effect of the gate 411, thereby reducing or eliminating the Miller platform (the broken line corresponding to the first gate in FIG. 4) in the process of the voltage rising of the gate 410. Therefore, compared to the single-gate lateral power semiconductor device, the lateral power semiconductor device 40a can realize smaller gate charge, accelerate the speed of turning on the device, and further reduce the loss.

[0103] Therefore, the lateral power semiconductor device 40a provided by the present application not only can ensure not to be broken down and reduce the loss generated by the specific on-resistance, but also can reduce the loss generated by the gate charge, thereby reducing the total loss of the lateral power semiconductor device 40a and improving the working efficiency of the lateral power semiconductor device 40a.

[0104] The second embodiment of the lateral power semiconductor device of the present application will be described in detail below in combination with FIG. 5-6. FIG. 5 shows a cross-sectional structure schematic diagram of a lateral power semiconductor device 40b; FIG. 6 shows a line graph of the first gate voltage and the second gate voltage varying with time in the lateral power semiconductor device 40b.

[0105] As shown in FIG. 5 and FIG. 6, the lateral power semiconductor device 40b is similar to the lateral power semiconductor device 40a, and the difference between the lateral power semiconductor device 40b and the lateral power semiconductor device 40a is that the gate electrode 416 is connected to the gate 411 of the lateral power semiconductor device 40b, and the gate electrode 416 can provide the bias voltage Vg' to the gate 411 in a period from the turn-on to the turn-off of the lateral power semiconductor device 40b. That is, compared with the lateral power semiconductor device 40a, the voltage of the gate 411 in the lateral power semiconductor device 40b is not maintained at a fixed potential.

[0106] Specifically, as shown in FIG. 6, the duration t1-t2 that the gate 411 is biased to the voltage Vg' includes the duration t3-t4 that the gate 410 is biased to the voltage Vg, that is, the voltage of the gate 411 can rise before the voltage of the gate 410 rises, and can fall after the voltage of the gate 410 falls. More specifically, the voltage amplitude of Vg' can be equal to Vg, or can be different from Vg; similarly, the size of Vg0 can be 0 potential, or can be a non-zero potential (including negative value).

[0107] In addition, the other structures and related descriptions of the lateral power semiconductor device 40b are the same as those of the lateral power semiconductor device 40a, and can be referred to the related paragraphs of the lateral power semiconductor device 40a described above, which will not be described here.

[0108] In other embodiments, the bias voltage provided by the gate electrode 416 to the gate 411 can also be other values.

[0109] In the above-described lateral power semiconductor device 40b, by setting the gate electrode 416 connected to the gate 411, the voltage of the gate 411 can be controlled individually, and by adjusting the size or biasing time of the bias voltage, the carrier distribution on the surface of the well region 403 and the drift region 402 under the gate 411 is controlled, so as to accelerate the turn-on or turn-off of the lateral power semiconductor device 40b, thereby further reducing the gate charge, and further reducing the loss.

[0110] The third embodiment of the lateral power semiconductor device of the present application will be described in detail below in combination with FIG. 7. FIG. 7 shows a cross-sectional structure schematic diagram of a lateral power semiconductor device 40c.

[0111] As shown in FIG. 7, the lateral power semiconductor device 40c is similar to the lateral power semiconductor device 40b, and the difference between the lateral power semiconductor device 40c and the lateral power semiconductor device 40b is that the lateral power semiconductor device 40c adds a field plate 417 (an example of the first field plate of the present application) on the basis of the structure of the lateral power semiconductor device 40b. The field plate 417 is located above and connected to the blocking layer 414.

[0112] In addition, the other structures of the lateral power semiconductor device 40c and the related descriptions are the same as those of the lateral power semiconductor device 40b, and the related paragraphs of the lateral power semiconductor device 40b described above can be referred to, and will not be described here.

[0113] The field plate 417 described above is used to modulate the electric field on the surface of the substrate 401, and specifically, by controlling the voltage of the field plate 417, the carrier distribution on the surface of the substrate 401 below the gate 411 can be controlled, thereby accelerating the turn-on or turn-off of the lateral power semiconductor device 40c, so that the gate charge can be further reduced. And the setting of the field plate 417 can not only further improve the breakdown voltage, but also further reduce the specific on-resistance by adjusting the electric field on the surface of the substrate 401, thereby optimizing the trade-off relationship between the specific on-resistance and the breakdown voltage of the lateral power semiconductor device 40c, while ensuring that the lateral power semiconductor device 40c is not broken down, the loss of the lateral power semiconductor device 40c is reduced.

[0114] In some embodiments, the voltage of the field plate 417 described above can be the same as the voltage of the source 412, at this time, the field plate 417 can be provided with a voltage by the same electrode (not shown) as the source 412 or provided with a voltage by different electrodes (not shown) respectively as the source 412; or the voltage of the field plate 417 can be different from the voltage of the source 412, at this time, the field plate 417 and the source 412 are provided with voltages by different electrodes respectively.

[0115] The fourth embodiment of the lateral power semiconductor device of the present application will be described in detail below in combination with FIG. 8. FIG. 8 shows a schematic diagram of the cross-sectional structure of a lateral power semiconductor device 40d.

[0116] As shown in FIG. 8, the lateral power semiconductor device 40d is similar to the lateral power semiconductor device 40a, and the difference between the lateral power semiconductor device 40d and the lateral power semiconductor device 40a is that the lateral power semiconductor device 40d replaces the source contact region 406 in the lateral power semiconductor device 40a with a source-drain doped region 406' with a lower doping ion concentration than the source contact region 406. In addition, the source-drain doped region 406' and the source contact region 406 have the same doping type.

[0117] The source-drain doped region 406' can be located at the same position as the source contact region 406. For details, refer to the description of the source contact region 406 above, which will not be repeated here.

[0118] In addition, the other structures and related descriptions of the lateral power semiconductor device 40d are the same as those of the lateral power semiconductor device 40a. For details, refer to the description of the lateral power semiconductor device 40a above, which will not be repeated here.

[0119] The source-drain doped region 406' can improve the problem of excessive electric field on the surface of the substrate 401 at the lower right corner of the gate 410 (the surface of the substrate 401 below the part of the gate 410 close to the gate 411). Specifically, when the drain 413 is biased at a high voltage, at the initial stage of the depletion region of the lateral power semiconductor device 40d, if the source-drain doped region 406' with a lower ion concentration is not provided, the surface of the substrate 401 close to the lower right corner of the gate 410 will have a very high electric field, which will cause premature breakdown of the device. After the source-drain doped region 406' is provided, the source-drain doped region 406' can reduce the electric field intensity on the surface of the substrate 401 at the lower right corner of the gate 410, thereby avoiding premature breakdown of the device.

[0120] In some embodiments, the source-drain doped region 406' can be formed by a lightly doped drain (LDD) process.

[0121] The fifth embodiment of the lateral power semiconductor device of the present application will be described in detail below in conjunction with FIG. 9. FIG. 9 shows a schematic diagram of the cross-sectional structure of a lateral power semiconductor device 40e.

[0122] As shown in FIG. 9, the lateral power semiconductor device 40e is similar to the lateral power semiconductor device 40d, and the difference between the lateral power semiconductor device 40e and the lateral power semiconductor device 40d is that the lateral power semiconductor device 40c adds a field plate 417 based on the structure of the lateral power semiconductor device 40d.

[0123] For details of the field plate 417, refer to the description of the field plate 417 in the above embodiments, which will not be repeated here.

[0124] In addition, the other structures and related descriptions of the lateral power semiconductor device 40e are the same as those of the lateral power semiconductor device 40d. For details, refer to the description of the lateral power semiconductor device 40d above, which will not be repeated here.

[0125] The transverse power semiconductor device 40e further has the field plate 417 provided on the basis of the source-drain doped region 406', and thus can not only reduce the electric field of the surface of the substrate 401 at the lower right corner of the gate 410, but also modulate the overall surface electric field of the substrate 401, so as to optimize the trade-off between the specific on-resistance and the breakdown voltage, and reduce the gate charge and the specific on-resistance while ensuring that the device is not broken down, so as to reduce the total loss of the transverse power semiconductor device 40e.

[0126] The sixth embodiment of the transverse power semiconductor device of the present application will be described in detail below in combination with FIG. 10. FIG. 10 shows a schematic diagram of the cross-sectional structure of a transverse power semiconductor device 40f.

[0127] As shown in FIG. 10, the transverse power semiconductor device 40f is similar to the transverse power semiconductor device 40d, and the difference between the transverse power semiconductor device 40f and the transverse power semiconductor device 40d is that the transverse power semiconductor device 40f further has a barrier layer 418 (an example of the second barrier layer of the present application) and a field plate 419 (an example of the second field plate of the present application) provided on the basis of the structure of the transverse power semiconductor device 40d. The field plate 419 is located above the gap between the gate 410 and the gate 411, and the barrier layer 418 is located between the field plate 419 and the substrate 401 and connected with the field plate 419.

[0128] In addition, the other structures and related descriptions of the transverse power semiconductor device 40f are the same as those of the transverse power semiconductor device 40d, and can be referred to the related paragraphs of the transverse power semiconductor device 40d described above, which will not be described herein again.

[0129] The field plate 419 can improve the problem of excessively high electric field of the surface of the substrate 401 at the lower right corner of the gate 410 (the surface of the substrate 401 below the part of the gate 410 close to the gate 411). By adjusting the electric potential of the field plate 419, the electric field intensity of the position close to the gate 410 in the source-drain doped region 406' can be reduced, so as to prevent the lower right corner of the gate 410 from being broken down in advance.

[0130] The barrier layer 418 is used to electrically isolate the field plate 419 from the gate 410 and the gate 411.

[0131] In some embodiments, the voltage of the field plate 419 can be the same as that of the source electrode 412, and in this case, the field plate 419 can be provided with the same voltage by the same electrode as the source electrode 412 or provided with different voltages by different electrodes. When the voltage of the field plate 419 is the same as that of the source electrode 412, the problem of electric field concentration caused by the dense potential line distribution at the edge of the gate 410 can be alleviated, and since the voltage is the same as that of the source electrode 412, the field plate 419 also functions as a shield, and can further reduce the gate charge.

[0132] In some embodiments, the voltage of the field plate 419 can also be different from the voltage of the source 412, in which case the field plate 419 and the source 412 are respectively provided with different voltages by different electrodes.

[0133] A seventh embodiment of the lateral power semiconductor device of the present application will be described in detail below with reference to FIG. 11. FIG. 11 shows a schematic diagram of a cross-sectional structure of a lateral power semiconductor device 40g.

[0134] As shown in FIG. 11, the lateral power semiconductor device 40g is similar to the lateral power semiconductor device 40d, and the difference between the lateral power semiconductor device 40g and the lateral power semiconductor device 40d is that the lateral power semiconductor device 40g further includes the field plate 417, the barrier layer 418 and the field plate 419 on the basis of the structure of the lateral power semiconductor device 40d.

[0135] The field plate 417, the barrier layer 418 and the field plate 419 have been described in the above embodiments, and reference can be made to the above embodiments, and thus will not be described herein.

[0136] In addition, the other structures and related descriptions of the lateral power semiconductor device 40g are the same as those of the lateral power semiconductor device 40d, and reference can be made to the related paragraphs of the lateral power semiconductor device 40d, and thus will not be described herein.

[0137] The lateral power semiconductor device 40g described above can simultaneously adjust the surface electric field of the substrate 401 under the gate 410 and the gate 411 by adding the field plate 417, the barrier layer 418 and the field plate 419, thereby preventing the substrate 401 under the gate 410 and the gate 411 from being broken down, and further accelerating the opening or closing of the device by adjusting the electric field, thereby further reducing the gate charge and the specific on-resistance, and thus reducing the total loss of the lateral power semiconductor device 40g.

[0138] An eighth embodiment of the lateral power semiconductor device of the present application will be described in detail below with reference to FIG. 12. FIG. 12 shows a schematic diagram of a cross-sectional structure of a lateral power semiconductor device 40h.

[0139] As shown in FIG. 12, the lateral power semiconductor device 40h is similar to the lateral power semiconductor device 40a, and the difference between the lateral power semiconductor device 40h and the lateral power semiconductor device 40a is that the lateral power semiconductor device 40h replaces the well region 403 with a well region 403' (an example of the second well region of the present application) having a smaller size along the x direction on the basis of the structure of the lateral power semiconductor device 40a, and does not provide the source contact region 406.

[0140] The gate 410 is located directly above the partial well region 403' and directly above the partial drift region 402, and the gate 411 is located directly above the drift region 402. In addition, the well region 403' and the well region 403 have the same doping type. Specifically, the orthogonal projection of the well region 403' on a plane perpendicular to the y direction partially overlaps the orthogonal projection of the gate 410 on the plane perpendicular to the y direction, and does not cut or overlap the orthogonal projection of the gate 411 on the plane perpendicular to the y direction.

[0141] In addition, the other structures and related descriptions of the lateral power semiconductor device 40h are the same as those of the lateral power semiconductor device 40a, and can be referred to the related paragraphs of the lateral power semiconductor device 40a described above, which will not be repeated here.

[0142] In the lateral power semiconductor device 40h described above, by setting the well region 403', compared with the lateral power semiconductor device 40a, the position of the right boundary of the well region is changed, so that the conductive channel only exists in the well region 403' under the gate 410, and only the accumulation layer of the majority carriers is formed under the gate 411, without forming the conductive channel, thereby reducing the on-resistance of the device to reduce the loss of the specific on-resistance. In addition, by canceling the source contact region 406, the doping concentration in the substrate 401 at the lower right corner of the gate 410 can be reduced, thereby reducing the electric field peak at the lower right corner of the gate 410, thereby further preventing the lateral power semiconductor device 40h from being broken down.

[0143] The ninth embodiment of the lateral power semiconductor device of the present application will be described in detail below in combination with FIG. 13. FIG. 13 shows a schematic diagram of the cross-sectional structure of a lateral power semiconductor device 40i.

[0144] As shown in FIG. 13, the lateral power semiconductor device 40i is similar to the lateral power semiconductor device 40h, and the difference between the lateral power semiconductor device 40i and the lateral power semiconductor device 40h is that the lateral power semiconductor device 40i adds a field plate 417 based on the structure of the lateral power semiconductor device 40h.

[0145] The related content of the field plate 417 has been described in the above embodiments, which can be referred to the above embodiments, and will not be repeated here.

[0146] In addition, the other structures and related descriptions of the lateral power semiconductor device 40i are the same as those of the lateral power semiconductor device 40h, and can be referred to the related paragraphs of the lateral power semiconductor device 40h described above, which will not be repeated here.

[0147] The tenth embodiment of the lateral power semiconductor device of the present application will be described in detail below in combination with FIG. 14. FIG. 14 shows a schematic diagram of the cross-sectional structure of a lateral power semiconductor device 40j.

[0148] As shown in FIG. 14, the lateral power semiconductor device 40j is similar to the lateral power semiconductor device 40h, and the difference between the lateral power semiconductor device 40j and the lateral power semiconductor device 40h is that the lateral power semiconductor device 40j adds the blocking layer 418 and the field plate 419 on the basis of the structure of the lateral power semiconductor device 40h.

[0149] The related content of the blocking layer 418 and the field plate 419 has been described in the above embodiments, and can be referred to the above embodiments, which will not be repeated here.

[0150] In addition, the other structures and related descriptions of the lateral power semiconductor device 40j are the same as those of the lateral power semiconductor device 40h, and can be referred to the related paragraphs of the lateral power semiconductor device 40h, which will not be repeated here.

[0151] The eleventh embodiment of the lateral power semiconductor device of the present application will be described in detail below with reference to FIG. 15. FIG. 15 shows a schematic diagram of a cross-sectional structure of a lateral power semiconductor device 40k.

[0152] As shown in FIG. 15, the lateral power semiconductor device 40k is similar to the lateral power semiconductor device 40h, and the difference between the lateral power semiconductor device 40k and the lateral power semiconductor device 40h is that the lateral power semiconductor device 40k adds the field plate 417, the blocking layer 418 and the field plate 419 on the basis of the structure of the lateral power semiconductor device 40h.

[0153] The related content of the field plate 417, the blocking layer 418 and the field plate 419 has been described in the above embodiments, and can be referred to the above embodiments, which will not be repeated here.

[0154] In addition, the other structures and related descriptions of the lateral power semiconductor device 40k are the same as those of the lateral power semiconductor device 40h, and can be referred to the related paragraphs of the lateral power semiconductor device 40h, which will not be repeated here.

[0155] The twelfth embodiment of the lateral power semiconductor device of the present application will be described in detail below with reference to FIG. 16. FIG. 16 shows a schematic diagram of a cross-sectional structure of a lateral power semiconductor device 40l.

[0156] As shown in FIG. 16, the lateral power semiconductor device 40l is similar to the lateral power semiconductor device 40h, and the difference between the lateral power semiconductor device 40l and the lateral power semiconductor device 40h is that the lateral power semiconductor device 40l adds a body contact region 420 (an example of the second body contact region of the present application) in the drift region 402 based on the structure of the lateral power semiconductor device 40h. The body contact region 420 has a normal projection in a plane perpendicular to the y direction that is tangent to the normal projection of the gate 410 in the plane perpendicular to the y direction and tangent to the normal projection of the gate 411 in the plane perpendicular to the y direction.

[0157] In some embodiments, the doping ions of the body contact region 420 are of the second type, and the doping ion concentration of the body contact region 420 is less than the doping ion concentration of the body contact region 404.

[0158] In the above body contact region 420, because the doping ions of the body contact region 420 are of a different type from the doping ions of the drift region 402, the charge distribution in the drift region 402 can be balanced, further reducing the specific on-resistance of the device. In addition, because the boundary of the body contact region 420 does not contact the well region 403', that is, the body contact region 420 is floating, almost no depletion region is generated, which is beneficial to reducing the potential difference between the gate 410 and the drift region 402 when the drain 413 is biased to a high voltage, thereby reducing the electric field strength. The depletion region is also called a space charge region. In a PN junction, due to the diffusion motion of free electrons and the drift motion caused by the internal electric field, a very thin charge region, i.e., a space charge region, is generated at the interface between the P region and the N region in the PN junction.

[0159] The thirteenth embodiment of the lateral power semiconductor device of the present application will be described in detail below with reference to FIG. 17. FIG. 17 shows a schematic diagram of a cross-sectional structure of a lateral power semiconductor device 40m.

[0160] As shown in FIG. 17, the lateral power semiconductor device 40m is similar to the lateral power semiconductor device 40l, and the difference between the lateral power semiconductor device 40m and the lateral power semiconductor device 40l is that the lateral power semiconductor device 40m adds a field plate 417 based on the structure of the lateral power semiconductor device 40l.

[0161] The related content of the field plate 417 has been described in the above embodiments, and can be referred to the above embodiments, which will not be described here again.

[0162] In addition, the other structures and related descriptions of the lateral power semiconductor device 40m are the same as those of the lateral power semiconductor device 40l, and can be referred to the related paragraphs of the lateral power semiconductor device 40l, which will not be described here again.

[0163] The fourteenth embodiment of the lateral power semiconductor device of the present application will be described in detail below with reference to FIG. 18. FIG. 18 shows a schematic cross-sectional structure of a lateral power semiconductor device 40n.

[0164] As shown in FIG. 18, the lateral power semiconductor device 40n is similar to the lateral power semiconductor device 40l, and the difference between the lateral power semiconductor device 40n and the lateral power semiconductor device 40l is that the lateral power semiconductor device 40n adds a source 421 (an example of the second source of the present application) based on the structure of the lateral power semiconductor device 40l. The source 421 is located above the substrate 401 and is connected to the body contact region 420.

[0165] In addition, the other structures and related descriptions of the lateral power semiconductor device 40n are the same as those of the lateral power semiconductor device 40l, and can be referred to the related paragraphs of the lateral power semiconductor device 40l described above, which will not be described here again.

[0166] In some embodiments, the voltage of the source 421 can be the same as that of the source 412, in which case the source 421 and the source 412 can be provided with voltage by the same electrode or different electrodes respectively; or the voltage of the source 421 can be different from that of the source 412, in which case the source 421 and the source 412 are provided with voltage by different electrodes respectively.

[0167] The source 421 provides voltage (potential) to the body contact region 420, which can further control the potential difference between the gate 410 and the drift region 402, thereby adjusting the electric field distribution to further reduce the loss of the device. In addition, when the body contact region 420 is provided with potential, the region with the same doping type as the body contact region 420 can be replenished with carriers (e.g. holes) more quickly during the process of turning on, turning off or freewheeling of the lateral power semiconductor device 40n, thereby making the dynamic performance of the lateral power semiconductor device 40n better to improve the working efficiency of the lateral power semiconductor device 40n.

[0168] The fifteenth embodiment of the lateral power semiconductor device of the present application will be described in detail below with reference to FIG. 19. FIG. 19 shows a schematic cross-sectional structure of a lateral power semiconductor device 40o.

[0169] As shown in FIG. 19, the lateral power semiconductor device 40o is similar to the lateral power semiconductor device 40l, and the difference between the lateral power semiconductor device 40o and the lateral power semiconductor device 40l is that the lateral power semiconductor device 40o adds a field plate 417 and a source 421 based on the structure of the lateral power semiconductor device 40l.

[0170] The field plate 417 and the source 421 have been described in the above embodiments, and thus the description is omitted here.

[0171] In addition, the other structures and related descriptions of the lateral power semiconductor device 40o are the same as those of the lateral power semiconductor device 40l, and thus the description is omitted here.

[0172] A sixteenth embodiment of the lateral power semiconductor device of the present application is described below with reference to FIG. 20. FIG. 20 shows a schematic cross-sectional structure of a lateral power semiconductor device 40p.

[0173] As shown in FIG. 20, the lateral power semiconductor device 40p is similar to the lateral power semiconductor device 40a, and the difference between the lateral power semiconductor device 40p and the lateral power semiconductor device 40a is that the lateral power semiconductor device 40p further includes a body contact region 420 (an example of the second body contact region of the present application), a source 421, and a drift region 422 (an example of the second drift region of the present application) based on the structure of the lateral power semiconductor device 40a, and does not include the source contact region 406. The drift region 422 is disposed in the well region 403, the body contact region 420 is disposed in the drift region 422, and the source 421 is disposed above the substrate 401 and connected to the body contact region 420.

[0174] In addition, the body contact region 420 and the source 421 have been described in the above embodiments, and thus the description is omitted here. In addition, the other structures and related descriptions of the lateral power semiconductor device 40p are the same as those of the lateral power semiconductor device 40a, and thus the description is omitted here.

[0175] Specifically, the drift region 422 has a projection in a plane perpendicular to the y direction that partially overlaps a projection of the gate 410 in the plane perpendicular to the y direction and partially overlaps a projection of the gate 411 in the plane perpendicular to the y direction.

[0176] In some embodiments, the drift region 422 includes a first type of dopant ion.

[0177] The type of the dopant ion in the drift region 422 is different from the type of the dopant ion in the body contact region 420. Since the body contact region 420 includes a second type of dopant ion, the drift region 422 including a first type of dopant ion can further balance the charge under the gate 410, and thus the electric field distribution is more uniform, so that a lower specific on-resistance and a higher breakdown voltage can be obtained, and the device can be further prevented from being broken down and the loss can be further reduced.

[0178] The seventeenth embodiment of the lateral power semiconductor device of the present application will be described below in detail with reference to FIG. 21. FIG. 21 is a schematic cross-sectional structure diagram of a lateral power semiconductor device 40q.

[0179] As shown in FIG. 21, the lateral power semiconductor device 40q is similar to the lateral power semiconductor device 40p, and the difference between the lateral power semiconductor device 40q and the lateral power semiconductor device 40p is that the lateral power semiconductor device 40q adds a field plate 417 on the basis of the structure of the lateral power semiconductor device 40p.

[0180] The related content of the field plate 417 has been described in the above embodiments, and can be referred to the above embodiments, which will not be described here again.

[0181] In addition, the other structures and related descriptions of the lateral power semiconductor device 40q are the same as those of the lateral power semiconductor device 40p, and can be referred to the related paragraphs of the lateral power semiconductor device 40p, which will not be described here again.

[0182] The eighteenth embodiment of the lateral power semiconductor device of the present application will be described below in detail with reference to FIG. 22. FIG. 22 is a schematic cross-sectional structure diagram of a lateral power semiconductor device 40r.

[0183] As shown in FIG. 22, the lateral power semiconductor device 40r is similar to the lateral power semiconductor device 40a, and the difference between the lateral power semiconductor device 40r and the lateral power semiconductor device 40a is that the lateral power semiconductor device 40r adds a barrier layer 418 and a field plate 419 on the basis of the structure of the lateral power semiconductor device 40a.

[0184] The related content of the barrier layer 418 and the field plate 419 has been described in the above embodiments, and can be referred to the above embodiments, which will not be described here again.

[0185] In addition, the other structures and related descriptions of the lateral power semiconductor device 40r are the same as those of the lateral power semiconductor device 40a, and can be referred to the related paragraphs of the lateral power semiconductor device 40a, which will not be described here again.

[0186] The nineteenth embodiment of the lateral power semiconductor device of the present application will be described below in detail with reference to FIG. 23. FIG. 23 is a schematic cross-sectional structure diagram of a lateral power semiconductor device 40s.

[0187] As shown in FIG. 23, the lateral power semiconductor device 40s is similar to the lateral power semiconductor device 40a, and the difference between the lateral power semiconductor device 40s and the lateral power semiconductor device 40a is that the lateral power semiconductor device 40s adds a field plate 417, a barrier layer 418 and a field plate 419 on the basis of the structure of the lateral power semiconductor device 40a.

[0188] The field plate 417, the blocking layer 418 and the field plate 419 are described in the above embodiments, and thus the descriptions are not repeated here.

[0189] In addition, the other structures and related descriptions of the lateral power semiconductor device 40s are the same as those of the lateral power semiconductor device 40a, and thus the descriptions are not repeated here.

[0190] A twentieth embodiment of the lateral power semiconductor device of the present application is described below in detail with reference to FIG. 24. FIG. 24 shows a schematic diagram of a cross-sectional structure of a lateral power semiconductor device 40t.

[0191] As shown in FIG. 24, the lateral power semiconductor device 40t is similar to the lateral power semiconductor device 40a, and the difference between the lateral power semiconductor device 40t and the lateral power semiconductor device 40a is that the lateral power semiconductor device 40t replaces the well region 403 with a well region 403' having a smaller size along the x direction based on the structure of the lateral power semiconductor device 40a, and a well region 423 (an example of the third well region of the present application) is arranged in the drift region 402, so that the source contact region 406 is arranged in the well region 423. The left boundary of the well region 423 is tangent to the right boundary of the well region 403'.

[0192] Specifically, the well region 423 partially overlaps the gate 410 and the gate 411 in the orthogonal projection of the well region 423 on a plane perpendicular to the y direction.

[0193] In addition, the well region 403' is described in the above embodiments, and thus the descriptions are not repeated here.

[0194] In addition, the other structures and related descriptions of the lateral power semiconductor device 40t are the same as those of the lateral power semiconductor device 40a, and thus the descriptions are not repeated here.

[0195] In some embodiments, the well region 423 is doped with ions of the second type.

[0196] The arrangement of the well region 423 can adjust the electric field distribution near the source contact region 406 to improve the problem of early breakdown of the device caused by the low diode breakdown voltage of the contact area between the source contact region 406 and the well region 403. In addition, the well region 423 can also adjust the threshold voltage of the conductive channel under the gate 411, thereby increasing the channel current, and thus improving the saturation current density and the working efficiency of the device.

[0197] A twenty-first embodiment of the lateral power semiconductor device of the present application will be described below with reference to FIG. 25. FIG. 25 is a cross-sectional structure diagram of a lateral power semiconductor device 40u.

[0198] As shown in FIG. 25, the lateral power semiconductor device 40u is similar to the lateral power semiconductor device 40t, and the difference between the lateral power semiconductor device 40u and the lateral power semiconductor device 40t is that the lateral power semiconductor device 40u adds a field plate 417 on the basis of the structure of the lateral power semiconductor device 40t.

[0199] The field plate 417 has been described in the above embodiments, and thus the description will not be repeated here.

[0200] In addition, the other structures and related descriptions of the lateral power semiconductor device 40u are the same as those of the lateral power semiconductor device 40t, and thus the description will not be repeated here.

[0201] A twenty-second embodiment of the lateral power semiconductor device of the present application will be described below with reference to FIG. 26. FIG. 26 is a cross-sectional structure diagram of a lateral power semiconductor device 40v.

[0202] As shown in FIG. 26, the lateral power semiconductor device 40v is similar to the lateral power semiconductor device 40t, and the difference between the lateral power semiconductor device 40v and the lateral power semiconductor device 40t is that the lateral power semiconductor device 40v adds a barrier layer 418 and a field plate 419 on the basis of the structure of the lateral power semiconductor device 40t.

[0203] The barrier layer 418 and the field plate 419 have been described in the above embodiments, and thus the description will not be repeated here.

[0204] In addition, the other structures and related descriptions of the lateral power semiconductor device 40v are the same as those of the lateral power semiconductor device 40t, and thus the description will not be repeated here.

[0205] A twenty-third embodiment of the lateral power semiconductor device of the present application will be described below with reference to FIG. 27. FIG. 27 is a cross-sectional structure diagram of a lateral power semiconductor device 40w.

[0206] As shown in FIG. 27, the lateral power semiconductor device 40w is similar to the lateral power semiconductor device 40t, and the difference between the lateral power semiconductor device 40w and the lateral power semiconductor device 40t is that the lateral power semiconductor device 40w adds the field plate 417, the barrier layer 418 and the field plate 419 on the basis of the structure of the lateral power semiconductor device 40t.

[0207] Among them, the related content of the field plate 417, the blocking layer 418 and the field plate 419 has been described in the above-mentioned embodiments, and can be referred to the above-mentioned embodiments, which will not be repeated here.

[0208] In addition, other structures and related descriptions of the lateral power semiconductor device 40w are the same as those of the lateral power semiconductor device 40t, and can be referred to the related paragraphs of the lateral power semiconductor device 40t described above, which will not be repeated here.

[0209] In some embodiments, the present application also provides a chip, which comprises the lateral power semiconductor device according to any one of the embodiments of the present application.

[0210] In some embodiments, the present application also provides an electronic device, which comprises the lateral power semiconductor device according to any one of the embodiments of the present application.

[0211] FIG. 28 shows a structural schematic diagram of an electronic device 100 according to some embodiments of the present application. Among them, the electronic device 100 comprises the semiconductor device described in any one of the above-mentioned embodiments.

[0212] The electronic device 100 described above can comprise a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) port 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a loudspeaker 170A, a receiver 170B, a microphone 170C, a headset interface 170D, a sensor module 180, a key 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. Among them, the sensor module 180 can comprise a pressure sensor 180A, a gyroscope sensor 180B, a barometric pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0213] It can be understood that the structure shown in the embodiments of the present application does not constitute a specific limitation on the electronic device 100. In some other embodiments of the present application, the electronic device 100 can comprise more or fewer components than those shown, or combine certain components, or split certain components, or different arrangement of components. The components shown can be implemented by hardware, software or a combination of software and hardware.

[0214] The processor 110 can include one or more processing units, e.g., the processor 110 can include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units can be independent devices or integrated in one or more processors.

[0215] The processor 110 can also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory can hold instructions or data that the processor 110 has just used or is recycling. If the processor 110 needs to use the instructions or data again, it can call them directly from the memory. This avoids repeated access and reduces the processor’s 110 latency, thus improving the efficiency of the system.

[0216] In some embodiments, the processor 110 can include one or more interfaces. The interfaces can include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0217] In some embodiments, the charging management module 140 is configured to receive a charging input from a charger.

[0218] In some embodiments, the power management module 141 is configured to connect the battery 142, and the charging management module 140 is configured to connect the processor 110.

[0219] In some embodiments, the wireless communication function of the electronic device 100 can be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor, and the baseband processor, etc.

[0220] In some embodiments, the antenna 1 and the antenna 2 are configured to transmit and receive electromagnetic wave signals. Each antenna in the electronic device 100 can be configured to cover a single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization of the antennas. For example, the antenna 1 can be multiplexed as a diversity antenna for wireless local area networks. In some other embodiments, the antennas can be used in combination with a tuning switch.

[0221] In some embodiments, the mobile communication module 150 can provide a solution for wireless communication including 2G / 3G / 4G / 5G, etc. applied to the electronic device 100.

[0222] In some embodiments, the modem processor can include a modulator and a demodulator.

[0223] In some embodiments, the wireless communication module 160 can provide a solution for wireless communication including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR) technology, etc. applied to the electronic device 100. The wireless communication module 160 can be one or more devices integrated with at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, performs frequency modulation and filtering processing on the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 can also receive signals to be sent from the processor 110, perform frequency modulation, amplification, and convert the signals to electromagnetic wave radiation via the antenna 2.

[0224] In some embodiments, the antenna 1 and the mobile communication module 150 of the electronic device 100 are coupled, and the antenna 2 and the wireless communication module 160 are coupled, so that the electronic device 100 can communicate with a network and other devices through wireless communication technology. The wireless communication technology can include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technology, etc. The GNSS can include global positioning system (GPS), global navigation satellite system (GLONASS), beidou navigation satellite system (BDS), quasi-zenith satellite system (QZSS), and / or satellite based augmentation systems (SBAS).

[0225] In some embodiments, the electronic device 100 implements a display function through a GPU, a display screen 194, an application processor, etc.

[0226] In some embodiments, the display screen 194 is used to display images, videos, etc.

[0227] In some embodiments, the electronic device 100 can implement a photographing function through an ISP, a camera 193, a video codec, a GPU, a display screen 194, an application processor, etc.

[0228] In some embodiments, the camera 193 is used to capture still images or videos.

[0229] In some embodiments, the external memory interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100.

[0230] In some embodiments, the internal memory 121 can be used to store computer executable program code, which includes instructions.

[0231] In some embodiments, the electronic device 100 can implement audio functions through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the earphone interface 170D, and the application processor, etc. For example, music playing, recording, etc.

[0232] In some embodiments, the audio module 170 is used to convert digital audio information into analog audio signals output, and also used to convert analog audio input into digital audio signals.

[0233] In some embodiments, the speaker 170A, also called "loudspeaker", is used to convert audio electrical signals into sound signals.

[0234] In some embodiments, the receiver 170B, also called "earpiece", is used to convert audio electrical signals into sound signals.

[0235] In some embodiments, the microphone 170C, also called "microphone", "sounder", is used to convert sound signals into electrical signals.

[0236] In some embodiments, the earphone interface 170D is used to connect wired earphones.

[0237] In some embodiments, the keys 190 include the power key, the volume key, etc.

[0238] In some embodiments, the motor 191 can generate vibration prompts.

[0239] In some embodiments, the indicator 192 can be an indicator light, which can be used to indicate the charging state, the power change, and also can be used to indicate messages, missed calls, notifications, etc.

[0240] In some embodiments, the SIM card interface 195 is used to connect the SIM card.

[0241] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting; it is not intended to exclude myriad other embodiments of the present application that other inventors can develop based on the description herein. It must be stressed, however, that any combination of the components or features taught according to any aspect of the present application can be important sufficient to confer "patentable" subject matter status on a patent application or patent. It should be noted that in the examples and description of the present application, relative terms such as first and second and the like are used merely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises", "comprising", or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0242] While the application has been illustrated and described in the context of certain illustrative embodiments, it will be understood by those skilled in the art that various changes in form and detail can be made therein without departing from the scope of the application.

Claims

A lateral power semiconductor device characterized by The semiconductor device comprises a substrate and a first source, a first drain, a first gate, a second gate, a first isolation layer and a second isolation layer arranged above the substrate; wherein, The first source, the first gate, the second gate and the first drain are arranged in sequence; The second gate comprises a first gate region and a second gate region, wherein the second gate region is closer to the first drain than the first gate region; and, The first isolation layer is between the first gate region and the substrate, and the second isolation layer is between the second gate region and the substrate; and, The thickness of the first isolation layer is less than the thickness of the second isolation layer. The semiconductor device according to Claim 1, wherein The bottom surface of the first gate region is closer to the substrate than the bottom surface of the second gate region; and / or The top surface of the first gate region is closer to the substrate than the top surface of the second gate region. The semiconductor device according to Claim 1, wherein The material of the first isolation layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbon nitride; and / or The material of the second isolation layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbon nitride. The semiconductor device according to any one of claims 1 to 3, characterized in that The semiconductor device further comprises a first barrier layer; wherein the first barrier layer is above the substrate and between the second gate region and the first drain, and the first barrier layer is also above the surface of the part of the second gate region close to the first drain. The semiconductor device according to claim 4, wherein The semiconductor device further comprises a first field plate; wherein the first field plate is above and connected to the first barrier layer. The semiconductor device according to any one of claims 1 to 3, characterized in that The semiconductor device further comprises a gate electrode; wherein the gate electrode is above the substrate and connected to the second gate, and the gate electrode is used to provide a bias voltage for the second gate. The semiconductor device according to any one of claims 1 to 3, characterized in that The semiconductor device further comprises a second field plate and a second barrier layer; wherein the second field plate is above the gap between the first gate and the second gate, and the second barrier layer is between the second field plate and the substrate and connected to the second field plate. The semiconductor device according to any one of claims 1 to 3, characterized in that The substrate comprises a base and a first drift region, a first well region, a first body contact region, a first source contact region and a first drain contact region above the base; wherein, The first well region and the first drain contact region are in the first drift region, and the first body contact region and the first source contact region are in the first well region and arranged in sequence; and, The orthographic projection of the first gate on a first plane is in the orthographic projection of the first well region on the first plane, and the orthographic projection of the second gate on the first plane partially overlaps with the orthographic projection of the first well region on the first plane; The first body contact region and the first source contact region are tangent and both connected to the first source; The orthographic projection of the first source contact region on the first plane is tangent to the orthographic projection of the first gate on the first plane; The first drain contact region is connected to the first drain, and the first plane is perpendicular to the thickness direction of the substrate. The semiconductor device according to claim 8, characterized in that The substrate further comprises a second source contact region; wherein the second source contact region is in the first well region; and, The first source contact region is connected to the first source, and the second source contact region is connected to the second source. The second source contact region is tangent to or partially overlaps the first gate in the first plane and tangent to or partially overlaps the second gate in the first plane. The semiconductor device according to claim 8, characterized in that, The substrate further comprises a second body contact region and a second drift region; wherein the second drift region is located in the first well region, and the second body contact region is located in the second drift region; and, The second drift region partially overlaps the first gate in the first plane and partially overlaps the second gate in the first plane; The second body contact region is tangent to the first gate in the first plane and tangent to the second gate in the first plane. The semiconductor device according to any one of claims 1 to 3, characterized in that The substrate comprises a base and a first drift region, a second well region, a first body contact region, a first source contact region and a first drain contact region located above the base; wherein, The second well region and the first drain contact region are located in the first drift region, and the first body contact region and the first source contact region are located in the second well region; and, The second well region partially overlaps the first gate in the first plane; The first body contact region and the first source contact region are tangent to the first source; The first source contact region is tangent to the first gate in the first plane; The first drain contact region is connected to the first drain, and the first plane is perpendicular to the thickness direction of the substrate. The semiconductor device according to claim 11, characterized by The substrate further comprises a second source contact region and a third well region; wherein, The third well region is located in the first drift region, the second source contact region is located in the third well region, and the third well region is tangent to the second well region; The third well region partially overlaps the first gate in the first plane and partially overlaps the second gate in the first plane; The second source contact region is tangent to or partially overlaps the first gate in the first plane and tangent to or partially overlaps the second gate in the first plane. The semiconductor device according to claim 11, characterized by The substrate further comprises a second body contact region; wherein the second body contact region is located in the first drift region, and the second body contact region is tangent to the first gate in the first plane and tangent to the second gate in the first plane. The semiconductor device according to claim 13, characterized by The semiconductor device further comprises a second source; wherein the second source is located above the substrate and connected to the second body contact region. A chip characterized by The semiconductor device comprises the semiconductor device as claimed in any one of claims 1-14. An electronic device, characterized by comprising: The semiconductor device comprises the semiconductor device as claimed in any one of claims 1-14.

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