Arithmetic logic unit, processor, computing chip, and computing device

Abstract

The present disclosure relates to an arithmetic logic unit, a processor, a computing chip, and a computing device. Disclosed is an arithmetic logic unit, which is used for receiving two binary integers and capable of implementing two or more operations for at least one of the two binary integers. The arithmetic logic unit comprises: an adder, used for receiving a first input, a second input, and a carry input, and outputting the sum of the first input, the second input, and the carry input, the carry input being 1 or 0; a first input selection module, comprising at least one input end and an output end coupled to the first input of the adder; a second input selection module, comprising at least two input ends and an output end coupled to the second input of the adder; a carry input selection module, comprising at least one input end and an output end coupled to the carry input of the adder; and an output selection module, comprising at least three input ends and an output end coupled to an output end of the arithmetic logic unit, wherein at least one input end is coupled to the sum outputted from the adder.

Description

Arithmetic logic units, processors, computing chips and computing devices

[0001] Cross-reference to Related Applications

[0002] This application is based on and claims priority to the application with CN application number 202410971000.X and filing date of July 19, 2024, the disclosure of which is incorporated herein in its entirety. TECHNICAL FIELD

[0003] The present application relates to the field of computers. In particular, the present application relates to a processor and a computing chip and a computing device comprising the processor, which is particularly suitable for neural network related computation. BACKGROUND

[0004] In various application scenarios related to the field of computers (e.g. neural networks, etc.), a large number of operations are usually required to be performed by a processor. An arithmetic logic unit (ALU) is a unit for performing arithmetic operations in a processor, which is usually capable of implementing a variety of operations, such as addition, subtraction, absolute value, maximum value, minimum value, etc. The power consumption and area of the arithmetic logic unit are crucial to the efficiency and cost of the processor and the entire computing device. It is desirable to implement an arithmetic logic unit with lower power consumption and smaller area, so as to improve the computing efficiency of the processor and reduce the production cost and running cost.

[0005] Therefore, there is a need for new technology. SUMMARY

[0006] It is one of the objectives of the present disclosure to provide an improved arithmetic logic unit.

[0007] According to one aspect of the present application, there is provided an arithmetic logic unit for receiving two binary integers a and b, capable of implementing two or more operations on at least one of a and b, the arithmetic logic unit comprising: an adder for receiving a first input A, a second input B and a carry input Ci, and outputting a sum S of the first input A, the second input B and the carry input Ci, wherein the carry input Ci is 1 or 0; a first input selection module comprising at least one input terminal, and an output terminal coupled to the first input A of the adder; a second input selection module comprising at least two input terminals, and an output terminal coupled to the second input B of the adder; a carry input selection module comprising at least one input terminal, and an output terminal coupled to the carry input Ci of the adder; an output selection module comprising at least three input terminals, and an output terminal coupled to an output terminal of the arithmetic logic unit, wherein at least one input terminal is coupled to the sum S outputted by the adder.

[0008] According to another aspect of the present application, a processor is provided that includes one or more of the above arithmetic logic units.

[0009] According to yet another aspect of the present application, a computing chip is provided that includes one or more of the above processors.

[0010] According to yet another aspect of the present application, a computing device is provided that includes one or more of the above computing chips.

[0011] Other characteristic features and advantages of the present application will become clear from the following description with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings are included to provide an illustrative disclosure of the application and are only for the purpose of providing an example of the possible structures and arrangements of the inventive apparatus disclosed herein and the method of applying it to a computing device. These drawings are in no way limiting of the scope of the embodiments, which are set forth in the claims. The embodiments are more fully described with reference to the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters designate like structural elements throughout the various figures.

[0013] FIG. 1 shows a schematic diagram of an arithmetic logic unit of the related art.

[0014] FIG. 2 shows a schematic diagram of an arithmetic logic unit according to one embodiment of the present application.

[0015] FIG. 3 shows a schematic diagram of a comparison module in an output selection module of an arithmetic logic unit according to one embodiment of the present application.

[0016] Note that, in the following embodiments, the same reference numbers are sometimes used across different drawings to indicate the same or similar parts or parts having the same function, and repetitive explanation thereof is omitted. In this specification, like numbers and letters designate like elements throughout the specification, and thus, once an element is defined in one drawing, further discussion of the same element is omitted in subsequent drawings.

[0017] For ease of understanding, the positions, sizes, ranges, and the like of the structures shown in the drawings and the like are sometimes not actual ones. Therefore, the disclosed application is not limited to the positions, sizes, ranges, and the like disclosed in the drawings and the like. Further, the drawings are not necessarily drawn to scale, and some features can be exaggerated to show specific components in detail. DETAILED DESCRIPTION

[0018] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps, numerical expressions, and numerical values set forth in these embodiments are not limiting of the scope of the present disclosure unless otherwise specifically stated.

[0019] The following description of at least one example embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses, nor is it intended to limit the scope of applicability or the scope of the art in which various embodiments of the present disclosure can be practiced. That is, the circuits herein are shown in an exemplary manner to illustrate different embodiments of circuits in the present disclosure, and are not intended to be limiting. This description will be understood by those skilled in the art to be a broad overview of the appropriate technology, methods and apparatus known to one of ordinary skill in the relevant art, and should be taken as a specification to this patent.

[0020] Techniques, methods, and apparatus known to those of ordinary skill in the relevant art can not be discussed in detail herein, but should be considered part of the specification to the extent that they are appropriately described in connection with the present disclosure.

[0021] In the present disclosure, each unit is generally implemented by a circuit, and each module of the unit is generally implemented by a sub-circuit of the circuit, and thus the terms "unit" and "circuit", "module" and "sub-circuit" are used interchangeably herein.

[0022] FIG. 1 shows a schematic diagram of an arithmetic logic unit 100 of the related art. The arithmetic logic unit 100 is configured to receive two numbers a and b, and is capable of implementing a plurality of operations on at least one of a and b, such as addition, subtraction, absolute value, maximum value, minimum value, etc. Each of a and b is a binary integer.

[0023] The arithmetic logic unit 100 includes a plurality of operation sub-units 111, 112, 113, 114, 115, and an output selection module 120. Each of the operation sub-units receives the two numbers a and b, and is configured to perform an operation (such as one of addition, subtraction, absolute value, maximum value, minimum value), and outputs the operation result to the output selection module 120.

[0024] The output selection module 120 receives the outputs of each of the operator units, and receives a flag indicating the operation to be implemented by the arithmetic logic unit 100. The flag is represented by the label 1100, including, for example, a flag ADD indicating that the arithmetic logic unit 100 is to implement an a plus b operation, a flag SUB indicating that the arithmetic logic unit 100 is to implement an a minus b operation, a flag ABS indicating that the arithmetic logic unit 100 is to implement an absolute value of a operation, a flag MAX indicating that the arithmetic logic unit 100 is to implement a maximum of a and b operation, and a flag MIN indicating that the arithmetic logic unit 100 is to implement a minimum of a and b operation. The output selection module 120 selects, as the output x of the arithmetic logic unit 100, the output of the operator unit in the plurality of operator units 111, 112, 113, 114, 115 that is used to perform the corresponding operation based on the flag 1100. For example, when ADD is 1 and the other flags are 0, indicating that the arithmetic logic unit 100 is to implement an a plus b operation, the output selection module 120 selects the output of the operator unit (e.g., the addition operator unit 111) that is used to perform the addition operation as the output x of the arithmetic logic unit 100. The addition operator unit 111 can be implemented by an adder that is used to calculate the sum of a plus b.

[0025] However, the arithmetic logic unit 100 of the related art has some problems. When the arithmetic logic unit 100 is running, each of the operator units performs an operation, but only one of the operation results is selected and output by the output selection module 120. In other words, the arithmetic logic unit 100 performs a large number of invalid operations, resulting in a large power consumption and a large area occupation.

[0026] The present disclosure aims to implement an arithmetic logic unit with lower power consumption and smaller area, thereby improving the computing efficiency of the processor and reducing the production cost and operating cost.

[0027] FIG. 2 shows a schematic diagram of an arithmetic logic unit 200 according to an embodiment of the present disclosure. The arithmetic logic unit 200 is used to receive two numbers a and b, and is capable of implementing a plurality of operations on at least one of a and b. Here, a and b are both binary integers.

[0028] The arithmetic logic unit 200 includes an adder 210, a first input selection module 220, a second input selection module 230, a carry input selection module 240, and an output selection module 250.

[0029] The adder 210 is configured to receive a first input A, a second input B, and a carry input Ci, and output a sum S of the first input A, the second input B, and the carry input Ci, where the carry input Ci is either 1 or 0. As will be described in detail below, the arithmetic logic unit 200 can utilize the adder 210 to implement a plurality of operations, including a + b, a - b, the absolute value of a, the maximum of a and b, the minimum of a and b, the comparison result of a and b, and the like.

[0030] The adder 210 can be implemented similarly to the adder in the adder operator unit 111 in the related-art arithmetic logic unit 100 shown in FIG. 1, except that the adder in the adder operator unit 111 in the related art is configured to calculate the sum of two N-bit binary numbers a and b, while the adder 210 is configured to calculate the sum of two N-bit binary numbers (the first input A, the second input B) and a 1-bit carry input (the carry input Ci). Those skilled in the art will appreciate that, in implementing an adder configured to calculate the sum of two N-bit binary numbers a and b, only the sum of the least significant bits of a and b needs to be calculated at the least significant bit, while the sum of the corresponding bits of a, the corresponding bits of b, and the carry from the previous bit needs to be calculated at each of the other bits. Thus, in implementing an adder configured to calculate the sum of two N-bit binary numbers a and b and a 1-bit carry input, a similar implementation as that of the adder configured to calculate the sum of two N-bit binary numbers a and b can be employed, except that the calculation module for the least significant bit is modified (i.e., to calculate the sum of the least significant bit of a, the least significant bit of b, and the 1-bit carry input), while the calculation modules for the other bits remain unchanged.

[0031] That is, the specific circuitry of the adder 210 configured to calculate the sum of two N-bit binary numbers a and b and a 1-bit carry input can be substantially the same as that of the adder configured to calculate the sum of two N-bit binary numbers a and b, except that the calculation module for the least significant bit is slightly different. In practical applications, N is usually large (e.g., 32 or 64), and thus the slight increase in calculation power consumption and area due to the slightly more complex calculation module for the least significant bit is almost negligible relative to the total power consumption and total area of the adder. That is, the power consumption and area of the adder 210 used by the arithmetic logic unit 200 of the present disclosure is substantially the same as that of the adder used in the adder operator unit 111 in the related-art arithmetic logic unit 100.

[0032] The arithmetic logic unit 200 of the present disclosure utilizes only the adder 210 to implement a plurality of operations, while omitting the other plurality of operator units (operator units 112, 113, 114, 115) used in the related-art arithmetic logic unit 100, thereby significantly reducing the calculation power consumption and area of the arithmetic logic unit 200 relative to the related art, improving the calculation efficiency of the processor, and reducing the production cost and operating cost.

[0033] The first input selection module 220 can selectively output a value as the first input A of the adder 210 according to the operation to be implemented by the arithmetic logic unit 200. The first input selection module 220 includes at least one input terminal, and an output terminal coupled to the first input A of the adder 210. In particular, the at least one input terminal of the first input selection module 220 can receive a.

[0034] Fig. 2 schematically shows that the two input terminals of the first input selection module 220 receive a and 0 respectively, and the first input selection module 220 selects the value received at one input terminal (i.e. a or 0) as the first input A of the adder 210 according to the operation to be implemented by the arithmetic logic unit 200. However, it should be understood that the implementation of the first input selection module 220 shown in Fig. 2 is only for intuitively illustrating its working principle, and the module can be implemented in a more simple and efficient manner.

[0035] In exemplary embodiments, the arithmetic logic unit 200 can implement the following operations: a plus b, a minus b, absolute value of a, maximum of a and b, minimum of a and b, etc. In particular, the first input selection module 220 can be configured to output a as the first input A of the adder 210 when the arithmetic logic unit 200 is to implement any one of a plus b, a minus b, maximum of a and b, minimum of a and b; and output 0 as the first input A of the adder 210 when the arithmetic logic unit 200 is to implement the absolute value of a.

[0036] In exemplary embodiments, as shown in Fig. 2, the first input selection module 220 can receive a flag representing the operation to be implemented by the arithmetic logic unit 200. The flag is represented by reference numeral 2100, including, for example, a flag ADD representing that the arithmetic logic unit 200 is to implement a plus b operation, a flag SUB representing that the arithmetic logic unit 200 is to implement a minus b operation, a flag ABS representing that the arithmetic logic unit 200 is to implement the absolute value of a operation, a flag MAX representing that the arithmetic logic unit 200 is to implement the maximum of a and b operation, and a flag MIN representing that the arithmetic logic unit 200 is to implement the minimum of a and b operation. For example, the flag is 1 when the arithmetic logic unit 200 is to implement the corresponding operation, wherein at most one of all the flags ADD, SUB, ABS, MAX, MIN, etc. is 1. In this way, the first input selection module 220 can be configured to output a as the first input A of the adder 210 when any one of the received flags ADD, SUB, MAX, MIN is 1; and output 0 as the first input A of the adder 210 when the received flag ABS is 1.

[0037] In some embodiments, the first input selection module 220 can be implemented by N AND gates with two inputs, where N is the number of bits of the binary number a and b. In particular, one input of each AND gate receives a respective bit of a, and the other input can receive either 0 or 1 in response to the operation to be implemented by the arithmetic logic unit 200. In particular, the other input can receive 1 when the arithmetic logic unit is to implement any one of the operations of a plus b, a minus b, maximum of a and b, minimum of a and b, and can receive 0 when the arithmetic logic unit is to implement the absolute value of a operation. For example, in embodiments where a flag ADD, SUB, MAX, MIN, etc. is set to 1 to indicate that the arithmetic logic unit 200 is to implement the corresponding operation, the other input of each AND gate can receive the result of the OR operation of the flags ADD, SUB, MAX, MIN, etc.

[0038] The second input selection module 230 can selectively output a value as the second input B of the adder 210 in response to the operation to be implemented by the arithmetic logic unit 200. The second input selection module 230 can include at least two inputs, and an output coupled to the second input B of the adder 210. In particular, at least one input of the second input selection module 230 can receive a or a value related thereto, and another at least one input can receive b or a value related thereto. Here, a value related to a or b means a value of a or b after simple processing, such as ~a or ~b, where the symbol ~ represents a bitwise inversion.

[0039] Figure 2 schematically illustrates that the three inputs of the second input selection module 230 receive b, ~a, and ~b, respectively, and the second input selection module 230 selects the value received at one input (i.e., b, ~a, or ~b) as the second input B of the adder 210 in response to the operation to be implemented by the arithmetic logic unit 200. However, it should be understood that the implementation of the second input selection module 230 shown in Figure 2 is only for the purpose of intuitively illustrating its working principle, and the module can be implemented in a more simple and efficient manner.

[0040] In particular, in exemplary embodiments, the second input selection module 230 can be configured to output b as the second input B of the adder 210 when the arithmetic logic unit 200 is to implement the a plus b operation, to output ~a as the second input B of the adder 210 when the arithmetic logic unit 200 is to implement the absolute value of a operation, and to output ~b as the second input B of the adder 210 when the arithmetic logic unit 200 is to implement any one of the operations of a minus b, maximum of a and b, and minimum of a and b.

[0041] In exemplary embodiments, as shown in FIG. 2, the second input selection module 230 can receive flags 2100 indicative of the operation to be implemented by the arithmetic logic unit 200. For example, in embodiments where a flag of 1 indicates that the corresponding operation is to be implemented by the arithmetic logic unit 200, the second input selection module 230 can be configured to output b as the second input B of the adder 210 when the received flag ADD is 1, to output ~a as the second input B of the adder 210 when the received flag ABS is 1, and to output ~b as the second input B of the adder 210 when any of the received flags SUB, MAX, MIN is 1.

[0042] In some embodiments, the second input selection module 230 can be implemented by a three-control-selector ao 222 including three input terminals that receive b, ~b, and ~a, respectively.

[0043] The carry input selection module 240 can selectively output 0 or 1 as the carry input Ci of the adder 210 depending on the operation to be implemented by the arithmetic logic unit 200. The carry input selection module 240 can include at least one input terminal, and an output terminal coupled to the carry input Ci of the adder 210.

[0044] FIG. 2 schematically shows that the two input terminals of the carry input selection module 240 receive 0 and 1, respectively, and the carry input selection module 240 selects the value (i.e., 0 or 1) received at one of the input terminals as the carry input Ci of the adder 210 depending on the operation to be implemented by the arithmetic logic unit 200. However, it should be understood that the implementation of the carry input selection module 240 shown in FIG. 2 is only for intuitively illustrating its working principle, and the module can be implemented in a more simple and efficient manner.

[0045] In particular, in exemplary embodiments, the carry input selection module 240 can be configured to output 0 as the carry input Ci of the adder when the arithmetic logic unit 200 is to implement the a + b operation, and to output 1 as the carry input Ci of the adder when the arithmetic logic unit 200 is to implement any of the a - b, the absolute value of a, the maximum of a and b, and the minimum of a and b operations.

[0046] In exemplary embodiments, as shown in FIG. 2, the carry input selection module 240 can receive flags 2100 indicative of the operation to be implemented by the arithmetic logic unit 200. For example, in embodiments where a flag of 1 indicates that the corresponding operation is to be implemented by the arithmetic logic unit 200, the carry input selection module 240 can be configured to output 0 as the carry input Ci of the adder 210 when the received flag ADD is 1, and to output 1 as the carry input Ci of the adder 210 when any of the received flags SUB, ABS, MAX, MIN is 1.

[0047] In some embodiments, the carry-in selection module 240 can be implemented by an OR gate having a plurality of inputs receiving at least a portion of the flags indicative of the operation to be implemented by the arithmetic logic unit 200. For example, the OR gate can have at least four inputs receiving the flags SUB, ABS, MAX, MIN, etc. respectively.

[0048] The output selection module 250 can selectively output one of the values as the output x of the arithmetic logic unit 200 according to the operation to be implemented by the arithmetic logic unit 200. The output selection module 250 can include at least three inputs and an output coupled to the output of the arithmetic logic unit 200. In particular, at least one of the inputs of the output selection module 250 can be coupled to the sum S output by the adder 210, another at least one of the inputs can receive a, and another at least one of the inputs can receive b.

[0049] Figure 2 schematically shows that the three inputs of the output selection module 250 receive a, b and S respectively, and the output selection module 250 can select the value received at one of the inputs (i.e. a, b or S) as the output x of the arithmetic logic unit 200 according to the operation to be implemented by the arithmetic logic unit 200. However, it should be understood that the implementation of the output selection module 250 shown in Figure 2 is only for the purpose of intuitively illustrating its working principle, and the module can be implemented in a more simple and efficient manner.

[0050] In particular, in the exemplary embodiments, the output selection module 250 can be configured to output the sum S as the output x of the arithmetic logic unit 200 when the arithmetic logic unit 200 is to implement either of the operations of a plus b, a minus b; select the sum S or a as the output x of the arithmetic logic unit 200 based on the sign bit of a when the arithmetic logic unit 200 is to implement the operation of taking the absolute value of a; select a or b as the output x of the arithmetic logic unit 200 based on the sign bit of the sum S when the arithmetic logic unit 200 is to implement either of the operations of taking the maximum of a and b, taking the minimum of a and b.

[0051] In particular, the output selection module 250 can be configured to select a as the output of the arithmetic logic unit 200 in response to the sign bit of a being 0 and select the sum S as the output of the arithmetic logic unit 200 in response to the sign bit of a being 1 when the arithmetic logic unit 200 is to implement an absolute value operation on a; select a as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 0 and select b as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 1 when the arithmetic logic unit 200 is to implement a maximum operation on a and b; select b as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 0 and select a as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 1 when the arithmetic logic unit 200 is to implement a minimum operation on a and b. It is understood by those skilled in the art that the sign bit of a binary integer being 0 indicates that the number is non-negative and the sign bit of a binary integer being 1 indicates that the number is negative.

[0052] In exemplary embodiments, the output selection module 250 can receive a flag 2100 of the operation to be implemented by the arithmetic logic unit 200, as shown in FIG. 2. For example, in embodiments where a flag of 1 indicates that the arithmetic logic unit 200 is to implement the corresponding operation, the output selection module 250 can be configured to output the sum S as the output of the arithmetic logic unit 200 when either of the received flags ADD, SUB is 1; select a as the output of the arithmetic logic unit 200 in response to the sign bit of a being 0 and select the sum S as the output of the arithmetic logic unit 200 in response to the sign bit of a being 1 when the received flag ABS is 1; select a as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 0 and select b as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 1 when the received flag MAX is 1; select b as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 0 and select a as the output of the arithmetic logic unit 200 in response to the sign bit of the sum S being 1 when the received flag MIN is 1.

[0053] In some embodiments, the arithmetic logic unit 200 can be further configured to implement a comparison result operation on a and b. In particular, the arithmetic logic unit 200 can output at least one of a flag indicating whether a is equal to b, a is greater than b, or a is less than b as the output x of the arithmetic logic unit 200. For example, the arithmetic logic unit 200 can output flags indicating that a is equal to b, a is not greater than b, and a is not less than b as the output x of the arithmetic logic unit 200.

[0054] In particular, the first input selection module 220 can be configured to output a as the first input A of the adder 210 when the arithmetic logic unit 200 is to implement a comparison result operation on a and b; the second input selection module 230 can be configured to output ~b as the second input B of the adder 210 when the arithmetic logic unit 200 is to implement a comparison result operation on a and b; the carry input selection module 240 can be configured to output 1 as the carry input Ci of the adder 210 when the arithmetic logic unit 200 is to implement a comparison result operation on a and b; and the output selection module 250 can be configured to output one of the flags representing that a is equal to b, a is greater than b, and a is less than b as the output x of the arithmetic logic unit 200 based on whether a and b are equal and the sign bit of S when the arithmetic logic unit 200 is to implement a comparison result operation on a and b.

[0055] In exemplary embodiments, the first input selection module 220, the second input selection module 230, the carry input selection module 240, and the output selection module 250 can receive a flag (not shown in FIG. 2) representing that the arithmetic logic unit 200 is to implement a comparison result operation on a and b. For example, the first input selection module 220, the second input selection module 230, the carry input selection module 240, and the output selection module 250 can output a as the first input A of the adder 210, output ~b as the second input B of the adder 210, output 1 as the carry input Ci of the adder 210, and output one of the flags representing that a is equal to b, a is greater than b, and a is less than b as the output x of the arithmetic logic unit 200 based on whether a and b are equal and the sign bit of S, respectively, in response to the flag being 1.

[0056] The output selection module 250 can include a comparison module 350 for implementing a comparison result operation on a and b. In particular, the comparison module 350 is configured to output one of the flags representing that a is equal to b, a is greater than b, and a is less than b as the output x of the arithmetic logic unit 200 based on whether a and b are equal and the sign bit of S.

[0057] FIG. 3 shows a schematic diagram of the comparison module 350 in the output selection module 250 of the arithmetic logic unit 200 according to one embodiment of the present application.

[0058] As shown in FIG. 3, the comparison module 350 can include an equality determination module 351, a sign bit determination module 352, and a greater than determination module 353.

[0059] The equality determination module 351 is configured to determine whether a and b are equal. The equality determination module 351 receives a and b, and outputs a flag indicating that a and b are equal (e.g., outputs 1 when a and b are equal). The comparison module 350 is configured to output the flag EQ indicating that a is equal to b as the output x of the arithmetic logic unit 200 in response to the equality determination module 351 outputting the flag indicating that a and b are equal (e.g., outputting 1) when the arithmetic logic unit 200 is to implement the comparison result operation of a and b. In particular, as shown in FIG. 3, the output of the equality determination module 351 can be directly coupled to the output of the comparison module 350.

[0060] In some embodiments, the equality determination module 351 can be implemented by a combination of multiple XNOR gates and one or more AND gates. For example, the equality determination module 351 can be implemented by a combination of N XNOR gates and one N-input AND gate, where N is the number of bits of the binary numbers a and b. Each XNOR gate has one input receiving one bit of a and the other input receiving the corresponding bit of b, and the output is coupled to a corresponding input of the N-input AND gate. The N-input AND gate outputs 1 if and only if a and b are equal. In some implementations, the N-input AND gate can be replaced by a combination of multiple AND gates with fewer inputs.

[0061] The sign bit determination module 352 is configured to determine the sign bit of the sum S. The sign bit determination module 352 receives the sum S, and outputs the sign bit of the sum S (e.g., outputs 1 when the sign bit of the sum S is 1, and outputs 0 otherwise). The comparison module 350 is configured to output the flag LT indicating that a is less than b as the output x of the arithmetic logic unit 200 in response to the sign bit of the sum S being 1 when the arithmetic logic unit 200 is to implement the comparison result operation of a and b. In particular, as shown in FIG. 3, the output of the sign bit determination module 352 can be directly coupled to the output of the comparison module 350.

[0062] The greater than determination module 353 is configured to determine whether a is greater than b. The greater than determination module 353 includes two inputs coupled to the outputs of the equality determination module 351 and the sign bit determination module 352, respectively. The greater than determination module 353 is configured to output the flag GT indicating that a is greater than b as the output x of the arithmetic logic unit 200 in response to the sign bit of the sum S being 0 and the equality determination module outputting the flag indicating that a and b are not equal when the arithmetic logic unit 200 is to implement the comparison result operation of a and b. In particular, the greater than determination module 353 can be implemented by an OR-NOT gate.

[0063] In one implementation, a processor can include one or more of the above arithmetic logic units. In one implementation, a computing chip can include one or more of the above processors. In one implementation, a computing device can include one or more computing chips. Multiple computing chips can perform computing tasks in parallel.

[0064] In all of the compositions and methods shown and discussed herein, any specific values should be interpreted as merely exemplary, and are not intended to be limiting. Thus, other examples of the exemplary embodiments can have different values.

[0065] It will also be understood that the term "comprising" or "including" when used herein, specifies the presence of stated features, integers, steps, operations, units and / or components but does not preclude the presence or addition of one or more other features, integers, steps, operations, units and / or components, and / or groups thereof.

[0066] While specific embodiments of the application have been shown and discussed in detail herein, it will be understood by those skilled in the art that the examples presented herein are intended to be illustrative only, and not limiting of the scope of the present application. Those skilled in the art will understand that the above-described embodiments can be modified in various ways without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. An arithmetic logic unit for receiving two binary integers a and b, capable of implementing two or more operations on at least one of a and b, the arithmetic logic unit comprising: a summer for receiving a first input A, a second input B, and a carry input Ci, and outputting a sum S of the first input A, the second input B, and the carry input Ci, wherein the carry input Ci is 1 or 0; a first input selection module comprising at least one input and an output coupled to the first input A of the summer; a second input selection module comprising at least two inputs and an output coupled to the second input B of the summer; a carry input selection module comprising at least one input and an output coupled to the carry input Ci of the summer; an output selection module comprising at least three inputs and an output coupled to an output of the arithmetic logic unit, wherein at least one of the inputs is coupled to the sum S output by the summer.

2. The arithmetic logic unit of claim 1, wherein the at least one input of the first input selection module receives a.

3. The arithmetic logic unit of claim 2, wherein the first input selection module is configured to: output a as the first input A of the summer when the arithmetic logic unit is to implement any one of a + b, a - b, max(a, b), min(a, b); output 0 as the first input A of the summer when the arithmetic logic unit is to implement an absolute value of a operation.

4. The arithmetic logic unit of claim 3, wherein the first input selection module is implemented by N AND gates comprising two inputs, wherein one input of each AND gate receives a respective bit of a, and the other input receives 1 when the arithmetic logic unit is to implement any one of a + b, a - b, max(a, b), min(a, b), and receives 0 when the arithmetic logic unit is to implement an absolute value of a operation, where N is the number of bits of the binary numbers a and b.

5. The arithmetic logic unit of claim 1, wherein at least one of the at least two inputs of the second input selection module receives a or ~a, and at least one other of the at least two inputs receives b or ~b, where the symbol ~ denotes a bitwise NOT.

6. The arithmetic logic unit of claim 5, wherein the second input selection module is configured to: output b as the second input B of the summer when the arithmetic logic unit is to implement a + b; output ~a as the second input B of the summer when the arithmetic logic unit is to implement an absolute value of a operation; output ~b as the second input B of the summer when the arithmetic logic unit is to implement any one of a - b, max(a, b), min(a, b).

7. The arithmetic logic unit of claim 6, wherein the second input selection module is implemented by a three-control-selector ao222 comprising three inputs that receive b, ~b, and ~a, respectively.

8. The arithmetic logic unit of claim 1, wherein the carry input selection module is configured to: when the arithmetic logic unit is to implement any one of a subtract b from a, an absolute value of a, a maximum of a and b, a minimum of a and b, output 1 as the carry-in input Ci to the adder.

9. The arithmetic logic unit of claim 8, wherein the carry-in input selection module is implemented by an OR gate having a plurality of inputs that each receive at least a portion of the flags indicative of the operation to be implemented by the arithmetic logic unit.

10. The arithmetic logic unit of claim 1, wherein another at least one of the at least three inputs to the output selection module receives a, and another at least one receives b.

11. The arithmetic logic unit of claim 10, wherein the output selection module is configured to: when the arithmetic logic unit is to implement any one of a add b from a, a subtract b from a, output the sum S as the output of the arithmetic logic unit; when the arithmetic logic unit is to implement an absolute value of a, select either the sum S or a as the output of the arithmetic logic unit based on the sign bit of a; when the arithmetic logic unit is to implement any one of a maximum of a and b, a minimum of a and b, select either a or b as the output of the arithmetic logic unit based on the sign bit of the sum S.

12. The arithmetic logic unit of claim 11, wherein the output selection module is configured to, when the arithmetic logic unit is to implement an absolute value of a, select a as the output of the arithmetic logic unit in response to the sign bit of a being 0, and select the sum S as the output of the arithmetic logic unit in response to the sign bit of a being 1.

13. The arithmetic logic unit of claim 11, wherein the output selection module is configured to: when the arithmetic logic unit is to implement a maximum of a and b, select a as the output of the arithmetic logic unit in response to the sign bit of the sum S being 0, and select b as the output of the arithmetic logic unit in response to the sign bit of the sum S being 1; when the arithmetic logic unit is to implement a minimum of a and b, select b as the output of the arithmetic logic unit in response to the sign bit of the sum S being 0, and select a as the output of the arithmetic logic unit in response to the sign bit of the sum S being 1.

14. The arithmetic logic unit of claim 10, wherein the output selection module includes an equality determination module for determining whether a and b are equal.

15. The arithmetic logic unit of claim 14, wherein: the first input selection module is configured to output a as the first input A to the adder when the arithmetic logic unit is to implement a compare result of a and b; the second input selection module is configured to output ~b as the second input B to the adder when the arithmetic logic unit is to implement a compare result of a and b; the carry-in input selection module is configured to output 1 as the carry-in input Ci to the adder when the arithmetic logic unit is to implement a compare result of a and b; and ​ The output selection module is configured to output, as an output of the arithmetic logic unit, one of a flag indicating that a is equal to b, a flag indicating that a is greater than b, and a flag indicating that a is less than b, based on the output of the equality determination module and the sign bit of the sum S, when the arithmetic logic unit is to implement a compare result operation on a and b.

16. The arithmetic logic unit of claim 15, wherein the output selection module is configured to, when the arithmetic logic unit is to implement a compare result operation on a and b: output, as an output of the arithmetic logic unit, the flag indicating that a is equal to b in response to the equality determination module outputting the flag indicating that a and b are equal; output, as an output of the arithmetic logic unit, the flag indicating that a is less than b in response to the sign bit of the sum S being 1; and output, as an output of the arithmetic logic unit, the flag indicating that a is greater than b in response to the sign bit of the sum S being 0 and the equality determination module outputting the flag indicating that a and b are not equal.

17. The arithmetic logic unit of claim 14, wherein the equality determination module is implemented by a combination of N XNOR gates and one or more AND gates, where N is the number of bits of the binary numbers a and b.

18. A processor comprising one or more arithmetic logic units as claimed in any of claims 1-17.

19. A computing chip comprising one or more processors as claimed in claim 18.

20. A computing device comprising one or more computing chips as claimed in claim 19.

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