Power amplification chip, power amplification system, and electronic device

Abstract

The present application discloses a power amplification chip, a power amplification system, and an electronic device. The power amplification chip comprises a housing, a wafer body, and a connection layer. The wafer body comprises at least two bare dies adjacently connected, and a scribe line is provided between every two adjacent bare dies. At least one of the housing and the connection layer is provided with a mounting cavity, and the bare dies are embedded in the mounting cavity. The connection layer and the housing are stacked, and the connection layer is connected to the housing. The surface of each bare die facing the connection layer is provided with a power amplification circuit, and the side of the connection layer facing away from a first end surface of the housing is provided with pads. The power amplification circuit comprised in each bare die is electrically connected to corresponding pins of the pads by means of the connection layer.

Description

Power amplification chip, power amplification system and electronic device

[0001] Cross-reference to related applications

[0002] The present application claims priority from Chinese Patent Application No. 202410975834.8 filed on July 19, 2024 in China, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of electronic products, in particular to a power amplification chip, a power amplification system and an electronic device. BACKGROUND

[0004] In related technologies, with the entry of consumer electronic products such as mobile phones and tablets into people's lives, people's lives have been greatly facilitated. At present, with the increasing demand for scenarios such as audio and video entertainment, the sound of mobile phones and tablets has gradually increased from a single loudspeaker to stereo sound, and even more channels.

[0005] For current mobile phones and other intelligent terminals, an audio power amplifier (PA) is generally used to drive a loudspeaker and other passive devices. Therefore, in order to experience a dual-loudspeaker, multi-loudspeaker, and other audio systems on a mobile phone and other intelligent terminals, more PAs are needed to achieve this. With the increase of each loudspeaker, a PA is needed to drive it, and the PA and its peripheral circuit occupy a large amount of board area. In the trend of increasingly tight internal space in mobile phones, the promotion of multi-channel systems in consumer intelligent terminals is limited. Therefore, in related technologies, when the number of PAs to be set in an electronic device is large, it is easy to cause the problem of excessive board area occupied by the PA. SUMMARY

[0006] The present application provides a power amplification chip, a power amplification system and an electronic device, which can reduce the board area occupied by at least two power amplifiers.

[0007] In a first aspect, an embodiment of the present application provides a power amplification chip, comprising: a shell, a wafer body and a connecting layer, the wafer body comprising at least two adjacent connected bare chips, and having a dicing groove between the two adjacent bare chips, at least one of the shell and the connecting layer being provided with a mounting cavity, and the bare chip being embedded in the mounting cavity;

[0008] The connecting layer and the shell are stacked and connected, the surface of the bare chip on the side facing the connecting layer is provided with a power amplification circuit, and the side of the connecting layer opposite to the first end face of the shell is provided with a solder pad;

[0009] Each of the bare chips includes a power amplification circuit, and the power amplification circuit is electrically connected to a corresponding pin in the pad through the connection layer.

[0010] In a second aspect, the embodiments of the present application provide a power amplification system, including a processor, at least two speakers, and the power amplification chip in the first aspect, the pad includes: at least two input pins corresponding to the at least two adjacently connected bare chips one by one, and at least two output pins corresponding to the at least two adjacently connected bare chips one by one; the processor is electrically connected to the at least two input pins, the at least two speakers correspond to the at least two output pins one by one, and the output pins are electrically connected to the corresponding speakers.

[0011] In a third aspect, the embodiments of the present application provide an electronic device including the power amplification system in the second aspect.

[0012] In the embodiments of the present application, at least two bare chips are arranged in the power amplification chip, and each of the bare chips has a power amplification circuit. Thus, the at least two bare chips are packaged into one power amplification chip through the connection layer and the pad, and each of the bare chips can form a power amplifier together with the connection layer and the pad. Thus, the power amplification chip has at least two power amplifiers. Compared with arranging at least two separate power amplifiers, the power amplification chip provided in the embodiments of the present application can replace the at least two separate power amplifiers, thereby reducing the board area occupied by the at least two power amplifiers, and relieving the problem that the board area occupied by the power amplifiers is too large when the number of power amplifiers to be arranged in the electronic device is large. In addition, the at least two power amplifiers are combined into one power amplification chip, thereby reducing the packaging cost of the power amplifiers and reducing the peripheral circuit devices. At the same time, since the existing bare chips are reused, it is not necessary to redesign the bare chips with different circuits, thereby reducing the development time cost and risk. In addition, since the at least two adjacently connected bare chips retain the scribe groove without cutting, the at least two bare chips are cut, packaged, tested, and the like together in the process of cutting the wafer to obtain the wafer body, thereby reducing the number of cutting knives, reducing the number of suction and placement times of the bare chips in the packaging process, and reducing the packaging cost and packaging time. BRIEF DESCRIPTION OF DRAWINGS

[0013] FIG. 1 is a structural exploded view of a power amplification chip provided in the embodiments of the present application;

[0014] FIG. 2 is another structural exploded view of the power amplification chip provided in the embodiments of the present application;

[0015] FIG. 3 is a structural schematic view of the power amplification chip provided in the embodiments of the present application;

[0016] Fig. 4 is a structural schematic diagram of a power amplification chip according to an embodiment of the present application;

[0017] Fig. 5 is a structural schematic diagram of a wafer according to an embodiment of the present application;

[0018] Fig. 6 is a structural exploded view of a power amplification chip according to an embodiment of the present application;

[0019] Fig. 7 is a structural exploded view of a power amplification chip according to an embodiment of the present application;

[0020] Fig. 8 is a circuit structural schematic diagram of a power amplification chip according to an embodiment of the present application;

[0021] Fig. 9 is a circuit structural schematic diagram of a power amplification system according to an embodiment of the present application;

[0022] Fig. 10 is a circuit structural schematic diagram of a power amplification chip according to an embodiment of the present application;

[0023] Fig. 11 is a circuit structural schematic diagram of a power amplification system according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described clearly below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0025] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of a kind and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", generally represents a "or" relationship between the front and rear associated objects.

[0026] A power amplification chip, a power amplification system and an electronic device according to an embodiment of the present application will be described in detail below with reference to the drawings and specific embodiments and their application scenarios.

[0027] Referring to FIGS. 1-11, a power amplifier chip provided by an embodiment of the present application includes a shell 100, a wafer body 200, and a connecting layer 300. The wafer body 200 includes at least two adjacent and connected bare chips 210, and a scribe groove 220 is arranged between the two adjacent bare chips 210. At least one of the shell 100 and the connecting layer 300 is provided with a mounting cavity 110, and the bare chip 210 is embedded in the mounting cavity 110.

[0028] The connecting layer 300 and the shell 100 are arranged in a stacked manner, and the connecting layer 300 is connected to the shell 100. The surface of the bare chip 210 on the side facing the connecting layer 300 is provided with a power amplifier circuit, and the side of the connecting layer 300 opposite to the first end face of the shell 100 is provided with a solder pad 330.

[0029] The power amplifier circuit of each bare chip 210 is electrically connected to the corresponding pin in the solder pad 330 through the connecting layer 300.

[0030] In the above, the wafer body 200 including at least two adjacent and connected bare chips 210 can specifically mean that the wafer body 200 includes at least two sequentially connected bare chips 210. More specifically, the wafer body 200 includes at least two arranged bare chips 210, and the two adjacent bare chips 210 are fixedly connected.

[0031] In some embodiments of the present application, the mounting cavity 110 can be arranged only on the side of the shell 100 facing the connecting layer 300, and the at least two bare chips 210 are embedded in the mounting cavity 110 of the shell 100. The number of mounting cavities on the surface of the shell 100 can be one or at least two. When the number of mounting cavities is one, the shape and size of the cross section of the mounting cavity can be the same as the shape and size of the cross section of the wafer body 200, so that the at least two bare chips 210 can be embedded in the same mounting cavity. Accordingly, when the number of mounting cavities on the surface of the shell 100 is at least two, at least one bare chip 210 can be embedded in each mounting cavity.

[0032] In another embodiment of the present application, the mounting cavity can also be arranged only in the connecting layer 300, and the at least two bare chips 210 are embedded in the mounting cavity of the connecting layer 300. In this case, the mounting cavity can be arranged on the surface of the connecting layer 300 facing the shell, or the mounting cavity can also be a closed cavity arranged in the connecting layer 300.

[0033] In some other embodiments of the present application, the connecting layer 300 can be provided with a mounting cavity on the side thereof facing the housing 100, and the housing 100 can be provided with a mounting cavity on the side thereof facing the connecting layer 300. The mounting cavity in the connecting layer 300 and the mounting cavity in the housing 100 can be oppositely arranged to jointly enclose the mounting space of the at least two bare chips 210.

[0034] It can be understood that each bare chip can jointly form a power amplifier with the connecting layer and the pad, and the power amplifier can be an audio power amplifier. The audio power amplifier is obtained by processing various power amplifier circuits on a silicon wafer by using developing, photolithography and other means. After photolithography, the wafer becomes a wafer body 200. Specifically, please refer to FIG. 5. Since the wafer has a large number of bare chips 210 arranged and connected in sequence, the connection relationship between two or more bare chips 210 can be maintained during the wafer cutting, and the wafer is cut to obtain two or more bare chip 210 assemblies connected in sequence. In the embodiments of the present application, the two or more bare chip 210 assemblies connected in sequence are referred to as a wafer body 200. That is, during the wafer cutting, the scribe groove 220 in the wafer body 200 is not cut.

[0035] The scribe groove 220 refers to a spacing structure on a wafer for separating adjacent bare chips 210. These spacing structures are usually referred to as dicing channels, sometimes also referred to as scribe grooves 220 or saw channels, which are located between different bare chips 210 and generally have a width of 80 μm to 150 μm, so as to facilitate the separation of each bare chip 210 having independent electrical performance from the wafer.

[0036] The power amplifier circuit is a power amplifier circuit processed on the bare chip 210 by using developing, photolithography and other means. It can be understood that the power amplifier circuit can be various audio power amplifier circuits in related technologies. Different bare chips 210 in the at least two bare chips 210 can include the same or different power amplifier circuits.

[0037] The housing 100 can specifically be used to provide support, heat dissipation and protection for the bare chip 210. The housing 100 can be made of plastic, glass or other materials. When the housing 100 is made of plastic, the housing 100 can be plastic encapsulation formed.

[0038] The connection layer 300 can include a trace layer 310, which can be a redistribution layer (RDL) or a circuit board structure with traces. The RDL, which is composed of metal layers and polyimide (PI) layers, is responsible for redistributing the pins on the die (DIE) to the pads 330, achieving electrical connection between the pins on the DIE and the pads 330 on the shell of the power amplifier chip. The RDL can include one layer of traces, or two or more layers of traces, each layer of traces can include a metal layer and a PI layer. The PI layer can separate different metal layers.

[0039] The pads 330 can include pins for connecting various electronic devices such as the at least two dies 210, a speaker, a processor 700, etc. For example, in some embodiments of the present application, the pads 330 can include at least two input pins corresponding to the at least two dies 210, and at least two output pins corresponding to the at least two dies 210, each die 210 can be electrically connected to the corresponding input pin and output pin to form a power amplifier. Since one die 210 can form a power amplifier, the power amplifier chip can include at least two power amplifiers corresponding to the at least two dies 210. In addition, the input pins can also be used to connect the processor 700 to receive the signal to be amplified transmitted by the processor 700, and the output pins can also be used to connect the speaker to transmit the amplified signal to the speaker for output.

[0040] In this embodiment, by arranging at least two bare chips 210 in the power amplification chip, and each bare chip 210 has a power amplification circuit, thus, by connecting the at least two bare chips 210 to the same power amplification chip through the connecting layer 300 and the bonding pad 330, and each bare chip 210 can jointly form a power amplifier with the connecting layer 300 and the bonding pad 330, thus, at least two power amplifiers can be arranged in one power amplification chip, compared with arranging at least two separate power amplifiers, using the power amplification chip provided in the embodiment of the present application to replace at least two separate power amplifiers, which is beneficial to reduce the board area occupied by at least two power amplifiers, so as to alleviate the problem that when the number of power amplifiers required to be arranged in the electronic device is large, the board area occupied by the power amplifiers is too large. In addition, by combining at least two power amplifiers into one power amplification chip, the packaging cost of the power amplifier can be reduced, and the peripheral circuit device can be reduced. At the same time, since the existing bare chip 210 is reused, there is no need to redesign the bare chip with different circuits, which is beneficial to reduce the development time cost and risk. In addition, since the at least two connected bare chips 210 retain the scribe groove 220 without cutting, that is, the at least two bare chips 210 are connected together for cutting, packaging, testing and other operations in the process of cutting the wafer to obtain the wafer body 200, which is beneficial to reduce the number of cutting knives, and also beneficial to reduce the number of suction and placement times of the bare chip 210 in the packaging process, thereby reducing the packaging cost and packaging time.

[0041] Optionally, the shell 100 is provided with at least two mounting cavities 110 on one side of the connecting layer 300, and each two adjacent mounting cavities 110 has a partition 120, the at least two mounting cavities 110 correspond to the at least two adjacent connected bare chips 210 one by one, the bare chip 210 is embedded in the corresponding mounting cavity 110, and the scribe groove 220 is opposite to the partition 120 between the two adjacent mounting cavities 110.

[0042] Please refer to FIG. 1, the above-mentioned partition 120 is a partition strip for separating the two adjacent mounting cavities 110, and the two opposite side walls of the partition 120 can form the groove walls of the corresponding mounting cavities 110, respectively. It can be understood that the number of scribe grooves 220 included in the wafer body 200 is the same as the number of partitions 120 included in the shell 100, and each scribe groove 220 of the wafer body 200 corresponds to a partition 120 in the shell 100, and the scribe groove 220 is arranged at the corresponding partition 120 to realize the connection between the wafer body 200 and the shell 100.

[0043] In the embodiment, at least two mounting cavities 110 are arranged on the side of the shell 100 facing the connecting layer 300. In this way, since the mounting cavities 110 do not need to be arranged in the connecting layer 300, the thickness space of the connecting layer 300 can be avoided, thereby facilitating the reduction of the thickness of the connecting layer 300, and further facilitating the reduction of the overall thickness of the power amplification chip.

[0044] Optionally, referring to FIGS. 6 and 7, the wafer body 200 further comprises a connecting body 230, two adjacent bare chips 210 are connected by a connecting body 230, and the connecting body 230 and the two adjacent bare chips 210 form the scribing groove 220. At least one wire 240 is arranged on the surface of the connecting body 230, and the power amplification circuits included in the two adjacent bare chips 210 are electrically connected by the at least one wire 240 on the surface of the corresponding connecting body 230.

[0045] The connecting body 230 is a connecting body 230 in the wafer for connecting adjacent bare chips 210. In the process of cutting the wafer, the corresponding connecting body 230 is cut along the scribing groove 220.

[0046] In the embodiment, since there may be some necessary electrical connections between different bare chips 210 in the power amplification chip, if the electrical connections between the bare chips 210 are realized by the connecting layer 300, the number of wire layers 310 included in the connecting layer 300 may increase, thereby increasing the thickness of the connecting layer 300 and the overall thickness of the power amplification chip. Based on this, in the embodiment of the application, at least one wire 240 is arranged on the surface of the connecting body 230 to realize the electrical connection between the two adjacent bare chips 210 by the at least one wire 240, thereby avoiding the need to arrange the wire layer 310 for realizing the electrical connection between the bare chips 210 in the connecting layer 300, facilitating the reduction of the thickness of the connecting layer 300, and further facilitating the reduction of the overall thickness of the power amplification chip.

[0047] Optionally, the power amplification circuit comprises a system control module 515, a clock module, and a power supply module. The system control modules 515 in two adjacent power amplification circuits are electrically connected by the wires 240 on the surface of the corresponding connecting body 230, the clock modules in two adjacent power amplification circuits are electrically connected by the wires 240 on the surface of the corresponding connecting body 230, and the power supply modules in two adjacent power amplification circuits are electrically connected by the wires 240 on the surface of the corresponding connecting body 230.

[0048] The at least two bare chips 210 are connected in sequence, specifically, the at least two bare chips 210 are connected in sequence through the connecting body 230. The surface of each connecting body 230 can be provided with at least three wires, which can include a control wire, a clock wire and a power supply wire, wherein the control wire is connected to the system control module 515 in the corresponding two bare chips 210. The clock wire is connected to the clock module in the corresponding two bare chips 210. The power supply wire is connected to the power supply module in the corresponding two bare chips 210. In this way, since the system control modules 515 in each bare chip 210 are connected in series through the control wire, only one set of control pins corresponding to all the system control modules 515 needs to be provided in the pad 330, and the control pins are electrically connected to any one system control module 515 through the connecting layer 300, so that the electrical connection between the control pins and all the system control modules 515 is established. Correspondingly, only one set of peripheral control lines is needed to uniformly control all the system control modules 515 in the power amplifier chip. Compared with the related art, in which each power amplifier needs to be provided with one set of control pins, and each set of control pins needs to be provided with one set of control lines, the power amplifier chip in the embodiment of the present application is beneficial to reducing the number of peripheral devices such as control lines. For example, referring to FIG. 8, in the embodiment of the present application, the power amplifier chip includes two bare chips 210, which are a first bare chip 510 and a second bare chip 520. The system control module 515 can be controlled by differential signals, so the system control module 515 can include two input terminals. The first input terminal of the system control module 515 included in the first bare chip 510 is electrically connected to the first input terminal of the system control module 515 included in the second bare chip 520 through a control wire, i.e., a first wire 540. The second input terminal of the system control module 515 included in the first bare chip 510 is electrically connected to the second input terminal of the system control module 515 included in the second bare chip 520 through a second wire 550. The pad 330 includes a first control pin (CTRL1) and a second control pin (CTRL2). The CTRL1 is electrically connected to the first wire 540, and the CTRL2 is electrically connected to the second wire 550. The first wire 540 and the second wire 550 are two different control wires provided on the surface of the connecting body 230.

[0049] In this embodiment, the clock module, the system control module 515 and the power supply module are connected together based on at least one wire 240 on the surface of the connecting body 230 to form one chip, which works simultaneously. However, the input and output of each bare chip 210 work separately and are led out to the external pad 330. This can realize multiplexing of the existing bare chip 210 to form at least two power amplifiers, which is beneficial to saving packaging and peripheral device costs.

[0050] Optionally, the at least two adjacent connected bare chips 210 are arranged along the length direction of the shell 100, and the length direction of the bare chips 210 is perpendicular to the length direction of the shell 100; or,

[0051] The at least two bare chips 210 are arranged along the length direction of the shell 100, and the length direction of the bare chips 210 is the same as the length direction of the shell 100.

[0052] In some embodiments of the present application, the power amplification chip includes two bare chips 210, the two bare chips 210 are arranged along the length direction of the shell 100, and the length direction of the bare chips 210 is perpendicular to the length direction of the shell 100.

[0053] In some embodiments of the present application, the power amplification chip includes two bare chips 210, and the length direction of the bare chips 210 is the same as the length direction of the shell 100, the bare chips 210 in the embodiment are arranged vertically, which is beneficial to save the required occupied horizontal space, and can be applied to the scene where the horizontal space of the electronic device is insufficient.

[0054] In some embodiments of the present application, the power amplification chip includes three bare chips 210, the three bare chips 210 are arranged along the length direction of the shell 100, and the length direction of the bare chips 210 is the same as the width direction of the shell 100. It can be understood that in another embodiment of the present application, the power amplification chip can also be provided with three bare chips 210, the three bare chips 210 are arranged along the length direction of the shell 100, and the length direction of the bare chips 210 is the same as the length direction of the shell 100.

[0055] In some embodiments of the present application, the power amplification chip includes four bare chips 210, the four bare chips 210 are arranged along the length direction of the shell 100, and the length direction of the bare chips 210 is the same as the width direction of the shell 100. It can be understood that in another embodiment of the present application, the power amplification chip can also be provided with four bare chips 210, the four bare chips 210 are arranged along the length direction of the shell 100, and the length direction of the bare chips 210 is the same as the length direction of the shell 100.

[0056] It can be understood that the number of bare chips 210 in the embodiment of the present application is not limited to four, and can be more than four, and the arrangement mode of each bare chip 210 is not limited to the arrangement mode listed in the above embodiment, and can be other arrangement modes.

[0057] Optionally, the number of the at least two bare chips 210 is four, and the four bare chips 210 are arranged in a rectangular array.

[0058] In some embodiments of the present application, the number of the bare chips 210 included in the power amplification chip is four, and the four bare chips 210 are arranged in a rectangular array.

[0059] In this embodiment, by improving the number and arrangement of the bare chips 210 included in the power amplification chip, the power amplification chip provided by the present application can be applied to various electronic devices.

[0060] Optionally, the pad 330 includes at least two input pins corresponding to the at least two bare chips 210 one by one, and at least two output pins corresponding to the at least two bare chips 210 one by one.

[0061] The power amplification circuit includes an input buffer module 511, a power amplification module 512 and an electromagnetic interference suppression module 513 connected in sequence, the input end of the input buffer module 511 is connected to the corresponding input pin electrical connection, and the output end of the electromagnetic interference suppression module 513 is connected to the corresponding output pin electrical connection.

[0062] Wherein, please refer to FIG. 8, the input buffer module 511 (INPUT BUFFER) is used for receiving input signals and providing buffering.

[0063] The above-mentioned power amplification module 512 can include various amplification circuits for amplifying power in related technologies, for example, the power amplification module 512 can be Class D or Class AB, wherein the power amplification module 512 is used for amplifying the sine wave signal of the input buffer and giving to the subsequent circuit. In the embodiment shown in FIG. 8, the power amplification module 512 is Class D.

[0064] The above-mentioned electromagnetic interference suppression module 513 (EMI Eliminate) can be an EMI suppression circuit, which is used for improving the anti-interference performance of the amplifier.

[0065] In this embodiment, by making the power amplification circuit include the input buffer module 511, the power amplification module 512 and the electromagnetic interference suppression module 513, thus, it is conducive to realizing power amplification of the received audio signal based on the power amplification circuit.

[0066] Optionally, the power amplification circuit further comprises a charge pump voltage boosting module 514, a system control module 515, an address configuration module 516 and a reset module 517, a first output end of the charge pump voltage boosting module 514 is electrically connected with the power amplification module 512, a second output end of the charge pump voltage boosting module 514 is electrically connected with the electromagnetic interference suppression module 513, an output end of the address configuration module 516, an output end of the reset module 517, a control end of the input buffer module 511 and a control end of the power amplification module 512 are electrically connected with the system control module 515.

[0067] The charge pump voltage boosting module 514 can be used to provide a high enough voltage for the power amplification module 512, and to raise the voltage of the power supply terminal (VBAT) of the bare chip 210 to two or more times, as shown in FIG. 8. The charge pump voltage boosting module 514 can be a charge pump, a Boost or other means. In the embodiment of the application, the charge pump voltage boosting module 514 is a charge pump.

[0068] In this embodiment, the power amplification circuit comprises the input buffer module 511, the power amplification module 512, the electromagnetic interference suppression module 513 and the charge pump voltage boosting module 514, which is conducive to power amplification of the received audio signal based on the power amplification circuit.

[0069] Optionally, the power amplification circuit further comprises a system control module 515, an address configuration module 516 and a reset module 517, an output end of the address configuration module 516, an output end of the reset module 517, a control end of the input buffer module 511 and a control end of the power amplification module 512 are electrically connected with the system control module 515.

[0070] The system control module 515 (SYSCTRL) can be used to control the hardware state or the register state of the power amplification module 512. The SYSCTRL can be IIC or other GPIO control mode, and the working state or mode of the PA is controlled by the high and low levels.

[0071] The address configuration module 516 (Address) is mainly used to configure the address of I2C. The power amplification circuits in all bare chips 210 can share an I2C address, and the power amplification circuits in different bare chips 210 correspond to different register addresses.

[0072] The reset module 517 (RESET) can reset the power amplification circuits in all bare chips 210 at the same time.

[0073] Please refer to Figure 9, when the power amplifier chip in the embodiment of the application is applied to the power amplifier system shown in Figure 9, the working principle of the power amplifier system is as follows:

[0074] The processor 700 controls the PA reset pin RSTN to be pulled from high to low by the GPIO, and simultaneously resets the two power amplifier circuits.

[0075] The processor 700 controls the working states of the two power amplifier circuits respectively through different register configurations according to the configured I2C address of the PA.

[0076] The two audio signals are input into the PA through the first input end INP1 / INN1 and the second input end INP2 / INN2 respectively, the first one enters the NPUT BUFFER1, and the second one enters the INPUT BUFFER2.

[0077] The signals are output through the output ports VOP1 / VON1 and VOP2 / VON2 after being amplified by Class D1 and Class D2 and passing through the EMI Eliminate1 and EMI Eliminate2 circuits, to drive the first loudspeaker 610 and the second loudspeaker 620.

[0078] In this embodiment, by causing the power amplifier circuit to include the input buffer module 511, the power amplifier module 512, the electromagnetic interference suppression module 513, the charge pump voltage boosting module 514, the system control module 515, the address configuration module 516 and the reset module 517, it is beneficial to realize power amplification of the received audio signal based on the power amplifier circuit.

[0079] Optionally, the connecting layer 300 includes a wiring layer 310 and a substrate 320, the shell 100, the wiring layer 310 and the substrate 320 are sequentially stacked, and the pad 330 is located on the surface of the side of the substrate 320 away from the wiring layer 310, and the power amplifier circuit is electrically connected to the corresponding pin through the wiring layer 310.

[0080] In some embodiments of the application, a substrate 320 can be arranged in the power amplifier chip, wherein the substrate 320 is responsible for carrying all modules, and the substrate 320 has a metal pad 330 at the bottom, which is used to realize the welding connection with the printed circuit board (PCB) when the power amplifier chip is applied, wherein the pad 330 can be various pads 330, for example, the pad 330 can be a ball grid array package (BGA), or the pad 330 can also be a quad flat no-leads package (QFN) and the like.

[0081] In this embodiment, by making the connecting layer 300 include the substrate 320, since the substrate 320 can realize support for each module in the power amplification chip, the stability of the power amplification chip structure can be improved.

[0082] Optionally, the connecting layer 300 is a wiring layer 310, and the pads 330 are arranged on the surface of the side of the wiring layer 310 away from the first end surface of the shell 100.

[0083] In the above embodiment, the substrate 320 is not necessarily arranged, for example, in another embodiment of the present application, the power amplification chip can not include the above-mentioned substrate 320, in this case, the pads 330 can be directly generated on the surface of the side of the wiring layer 310 away from the shell 100. Wherein, the pads 330 can be various pads 330, for example, the pads 330 can be a ball grid array package (Ball Grid Array, BGA), or the pads 330 can also be a square flat no-leads package (Quad Flat No-leads Package, QFN) and the like. In this way, it is beneficial to further reduce the thickness of the power amplification chip to be suitable for the scene where the thickness installation space is insufficient.

[0084] In this embodiment, by further improving the structure of the pads 330, the overall thickness of the power amplification chip can be reduced.

[0085] Referring to FIGS. 8-9, in the embodiment of the present application, the power amplification chip includes two bare chips 210, which are referred to as a first bare chip 510 and a second bare chip 520, respectively. The pads 330 include INP1 / INN1 pins, CTRL1 / CTRL 2 pins, INP2 / INN2 pins, AD pins, GND pins, CP2 / CN2 pins, OUTP2 / OUTN2 pins, PVDD2 pins, OUTP1 / OUTN1 pins, PVDD1 pins, CP1 / CN1 pins, and VDD pins. The INP1 / INN1 pins are respectively connected to two input ends of an NPUT BUFFER of the first bare chip 510. The CTRL1 / CTRL 2 pins are respectively electrically connected to any one of the first traces 540 and the second traces 550. The INP2 / INN2 pins are respectively connected to two input ends of an NPUT BUFFER of the second bare chip 520. The AD pins are electrically connected to traces for connecting address configuration modules 516. The GND pins are electrically connected to traces for connecting grounding points. The CP2 / CN2 pins are respectively electrically connected to two input ends of a ChargePump in the second bare chip 520. The OUTP2 / OUTN2 pins are respectively electrically connected to two output ends of an EMI Eliminate in the second bare chip 520. The PVDD2 pins are electrically connected to a third output end of the ChargePump in the second bare chip 520. The OUTP1 / OUTN1 pins are respectively electrically connected to two output ends of an EMI Eliminate in the first bare chip 510. The PVDD1 pins are electrically connected to a third output end of the ChargePump in the first bare chip 510. The CP1 / CN1 pins are respectively electrically connected to two input ends of a ChargePump in the first bare chip 510. The VDD pins are electrically connected to traces for connecting power supply modules in the bare chips 210.

[0086] Referring to FIGS. 10-11, in the embodiment of the present application, the power amplification chip includes three bare chips 210, which are referred to as a first bare chip 510, a second bare chip 520, and a third bare chip 530. The pads 330 include INP1 / INN1 pins, CTRL1 / CTRL 2 pins, INP2 / INN2 pins, INP3 / INN3 pins, AD pins, GND pins, CP2 / CN2 pins, CP3 / CN3 pins, OUTP3 / OUTN3 pins, PVDD3 pins, OUTP2 / OUTN2 pins, PVDD2 pins, OUTP1 / OUTN1 pins, PVDD1 pins, CP1 / CN1 pins, and VDD pins. The INP1 / INN1 pins are respectively connected to two input ends of an NPUT BUFFER of the first bare chip 510. The CTRL1 / CTRL 2 pins are respectively electrically connected to the first trace 540 and the second trace 550. The INP2 / INN2 pins are respectively connected to two input ends of an NPUT BUFFER of the second bare chip 520. The INP3 / INN3 pins are respectively connected to two input ends of an NPUT BUFFER of the third bare chip 530. The AD pins are electrically connected to traces for connecting address configuration modules 516. The GND pins are electrically connected to traces for connecting grounding points. The CP2 / CN2 pins are respectively electrically connected to two input ends of a ChargePump in the second bare chip 520. The CP3 / CN3 pins are respectively electrically connected to two input ends of a ChargePump in the third bare chip 530. The OUTP3 / OUTN3 pins are respectively electrically connected to two output ends of an EMI Eliminate in the third bare chip 530. The PVDD3 pins are electrically connected to a third output end of a ChargePump in the third bare chip 530. The OUTP2 / OUTN2 pins are respectively electrically connected to two output ends of an EMI Eliminate in the second bare chip 520. The PVDD2 pins are electrically connected to a third output end of a ChargePump in the second bare chip 520. The OUTP1 / OUTN1 pins are respectively electrically connected to two output ends of an EMI Eliminate in the first bare chip 510. The PVDD1 pins are electrically connected to a third output end of a ChargePump in the first bare chip 510. The CP1 / CN1 pins are respectively electrically connected to two input ends of a ChargePump in the first bare chip 510. The VDD pins are electrically connected to traces for connecting power supply modules in the bare chips 210.

[0087] The embodiment of the present application also provides a power amplification system, which comprises a processor 700, at least two loudspeakers and the power amplification chip, the pads 330 comprise at least two input pins corresponding to the at least two bare chips 210 one by one, and at least two output pins corresponding to the at least two bare chips 210 one by one; the processor 700 is electrically connected with the at least two input pins, the at least two loudspeakers correspond to the at least two output pins one by one, and the output pins are electrically connected with the corresponding loudspeakers.

[0088] Please refer to Fig. 9, which is a structural schematic diagram of a power amplification system comprising the power amplification chip in the embodiment shown in Fig. 8, wherein the power amplification system comprises a processor 700, a first loudspeaker 610, a second loudspeaker 620 and the power amplification chip shown in Fig. 8, wherein the processor 700 is electrically connected with the INP1 / INN1 pin, the CTRL1 / CTRL2 pin, the INP2 / INN2 pin and the reset pin of the power amplification chip through wires respectively, the AD pin and the GND pin are grounded respectively, the CP2 pin and the CN2 pin are electrically connected through a capacitor, and the PVDD2 pin is grounded through a capacitor. The OUTP2 / OUTN2 pin is connected with two input ends of the second loudspeaker 620 correspondingly. The OUTP1 / OUTN1 pin is connected with two input ends of the first loudspeaker 610 correspondingly. The PVDD1 pin is grounded through a capacitor. The CP1 pin and the CN1 pin are electrically connected through a capacitor, and the VDD pin is electrically connected with VBAT, wherein VBAT is a power supply terminal in an electronic device, and the VBAT comprises a decoupling capacitor 560. In the related art, when each power amplifier is arranged separately, a group of independent decoupling capacitors 560 need to be arranged for each power amplifier, and in the embodiment of the present application, a decoupling circuit needs to be arranged for each power amplification chip, that is, only a group of decoupling capacitors 560 need to be arranged for at least two power amplifiers, so that the material cost and the board area are reduced.

[0089] Correspondingly, referring to FIG. 11, for the power amplification system including the power amplification chip in the embodiment shown in FIG. 10, a structure schematic diagram of the power amplification system is provided, wherein the power amplification system includes a processor 700, a first speaker 610, a second speaker 620, a third speaker 630, and the power amplification chip shown in FIG. 10. The processor 700 is electrically connected to the INP1 / INN1 pin, the CTRL1 / CTRL2 pin, the INP2 / INN2 pin, the INP3 / INN3 pin, and the reset pin of the power amplification chip through wires respectively. The AD pin and the GND pin are grounded respectively. The CP2 pin and the CN2 pin are electrically connected through a capacitor. The CP3 pin and the CN3 pin are electrically connected through a capacitor. The PVDD2 pin is grounded through a capacitor. The PVDD3 pin is grounded through a capacitor. The OUTP3 / OUTN3 pin is correspondingly connected to two input ends of the third speaker 630. The OUTP2 / OUTN2 pin is correspondingly connected to two input ends of the second speaker 620. The OUTP1 / OUTN1 pin is correspondingly connected to two input ends of the first speaker 610. The PVDD1 pin is grounded through a capacitor. The CP1 pin and the CN1 pin are electrically connected through a capacitor. The VDD pin is electrically connected to the VBAT. The VBAT is a power supply terminal in an electronic device, and includes a decoupling capacitor 560. In the related art, when each power amplifier is separately arranged, a set of independent decoupling capacitors 560 needs to be arranged for each power amplifier. In the embodiment, a decoupling circuit needs to be arranged for one power amplification chip, that is, only one set of decoupling capacitors 560 needs to be arranged for at least two power amplifiers. In this way, the material cost and the board area are reduced.

[0090] In the embodiment, since the power amplification system includes the power amplification chip in the above embodiment, the power amplification system can implement the processes of the power amplification chip, and has the same beneficial effects. To avoid repetition, details are not described herein again.

[0091] The embodiment also provides an electronic device including the power amplification system in the above embodiment.

[0092] In the embodiment, since the electronic device includes the power amplification system in the above embodiment, the electronic device can implement the processes of the power amplification system, and has the same beneficial effects. To avoid repetition, details are not described herein again.

[0093] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the specific embodiments described above, and the specific embodiments described above are merely illustrative, but not restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims.

Claims

1. A power amplification chip, comprising: A shell, a wafer body and a connecting layer, the wafer body comprising at least two adjacent connected bare chips, and a scribe groove between the two adjacent bare chips, at least one of the shell and the connecting layer being provided with a mounting cavity, and the bare chip being embedded in the mounting cavity; The connecting layer is stacked with the shell, and the connecting layer is connected with the shell, the surface of the bare chip on the side facing the connecting layer is provided with a power amplifier circuit, and the side of the connecting layer opposite to the first end face of the shell is provided with a solder pad; The power amplifier circuit of each bare chip is electrically connected with the corresponding pin of the solder pad through the connecting layer.

2. The power amplifier chip of claim 1, wherein, The shell is provided with at least two mounting cavities on the side facing the connecting layer, and a partition is provided between the two adjacent mounting cavities, the at least two mounting cavities correspond to the at least two adjacent connected bare chips one by one, the bare chip is embedded in the corresponding mounting cavity, and the scribe groove is opposite to the partition between the two adjacent mounting cavities.

3. The power amplifier chip of claim 1 or 2, wherein, The wafer body further comprises a connecting body, the two adjacent bare chips are connected through a connecting body, and the connecting body and the two adjacent bare chips form the scribe groove; the surface of the connecting body is provided with at least one wire, and the power amplifier circuits of the two adjacent bare chips are electrically connected through the at least one wire on the surface of the corresponding connecting body.

4. The power amplifier chip of claim 3, wherein, The power amplifier circuit comprises a system control module, a clock module and a power supply module, the system control modules in the two adjacent power amplifier circuits are electrically connected through the wire on the surface of the corresponding connecting body, the clock modules in the two adjacent power amplifier circuits are electrically connected through the wire on the surface of the corresponding connecting body, and the power supply modules in the two adjacent power amplifier circuits are electrically connected through the wire on the surface of the corresponding connecting body.

5. The power amplifier chip of claim 1 or 2, wherein, The at least two adjacent connected bare chips are arranged at intervals along the length direction of the shell, and the length direction of the bare chip is perpendicular to the length direction of the shell; or The at least two bare chips are arranged at intervals along the length direction of the shell, and the length direction of the bare chip is the same as the length direction of the shell.

6. The power amplifier chip of claim 1 or 2, wherein, The solder pad comprises at least two input pins corresponding to the at least two bare chips one by one, and at least two output pins corresponding to the at least two bare chips one by one; The power amplifier circuit comprises an input buffer module, a power amplifier module and an electromagnetic interference suppression module connected in sequence, the input end of the input buffer module is connected to the corresponding input pin, and the output end of the electromagnetic interference suppression module is connected to the corresponding output pin.

7. The power amplifier chip of claim 6, wherein, The power amplifier circuit further comprises a charge pump voltage boosting module, a system control module, an address configuration module and a reset module, the first output end of the charge pump voltage boosting module is electrically connected with the power amplifier module, the second output end of the charge pump voltage boosting module is electrically connected with the electromagnetic interference suppression module, the output end of the address configuration module, the output end of the reset module, the control end of the input buffer module and the control end of the power amplifier module are respectively electrically connected with the system control module.

8. The power amplifier chip of claim 1 or 2, wherein, The connecting layer comprises a trace layer and a substrate, the shell, the trace layer and the substrate are sequentially stacked, and the pad is located on the surface of the side of the substrate away from the trace layer, and the power amplification circuit is electrically connected with the corresponding pin through the trace layer.

9. The power amplifier chip of claim 1 or 2, wherein, The connecting layer is a trace layer, and the pad is arranged on the surface of the side of the first end face of the trace layer away from the shell.

10. A power amplification system comprising a processor, at least two speakers and a power amplification chip as claimed in any one of claims 1 to 9, the pads comprising: At least two input pins corresponding to the at least two adjacent connected bare chips, and at least two output pins corresponding to the at least two adjacent connected bare chips; the processor is electrically connected with the at least two input pins, the at least two speakers correspond to the at least two output pins one by one, and the output pins are electrically connected with the corresponding speakers.

11. An electronic device comprising the power amplification system of claim 10.

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