Communication method and communication apparatus

Abstract

A communication method and a communication apparatus. In the method, a device can perform encoding or decoding on the basis of an LDPC matrix, wherein a first shift value of a first element in a base matrix is determined on the basis of one shift value in a plurality of second shift values, which correspond to the first element, among a first group of second shift values, the first group of second shift values are one group of second shift values among a plurality of predefined groups of second shift values, each predefined group of second shift values comprise a second shift value corresponding to each element 1 in the base matrix, the plurality of predefined groups of second shift values correspond to a plurality of predefined lifting value sets on a one-to-one basis, a first lifting value set among the plurality of lifting value sets corresponds to the first group of second shift values, the first lifting value set comprises a lifting value Zc corresponding to the base matrix, and one second shift value is determined on the basis of Zc and from among the plurality of second shift values corresponding to the first element. The method can ensure the performance of LDPC codes.

Description

Communication methods and communication devices

[0001] This application claims priority to Chinese Patent Application No. 202410959632.4, filed on July 16, 2024, entitled "Communication Method and Communication Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of coding, and more specifically, to a communication method and a communication device. Background Technology

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, they can be encoded using simple feedback shift registers, reducing the coding complexity of LDPC codes.

[0004] Generally, one initial translation value corresponding to each 1 element in the basis matrix of the LDPC code can be pre-stored. Then, the same translation value determination method is used globally to determine the final translation value corresponding to each 1 element in the basis matrix. For example, the global translation value determination method of the basis matrix is ​​to take the modulus of the initial translation value. Such a translation value determination method has great limitations on the translation value and cannot guarantee the performance of the LDPC code. Summary of the Invention

[0005] Embodiments of this application provide a communication method and a communication device that flexibly configures different numbers of initial translation values ​​for the 1 element of the base matrix based on different needs, so that different regions of the base matrix use different translation value determination methods, thereby ensuring the performance of the LDPC code.

[0006] In a first aspect, a communication method is provided, which can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0007] The method includes: acquiring an information bit sequence; determining an LDPC parity-check matrix, wherein the LDPC parity-check matrix is ​​determined based on a first shift value of an LDPC base matrix, wherein the first shift value of the first element in the base matrix is ​​determined based on one of a plurality of second shift values ​​corresponding to the first element in a first group of second shift values, the first element being any 1 element corresponding to the plurality of second shift values, the first group of second shift values ​​being a set of second shift values ​​in a predefined plurality of second shift values, each of the predefined plurality of second shift values ​​including the second shift value corresponding to each 1 element in the base matrix, the predefined plurality of second shift values ​​corresponding one-to-one with a predefined plurality of lift value sets, the first lift value set in the plurality of lift value sets corresponding to the first group of second shift values, the first lift value set including the lift value Zc corresponding to the base matrix, and the second shift value being determined based on Zc among the plurality of second shift values ​​corresponding to the first element; encoding the information bit sequence according to the LDPC parity-check matrix to obtain a codeword sequence; and outputting the codeword sequence.

[0008] In the above technical solution, a set of predefined second translation values ​​can be determined based on the lift value Zc. Then, based on the lift value Zc, a second translation value is selected from the set of second translation values ​​corresponding to the first element to determine the final translation value corresponding to the first element (i.e., the first translation value of the first element). The method of determining the first translation value of an element with multiple second translation values ​​is different from the current method of determining the translation value of an element. Therefore, different numbers of second translation values ​​can be flexibly configured for the elements of the base matrix based on different needs, so that different regions of the base matrix use different translation value determination methods, thereby ensuring the performance of the LDPC code.

[0009] Optionally, the first translation value of the first element is determined based on one of a plurality of second translation values ​​of the first element and the lift value Zc.

[0010] Secondly, a communication method is provided, which can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., a network device, a terminal device), a component in the receiving device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the receiving device.

[0011] The method includes: acquiring a symbol sequence; determining an LDPC parity-check matrix, wherein the LDPC parity-check matrix is ​​determined based on a first shift value of an LDPC base matrix, wherein the first shift value of the first element in the base matrix is ​​determined based on one of a plurality of second shift values ​​corresponding to the first element in a first group of second shift values, the first element being any 1 element corresponding to the plurality of second shift values, the first group of second shift values ​​being a set of second shift values ​​in a predefined plurality of second shift values, each of the predefined plurality of second shift values ​​including the second shift value corresponding to each 1 element in the base matrix, the predefined plurality of second shift values ​​corresponding one-to-one with a predefined plurality of lift value sets, the first lift value set in the plurality of lift value sets corresponding to the first group of second shift values, the first lift value set including Zc, and the second shift value being determined based on Zc among the plurality of second shift values ​​corresponding to the first element; and decoding the symbol sequence according to the LDPC parity-check matrix to obtain an information bit sequence.

[0012] For the beneficial effects of the second aspect, please refer to the description of the first aspect, which will not be repeated here.

[0013] In some implementations of the first or second aspect, the first translation value of the second element in the basis matrix is ​​determined based on the second translation value of the second element, wherein the second element is any 1 element corresponding to a second translation value, and a second translation value of the second element is a predefined translation value.

[0014] In some implementations of the first or second aspect, the second element is a 1-element located at row i and column j in the basis matrix, and the first translation value of the second element is SV. i,j Satisfying the formula: SV i,j =P i,j , or SV i,j =P i,j +w, or SV i,j =mod(P i,j ,Zc), or SV i,j =mod(P i,j +w,Zc), where P i,j is the second translation value corresponding to the second element, and w is a preset fixed value.

[0015] The above technical solution provides a possible specific implementation method for determining the first translation value of the second element.

[0016] In some implementations of the first or second aspect, the first element is the element at row i and column j in the basis matrix, and the first translation value of the first element is SV. i,j Satisfying the formula: in, is one of the multiple second translation values ​​of the first element, and w is a preset fixed value.

[0017] The above technical solution provides a possible specific implementation method for determining the first translation value of the first element.

[0018] In some implementations of the first or second aspect, the second translation values ​​of the multiple second translation values ​​of the first element are not the same as the second lift value and the second lift value, and the first lift value and the second lift value are adjacent lift values ​​in the set of first lift values.

[0019] For example, any lift value in the first lift value set satisfies a1×2 k If any two lift values ​​are in the form of and the a1 value is the same and the k value is different, where k is an integer greater than or equal to 0 and a1 is an integer greater than 1, then the first lift value and the second lift value mentioned above are adjacent lift values ​​in the first lift value set. This means that the absolute value of the difference between the k corresponding to the first lift value and the second lift value is 1. For example, the k corresponding to the first lift value is k1 and the k corresponding to the second lift value is k1+1.

[0020] In some implementations of the first or second aspect, among a plurality of second translation values ​​of the first element, the second translation value corresponding to the first lift value and the third lift value is the same, and the first lift value and the third lift value are non-adjacent lift values ​​in the set of first lift values.

[0021] For example, the first boost and the third boost mentioned above are non-adjacent boosts in the first boost set. They can be the absolute value of the difference between the k corresponding to the first boost and the third boost, where h is an integer greater than 1. For example, the k corresponding to the first boost is k1, and the k corresponding to the second boost is k1+h.

[0022] For example, h is 2, 3, or 4.

[0023] For example, multiple predefined sets of promotion values ​​all correspond to the same h.

[0024] In some implementations of the first or second aspect, different lift values ​​in the first lift value set correspond to different second translation values ​​among a plurality of second translation values ​​of the first element.

[0025] In some implementations of the first or second aspect, the basis matrix comprises X rows and Y columns, wherein the matrix corresponding to the region formed by the x1+1 to X rows and the y2+1 to Y columns of the basis matrix is ​​the identity matrix, the matrix corresponding to the region formed by the 1 to x1 rows and the y2+1 to Y columns of the basis matrix is ​​an all-zero matrix, and the matrix corresponding to the region formed by the 1 to x1 rows and the y1+1 to y2 columns of the basis matrix is ​​a square matrix, wherein 1 < x1 < X, 1 < y1 < y2 < Y, and x1, X, y1, y2, and Y are all integers.

[0026] In some implementations of the first or second aspect, the basis matrix includes a first region and a second region, where a 1 element in the first region corresponds to multiple second translation values ​​and a 1 element in the second region corresponds to a single second translation value.

[0027] For example, the first region is the region consisting of rows 1 to x1 and columns y1+1 to y2 of the base matrix, the second region is the region consisting of rows 1 to x1 and columns 1 to y1 of the base matrix and rows x1+1 to x and columns 1 to y2 of the base matrix, or the second region is all the remaining regions in the base matrix except for the first region.

[0028] The advantage of this example is that part B can use a translation value determination method that optimizes the trap set in this region, while other regions outside part B can use a translation value determination method that better optimizes the loop property, thus taking into account optimization in both aspects.

[0029] For example, the first region is the region consisting of rows 1 to x1 and columns 1 to y1 of the base matrix and the region consisting of rows 1 to x1 and columns y1+1 to y2 of the base matrix; the second region is the region consisting of rows x1+1 to x and columns 1 to y2 of the base matrix; or, the second region is all the remaining regions in the base matrix except for the first region.

[0030] The advantage of this example is that it prioritizes supporting high bitrate regions (part A + part B) before supporting low bitrate regions, which makes the performance of flexible bitrates more stable.

[0031] For example, the first region is a portion of the region consisting of rows 1 to x1 and columns 1 to y1 of the base matrix, the region consisting of rows 1 to x1 and columns y1+1 to y2 of the base matrix, and the region consisting of rows x1+1 to x and columns 1 to y2 of the base matrix. The second region is the region remaining in the region consisting of rows x1+1 to x and columns 1 to y2 of the base matrix, excluding the region occupied by the first region. Alternatively, the second region is all the regions remaining in the base matrix except for the first region.

[0032] The advantage of this example is that it allows for more granular bitrate division, supports communication scenarios with a high degree of flexibility in bitrate, and offers stable performance.

[0033] In some implementations of the first or second aspect, the basis matrix includes a first region and a second region, where a 1 element in the first region corresponds to multiple second translation values ​​and a 1 element in the second region corresponds to a single second translation value.

[0034] Example 1: The first region is the region consisting of all rows of the base matrix and at least one column from column y1+1 to y2. The second region is the region remaining in the region consisting of all rows of the base matrix and columns 1 to y2, excluding the region occupied by the first region. Alternatively, the second region is all regions remaining in the base matrix excluding the first region.

[0035] Example 2: The first region is the region consisting of at least one column from the first to the x1th rows and the y1+1th to the y2th columns of the base matrix; the second region is the region remaining in the base matrix excluding the region occupied by the first region, consisting of all the rows of the base matrix and the first to the y2th columns of the base matrix; or, the second region is all the regions remaining in the base matrix excluding the first region.

[0036] For example, at least one column from column y1+1 to y2 includes all columns from column y1+1 to y2.

[0037] For example, at least one of the columns from y1+1 to y2 includes the first column, which satisfies the first condition, which is that the column weight of the first column in the region formed by the first to x1 rows of the base matrix and the y1+1 to y2 columns is an odd number greater than 1.

[0038] The advantage of the above examples is that they maintain simple hardware coding while ensuring the absence of small trap sets, resulting in better performance in terms of error floors. Specifically, Example 1 has better characteristics regarding low-to-medium bitrate trap sets, while Example 2 offers greater design space for the second region, simplifying the design of translation values ​​and reducing implementation difficulty.

[0039] In some implementations of the first or second aspect, the basis matrix includes a first region and a second region, where a 1 element in the first region corresponds to multiple second translation values ​​and a 1 element in the second region corresponds to a single second translation value.

[0040] For example, the first region is the region consisting of at least one row from row 1 to x1 and column 1 to y2 of the base matrix, and the second region is the region remaining in the region consisting of row 1 to x1 and column 1 to y2 of the base matrix excluding the region occupied by the first region, or the second region is all the regions remaining in the base matrix excluding the first region.

[0041] For example, the first region is the region consisting of at least one row from row x1+1 to X and columns 1 to y2 of the base matrix, and the second region is the region remaining in the region consisting of row x1+1 to X and columns 1 to y2 of the base matrix excluding the region occupied by the first region, or the second region is all the regions remaining in the base matrix excluding the first region.

[0042] The advantage of the above example is that it avoids the formation of small-scale trap sets, which reduce the error level of LDPC at a specific bitrate.

[0043] In some implementations of the first or second aspect, the lift value in any of the predefined lift value sets satisfies a×2 k The form is: where different sets of promotion values ​​correspond to different a, and each promotion value in the same set of promotion values ​​corresponds to the same a and different k, where k is an integer greater than or equal to 0, and a is an integer greater than 1.

[0044] In some implementations of the first or second aspect, the a corresponding to the first lift value set is equal to a1, and multiple second translation values ​​of the first element satisfy... in, and Let k0 be any two of the multiple second translation values ​​of the first element, where k0 is a positive integer.

[0045] In some implementations of the first or second aspect, for any integer k1 ≥ k0, multiple second translation values ​​of the first element also satisfy...

[0046] By meeting the above conditions, small-scale trap sets can be avoided under various code lengths, thus ensuring the performance of LDPC codes.

[0047] For example, k0 = 2, 3, 4, or 5, or k0 is the smallest lift in the first lift set.

[0048] For example, multiple predefined sets of promotion values ​​all have the same k0.

[0049] Thirdly, a communication apparatus is provided for performing the method provided by any of the above aspects or their implementations. Specifically, the apparatus may include units and / or modules for performing the method provided by any of the above aspects or their implementations, such as processing units and / or transceiver units.

[0050] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0051] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0052] Fourthly, a communication device is provided, comprising: a memory for storing a program; and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided in any of the foregoing aspects or their implementations.

[0053] In one implementation, the device is either a transmitting device or a receiving device.

[0054] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0055] Fifthly, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in any of the foregoing aspects or their implementations. The communication interface may be implemented in hardware or software.

[0056] In one implementation, the device further includes the memory.

[0057] Sixthly, a processor is provided for executing the methods provided in the above aspects.

[0058] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0059] In a seventh aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing any of the foregoing aspects or their implementations.

[0060] Eighthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in any of the foregoing aspects or their implementations.

[0061] Ninthly, a chip is provided, comprising a processor and a communication interface. The processor reads instructions stored in a memory through the communication interface and executes the methods provided in any of the above aspects or their implementations. The communication interface can be implemented in hardware or software.

[0062] Optionally, as one implementation, the chip also includes a memory that stores computer programs or instructions. The processor is used to execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the methods provided by any of the above aspects or their implementations.

[0063] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0064] In a tenth aspect, a computer program is provided that, when run on a computer, causes the methods provided by any of the foregoing aspects or their implementations to be executed.

[0065] Eleventhly, a communication system is provided, including at least one of the transmitting end device or receiving end device described above. Attached Figure Description

[0066] Figure 1 is a schematic diagram of a network architecture to which embodiments of this application can be applied.

[0067] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0068] Figure 3 shows the Tanner plot of the parity-check matrix H of an LDPC.

[0069] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0070] Figure 5 is a schematic diagram of the information transmission process.

[0071] Figure 6 is a schematic flowchart of a communication method 600 provided in this application.

[0072] Figure 7 is a schematic diagram of the coding structure corresponding to part B under different scales.

[0073] Figure 8 is a schematic diagram of the first region under different division methods.

[0074] Figure 9 is a schematic block diagram of a communication device 1000 provided in an embodiment of this application.

[0075] Figure 10 is a schematic block diagram of the communication device 1100 provided in an embodiment of this application. Detailed Implementation

[0076] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0077] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words "exemplary," "for example," "exemplary," "as another example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, while "more" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when…", "in the case of…", "if", and "if" indicate that the device will take corresponding action under certain objective circumstances, not a time limit, nor requiring the device to perform a judgment action during implementation, nor implying any other limitations. Phrases such as "corresponding to…", "correspondingly", and equivalent expressions indicate a correspondence between the preceding and following elements, which may include indirect correspondence. For example, corresponding to a certain objective situation, the device will directly or indirectly take corresponding action, without requiring the corresponding action to immediately follow that objective situation.

[0078] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0079] The following describes a communication system to which embodiments of this application can be applied.

[0080] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0081] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0082] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of this application. As shown in Figure 1, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 only uses uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application in other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0083] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0084] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, RAN equipment including CU and DU nodes, RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes, or, in a cloud radio access network (CRAN) scenario, wireless controllers, relay stations, vehicle-mounted equipment, and wearable devices. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication networks. A base station may support networks with the same or different access technologies, without limitation.

[0085] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0086] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0087] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, URLLC (ultra-reliable low-latency communication) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0088] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0089] 1. LDPC code

[0090] LDPC codes are a type of linear block code. Linear block codes divide the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0091] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit sequence length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0092] In 1981, Tanner represented the parity-check matrix H graphically, and this type of graph is now called a Tanner graph. There is a one-to-one correspondence between the Tanner graph and the parity-check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint, which will be explained below with reference to Figures 2 and 3.

[0093] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0094] In Figure 2, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CNs). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 2, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner graph.

[0095] Figure 3 is a Tanner plot of the parity-check matrix H of an LDPC.

[0096] As shown in Figure 3, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph consists of interconnected vertices. The cycle starts and ends at one vertex in this group of vertices and passes through each node only once. The length of a cycle is defined as the number of edges it contains, and the perimeter of the graph, also known as the graph's circumference, is defined as the minimum cycle length in the graph. In Figure 3, the perimeter is 4, as shown by the bolded lines. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bits in the LDPC. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, then the element (i, j) in the H matrix has a value of 1; if there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as: there is a connection or an edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge. Furthermore, in a Tanner graph, a cycle is a closed loop formed by connecting variable nodes, check nodes, and edges end-to-end.

[0097] 2. QC-LDPC code

[0098] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base graph (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, which can be referred to as the base matrix H in this application. BG Basis matrix H BGAn element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The expansion process of the base matrix is ​​described below.

[0099] Based on the base matrix and the lifting size Zc, the base matrix can be expanded into a complete parity-check matrix for encoding or decoding. In this application, Zc... c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process involves lifting all elements of the base matrix into a Zc×Zc square matrix, where 0 is lifted into a Zc×Zc 0 matrix, and 1 is lifted into an identity matrix. This identity matrix is ​​then cyclically shifted based on the shifting value (SV) corresponding to 1. This cyclic shift can be left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, and 3, the cyclically shifted matrix after a rightward cyclic shift is as follows:

[0100] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0101] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0102] (3) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0103] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrix is ​​represented by an exponential matrix H, where each element indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. This significantly reduces the storage space required for the complete parity check matrix H. b The elements in it can also be called QC blocks.

[0104] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0105] It can be seen that the exponent matrix Hb The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the array represents a Z. c Square matrix of order Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0106] For example, As shown below:

[0107] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0108] It is understandable that the above exponent matrix H b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0109] Next, the information bit sequence c can be encoded based on the parity-check matrix H to obtain a codeword sequence. The codeword sequence includes (N+2*Zc-K) parity bits w, where N is the length of the codeword sequence, K = Kb*Zc, Kb is the number of columns corresponding to the information column in the base map, and Zc is the boost value. For details on Zc, please refer to the explanation in Terminology 3. Specifically, the parity bits w are determined based on the information bit sequence c and the parity-check matrix H, where the parity bits are w = [w0, w1, w2, ..., wN+2*Zc-K-1]. T c = [c0, c1, c2, ..., c K-1 ] T The encoding process is solving equations The process of obtaining w.

[0110] 3. Increase value Z c (Lifting Size) and (Shifting Value)

[0111] The storage content of the 5G LDPC code regarding shifting values ​​includes: (1) a list of lifting sizes; and (2) a list of shifting values ​​that correspond one-to-one with the rows of the lifting size list.

[0112] For example, the list of Lifting Sizes is shown in Table 1.

[0113] Table 1

[0114] The j-th row of the Lifting Size list includes Where a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}; The row index of Lifting Size corresponds one-to-one with the column index of Shifting Value, that is, the lifting size in each row of the Lifting Size list corresponds to a set of Shifting Values.

[0115] For example, the list of Shifting Values ​​is shown in Table 2.

[0116] Table 2

[0117] For a fixed lift index, a non-zero position in the base matrix corresponds to one translation value. For example, H... BG The shift value corresponding to row 0, column 0 when the promotion index is 0 is 211, H BG The shift value corresponding to the 6th column of the 1st row in the middle when the lifting index = 3 is 66, H BG The shift value corresponding to the second row and ninth column of the middle column when the promotion index is 7 is 206.

[0118] It's understandable that LDPC encoding requires first determining the lift value, and then constructing a parity check matrix based on the corresponding shift value. For example, if the determined lift value is 40, and the lift value index corresponding to 40 in Table 1 is 2, then the parity check matrix can be constructed based on the shift value in the column corresponding to lift value index = 2 in Table 2.

[0119] 4. Column weight and row weight

[0120] For a given column of a matrix, column weight refers to the number of non-zero elements contained in that column. For a given row of a matrix, row weight refers to the number of non-zero elements contained in that row. It can be understood that the matrix involved in the descriptions of row and column weights is the parity check matrix H.

[0121] 5. Structure of the parity-check matrix and the basis matrix

[0122] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0123] As shown in Figure 4(a), the parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 4(b). Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to the core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or it can be a parity with a degree greater than or equal to 2, or it can be the parity node corresponding to the row set with the largest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C in Figure 4(b) and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 4(b). The raptor-like region can correspond to part E in Figure 4(b) and can be an identity matrix corresponding to the parity bits of the low-rate extension.

[0124] The parity-check matrix of the LDPC code shown in Figure 4 adopts a "raptor-like" structure, which can be gradually extended to low code rates from a high code rate core matrix. In actual use, as shown in Figure 4(a), the first X rows and the first Y columns of the parity-check matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0125] It should be noted that the parity check matrix can be obtained by extending the LDPC basis matrix. Therefore, the structure of the LDPC basis matrix is ​​similar to that of the parity check matrix, and will not be described in detail here.

[0126] 6. Information column and validation column

[0127] The columns of the LDPC base matrix consist of information columns and check columns.

[0128] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0129] Check columns: Corresponding to check bits (or check digits, etc.), these are the columns corresponding to parts B and C, and can include core check columns and extended check columns. The core check columns are those corresponding to part B, while the extended check columns are those corresponding to parts C or E. Extended check columns can also be called raptor-like columns. Alternatively, the core check columns are the check columns in part B with a column weight greater than 1 (part B has 1 elements both above and below its diagonal), and the extended check columns are the remaining check columns excluding the core check columns.

[0130] 7. Core rows, core columns, and core matrix

[0131] Core rows: The core rows of the LDPC basis matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C.

[0132] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0133] The kernel matrix is ​​a matrix region consisting of all the kernel rows and columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high-rate region of the LDPC base matrix, or the part consisting of part A and part B.

[0134] 8. Message length, code length, and code rate

[0135] The information length is the length of the bit sequence of information to be sent (i.e., the number of bits contained therein). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0136] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0137] Code rate refers to the ratio of the length of the bit sequence of information to be transmitted to the code length.

[0138] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0139] 9. Information Transmission Process

[0140] Figure 5 is a schematic diagram of the information transmission process applicable to this application. As shown in Figure 5, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation) is performed at the transmitting end device, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the receiving end device. The embodiments of this application mainly involve the source coding, channel coding, channel decoding, and source recovery shown in Figure 5.

[0141] As described in the background section, current methods for determining translation values ​​cannot guarantee the performance of LDPC codes. In view of this, this application proposes a communication method that can effectively solve the aforementioned technical problems. The method proposed in this application is described in detail below.

[0142] Figure 6 is a schematic flowchart of a communication method 600 provided in this application. The method includes the following steps.

[0143] It is understood that method 600 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0144] S610, the transmitting device obtains the information bit sequence.

[0145] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0146] The process of the transmitting device acquiring the information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0147] S620, the transmitting device determines the LDPC check matrix.

[0148] The LDPC parity-check matrix is ​​determined based on the first translation value of the LDPC base matrix (hereinafter referred to as the base matrix). The first translation value of the first element in the base matrix is ​​determined based on one of the multiple second translation values ​​corresponding to the first element in the first group of second translation values. The first element is any 1 element corresponding to the multiple second translation values. The first group of second translation values ​​is a set of second translation values ​​in a predefined set of multiple groups of second translation values. Each set of second translation values ​​in the predefined set of multiple groups of second translation values ​​includes the second translation value corresponding to each 1 element in the base matrix. The predefined set of multiple groups of second translation values ​​corresponds one-to-one with a predefined set of multiple lift values. The first lift value set in the multiple lift value sets corresponds to the first group of second translation values. The first lift value set includes the lift value Zc corresponding to the base matrix. The second translation value used to determine the first translation value of the first element is determined based on Zc among the multiple second translation values ​​corresponding to the first element.

[0149] Optionally, the boost values ​​in any of the predefined boost value sets can satisfy a×2. k The form is: where different sets of promotion values ​​correspond to different values ​​of 'a'. Within the same set of promotion values, all promotion values ​​have the same value of 'a' and different values ​​of 'k', where 'k' is an integer greater than or equal to 0, and 'a' is an integer greater than 1. For example, several predefined sets of promotion values ​​are shown in Table 1, where the values ​​of 'a' corresponding to these sets are {2, 3, 5, 7, 9, 11, 13, 15}.

[0150] In one possible implementation, similar to Table 1, each lift value set can correspond to a lift value index. Similar to Table 2, each lift value index corresponds to a set of second translation values, which includes the second translation value corresponding to each 1 element in the base matrix. The difference from Table 2 is that in this application, in a set of second translation values ​​corresponding to a lift value index, at least one 1 element in the base matrix corresponds to multiple second translation values.

[0151] Optionally, the boost value Zc corresponding to the basis matrix is ​​determined based on the target code length, code rate, and communication scenario.

[0152] Optionally, the first translation value of the second element in the basis matrix is ​​determined based on the second translation value of the second element. The second element is any 1 element corresponding to a second translation value, and a second translation value of the second element is a predefined translation value. Simply put, the first element corresponds to multiple second translation values, while the second element corresponds to only one second translation value.

[0153] It can also be understood that only 1 elements in the base matrix have translation values, while 0 elements do not. Therefore, the LDPC parity check matrix is ​​determined based on the first translation value of the base matrix, meaning that the LDPC parity check matrix is ​​determined based on the first translation value of each 1 element in the base matrix.

[0154] Optionally, in this application, the second translation value corresponding to the first element and the second translation value corresponding to the second element in the base matrix can be stored in the same table or in different tables, and this application does not limit this.

[0155] The first translation value of the first element and the second element is described below with examples.

[0156] (1) The first element is the element in row i and column j of the basis matrix, and the first translation value of the first element is SV. i,j Satisfying the formula: in, w is a second translation value used to determine the first translation value of the first element among multiple second translation values ​​of the first element, where w is a preset fixed value.

[0157] Here, mod represents the modulo operator, mod(a, b) = a mod b = c, indicating that the remainder when a is divided by b is c.

[0158] For example, all rows and all columns of the base matrix correspond to the same preset fixed value w.

[0159] For example, each row of the basis matrix corresponds to a different preset fixed value w, and each column of the basis matrix corresponds to a different preset fixed value w.

[0160] Among them, in (1) above This can be understood as determining a second translation value based on Zc in the first lift value set among multiple second translation values ​​of the first element.

[0161] Optionally, among the multiple second translation values ​​of the first element, the second translation values ​​corresponding to the first lift value and the second lift value in the first lift value set respectively satisfy a first feature. The first feature is that the translation value #1 corresponding to the first lift value and the translation value #2 corresponding to the second lift value are different. The first lift value and the second lift value are adjacent lift values ​​in the first lift value set. The multiple second translation values ​​of the first element include translation value #1 and translation value #2.

[0162] For example, any lift value in the first lift value set satisfies a×2 k If any two lift values ​​are in the form of and the value of 'a' is the same and the value of 'k' is different, where 'k' is an integer greater than or equal to 0 and 'a' is an integer greater than 1, then the first lift value and the second lift value are any two adjacent lift values ​​in the first lift value set. This means that the absolute value of the difference between the k values ​​corresponding to the first lift value and the second lift value is 1. For example, the k value corresponding to the first lift value is k1 and the k value corresponding to the second lift value is k1+1.

[0163] Optionally, in addition to satisfying the first feature, the second shift values ​​of the multiple second shift values ​​of the first element, which correspond to the first shift value and the third shift value in the first shift value set respectively, also satisfy the second feature. The second feature is that the second shift value corresponding to the first shift value and the second shift value corresponding to the third shift value are both shift value #1. The first shift value and the third shift value are non-adjacent shift values ​​in the first shift value set. The multiple second shift values ​​of the first element include shift value #1.

[0164] For example, the first boost and the third boost mentioned above are non-adjacent boosts in the first boost set. They can be the absolute value of the difference between the k corresponding to the first boost and the third boost, where h is an integer greater than 1. For example, the k corresponding to the first boost is k1, and the k corresponding to the second boost is k1+h.

[0165] For example, h is 2, 3, or 4.

[0166] For example, multiple predefined sets of promotion values ​​all correspond to the same h.

[0167] For example, the desired second shift value can be selected from multiple second shift values ​​of the first element based on the lift value Zc as follows: when mod(k,h)=0, the first second shift value among multiple second shift values ​​of the first element is selected; when mod(k,h)=1, the second second shift value among multiple second shift values ​​of the first element is selected, and so on. It can be seen that when mod(k,h)=0, then mod(k+h,h)=0; when mod(k,h)=1, then mod(k+h,h)=1; ... Therefore, when the absolute value of the difference between k corresponding to the first lift value and the third lift value is h, the first lift value and the third lift value correspond to the same second shift value among multiple second shift values ​​of the first element.

[0168] Optionally, each lift value in the first lift value set corresponds to a different second shift value among multiple second shift values ​​of the first element. It can be understood that in this method, the number of second shift values ​​corresponding to the first element is greater than or equal to the number of lift values ​​in the first lift value set.

[0169] (2) The second element is the 1 element in row i and column j of the basis matrix, and the first translation value of the second element is SV. i,j Satisfying the formula: SV i,j =P i,j , or SV i,j =P i,j +w, or SV i,j =mod(P i,j ,Zc), or SV i,j =mod(P i,j +w,Zc), where Pi,j The second translation value corresponds to the second element, and w is a preset fixed value. For details about w, please refer to the description in (1), which will not be repeated here.

[0170] In one possible implementation, the basis matrix includes a first region and a second region. In the first region, a 1 element corresponds to multiple second translation values, while in the second region, a 1 element corresponds to only one second translation value. Examples of the first and second regions are given below.

[0171] Optionally, the union of the first and second regions is all regions of the basis matrix. For example, the basis matrix consists of the first and second regions, meaning that each element in the basis matrix either lies in the first region or belongs to the second region.

[0172] Optionally, the union of two regions is a partial region of the basis matrix. For example, according to the region division in Figure 4(b), by default, the translation values ​​of part E are all 0, and part C has no 1 elements, so there is no translation value. Then the union of the first and second regions is the region corresponding to parts A, B and D of the basis matrix.

[0173] Before introducing the specific implementation method, we first describe the row and column characteristics of the basis matrix. The basis matrix has a total of X rows and Y columns. The regions formed by some rows and some columns of the basis matrix have the following characteristics: the matrix corresponding to the region formed by the x1+1 to X rows and the y2+1 to Y columns of the basis matrix is ​​the identity matrix (i.e., the E part of the corresponding basis matrix); the matrix corresponding to the region formed by the 1 to x1 rows and the y2+1 to Y columns of the basis matrix is ​​the matrix of all zeros (i.e., the C part of the corresponding basis matrix); and the matrix corresponding to the region formed by the 1 to x1 rows and the y1+1 to y2 columns of the basis matrix is ​​the square matrix (i.e., the B part of the corresponding basis matrix). Where 1 < x1 < X, 1 < y1 < y2 < Y, and x1, X, y1, y2, and Y are all integers.

[0174] For example, rows 1 to x1 of the base matrix can be called core rows, columns 1 to y1+1 of the base matrix can be called information columns, columns y1+1 to y2 of the base matrix can be called core check columns, columns 1 to y2 of the base matrix can be called core columns, and columns y2+1 to Y can be called extended check columns. The following describes specific implementation methods for possible region division based on the above row and column characteristics.

[0175] Example 1: The first region is the region consisting of rows 1 to x1 and columns y1+1 to y2 of the base matrix (i.e., the B part of the corresponding base matrix); the second region is the region consisting of rows 1 to x1 and columns 1 to y1 of the base matrix and rows x1+1 to X and columns 1 to y2 of the base matrix (i.e., the A part + D part of the corresponding base matrix); or, the second region is all the remaining regions in the base matrix except for the first region.

[0176] The advantage of this example is that part B can use a translation value determination method that optimizes the trap set in this region, while other regions outside part B can use a translation value determination method that better optimizes the loop property, thus taking into account optimization in both aspects.

[0177] Example 2: The first region is the region consisting of rows 1 to x1 and columns 1 to y1 of the base matrix and the region consisting of rows 1 to x1 and columns y1+1 to y2 of the base matrix (i.e., the A part + B part of the base matrix). The second region is the region consisting of rows x1+1 to x and columns 1 to y2 of the base matrix (i.e., the D part of the base matrix), or the second region is all the remaining regions in the base matrix except for the first region.

[0178] The advantage of this example is that it prioritizes supporting high bitrate regions (part A + part B) before supporting low bitrate regions, which makes the performance of flexible bitrates more stable.

[0179] Example 3: The first region is a portion of the region consisting of rows 1 to x1 and columns 1 to y1 of the base matrix, the region consisting of rows 1 to x1 and columns y1+1 to y2 of the base matrix, and the region consisting of rows x1+1 to X and columns 1 to y2 of the base matrix (i.e., the A part + B part + part D part of the base matrix). The second region is the remaining region in the region consisting of rows x1+1 to X and columns 1 to y2 of the base matrix excluding the region occupied by the first region (i.e., the remaining region in part D of the base matrix excluding the region occupied by the first region), or the second region is all the remaining regions in the base matrix excluding the first region.

[0180] The advantage of this example is that it allows for more granular bitrate division, supports communication scenarios with a high degree of flexibility in bitrate, and offers stable performance.

[0181] Example 4: The first region is the region consisting of all rows of the base matrix and at least one column from column y1+1 to y2 (i.e., the core verification column); the second region is the region remaining in the base matrix excluding the region occupied by the first region, consisting of all rows of the base matrix and column 1 to y2 (information column); or, the second region is all regions remaining in the base matrix excluding the first region.

[0182] Optionally, at least one column from column y1+1 to y2 is all columns from column y1+1 to y2.

[0183] Optionally, at least one of the columns from y1+1 to y2 includes the first column, which satisfies the first condition: the column weight of the first column in the region formed by rows 1 to x1 and columns y1+1 to y2 of the base matrix (i.e., part B of the base matrix) is an odd number greater than 1. It is important to emphasize that an odd number of column weights greater than 1 here means that the number of 1s in the elements of the first column located in part B is an odd number greater than 1.

[0184] It is understandable that the encoding structure of part B of the base matrix in the current 5G standard is a double diagonal structure. Figure 7 is a schematic diagram of the encoding structure corresponding to part B at different scales. As shown in Figure 7, any box in the figure represents the size of the matrix corresponding to part B of the base matrix. 0 and 1 in each box represent translation values. Since 1 elements of the base matrix have translation values ​​and 0 elements do not, the element corresponding to the position with a translation value in each box is a 1 element, and the element corresponding to the position without a translation value in the figure is a 0 element. The column degree distribution in part B is that there is one triple column (i.e., the first column in each box), and the rest are double columns (i.e., the remaining columns in each box). The two translation values ​​of the double column are the same (both are 0 as shown in Figure 7), and two of the three translation values ​​of the triple column are the same (two of the three translation values ​​of the triple column are 1, and the other translation value is 0 as shown in Figure 7). The special properties of the translation values ​​ensure that they can be encoded in a simple way. It can be understood that the first column that satisfies the first condition includes the triple column of part B (that is, the first column in part B, corresponding to the y1+1th column of the basis matrix).

[0185] Optionally, the first region is the region consisting of the three columns of part B and all rows of the basis matrix, and the remaining region in the basis matrix excluding the first region is the second region. Optionally, further, the first region is the region consisting of all columns corresponding to part B and all rows of the basis matrix, and the remaining region in the basis matrix excluding the first region is the second region.

[0186] Example 5: The first region is the region consisting of at least one column from the first to the x1st rows (i.e., core rows) and the y1+1st to the y2th columns (i.e., core check columns) of the base matrix. The second region is the region remaining in the base matrix excluding the region occupied by the first region, which is the region consisting of all rows of the base matrix and the region consisting of the first to the y2th columns of the base matrix. Alternatively, the second region is all the regions remaining in the base matrix excluding the first region.

[0187] Optionally, at least one column from column y1+1 to y2 is all columns from column y1+1 to y2.

[0188] Optionally, at least one of the columns from y1+1 to y2 includes the first column, which satisfies the first condition, which is that the column weight of the first column in the region formed by the first to x1 rows of the base matrix and the y1+1 to y2 columns (i.e., part B of the base matrix) is an odd number greater than 1.

[0189] It is understandable that the difference between Example 5 and Example 4 is that the first region in Example 5 includes all elements in the base matrix of a certain column of the core check column, while the first region in Example 5 only includes all elements in part B of a certain column of column y1+1 to y2 (i.e., the core check column). Taking Figure 8 as an example, if at least one column of column y1+1 to y2 is all columns of column y1+1 to y2, then based on Example 4, the first region is the region composed of rows 1 to X and columns y1+1 to y2, specifically the region filled in Figure 8(a). Based on Example 5, the first region is the region composed of rows 1 to x1 and columns y1+1 to y2, specifically the region filled in Figure 8(b).

[0190] The advantage of Examples 4 and 5 is that they maintain simple hardware coding while ensuring the absence of small trap sets, resulting in better performance in error leveling. Specifically, Example 4 has better trap set properties at low to medium bit rates, while Example 5 offers greater design space for the second region, simplifying translation value design and reducing implementation difficulty.

[0191] The above provides a detailed description of the first translation values ​​corresponding to the first and second elements in the basis matrix, as well as the first and second regions where the first and second elements are located. The following section introduces the numerical characteristics among the multiple second translation values ​​corresponding to the first element.

[0192] It can be understood that Zc is included in the first lift value set, and the value of any lift value in the first lift value set is equal to a1×2. k And any two lift values ​​have the same a1 value and different k values, where k is an integer greater than or equal to 0 and a1 is an integer greater than 1.

[0193] Optionally, multiple second translation values ​​of the first element satisfy... in, and Let k0 be any two of the multiple second translation values ​​of the first element, where k0 is a positive integer.

[0194] Optionally, for any integer k1 ≥ k0, multiple second translation values ​​of the first element also satisfy...

[0195] For example, k0 = 2, 3, 4, or 5, or k0 is the smallest lift in the first lift set.

[0196] For example, multiple predefined sets of promotion values ​​all have the same k0.

[0197] S630: The transmitting device encodes the information bit sequence according to the LDPC parity check matrix and outputs the codeword sequence.

[0198] S640, the transmitting device determines the symbol sequence based on the codeword sequence.

[0199] It is understandable that a symbol sequence can be a rate-matched sequence or a modulated sequence. For example, the transmitting device performs rate matching on the codeword sequence, then modulates the rate-matched sequence to obtain a symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0200] S650, the transmitting device sends a symbol sequence to the receiving device. Correspondingly, the receiving device receives the symbol sequence from the transmitting device.

[0201] It is understandable that the symbol sequence #1 sent by the transmitting device and the symbol sequence #2 received by the receiving device may be different because channel noise signals may be introduced during the transmission of the symbol sequence.

[0202] S660: The receiving device decodes the symbol sequence according to the LDPC parity check matrix to obtain the information bit sequence.

[0203] The LDCP check matrix used for decoding by the receiving device is the same as the LDPC check matrix used for encoding by the sending device. The specific method by which the receiving device determines the LDPC check matrix can be found in the description on the sending device side, and will not be detailed here.

[0204] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0205] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0206] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0207] The method embodiments provided in this application have been described in detail above with reference to Figures 1 to 8. The apparatus embodiments of this application will now be described with reference to Figures 9 and 10. It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 9 and 10 include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0208] Figures 9 and 10 are schematic diagrams of possible apparatus structures provided in embodiments of this application. These apparatuses can be used to implement the functions of the transmitting or receiving devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0209] Figure 9 is a schematic block diagram of a communication device 1000 provided in an embodiment of this application. As shown in Figure 9, the device 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside world, and the processing unit 1020 is used for data processing. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

[0210] In one possible design, the device 1000 can implement the steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 1020 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 1010 is used to perform transmission-related operations of the transmitting device in the above method embodiments.

[0211] In another possible design, the device 1000 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 1010 is used to perform the receiving-related operations of the receiving device in the above method embodiments, and the processing unit 1020 is used to perform the processing-related operations of the receiving device in the above method embodiments.

[0212] It is understood that the device 1000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the device 1000 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, the device 1000 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0213] The apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0214] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In the embodiments of this application, the device in FIG9 can be the receiving end device or transmitting end device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitation is made here.

[0215] Figure 10 is a schematic block diagram of a communication device 1100 provided in an embodiment of this application. The device 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is used to execute instructions to control the transceiver 1120 to send and / or receive signals.

[0216] Optionally, the device 1100 may further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 via an internal connection path. The memory 1130 stores instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0217] Optionally, the memory 1130 may be integrated into the processor 1110.

[0218] In one possible scenario, device 1100 includes at least one processor with integrated memory, and other memory besides the memory integrated on the processor.

[0219] It is understood that the device 1100 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 1120 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 1100 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments.

[0220] Optionally, the memory 1130 may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include non-volatile random access memory. For example, the memory may also store device type information. The processor 1110 may be used to execute instructions stored in the memory, and when the processor 1110 executes instructions stored in the memory, the processor 1110 is used to perform the various steps and / or processes of the method embodiments corresponding to the transmitting or receiving devices described above.

[0221] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0222] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0223] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0224] Optionally, the memory (e.g., 1130) in the embodiments of this application may be integrated into the processor (e.g., 1110).

[0225] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0226] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0227] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0228] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0229] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0230] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0231] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0232] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0233] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0234] It can also be understood that in this application, "when," "if," and "if" all refer to the network element making corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0235] It can also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it can also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

Claims

1. A communication method based on a low-density parity-check (LDPC) code, characterized by, The method comprises: obtaining an information bit sequence; determining an LDPC check matrix, the LDPC check matrix being determined based on a first shift value of an LDPC base matrix, wherein the first shift value of a first element in the base matrix is determined based on one of a plurality of second shift values corresponding to the first element in a first set of second shift values, the first element being any 1 element corresponding to the plurality of second shift values, the first set of second shift values being one of a plurality of predefined sets of second shift values, each set of second shift values in the plurality of predefined sets of second shift values comprising a second shift value corresponding to each 1 element in the base matrix, the plurality of predefined sets of second shift values corresponding to a plurality of predefined sets of lifting values one by one, a first set of lifting values in the plurality of sets of lifting values corresponding to the first set of second shift values, the first set of lifting values comprising a lifting value Zc corresponding to the base matrix, and the one of the plurality of second shift values corresponding to the first element being determined based on the Zc. encoding the information bit sequence according to the LDPC check matrix to obtain a codeword sequence; and outputting the codeword sequence.

2. A communication method based on a low-density parity-check (LDPC) code, comprising: obtaining a symbol sequence; determining an LDPC check matrix, the LDPC check matrix being determined based on a first shift value of an LDPC base matrix, wherein the first shift value of a first element in the base matrix is determined based on one of a plurality of second shift values corresponding to the first element in a first set of second shift values, the first element being any 1 element corresponding to the plurality of second shift values, the first set of second shift values being one of a plurality of predefined sets of second shift values, each set of second shift values in the plurality of predefined sets of second shift values comprising a second shift value corresponding to each 1 element in the base matrix, the plurality of predefined sets of second shift values corresponding to a plurality of predefined sets of lifting values one by one, a first set of lifting values in the plurality of sets of lifting values corresponding to the first set of second shift values, the first set of lifting values comprising a lifting value Zc corresponding to the base matrix, and the one of the plurality of second shift values corresponding to the first element being determined based on the Zc. decoding the symbol sequence according to the LDPC check matrix to obtain an information bit sequence. the first shift value of a second element in the base matrix is determined based on a second shift value of the second element, the second element being any 1 element corresponding to one second shift value, the second shift value of the second element being a predefined shift value.

3. The method according to claim 1 or 2, characterized in that, for the one of the plurality of second shift values of the first element, the w being a preset fixed value.

4. The method of claim 3, wherein, The second element is the 1 element in the base matrix located at row i and column j, and the first shift value of the second element is SV i,j satisfies the formula: SV i,j = P i,j , or, SV i,j = P i,j + w, or, SV i,j = mod(P i,j , Zc), or, SV i,j = mod(P i,j + w, Zc), wherein P i,j is a second translation value corresponding to the second element, and w is a preset fixed value.

5. The method according to any one of claims 1 to 4, characterized in that, The first element is a 1 element in the base matrix located at row i and column j, and the first shift value of the first element is SV i,j The formula is satisfied: wherein the one of the plurality of second shift values of the first element corresponding to a first lifting value and a second lifting value is different, the first lifting value and the second lifting value being adjacent lifting values in the first set of lifting values.

6. The method according to any one of claims 1 to 5, characterized in that, 7. The method of claim 6, comprising: ​ The second translation value corresponding to the first lifting value and the third lifting value in the plurality of second translation values of the first element is same, and the first lifting value and the third lifting value are non-adjacent lifting values in the first lifting value set.

8. The method of claim 6, wherein, Different lifting values in the first lifting value set correspond to different second translation values in the plurality of second translation values of the first element.

9. The method according to any one of claims 1 to 8, characterized in that, The base matrix comprises X rows and Y columns, the base matrix comprises a first region and a second region, the 1 elements in the first region correspond to a plurality of second translation values, and the 1 elements in the second region correspond to one second translation value, The first region is a region composed of the 1st-x1 rows and the y1+1-y2 columns of the base matrix, the second region is a region composed of the 1st-x1 rows and the 1st-y1 columns of the base matrix and a region composed of the x1+1-X rows and the 1st-y2 columns of the base matrix, or the second region is all the regions remaining in the base matrix except the first region, Or, The first region is a region composed of the 1st-x1 rows and the 1st-y1 columns of the base matrix and a region composed of the 1st-x1 rows and the y1+1-y2 columns of the base matrix, and the second region is a region composed of the x1+1-X rows and the 1st-y2 columns of the base matrix, or the second region is all the regions remaining in the base matrix except the first region, Or, The first region is a region composed of the 1st-x1 rows and the 1st-y1 columns of the base matrix, a region composed of the 1st-x1 rows and the y1+1-y2 columns of the base matrix, and a region composed of the x1+1-X rows and the 1st-y2 columns of the base matrix, and the second region is a region composed of the x1+1-X rows and the 1st-y2 columns of the base matrix, or the second region is all the regions remaining in the base matrix except the first region, Wherein, 1 10. The method according to any one of claims 1 to 8, characterized in that, The base matrix comprises X rows and Y columns, the base matrix comprises a first region and a second region, the 1 elements in the first region correspond to a plurality of second translation values, and the 1 elements in the second region correspond to one second translation value, The first region is a region composed of all rows of the base matrix and at least one column of the y1+1-y2 columns, The second region is a region composed of all rows of the base matrix and the 1st-y2 columns of the base matrix, or the second region is all the regions remaining in the base matrix except the first region, Wherein, 1 11. The method according to any one of claims 1 to 8, characterized in that, The base matrix comprises X rows and Y columns, the base matrix comprises a first region and a second region, the 1 elements in the first region correspond to a plurality of second translation values, and the 1 elements in the second region correspond to one second translation value, The first region is a region composed of at least one column of 1st-x1 rows and y1+1-y2 columns of the base matrix, The second region is a region composed of all rows of the base matrix and 1st-y2 columns of the base matrix, except for the region occupied by the first region, or the second region is all regions of the base matrix except for the first region, Wherein, 1 12. The method of claim 10 or 11, wherein, The at least one column of the y1+1-y2 columns includes all columns of the y1+1-y2 columns, Or, The at least one column of the y1+1-y2 columns includes a first column, and the first column satisfies a first condition, and the first condition is that the first column corresponds to an odd number of columns with a column weight greater than 1 in a region composed of 1st-x1 rows and y1+1-y2 columns of the base matrix.

13. The method according to any one of claims 1 to 8, characterized in that, The base matrix includes X rows and Y columns, the base matrix includes a first region and a second region, and a 1 element in the first region corresponds to a plurality of second translation values, and a 1 element in the second region corresponds to one second translation value, The first region is a region composed of at least one row of 1st-x1 rows and 1st-y2 columns of the base matrix, and the second region is a region composed of 1st-x1 rows and 1st-y2 columns of the base matrix, except for the region occupied by the first region, or the second region is all regions of the base matrix except for the first region, Or, The first region is a region composed of at least one row of x1+1-X rows and 1st-y2 columns of the base matrix, and the second region is a region composed of x1+1-X rows and 1st-y2 columns of the base matrix, except for the region occupied by the first region, or the second region is all regions of the base matrix except for the first region, Wherein, 1 14. The method according to any one of claims 1 to 13, characterized in that, The base matrix includes X rows and Y columns, wherein, A region composed of x1+1-X rows and y2+1-Y columns of the base matrix corresponds to an identity matrix, A region composed of 1st-x1 rows and y2+1-Y columns of the base matrix corresponds to an all-0 matrix, A region composed of 1st-x1 rows and y1+1-y2 columns of the base matrix corresponds to a square matrix, Wherein, 1 15. The method according to any one of claims 1 to 8, characterized in that, The base matrix includes X rows and Y columns, the base matrix includes a first region and a second region, and a 1 element in the first region corresponds to a plurality of second translation values, and a 1 element in the second region corresponds to one second translation value, wherein, The first region is included in a third region, the third region is a region composed of 1st-x1 rows and y1+1-y2 columns of the base matrix, and the second region is a region of the base matrix except for the first region, And, The matrix corresponding to the region composed of the x1+1~Xth row and the y2+1~Yth column of the base matrix is a unit matrix, The matrix corresponding to the region composed of the 1~x1th row and the y2+1~Yth column of the base matrix is a full 0 matrix, The matrix corresponding to the third region is a square matrix, 1 16. The method of claim 15, wherein, The first region is the third region.

17. The method of claim 15, wherein, The first region is a region composed of the 1~x1th row and the first column of the base matrix, and the first column satisfies a first condition, and the first condition is that the corresponding column weight of the first column in the third region is an odd number greater than 1.

18. The method of any one of claims 1 to 8, wherein, The base matrix includes X rows and Y columns, the base matrix includes a first region and a second region, and the 1 element in the first region corresponds to a plurality of second translation values, and the 1 element in the second region corresponds to one second translation value, wherein, The first region is a region composed of all rows of the base matrix and the first column that satisfies a first condition in the y1+1~y2th column, the first condition is that the corresponding column weight of the first column in the third region is an odd number greater than 1, the third region is a region composed of the 1~x1th row and the y1+1~y2th column of the base matrix, and the second region is a region remaining in the base matrix except the first region, The matrix corresponding to the region composed of the x1+1~Xth row and the y2+1~Yth column of the base matrix is a unit matrix, The matrix corresponding to the region composed of the 1~x1th row and the y2+1~Yth column of the base matrix is a full 0 matrix, The matrix corresponding to the third region is a square matrix, 1 The a corresponding to the first set of lifting values is equal to a1, 19. The method of any one of claims 1 to 18, wherein, The lifting value in any of the predefined plurality of lifting value sets satisfies a x 2 k wherein different lifting value sets correspond to different a, each lifting value in a same lifting value set corresponds to a same a and different k, the k is an integer greater than or equal to 0, and the a is an integer greater than 1.

20. The method of claim 19, wherein, Any two second translation values in the plurality of second translation values of the first element, and k0 is a positive integer. a plurality of second translation values of the first element satisfy wherein, and The k0 corresponding to the plurality of predefined sets of lifting values is the same.

21. The method of claim 20, wherein, For any integer k1≥ k0, the plurality of second translation values of the first element further satisfy 22. The method of claim 20 or 21, wherein, k0=2 or 3 or 4 or 5, or the k0 is the smallest lifting value in the first set of lifting values.

23. The method of any one of claims 20-22, wherein, The communication device includes at least one processor and interface circuitry for receiving signals from other communication devices outside the communication device and transmitting signals to the processor or sending signals from the processor to other communication devices outside the communication device, and the processor is enabled to implement the method of any one of claims 1 to 23 through logic circuitry or execution of code instructions.

24. A communications device, characterized by The communication device is a chip or a chip system.

25. The communication apparatus according to claim 24, wherein, The storage medium stores a computer program or instructions, and when the computer program or instructions are executed, the method of any one of claims 1 to 23 is implemented.

26. A computer-readable storage medium, characterized in that, The computer program is executed to implement the method of any one of claims 1 to 23.

27. A computer program product, characterised in that, It includes:

28. A communication system, characterized by A sending end device for executing the method of any one of claims 1, or 3 to 23; A receiving end device for executing the method of any one of claims 2 to 23. ​ 29. A communications device, characterized by comprising at least one means for performing the method of any one of claims 1, or, 3 to 23; or, comprising at least one means for performing the method of any one of claims 2 to 23.

30. A processor, comprising: for performing the method of any one of claims 1, or, 3 to 23, or for performing the method of any one of claims 2 to 23.

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