Leakage compensation circuit, crystal oscillator circuit, and microprocessor chip

Abstract

A leakage compensation circuit (1101), a crystal oscillator circuit, and a microprocessor chip (1100). The leakage compensation circuit (1101) comprises: an IO module (100); a leakage compensation module (200), which comprises a source follower transistor (210) and a leakage current mirror transistor (220), wherein the source follower transistor (210) is electrically connected to an output end of the IO module (100) and is used for receiving and outputting a leakage current of the IO module (100), and the leakage current mirror transistor (220) is electrically connected to an output end of the source follower transistor (210) and is used for outputting a leakage compensation current on the basis of the leakage current of the IO module (100); and a crystal oscillator driving module (300), which is electrically connected to the output end of the IO module (100) and an output end of the leakage compensation module (200), and is used for receiving the leakage current and the leakage compensation current, and outputting a leakage compensation result on the basis of the leakage current and the leakage compensation current. The leakage compensation circuit can perform leakage compensation on an IO circuit, thereby ensuring the normal operation of the IO circuit.

Description

Leakage compensation circuit, crystal oscillator circuit and micro processing chip

[0001] The present application claims priority to the Chinese patent application No. 202410970978.4, filed on July 18, 2024, and entitled "Leakage compensation circuit, crystal oscillator circuit and micro processing chip", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of electronic technology, in particular to a leakage compensation circuit, a crystal oscillator circuit and a micro processing chip. BACKGROUND

[0003] The IO circuit needs to consider the driving capability design. Generally, the stronger the driving capability is, the larger the size of the IO driving tube will be. Although with the development of process characteristics, especially the application of short channel devices, the size of the IO driving tube is continuously reduced, but the leakage current of the short channel device at high temperature often has tens to hundreds of nA. This current will flow through the crystal oscillator feedback resistance of the IO circuit, and the size of the low-speed crystal oscillator feedback resistance is generally about 15MΩ-20MΩ. Therefore, the leakage current will cause the voltage drop across the feedback resistance to be too large, so that the working point of the crystal oscillator deviates from the normal working area, causing the problem of crystal oscillator not oscillating. SUMMARY

[0004] Therefore, the present application provides a leakage compensation circuit, a crystal oscillator circuit and a micro processing chip to compensate for the leakage of the IO circuit and ensure the normal operation of the IO circuit.

[0005] In a first aspect, the embodiments of the present application provide a leakage compensation circuit, which comprises:

[0006] an IO module;

[0007] a leakage compensation module comprising a source follower transistor and a leakage current mirror tube, the source follower transistor being electrically connected to the output end of the IO module for receiving and outputting the leakage current of the IO module, and the leakage current mirror tube being electrically connected to the output end of the source follower transistor for outputting a leakage compensation current based on the leakage current of the IO module;

[0008] a crystal oscillator driving module electrically connected to the output end of the IO module and the output end of the leakage compensation module for receiving the leakage current and the leakage compensation current and outputting a leakage compensation result based on the leakage current and the leakage compensation current.

[0009] The embodiments of the present application can compensate for the leakage of the leakage current of the IO module through the leakage compensation module to ensure the normal operation of the crystal oscillator driving module.

[0010] In some possible implementation manners, the IO module comprises:

[0011] a driving tube comprising a first transistor and a second transistor connected in series;

[0012] a leakage compensation tube connected in parallel with the driving tube, configured to obtain a leakage current of the driving tube and process the leakage current of the driving tube according to a preset proportion to obtain a leakage current of the IO module.

[0013] The leakage current of the driving tube is processed by the leakage compensation tube, so that the current loss in the subsequent circuit can be reduced, and the leakage compensation current can be fine-tuned subsequently, and the leakage compensation accuracy is ensured.

[0014] In some possible implementation manners, the specific connection relationship of the first transistor and the second transistor connected in series is that a first end of the first transistor is electrically connected with an external power supply, a control end of the first transistor is electrically connected with the first end of the first transistor, a second end of the first transistor is electrically connected with a first end of the second transistor, and a control end of the second transistor and a second end of the second transistor are grounded.

[0015] In the embodiment of the application, the first transistor is M1 in FIG. 3, and the second transistor is M2 in FIG. 3.

[0016] In some possible implementation manners, the leakage compensation tube comprises:

[0017] a third transistor, a first end of the third transistor is electrically connected with the external power supply, a control end of the third transistor is electrically connected with the first end of the third transistor, and a second end of the third transistor is electrically connected with a first input end of the leakage compensation module; the third transistor is configured to obtain a leakage current of the first transistor and process the leakage current of the first transistor according to a first preset proportion to obtain a first leakage current of the IO module;

[0018] a fourth transistor, a first end of the fourth transistor is electrically connected with a second input end of the leakage compensation module, a control end of the fourth transistor and a second end of the fourth transistor are grounded; the fourth transistor is configured to obtain a leakage current of the second transistor and process the leakage current of the second transistor according to a second preset proportion to obtain a second leakage current of the IO module.

[0019] In the embodiment of the application, the third transistor is M3 in FIG. 3, the fourth transistor is M4 in FIG. 3, and the drain-source voltage of M3 is equal to that of M1, and the drain-source voltage of M4 is equal to that of M1.

[0020] In some possible implementation manners, the source follower transistor comprises:

[0021] The fifth transistor has a first end electrically connected with the first input end of the leakage current mirror tube, a control end electrically connected with the input end of the crystal oscillator driving module, and a second end electrically connected with the second output end of the IO module; the fifth transistor is configured to receive and output the second leakage current of the IO module.

[0022] The sixth transistor has a first end electrically connected with the first output end of the IO module, a control end electrically connected with the input end of the crystal oscillator driving module, and a second end electrically connected with the second input end of the leakage current mirror tube; the sixth transistor is configured to receive and output the first leakage current of the IO module.

[0023] In the embodiments of the present application, the fifth transistor is M5 in FIG. 3, and the sixth transistor is M6 in FIG. 3; the gate-source voltage of M5 and M6 can be ignored.

[0024] According to the source follower transistor, the current and voltage loss can be reduced, the consistency of input and output current and voltage can be ensured, the current loss can be reduced by the leakage current mirror tube for leakage compensation, the chip area can be reduced, and the cost can be reduced.

[0025] In some possible implementation manners, the leakage current mirror tube comprises:

[0026] The seventh transistor has a first end electrically connected with an external power supply, a control end electrically connected with a second end of the seventh transistor, and the second end electrically connected with the first end of the fifth transistor.

[0027] The eighth transistor has a first end electrically connected with the external power supply, a control end electrically connected with the control end of the seventh transistor, and a second end electrically connected with the input end of the crystal oscillator driving module.

[0028] The ninth transistor has a first end electrically connected with the second end of the sixth transistor, a control end electrically connected with the first end of the ninth transistor, and a second end grounded.

[0029] The tenth transistor has a first end electrically connected with the input end of the crystal oscillator driving module, a control end electrically connected with the control end of the ninth transistor, and a second end grounded.

[0030] The seventh transistor and the eighth transistor are configured to output a second leakage compensation current based on a second leakage current of the IO module.

[0031] The ninth transistor and the tenth transistor are configured to output a first leakage compensation current based on a first leakage current of the IO module.

[0032] In the embodiments of the present application, the seventh transistor is M7 in FIG. 3, the eighth transistor is M8 in FIG. 3, the ninth transistor is M9 in FIG. 3, and the tenth transistor is M10 in FIG. 3. The current mirror composed of M7 and M8 can absorb the leakage current of M2, and the current mirror composed of M9 and M10 can absorb the leakage current of M1, so that the leakage current does not affect the normal operation of the crystal oscillator driving module.

[0033] In some possible implementation manners, the circuit further includes:

[0034] A resistance trimming circuit is arranged at the first end of the eighth transistor and / or the second end of the tenth transistor, and the resistance trimming circuit is configured to adjust the leakage compensation current output by the leakage compensation module.

[0035] The embodiments of the present application adjust the leakage compensation current output by the leakage compensation module by controlling the resistance value of the resistance trimming circuit, thereby improving the leakage compensation accuracy.

[0036] In some possible implementation manners, the resistance trimming circuit includes a plurality of resistors connected in series, when the resistance trimming circuit is arranged at the first end of the eighth transistor, the first end and the second end of each resistor are electrically connected to the external power supply through a short-circuit switch, and the connection ends of adjacent two resistors share one short-circuit switch.

[0037] When the resistance trimming circuit is arranged at the second end of the tenth transistor, the first end and the second end of each resistor are grounded through a short-circuit switch, and the connection ends of adjacent two resistors share one short-circuit switch.

[0038] The embodiments of the present application can improve the resistance change accuracy by adjusting the number of resistors, the resistance value, and the like, thereby improving the leakage compensation accuracy.

[0039] In some possible implementation manners, the resistance trimming circuit includes a plurality of resistors connected in series, and one short-circuit switch is connected in parallel to each resistor, and the short-circuit switch is configured to short-circuit the resistor corresponding to the short-circuit switch.

[0040] The embodiments of the present application can improve the resistance change accuracy by adjusting the number of resistors, the resistance value, and the like, thereby improving the leakage compensation accuracy.

[0041] In some possible implementation manners, the circuit further includes:

[0042] The eleventh transistor includes N eleventh sub-transistors, first ends of the N eleventh sub-transistors are electrically connected with the external power supply, control ends of the N eleventh sub-transistors are electrically connected with the control end of the seventh transistor, and second ends of the N eleventh sub-transistors are electrically connected with the input end of the crystal oscillator driving module through corresponding first switches; and the eleventh transistor is configured to adjust the second leakage compensation current output by the leakage compensation module.

[0043] The twelfth transistor includes N twelfth sub-transistors, first ends of the N twelfth sub-transistors are electrically connected with the input end of the crystal oscillator driving module through corresponding second switches, control ends of the N twelfth sub-transistors are electrically connected with the control end of the ninth transistor, and second ends of the N twelfth sub-transistors are grounded; and the twelfth transistor is configured to adjust the first leakage compensation current output by the leakage compensation module.

[0044] In the embodiments of the present application, the eleventh sub-transistors are MP1, MP2, MP3, and the twelfth sub-transistors are MN1, MN2, MN3 in FIG. 8, the first switches are S21, S22, S23 in FIG. 8, and the second switches are S21', S22', S23' in FIG. 8.

[0045] In the embodiments of the present application, the leakage compensation current output by the current mirror is adjusted, the leakage compensation precision is improved, and compared with other modes, the current mirror can reduce the circuit area and reduce the cost.

[0046] In some possible implementation manners, the first switch and the second switch are mutually exclusive switches.

[0047] In some possible implementation manners, the crystal oscillator driving module includes a comparator, a first input end of the comparator is electrically connected with an output end of the IO module and an output end of the leakage compensation module, configured to receive the leakage current and the leakage compensation current, and obtain a first voltage based on the leakage current and the leakage compensation current, a second input end of the comparator is configured to obtain a reference voltage, and the comparator is configured to compare the first voltage with the reference voltage, and output a leakage compensation result according to a comparison result.

[0048] In some possible implementation manners, the circuit further includes:

[0049] a logic module, a first input end of the logic module is electrically connected with an output end of the comparator, a second input end of the logic module is used for receiving a preset clock signal, and an output end of the logic module is electrically connected with a control circuit of the first switch and the second switch, the logic module is used for outputting a control signal according to the comparison result and the preset clock signal, and the control signal is used for controlling the control circuit to perform switch control on the first switch and the second switch.

[0050] The embodiments of the present application associate the result of the comparator with the controller, so that the leakage compensation circuit can automatically adjust the size of the leakage compensation current without human intervention, and the program can be executed when the chip is powered on, so that the leakage compensation current can be adjusted in time, without affecting the normal work of the crystal oscillator.

[0051] In a second aspect, the embodiments of the present application provide a crystal oscillator circuit, including the leakage compensation circuit of any one of the first aspect, wherein the crystal oscillator circuit further includes:

[0052] a crystal oscillator, a first end of the crystal oscillator is electrically connected with a first input end of the comparator, and a second end of the crystal oscillator is electrically connected with a second input end of the comparator;

[0053] a feedback resistor, a first end of the feedback resistor is electrically connected with the first input end of the comparator, and a second end of the feedback resistor is electrically connected with the second input end of the comparator;

[0054] an inverter, the inverter is connected in parallel with the crystal oscillator;

[0055] a first capacitor, a first end of the first capacitor is electrically connected with the first end of the crystal oscillator, and a second end of the first capacitor is grounded;

[0056] a second capacitor, a first end of the second capacitor is electrically connected with the second end of the crystal oscillator, and a second end of the second capacitor is grounded.

[0057] In a third aspect, the embodiments of the present application provide a micro-processing chip, including the leakage compensation circuit of any one of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0059] FIG. 1 is a circuit block diagram of a leakage compensation circuit provided by the embodiments of the present application;

[0060] Fig. 2 is a circuit block diagram of another leakage compensation circuit according to an embodiment of the present application;

[0061] Fig. 3 is a circuit structure diagram of a leakage compensation circuit according to an embodiment of the present application;

[0062] Fig. 4 is a circuit structure diagram of another leakage compensation circuit according to an embodiment of the present application;

[0063] Fig. 5 is a circuit structure diagram of another leakage compensation circuit according to an embodiment of the present application;

[0064] Fig. 6 is a circuit structure diagram of a resistance fine-tuning circuit according to an embodiment of the present application;

[0065] Fig. 7 is a circuit structure diagram of another resistance fine-tuning circuit according to an embodiment of the present application;

[0066] Fig. 8 is a circuit structure diagram of another leakage compensation circuit according to an embodiment of the present application;

[0067] Fig. 9 is a circuit structure diagram of another leakage compensation circuit according to an embodiment of the present application;

[0068] Fig. 10 is a circuit structure diagram of a crystal oscillator circuit according to an embodiment of the present application;

[0069] Fig. 11 is a structure block diagram of a micro-processing chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0070] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0071] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0072] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0073] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0074] It should be understood that in the following description, "circuitry" refers to an electrical circuit comprising at least one element or sub-circuitry constructed by electrical or electromagnetic connections. When an element or circuit is said to be "connected to" another element or said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be intermediate elements, and the connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0075] In this application, a transistor is a transistor working in a linear mode to provide a current path, including one selected from a bipolar transistor or a field effect transistor. The first end and the second end of the transistor are the high potential end and the low potential end on the current path, respectively, and the control end is used to receive a driving signal to control the voltage drop of the transistor. The transistor can be a P-type MOSFET or an N-type MOSFET. The first end, the second end and the control end of the P-type MOSFET are the source, the drain and the gate, respectively, and the first end, the second end and the control end of the N-type MOSFET are the drain, the source and the gate, respectively.

[0076] The IO circuit needs to consider the driving capability design. Generally, the stronger the driving capability is, the larger the size of the IO driving tube will be. Although with the development of process characteristics, especially the application of short channel devices, the size of the IO driving tube is continuously reduced, but the leakage current of the short channel device at high temperature is often several tens to hundreds of nA. This current will flow through the feedback resistance of the crystal oscillator of the IO circuit, and the size of the low-speed crystal oscillator feedback resistance is generally about 15MΩ-20MΩ. Therefore, the leakage current will cause the voltage drop across the feedback resistance to be too large, so that the working point of the crystal oscillator deviates from the normal working area, causing the problem of the crystal oscillator not oscillating.

[0077] In view of the above problems, the embodiments of the present application provide a leakage compensation circuit and a micro processing chip. The leakage compensation circuit can compensate the leakage of the IO module and ensure the normal working of the crystal oscillator.

[0078] The following will be described with reference to the accompanying drawings.

[0079] Referring to FIG. 1, a circuit block diagram of a leakage compensation circuit is provided in an embodiment of the present application. As shown in FIG. 1, the leakage compensation circuit includes an IO module 100, a leakage compensation module 200, and a crystal oscillator driving module 300. The output terminal of the IO module 100 is electrically connected to the input terminal of the leakage compensation module 200 and the input terminal of the crystal oscillator driving module 300. The output terminal of the leakage compensation module 200 is electrically connected to the input terminal of the crystal oscillator driving module 300. In the working process of the leakage compensation circuit, the leakage compensation module 200 is configured to receive the leakage current of the IO module 100 and output a leakage compensation current based on the leakage current of the IO module 100. The crystal oscillator driving module 300 is configured to receive the leakage current and the leakage compensation current and output a leakage compensation result based on the leakage current and the leakage compensation current.

[0080] The circuits in FIG. 1 are described in detail below.

[0081] Referring to FIG. 2, a circuit block diagram of another leakage compensation circuit is provided in an embodiment of the present application. As shown in FIG. 2, the IO module 100 includes a driving tube 110 and a leakage compensation tube 120. The leakage compensation tube 120 is connected in parallel to the driving tube 110, configured to obtain the leakage current of the driving tube 110, and process the leakage current of the driving tube 110 according to a preset ratio to obtain the leakage current of the IO module 100.

[0082] In some possible implementation manners, as shown in FIG. 3, the driving tube 110 includes a first transistor M1 and a second transistor M2 connected in series. Specifically, the first end of the first transistor M1 is electrically connected to an external power supply. The control terminal of the first transistor M1 is electrically connected to the first end of the first transistor M1. The second end of the first transistor M1 is electrically connected to the first end of the second transistor M2. The control terminal of the second transistor M2 and the second end of the second transistor M2 are grounded. In specific implementation, the first transistor M1 and the second transistor M2 are electro-static discharge (ESD) tubes.

[0083] In some possible implementation manners, as shown in FIG. 3, the leakage compensation tube 120 includes a third transistor M3 and a fourth transistor M4. Specifically, the first end of the third transistor M3 is electrically connected to an external power supply. The control terminal of the third transistor M3 is electrically connected to the first end of the third transistor M3. The second end of the third transistor M3 serves as the first output terminal of the IO module 100 and is electrically connected to the first input terminal of the leakage compensation module 200. The first end of the fourth transistor M4 serves as the second output terminal of the IO module 100 and is electrically connected to the second input terminal of the leakage compensation module 200. The control terminal of the fourth transistor M4 and the second end of the fourth transistor M4 are grounded.

[0084] In specific implementation, the third transistor M3 is configured to obtain the leakage current I of the first transistor M1. The fourth transistor M4 is configured to obtain the leakage current I of the second transistor M2.leakM1 and the drain current of the first transistor M1 is reduced by a first preset ratio to obtain a first leakage current I leakM3 ; the fourth transistor M4 is configured to obtain a drain current I leakM2 of the second transistor M2, and the drain current of the second transistor M2 is reduced by a second preset ratio to obtain a second leakage current I leakM4 .

[0085] In the embodiments of the present application, the first transistor M1 and the third transistor M3, and the second transistor M2 and the fourth transistor M4 have the same device size and different numbers (m), for example, the number m of the first transistor M1 is a, the number m of the second transistor M2 is b, and so on.

[0086] In specific implementations, since the drain-source voltages Vds of the first transistor M1 and the third transistor M3 are equal, and the drain-source voltages Vds of the second transistor M2 and the fourth transistor M4 are equal, the first preset ratio is the number ratio of the third transistor M3 to the first transistor M1, and the second preset ratio is the number ratio of the fourth transistor M4 to the second transistor M2. For example, as shown in FIG. 3, the first preset ratio can be 1 / a, that is, I leakM3 / I leakM1 a, and the second preset ratio can be 1 / b, that is, I leakM4 / I leakM2 b.

[0087] Please continue to refer to FIG. 2. As shown in FIG. 2, the leakage compensation tube 120 includes a source follower transistor 210 and a leakage current mirror tube 220, wherein the source follower transistor 210 is electrically connected to the output end of the IO module 100, configured to receive and output the leakage current of the IO module 100, and the leakage current mirror tube 220 is electrically connected to the output end of the source follower transistor 210, configured to output a leakage compensation current based on the leakage current of the IO module 100.

[0088] In some possible implementation manners, as shown in FIG. 3, the source follower transistor 210 includes a fifth transistor M5 and a sixth transistor M6, wherein a first end of the fifth transistor M5 is electrically connected to a first input end of the leakage current mirror tube 220 as a first output end of the source follower transistor 210, a control end of the fifth transistor M5 is electrically connected to an input end of the crystal oscillator driving module 300, a second end of the fifth transistor M5 is electrically connected to a second output end of the IO module 100 as a second input end of the leakage compensation module 200, and the fifth transistor M5 is configured to receive and output a second leakage current of the IO module 100; a first end of the sixth transistor M6 is electrically connected to a first output end of the IO module 100 as a first input end of the leakage compensation module 200, a control end of the sixth transistor M6 is electrically connected to the input end of the crystal oscillator driving module 300, a second end of the sixth transistor M6 is electrically connected to a second input end of the leakage current mirror tube 220 as a second output end of the source follower transistor 210, and the sixth transistor M6 is configured to receive and output a first leakage current of the IO module 100.

[0089] In some possible implementation manners, as shown in FIG. 3, the leakage current mirror tube 220 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10, wherein a first end of the seventh transistor M7 is electrically connected to an external power supply, a control end of the seventh transistor M7 is electrically connected to a second end of the seventh transistor M7, the second end of the seventh transistor M7 is electrically connected to the first end of the fifth transistor as a first input end of the leakage current mirror tube 220; a first end of the eighth transistor M8 is electrically connected to the external power supply, a control end of the eighth transistor M8 is electrically connected to the control end of the seventh transistor M7, and a second end of the eighth transistor M8 is electrically connected to the input end of the crystal oscillator driving module 300 as a first output end of the leakage current mirror tube 220; a first end of the ninth transistor M9 is electrically connected to the second end of the sixth transistor M6 as a second input end of the leakage current mirror tube 220, a control end of the ninth transistor M9 is electrically connected to the first end of the ninth transistor M9, and a second end of the ninth transistor M9 is grounded; a first end of the tenth transistor M10 is electrically connected to the input end of the crystal oscillator driving module 300 as a second output end of the leakage current mirror tube 220, a control end of the tenth transistor M10 is electrically connected to the control end of the ninth transistor M9, and a second end of the tenth transistor M10 is grounded.

[0090] In specific implementation, the seventh transistor M7 and the eighth transistor M8 are configured to output a second leakage compensation current based on the second leakage current of the IO module 100, and the ninth transistor M9 and the tenth transistor M10 are configured to output a first leakage compensation current based on the first leakage current of the IO module 100.

[0091] In the embodiment of the present application, since the width-length ratios of the seventh transistor M7, the eighth transistor M8, the ninth transistor M9 and the tenth transistor M10 are large, the leakage current is in the order of nA, and the gate-source voltage Vgs of the fifth transistor M5 and the sixth transistor M6 can be ignored, so that LEAKP = LEAKN = Xin, where LEAKP is the voltage signal of the third transistor M3, LEAKN is the voltage signal of the fourth transistor M4, and Xin is the input voltage signal of the crystal oscillator driving module 300. Meanwhile, the drain-source voltage Vds of the first transistor M1 and the third transistor M3, and the second transistor M2 and the fourth transistor M4 are consistent. Here, the first transistor M1 is taken as an example of PMOS transistor leakage, at this time, the third transistor M3 and the sixth transistor M6 are PMOS transistors, and the ninth transistor M9 and the tenth transistor M10 are NMOS transistors, as shown in FIG. 3. Specifically, since the Vds voltages of the first transistor M1 and the third transistor M3 are equal, the first leakage current I leakM3 = I leakM1 / a, the first leakage current I leakM3 flows into the ninth transistor M9 after passing through the sixth transistor M6, and the ninth transistor M9 and the tenth transistor M10 form an NMOS current mirror, so that the first leakage current I leakM3 passes through the NMOS current mirror to obtain a times mirror current to the Xin port. The a times mirror current is the first leakage compensation current, that is, the PMOS leakage of the IO module 100 on the Xin port is completely absorbed by the NMOS current mirror of the leakage compensation module 200. Similarly, the leakage of the NMOS transistor (the second transistor M2) of the IO module 100 is also absorbed by the PMOS current mirror of the leakage compensation module 200, so that the leakage does not affect the normal operation of the crystal oscillator.

[0092] Please continue to refer to FIG. 2. As shown in FIG. 2, the crystal oscillator driving module 300 includes a comparator 310, wherein the first input terminal of the comparator 310 is electrically connected with the output terminal of the IO module 100 and the output terminal of the leakage compensation module 200, for receiving the leakage current and the leakage compensation current, and obtaining the first voltage Xin based on the leakage current and the leakage compensation current. Specifically, the first input terminal of the comparator 310 is electrically connected with the output terminal of the driving tube 110, the output terminal of the leakage compensation tube 120 and the output terminal of the leakage current mirror tube 220, to obtain the first voltage Xin based on the electrical signals output by the driving tube 110, the leakage compensation tube 120 and the leakage current mirror tube 220. The second input terminal of the comparator 310 is used to obtain a reference voltage Xout. In a specific implementation, the comparator 310 is used to compare the first voltage Xin with the reference voltage Xout, and output a leakage compensation result according to the comparison result.

[0093] In some possible implementation, as shown in FIG. 3, the crystal oscillator driving module 300 further includes a feedback resistor Rf, a thirteenth transistor M11 and a fourteenth transistor M12, wherein a first end of the feedback resistor Rf is electrically connected with a first input end of the comparator 310, a second end of the feedback resistor Rf is electrically connected with a second input end of the comparator 310, a first end of the thirteenth transistor M11 is connected with a voltage source, a control end of the thirteenth transistor M11 is electrically connected with a control signal PB, a second end of the thirteenth transistor M11 is electrically connected with a first end of the fourteenth transistor M12, a control end of the fourteenth transistor M12 is electrically connected with the first end of the feedback resistor Rf, and a second end of the fourteenth transistor M12 is grounded. In a specific implementation, the thirteenth transistor M11 and the fourteenth transistor M12 are combined to be equivalent to an inverter, to provide a phase difference for oscillation of the crystal oscillator driving module 300, and the feedback resistor Rf is configured to ensure that the reference voltage Xout is a certain value.

[0094] In the embodiment of the present application, when the input port of the crystal oscillator driving module 300 has a leakage but no leakage compensation, a current will flow through the feedback resistor Rf, so that the voltage Xin and the voltage Xout generate a voltage deviation, wherein when the leakage of the first transistor M1 (PMOS transistor) is greater than the leakage of the second transistor M2 (NMOS), the voltage Xin > the voltage Xout, the output signal DET OUT of the comparator 310 = 1, and when the leakage of the first transistor M1 (PMOS transistor) is less than the leakage of the second transistor M2 (NMOS), the voltage Xin < the voltage Xout, the output signal DET OUT of the comparator 310 = 0, thus, the leakage of the IO module 100 can be determined by the output of the comparator 310 of the crystal oscillator driving module 300. When the input port of the crystal oscillator driving module 300 has leakage compensation, the leakage compensation result can be determined according to the DET OUT, if the DET OUT = 1, it is considered that the leakage absorption of the first transistor M1 (PMOS transistor) is insufficient, if the DET OUT = 0, it is considered that the leakage absorption of the second transistor M2 (NMOS) is insufficient. Generally, when the value of the DET OUT jumps from 1 to 0 or from 0 to 1, it is considered that the leakage of the first transistor M1 (PMOS transistor) and the leakage of the second transistor M2 (NMOS) are well absorbed, at this time, the leakage of the first transistor M1 (PMOS transistor) and the leakage of the second transistor M2 (NMOS) will not affect the work of the crystal oscillator driving module 300.

[0095] Referring to FIG. 4, another circuit structure schematic diagram of a leakage compensation circuit provided by an embodiment of the present application is shown. As shown in FIG. 4, on the basis of the circuit structure shown in FIG. 3, a resistance trimming circuit RT (RES_TRIM) 230 is arranged at the second end of the tenth transistor M10 in the embodiment of the present application, and the RT 230 is used to adjust the first leakage compensation current output by the leakage compensation module 200, so as to make the output first leakage compensation current more accurate.

[0096] In a possible implementation, the RT 230 can also be arranged at the first end of the eighth transistor M8, and used to adjust the second leakage compensation current output by the leakage compensation module 200, so as to make the output second leakage compensation current more accurate, as shown in FIG. 5.

[0097] In another possible implementation, the RT 230 can also be arranged at the first end of the eighth transistor M8 and the second end of the tenth transistor M10 at the same time, and used to adjust the first leakage compensation current and the second leakage compensation current output by the leakage compensation module 200.

[0098] In the embodiment of the present application, taking the leakage of the second transistor M2 (NMOS transistor) of the IO module 100 as an example, since the Vds voltage of the second transistor M2 is equal to that of the fourth transistor M4, the second leakage current I leakM4 = I leakM2 / b, and after the fourth transistor M4 current passes through the fifth transistor M5, all the current will flow into the seventh transistor M7, and the seventh transistor M7 and the eighth transistor M8 form a PMOS current mirror, so the second leakage current I leakM4 After passing through the PMOS current mirror, a b times mirror current is obtained to the XIN port, and the b times mirror current is the second leakage compensation current, that is, the NMOS leakage of the IO module 100 on the Xin port is all absorbed by the PMOS current mirror of the leakage compensation module 200, when the RT 230 arranged at the second end of the eighth transistor M8 is equal to 0 (R RT = 0), at this time, the second leakage compensation current is b+2 times, and when the RT 230 is adjusted to increase, the leakage compensation of the eighth transistor M8 gradually decreases, so that the b times current which can exactly compensate the NMOS leakage of the IO module 100 can be obtained by adjustment, so that the NMOS leakage of the IO module 100 is absorbed, thereby not affecting the normal work of the crystal oscillator. The PMOS leakage of the IO module 100 is compensated by the tenth transistor M10 in the same way, when R RT = 0, at this time, the compensation leakage is a+2 times, and when the RT is adjusted to increase, the leakage compensation of the tenth transistor M10 gradually decreases, so that the a times current which can exactly compensate the PMOS leakage of the IO module 100 can be obtained by adjustment, so that the PMOS leakage of the IO module 100 is all absorbed, thereby not affecting the normal work of the crystal oscillator.

[0099] In a possible implementation, the RT 230 includes a plurality of resistors connected in series. In specific implementation, when the RT 230 is arranged at the first end of the eighth transistor M8, the first end and the second end of each resistor are electrically connected to an external power supply through a shorting switch, and the connection ends of adjacent two resistors share a shorting switch; when the RT 230 is arranged at the second end of the tenth transistor M10, the first end and the second end of each resistor are grounded through a shorting switch, and the connection ends of adjacent two resistors share a shorting switch.

[0100] For example, when the RT 230 is arranged at the second end of the tenth transistor M10, as shown in FIG. 6, the RT 230 includes resistors R1, R2, …, R6 and R7 connected in series, wherein the second end of the resistor R1 is grounded through the switch S0, the first end of the resistor R1 and the second end of the resistor R2 are grounded through the switch S1, the first end of the resistor R2 and the second end of the resistor R3 are grounded through the switch S2, …, the first end of the resistor R6 and the second end of the resistor R7 are grounded through the switch S6, and the first end of the resistor R7 is grounded through the switch S7. In specific implementation, the switches S1 to S7 can be controlled by a controller, and according to the number of switches, a corresponding register is arranged in the controller, and the output value of the register is analyzed by a decoder to output the control signals of the switches S1 to S7. Here, according to the number of switches, the trim<2:0> mode is selected, when trim<2:0> = 000, the switch S7 is closed and the other switches are opened, at this time, the resistors R1, R2, …, R6 and R7 are all short-circuited, which is equivalent to that the second end of the tenth transistor M10 is directly grounded. Since the mirror drain current compensation of the NMOS current mirror composed of the ninth transistor M9 and the tenth transistor M10 is a+2 times, and the PMOS drain current of the IO module 100 is a times, the voltage Xin is pulled down, Xin < Xout, and DET_OUT = 0; when the code value of trim increases, the resistance gradually increases, and when it increases to a value that can just compensate a*I RT leakM3 , at this time, it is a critical value, assuming that the tenth transistor M10 works in the saturation region by parameter design, thus:

[0101] In formula (1), u n is the carrier mobility, C ox is the unit area capacitance of the gate and the channel, W4 is the width of the tenth transistor M10, L4 is the length of the tenth transistor M10, R RT ' is the critical resistance value, V th is the threshold voltage of the tenth transistor M10.

[0102] ​According to formula (1), when R RT =R RT ', Xin=Xout. When R RT >R RT ', the pull-up ability is strong, Xin>Xout, and DET_OUT=1. Therefore, the trim<2:0> can be adjusted from 000 to 111, and when DET_OUT changes from 0 to 1, the appropriate compensation current is obtained. The embodiment of the application can increase the number of resistors and registers to improve the resistance change precision and the current compensation precision. Similarly, referring to the embodiment shown in FIG. 6, the leakage compensation current output by the eighth transistor M8 can be adjusted to improve the current compensation precision.

[0103] The embodiment of the application can adjust the leakage compensation current in real time according to the change of the Xin voltage to ensure the precision of the leakage compensation current. Meanwhile, for the matching error of the transistors, for example, the mirror leakage compensation current of the NMOS current mirror composed of the ninth transistor M9 and the tenth transistor M10 should actually be a times, but due to the matching error of the devices, it becomes a+2 times, and the resistance trimming circuit can be used to adjust the compensation multiple to improve the current compensation precision.

[0104] In another possible implementation, the RT 230 includes a plurality of resistors connected in series, and a short-circuit switch is connected in parallel with each resistor, and the short-circuit switch is configured to short-circuit the resistor corresponding to the short-circuit switch.

[0105] For example, as shown in FIG. 7, the RT 230 includes resistors R1, R2,..., R6 and R7 connected in series, wherein the resistor R1 is connected in parallel with a short-circuit switch S11, the resistor R2 is connected in parallel with a short-circuit switch S12,..., the resistor R6 is connected in parallel with a short-circuit switch S16, and the resistor R7 is connected in parallel with a short-circuit switch S17. According to the number of switches, the trim<2:0> mode is selected. When trim<2:0>=000, the short-circuit switches S11 to S17 are all in the closed state, and the resistors R1, R2,..., R6 and R7 are all short-circuited, which is equivalent to that the second end of the tenth transistor M10 is directly connected to the ground. Since the mirror leakage compensation of the NMOS current mirror composed of the ninth transistor M9 and the tenth transistor M10 is a+2 times, and the PMOS leakage of the IO module 100 is a times, the voltage Xin is pulled down, XinXout, and DET_OUT=0. When the code value of the trim increases, R RT gradually increases (for example, trim<2:0>=001, the short-circuit switch S11 is opened), and when it increases to a value that can compensate a*I leakM3At this time, the critical value, assuming that the tenth transistor M10 through the parameter design, working in the saturation region, thus can be derived formula (1). According to formula (1) can be known when R RT = R RT ', Xin = Xout. And when R RT > R RT ', this time the pull-up ability, Xin > Xout, DET_OUT = 1. Therefore, can be adjusted by trimming adjustment trim <2:0> from 000 to 111, in the process, when you see DET_OUT from 0 to 1 can be obtained the appropriate compensation current. The present embodiment can be increased by adjusting the number of resistors, the number of registers and other ways to improve the accuracy of resistance changes, thereby improving the accuracy of current compensation. Similarly, can be referred to as the embodiment shown in Figure 7, adjust the eighth transistor M8 output leakage compensation current, improve the accuracy of current compensation.

[0106] The present embodiment relative to the way shown in Figure 6, can reduce the number of switches, reduce the cost of use.

[0107] In practical applications, in addition to the output accuracy of the leakage compensation current by adjusting the resistance, the leakage compensation current can also be adjusted by the transistor.

[0108] Referring to Figure 8, another leakage compensation circuit provided by the present embodiment of the circuit structure schematic diagram. As shown in Figure 8, the present embodiment in the circuit structure shown in Figure 3, in the leakage compensation module 200 module 240 is set, including the eleventh transistor MP and the twelfth transistor MN, to adjust the leakage compensation module 200 output leakage compensation current by the eleventh transistor MP and the twelfth transistor MN, so as to ensure the accuracy of leakage compensation.

[0109] Specifically, the eleventh transistor MP includes N eleventh sub-transistors, the first ends of the N eleventh sub-transistors are electrically connected with the external power supply, the control ends of the N eleventh sub-transistors are electrically connected with the control end of the seventh transistor M7, and the second ends of the N eleventh sub-transistors are electrically connected with the input end of the crystal oscillator driving module 300 through corresponding first switches; the eleventh transistor MP is configured to adjust the second leakage compensation current output by the leakage compensation module 200; the twelfth transistor MN includes N twelfth sub-transistors, the first ends of the N twelfth sub-transistors are electrically connected with the input end of the crystal oscillator driving module 300 through corresponding second switches, the control ends of the N twelfth sub-transistors are electrically connected with the control end of the ninth transistor M9, and the second ends of the N twelfth sub-transistors are grounded; the twelfth transistor MN is configured to adjust the first leakage compensation current output by the leakage compensation module 200. In a specific implementation, the first switch and the second switch are mutually exclusive switches, that is, when the first switch is 1, the second switch is 0, the first switch is turned on, and the second switch is turned off; when the first switch is 0, the second switch is 1, the first switch is turned off, and the second switch is turned on.

[0110] The embodiments of the present application can adjust the number of the eleventh sub-transistors and the twelfth sub-transistors of the access circuit by controlling the opening and closing of the first switch and the second switch, so as to adjust the size of the leakage compensation current output by the leakage compensation module 200.

[0111] As shown in FIG. 8, the eleventh transistor MP includes an eleventh sub-transistor MP1, an eleventh sub-transistor MP2, …, an eleventh sub-transistor MP14, and an eleventh sub-transistor MP15, wherein the second end of the eleventh sub-transistor MP1 is electrically connected to the input end of the crystal oscillator driving module 300 through the first switch S21, the second end of the eleventh sub-transistor MP2 is electrically connected to the input end of the crystal oscillator driving module 300 through the first switch S22, …, the second end of the eleventh sub-transistor MP14 is electrically connected to the input end of the crystal oscillator driving module 300 through the first switch S34, and the second end of the eleventh sub-transistor MP15 is electrically connected to the input end of the crystal oscillator driving module 300 through the first switch S35. The twelfth transistor MN includes a twelfth sub-transistor MN1, a twelfth sub-transistor MN2, …, a twelfth sub-transistor MN14, and a twelfth sub-transistor MN15, wherein the first end of the twelfth sub-transistor MN1 is electrically connected to the input end of the crystal oscillator driving module 300 through the second switch S21', the first end of the twelfth sub-transistor MN2 is electrically connected to the input end of the crystal oscillator driving module 300 through the second switch S22', …, the first end of the twelfth sub-transistor MN14 is electrically connected to the input end of the crystal oscillator driving module 300 through the second switch S34', and the first end of the twelfth sub-transistor MN15 is electrically connected to the input end of the crystal oscillator driving module 300 through the second switch S35'. Here, according to the number of switches, the trim<3:0> mode is selected, at this time, the value output by the register can be operated through the adder, and the control signal of the first switch and the second switch is controlled according to the operation result. Specifically, when trim<3:0> = 0000, the first switch S21-S35 = 0, and the second switch S21'-S35' = 1, at this time, the pull-up current of the Xin port is large, Xin < Xout, and DET_OUT = 0. Gradually increase the trim<3:0> register code value, then the output current of the twelfth transistor MN gradually decreases, and the output current of the eleventh transistor MP gradually increases. When the device matching error is not considered, when trim<3:0> = 1000, S21-S28 = 1, S29'-S35' = 1, then the PMOS and NMOS leakage of the IO module 100 is completely absorbed, and the ideal working state is reached. When trim<3:0> > 1000, the pull-up current of the Xin port is large, Xin > Xout, and DET_OUT = 1.

[0112] But in fact, due to the device matching error, the leakage compensation cannot reach the ideal state completely, and thus can only be judged by the change of the DET OUT signal output by the comparator. When the trim<3:0> changes from 0000 to 1111, if the DET OUT signal changes from 0 to 1 when the trim<3:0> is equal to a certain value, the leakage at this time reaches the minimum state and almost does not affect the working point of the crystal oscillator.

[0113] The embodiment of the present application can adjust the precision of the leakage compensation by increasing or decreasing the number of current mirrors, the number of registers, and the current size of the current mirror.

[0114] The embodiment of the present application adjusts the leakage compensation current output by the current mirror, which can reduce the circuit area and cost compared with other ways.

[0115] Referring to FIG. 9, it is a circuit structure schematic diagram of another leakage compensation circuit provided by the embodiment of the present application. As shown in FIG. 9, the embodiment of the present application adds a logic module 400 on the basis of the circuit structure shown in FIG. 8, wherein the first input end of the logic module 400 is electrically connected with the output end of the comparator 310, the second input end of the logic module 400 is used for receiving a preset clock signal CLK, and the output end of the logic module is electrically connected with the control circuit of the first switch and the second switch. In the specific implementation, the logic module 400 is used for outputting a control signal according to the comparison result output by the comparator 310 and the preset clock signal, and the control signal is used for controlling the control circuit to switch control the first switch and the second switch.

[0116] For example, the frequency of CLK is 1KHz, trim<3:0> is selected according to the number of switches. The initial state of trim<3:0> is 0000, and trim<3:0> is increased by one bit when a CLK rising edge sample (or falling edge sample) is received. When the DET_OUT signal is detected to change from 0 to 1, the output of trim<3:0> at this time is kept, so that it no longer changes with CLK. Since the first switch and the second switch are mutually exclusive switches, when trim<3:0> is 0000, the first switch S21-S35 is 0, and the second switch S21'-S35' is 1. At this time, the pull-down current of the Xin port is large, XinXout, and DET_OUT is 0. Gradually increasing the value of the trim<3:0> register, the output current of the twelfth transistor MN gradually decreases, and the output current of the eleventh transistor MP gradually increases. When the device matching error is not considered, when trim<3:0> is 1000, S21-S28 is 1, and S29'-S35' is 1. At this time, the PMOS and NMOS leakage of the IO module 100 is completely absorbed, and the ideal working state is reached. When trim<3:0> is greater than 1000, the pull-up current of the Xin port is large, XinXout, and DET_OUT is 1.

[0117] However, in actual situations, due to device matching errors, the leakage compensation cannot completely reach the ideal state, so the change of the DET_OUT signal output by the comparator can only be used for judgment. When trim<3:0> changes from 0000 to 1111, if the DET_OUT signal changes from 0 to 1 when trim<3:0> is equal to a certain value, the leakage at this time reaches the minimum state, and almost does not affect the working point of the crystal oscillator. The embodiment of the application can adjust the precision of leakage compensation by increasing or decreasing the number of current mirrors, the number of registers, and the size of the current mirror image.

[0118] The embodiment of the application associates the result of the comparator with the controller, so that the leakage compensation circuit can automatically adjust the size of the leakage compensation current without human intervention, and the program can be executed when the chip is powered on, so that the leakage compensation current can be adjusted in time without affecting the normal operation of the crystal oscillator.

[0119] It should be noted that the frequency of CLK can be adjusted according to actual needs, and the embodiment of the application does not make specific requirements.

[0120] It should be noted that in the above embodiments, the code values of trim<2:0> and trim<3:0> and the corresponding relationship between the code values and the control of the opening and closing of the switch can be set according to actual needs, and the embodiments of the present application do not make specific requirements thereon, for example, when trim<2:0> = 111, S7 is closed, when trim<3:0> = 0000, the first switch S21-S35 = 1, the second switch S21'-S35' = 0, and the like.

[0121] Corresponding to the above embodiments, the present application also provides a crystal oscillator circuit, including the leakage compensation circuit shown in FIGS. 1-9. Wherein, the circuit structure of the crystal oscillator circuit is shown in FIG. 10. Specifically, the crystal oscillator circuit adds a module 320 on the basis of the crystal oscillator driving module shown in FIGS. 1-9, including: a crystal oscillator Y1, an inverter I, a first capacitor C1 and a second capacitor C2, wherein the first end of the crystal oscillator Y1 is electrically connected with the first input end of the comparator 310, the second end of the crystal oscillator Y1 is electrically connected with the second input end of the comparator 310, the inverter I is connected in parallel with the crystal oscillator Y1, the first end of the first capacitor C1 is electrically connected with the first end of the crystal oscillator Y1, the second end of the first capacitor C1 is grounded, the first end of the second capacitor C2 is electrically connected with the second end of the crystal oscillator Y1, and the second end of the second capacitor C2 is grounded. In a specific implementation, the inverter I is used to provide a 180° phase difference for the crystal oscillator oscillation, and is arranged at the first input end and the second input end of the comparator 310, that is, the feedback resistor Rf connected in parallel with the crystal oscillator Y1 is used to provide negative feedback for the input pin of the crystal oscillator Y1, so as to ensure that the inverter I works in the high-gain linear region. The value of the feedback resistor Rf is selected according to the oscillation frequency of the crystal oscillator Y1.

[0122] Corresponding to the above embodiments, the present application also provides a micro processing chip.

[0123] Referring to FIG. 11, a structure block diagram of a micro processing chip provided by an embodiment of the present application is shown. As shown in FIG. 11, the micro processing chip 1100 includes a leakage compensation circuit 1101. Wherein, the specific content of the leakage compensation circuit 1101 can be referred to the description of the above embodiments, and for the sake of brief description, it will not be repeated here.

[0124] In a specific implementation, the micro processing chip can be a control module, a micro control unit (MCU), a digital signal processor (DSP), a micro processor (MPU), a micro CPU, and the like, which is a micro central control chip, a system on chip, capable of processing digital signals, analog signals, or playing a signal control function, instruction processing and operation, and the like.

[0125] Corresponding to the above-mentioned embodiments, the embodiments of the present application further provide a computer-readable storage medium, wherein the computer-readable storage medium can store a program, wherein when the program is running, the computer-readable storage medium can control the device where the computer-readable storage medium is located to execute part or all steps of the above-mentioned method embodiments. In a specific implementation, the computer-readable storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM) and the like.

[0126] Corresponding to the above-mentioned embodiments, the embodiments of the present application further provide a computer program product, which contains executable instructions, when the executable instructions are executed on a computer, the computer executes part or all steps of the above-mentioned method embodiments.

[0127] In the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the cases of A alone, A and B together, and B alone. Wherein A and B can be singular or plural. The character " / " generally represents that the associated objects before and after are in an "or" relationship. "At least one of the following" and the like expressions mean any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, and c can be single or multiple.

[0128] Those of ordinary skill in the art can realize that the units and algorithm steps described in the embodiments disclosed herein can be realized in electronic hardware, computer software and a combination of electronic hardware and computer software. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of the present application.

[0129] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-mentioned system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0130] In several embodiments provided by the embodiments of the present application, any function if realized in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application essentially or in other words, the part of the prior art that makes a contribution or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0131] The above is only a specific implementation of the embodiments of the present application. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the embodiments of the present application, which should be covered within the protection scope of the embodiments of the present application. The protection scope of the embodiments of the present application should be subject to the protection scope of the claims.

Claims

1. A leakage compensation circuit, characterized by, The circuit comprises: an IO module; a leakage compensation module comprising a source follower transistor and a leakage current mirror tube, the source follower transistor being electrically connected to an output end of the IO module, configured to receive and output a leakage current of the IO module, the leakage current mirror tube being electrically connected to an output end of the source follower transistor, configured to output a leakage compensation current based on the leakage current of the IO module; a crystal oscillator driving module electrically connected to the output end of the IO module and the output end of the leakage compensation module, configured to receive the leakage current and the leakage compensation current, and output a leakage compensation result based on the leakage current and the leakage compensation current.

2. The leakage compensation circuit according to claim 1, characterized by, The IO module comprises: a driving tube comprising a first transistor and a second transistor connected in series; a leakage compensation tube connected in parallel with the driving tube, configured to obtain a leakage current of the driving tube, and process the leakage current of the driving tube according to a preset ratio to obtain a leakage current of the IO module.

3. The leakage compensation circuit of claim 2, wherein, The leakage compensation tube comprises: a third transistor, a first end of the third transistor being electrically connected to an external power supply, a control end of the third transistor being electrically connected to the first end of the third transistor, and a second end of the third transistor being electrically connected to a first input end of the leakage compensation module; the third transistor is configured to obtain a leakage current of the first transistor, and process the leakage current of the first transistor according to a first preset ratio to obtain a first leakage current of the IO module; a fourth transistor, a first end of the fourth transistor being electrically connected to a second input end of the leakage compensation module, a control end of the fourth transistor and a second end of the fourth transistor being grounded; the fourth transistor is configured to obtain a leakage current of the second transistor, and process the leakage current of the second transistor according to a second preset ratio to obtain a second leakage current of the IO module.

4. The leakage compensation circuit of claim 1, wherein, The source follower transistor comprises: a fifth transistor, a first end of the fifth transistor being electrically connected to a first input end of the leakage current mirror tube, a control end of the fifth transistor being electrically connected to an input end of the crystal oscillator driving module, and a second end of the fifth transistor being electrically connected to a second output end of the IO module; the fifth transistor is configured to receive and output the second leakage current of the IO module; a sixth transistor, a first end of the sixth transistor being electrically connected to a first output end of the IO module, a control end of the sixth transistor being electrically connected to the input end of the crystal oscillator driving module, and a second end of the sixth transistor being electrically connected to a second input end of the leakage current mirror tube; the sixth transistor is configured to receive and output the first leakage current of the IO module.

5. The leakage compensation circuit according to claim 4, characterized in that, The leakage current mirror tube comprises: a seventh transistor, a first end of the seventh transistor being electrically connected to an external power supply, a control end of the seventh transistor being electrically connected to a second end of the seventh transistor, and the second end of the seventh transistor being electrically connected to the first end of the fifth transistor; an eighth transistor, a first end of the eighth transistor being electrically connected with the external power supply, a control end of the eighth transistor being electrically connected with the control end of the seventh transistor, and a second end of the eighth transistor being electrically connected with the input end of the crystal oscillator driving module; a ninth transistor, a first end of the ninth transistor being electrically connected with the second end of the sixth transistor, a control end of the ninth transistor being electrically connected with the first end of the ninth transistor, and a second end of the ninth transistor being grounded; a tenth transistor, a first end of the tenth transistor being electrically connected with the input end of the crystal oscillator driving module, a control end of the tenth transistor being electrically connected with the control end of the ninth transistor, and a second end of the tenth transistor being grounded; wherein the seventh transistor and the eighth transistor are configured to output a second leakage compensation current based on a second leakage current of the IO module; the ninth transistor and the tenth transistor are configured to output a first leakage compensation current based on a first leakage current of the IO module.

6. The leakage compensation circuit according to claim 5, wherein The circuit further comprises: a resistance trimming circuit, the resistance trimming circuit being arranged at the first end of the eighth transistor and / or the second end of the tenth transistor, and the resistance trimming circuit being configured to adjust the leakage compensation current output by the leakage compensation module.

7. The leakage compensation circuit according to claim 6, characterized in that, The resistance trimming circuit comprises a plurality of resistors connected in series, when the resistance trimming circuit is arranged at the first end of the eighth transistor, the first end and the second end of each resistor are electrically connected with the external power supply through a short-circuit switch, and the connection ends of adjacent two resistors share one short-circuit switch; when the resistance trimming circuit is arranged at the second end of the tenth transistor, the first end and the second end of each resistor are grounded through a short-circuit switch, and the connection ends of adjacent two resistors share one short-circuit switch.

8. The leakage compensation circuit of claim 6, wherein, The resistance trimming circuit comprises a plurality of resistors connected in series, and one short-circuit switch is connected in parallel with each resistor, and the short-circuit switch is configured to short-circuit the resistor corresponding to the short-circuit switch.

9. The leakage compensation circuit of claim 5, wherein, The circuit further comprises: an eleventh transistor, the eleventh transistor comprising N eleventh sub-transistors, the first ends of the N eleventh sub-transistors are electrically connected with the external power supply, the control ends of the N eleventh sub-transistors are electrically connected with the control end of the seventh transistor, and the second ends of the N eleventh sub-transistors are electrically connected with the input end of the crystal oscillator driving module through corresponding first switches; the eleventh transistor is configured to adjust the second leakage compensation current output by the leakage compensation module; a twelfth transistor, the twelfth transistor comprising N twelfth sub-transistors, the first ends of the N twelfth sub-transistors are electrically connected with the input end of the crystal oscillator driving module through corresponding second switches, the control ends of the N twelfth sub-transistors are electrically connected with the control end of the ninth transistor, and the second ends of the N twelfth sub-transistors are grounded; the twelfth transistor is configured to adjust the first leakage compensation current output by the leakage compensation module.

10. The leakage compensation circuit according to claim 9, wherein, The crystal oscillator driving module comprises a comparator, a first input end of the comparator is electrically connected with an output end of the IO module and an output end of the leakage compensation module, used for receiving the leakage current and the leakage compensation current, and obtaining a first voltage based on the leakage current and the leakage compensation current, a second input end of the comparator is used for obtaining a reference voltage, and the comparator is used for comparing the first voltage with the reference voltage and outputting a leakage compensation result according to a comparison result.

11. The leakage compensation circuit according to claim 10, wherein, The circuit further comprises: a logic module, a first input end of the logic module is electrically connected with an output end of the comparator, a second input end of the logic module is used for receiving a preset clock signal, and an output end of the logic module is electrically connected with a control circuit of the first switch and the second switch, the logic module is used for outputting a control signal according to the comparison result and the preset clock signal, and the control signal is used for controlling the control circuit to switch control the first switch and the second switch.

12. A crystal oscillator circuit, characterized by comprising: The leakage compensation circuit comprises the leakage compensation circuit according to any one of claims 1-11, wherein the crystal oscillator circuit further comprises: a crystal oscillator, a first end of the crystal oscillator is electrically connected with a first input end of the comparator, and a second end of the crystal oscillator is electrically connected with a second input end of the comparator; a feedback resistor, a first end of the feedback resistor is electrically connected with the first input end of the comparator, and a second end of the feedback resistor is electrically connected with the second input end of the comparator; an inverter, the inverter is connected in parallel with the crystal oscillator; a first capacitor, a first end of the first capacitor is electrically connected with the first end of the crystal oscillator, and a second end of the first capacitor is grounded; a second capacitor, a first end of the second capacitor is electrically connected with the second end of the crystal oscillator, and a second end of the second capacitor is grounded.

13. A microprocessing chip, characterized by The leakage compensation circuit comprises the leakage compensation circuit according to any one of claims 1-11.

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