Electrostatic chuck power supply and semiconductor process device

Abstract

The present disclosure provides an electrostatic chuck power supply and a semiconductor process device. The electrostatic chuck power supply comprises a voltage control circuit, an interlock circuit and first to fourth switches. The voltage control circuit outputs a first voltage, a second voltage, a first control signal and a second control signal. On the basis of the first control signal and the second control signal, the interlock circuit generates first to fourth switch signals, which are used for controlling the first switch to output the first voltage and controlling the fourth switch to output the second voltage, or controlling the second switch to output the first voltage and controlling the third switch to output the second voltage, or controlling the first switch and the second switch to both output the first voltage, or controlling the third switch and the fourth switch to both output the second voltage, and controlling the first switch and the third switch to give outputs at different times and controlling the second switch and the fourth switch to give outputs at different times. The single electrostatic chuck power supply outputs four voltage combinations, and the problems of short circuits of the electrostatic chuck power supply and damage to an electrostatic chuck are also avoided.

Description

An electrostatic chuck power supply and semiconductor process equipment Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to an electrostatic chuck power supply and semiconductor process equipment. Background Technology

[0002] With the development of semiconductor technology, the power supply for electrostatic chucks needs to meet the process requirement of providing four voltage combinations to the first and second electrodes in the electrostatic chuck. The first voltage combination is: providing a positive voltage to the first electrode and a negative voltage to the second electrode; the second voltage combination is: providing a negative voltage to the first electrode and a positive voltage to the second electrode; the third voltage combination is: providing a positive voltage to both the first and second electrodes; and the fourth voltage combination is: providing a negative voltage to both the first and second electrodes.

[0003] Currently, a single electrostatic chuck power supply can only provide the first and second voltage combinations, not the third and fourth. Although the positive and negative voltages from two electrostatic chuck power supplies can be combined to obtain the four voltage combinations mentioned above, this is not only costly but also requires control software to input control signals to each of the two power supplies to achieve interlocking between the positive and negative voltages output by the two power supplies. This is to prevent the simultaneous application of positive and negative voltages to the same electrode (first or second electrode) of the electrostatic chuck, which could lead to a short circuit in the power supply and damage to the electrostatic chuck. However, the reliability of interlocking positive and negative voltages through control software is poor, which can easily lead to poor stability of the electrostatic chuck power supply. Summary of the Invention

[0004] This application discloses an electrostatic chuck power supply and semiconductor process equipment, so that a single electrostatic chuck power supply can provide the above four voltage combinations while also achieving interlocking between positive and negative voltages.

[0005] In a first aspect, this application discloses an electrostatic chuck power supply, including a voltage control circuit, an interlock circuit, a first switch, a second switch, a third switch, a fourth switch, a first power output terminal, and a second power output terminal. The voltage control circuit generates and outputs a first voltage and a second voltage according to a received first instruction, and generates and outputs a first control signal and a second control signal according to a received second instruction. One of the first voltage and the second voltage is a positive voltage, and the other is a negative voltage. The interlock circuit is connected to the voltage control circuit and receives the first control signal and the second control signal. Based on the first control signal and the second control signal, it generates a first switch signal to a fourth switch signal and transmits the first switch signal to the fourth switch signal to the control terminals of the first switch to the fourth switch, respectively, to control the output state and interlock state of the first switch to the fourth switch. The input terminals of both the first switch and the second switch are used to receive the first voltage. The output terminal of the first switch is connected to the first power output terminal, and the output terminal of the second switch is connected to the second power output terminal. The input terminals of both the third and fourth switches are used to receive the second voltage. The output terminal of the third switch is connected to the first power output terminal, and the output terminal of the fourth switch is connected to the second power output terminal. The first switch signal to the fourth switch signal is used to control the first switch to output the first voltage to the first power output terminal and the fourth switch to output the second voltage to the second power output terminal, or to control the second switch to output the first voltage to the second power output terminal and the third switch to output the second voltage to the first power output terminal, or to control the first switch and the second switch to output the first voltage to the first power output terminal and the second power output terminal respectively, or to control the third switch and the fourth switch to output the second voltage to the first power output terminal and the second power output terminal respectively, and to control the first switch and the third switch not to output voltage at the same time and the second switch and the fourth switch not to output voltage at the same time, so that the first switch and the third switch are in an interlocked state, and the second switch and the fourth switch are in an interlocked state.

[0006] In some embodiments, the interlock circuit includes a first interlock circuit and a second interlock circuit; the first interlock circuit is used to generate a first switch signal and a third switch signal according to a first control signal and a first enable signal; the first enable signal is used to control the enable state of the first interlock circuit; the second interlock circuit is used to generate a second switch signal and a fourth switch signal according to the second control signal and the second enable signal; the second enable signal is used to control the enable state of the second interlock circuit; wherein, when the first enable signal controls the first interlock circuit to be in the enabled state, the first switch signal and the third switch signal control the first switch and the third switch not to output voltage simultaneously; when the second enable signal controls the second interlock circuit to be in the enabled state, the second switch signal and the fourth switch signal control the second switch and the fourth switch not to output voltage simultaneously.

[0007] In some embodiments, the first switch and the third switch are MOSFETs of the same type. When the first enable signal is a first-level signal and the first control signal is a first-level signal, the first interlock circuit is enabled, the first switch signal is a first-level signal, and the third switch signal is a second-level signal; when the first enable signal is a first-level signal and the first control signal is a second-level signal, the first interlock circuit is enabled, the first switch signal is a second-level signal, and the third switch signal is a first-level signal; and / or, the second switch and the fourth switch are MOSFETs of the same type. When the second enable signal is a first-level signal and the second control signal is a first-level signal, the second interlock circuit is enabled, the second switch signal is a first-level signal, and the fourth switch signal is a second-level signal; when the second enable signal is a first-level signal and the second control signal is a second-level signal, the second interlock circuit is enabled, the second switch signal is a second-level signal, and the fourth switch signal is a first-level signal; wherein, one of the first level signal and the second level signal is a high-level signal and the other is a low-level signal.

[0008] In some embodiments, the first interlock circuit includes a first NOT gate, a first OR gate, and a second OR gate; the input terminal of the first NOT gate is used to receive the first control signal, the output terminal of the first NOT gate is connected to the first input terminal of the first OR gate, and the first NOT gate is used to transmit the inverted signal of the first control signal to the first OR gate; the second input terminal of the first OR gate is used to receive the first enable signal, and the first OR gate is used to perform a logical OR operation on the inverted signal of the first control signal and the first enable signal, and output the operation result as the first switch signal; the first input terminal of the second OR gate is connected to the input terminal of the first NOT gate and is used to receive the first control signal; the second input terminal of the second OR gate is connected to the second input terminal of the first OR gate and is used to receive the first enable signal; the second OR gate is used to perform a logical OR operation on the first control signal and the first enable signal, and output the operation result as the third switch signal.

[0009] In some embodiments, the second interlock circuit includes a second NOT gate, a third OR gate, and a fourth OR gate; the input terminal of the second NOT gate is used to receive the second control signal, the output terminal of the second NOT gate is connected to the first input terminal of the third OR gate, and the second NOT gate is used to transmit the inverted signal of the second control signal to the third OR gate; the second input terminal of the third OR gate is used to receive the second enable signal, and the third OR gate is used to perform a logical OR operation on the inverted signal of the second control signal and the second enable signal, and output the operation result as the second switch signal; the first input terminal of the fourth OR gate is connected to the input terminal of the second NOT gate and is used to receive the second control signal; the second input terminal of the fourth OR gate is connected to the first input terminal of the third OR gate and is used to receive the second enable signal; the fourth OR gate is used to perform a logical OR operation on the second control signal and the second enable signal, and output the operation result as the fourth switch signal.

[0010] In some embodiments, the voltage control circuit includes a control circuit and a boost circuit; the control circuit is configured to generate a control voltage according to the first instruction and output the control voltage to the boost circuit, generate a first control signal and a second control signal according to the second instruction, and output the first control signal and the second control signal to the interlock circuit; the boost circuit is configured to boost the control voltage, generate the first voltage and the second voltage according to the boosted control voltage, transmit the first voltage to the input terminals of the first switch and the second switch, and transmit the second voltage to the input terminals of the third switch and the fourth switch.

[0011] In some embodiments, the second instruction includes a first indication signal, a second indication signal, a third indication signal, and a fourth indication signal; the control circuit includes a logic control circuit, which is configured to generate a first control signal and a second control signal based on the first indication signal, the second indication signal, the third indication signal, and the fourth indication signal; when only one of the first indication signal, the second indication signal, the third indication signal, and the fourth indication signal is a first-level signal, one of the first control signal and the second control signal is a first-level signal and the other is a second-level signal, or both the first control signal and the second control signal are first-level signals or second-level signals; when at least two of the first indication signal, the second indication signal, the third indication signal, and the fourth indication signal are first-level signals, both the first control signal and the second control signal are second-level signals; wherein, one of the first-level signal and the second-level signal is a high-level signal and the other is a low-level signal.

[0012] In some embodiments, the logic control circuit includes a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a first AND gate, a second AND gate, a third AND gate, a fifth OR gate, and a sixth OR gate; the input of the third NOT gate is used to receive the first indication signal, and the output of the third NOT gate is connected to the first input of the first AND gate, the second AND gate, and the first input of the third AND gate; the input of the fourth NOT gate is used to receive the second indication signal, and the output of the fourth NOT gate is connected to the second input of the second AND gate and the third AND gate; the second input of the first AND gate is used to receive the second indication signal; the input of the fifth NOT gate is used to receive the third indication signal, and the output of the fifth NOT gate is connected to the third input of the first AND gate and the second AND gate. The third AND gate is connected to the fourth AND gate; the third input of the third AND gate is used to receive the third indication signal; the input of the sixth NOT gate is used to receive the fourth indication signal, and the output of the sixth NOT gate is connected to the fourth input of the first AND gate and the third AND gate; the fourth input of the second AND gate is used to receive the fourth indication signal; the output of the first AND gate is connected to the first input of the fifth OR gate, the output of the second AND gate is connected to the second input of the fifth OR gate, the output of the first AND gate is also connected to the first input of the sixth OR gate, and the output of the third AND gate is connected to the second input of the sixth OR gate; the output of the fifth OR gate is used to output the first control signal, and the output of the sixth OR gate is used to output the second control signal.

[0013] In some embodiments, the first instruction and the second instruction are sent by the host computer of the semiconductor process equipment where the electrostatic chuck power supply is located.

[0014] Secondly, this application discloses a semiconductor process apparatus, including an electrostatic chuck and an electrostatic chuck power supply as described in any of the preceding claims, wherein the electrostatic chuck includes at least a first electrode and a second electrode, the first electrode and the second electrode being respectively connected to the first power supply output terminal and the second power supply output terminal.

[0015] The electrostatic chuck power supply and semiconductor process equipment disclosed in this application include a voltage control circuit, an interlock circuit, a first to a fourth switch, a first power output terminal, and a second power output terminal. The voltage control circuit generates and outputs a first voltage and a second voltage according to a received first instruction, and generates and outputs a first control signal and a second control signal according to a received second instruction. The interlock circuit generates a first to a fourth switch signal according to the first and second control signals, and transmits the first to fourth switch signals to the control terminals of the first to fourth switches respectively to control the output state and interlock state of the first to fourth switches. The input terminals of the first and second switches are both used to receive the first voltage. The output terminal of the first switch is connected to the first power output terminal, and the output terminal of the second switch is connected to the second power output terminal. The input terminals of the third and fourth switches are both used to receive the second voltage. The output terminal of the third switch is connected to the first power output terminal, and the output terminal of the fourth switch is connected to the second power output terminal.

[0016] The first to fourth switch signals are used to control the first switch to output a first voltage to the first power supply output terminal and the fourth switch to output a second voltage to the second power supply output terminal; or, to control the second switch to output a first voltage to the second power supply output terminal and the third switch to output a second voltage to the first power supply output terminal; or, to control the first and second switches to output the first voltage to the first and second power supply output terminals respectively; or, to control the third and fourth switches to output the second voltage to the first and second power supply output terminals respectively. Because one of the first and second voltages is a positive voltage and the other is a negative voltage, the above four voltage combinations can be achieved using a single electrostatic chuck power supply.

[0017] Furthermore, because the first and fourth switch signals control the first and third switches to output at different times, and the second and fourth switches to output at different times—that is, the first and third switches are interlocked, and the second and fourth switches are interlocked—the problem of short circuits in the electrostatic chuck power supply and damage to the electrostatic chuck caused by the simultaneous transmission of positive and negative voltages to the same power output terminal and the same electrostatic chuck electrode can be avoided. In addition, the interlocking circuit in this embodiment is a hardware circuit structure, therefore, it has higher reliability and greater stability of the electrostatic chuck power supply compared to control software. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0019] Figure 1 is a schematic diagram of a semiconductor process equipment.

[0020] Figure 2 is a schematic diagram of the connection relationship between two electrostatic chuck power supplies that provide four voltage combinations.

[0021] Figure 3 is a schematic diagram of the structure of an electrostatic chuck power supply disclosed in an embodiment of this application.

[0022] Figure 4 is a schematic diagram of another electrostatic chuck power supply disclosed in an embodiment of this application.

[0023] Figure 5 is a schematic diagram of the structure of a control circuit disclosed in an embodiment of this application.

[0024] Figure 6 is a schematic diagram of the structure of a logic control circuit disclosed in an embodiment of this application.

[0025] Figure 7 is a schematic diagram of an interlock circuit disclosed in an embodiment of this application.

[0026] Figure 8 is a schematic diagram of another interlock circuit disclosed in an embodiment of this application.

[0027] Figure 9 is a schematic diagram of the structure of a semiconductor process equipment disclosed in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] As shown in Figure 1, a conventional semiconductor process equipment includes a process chamber 9 and an electrostatic chuck disposed within the process chamber 9. The electrostatic chuck includes a chuck base 5 and a ceramic layer 4, with a first electrode 7 and a second electrode 8 embedded inside the ceramic layer 4. The electrostatic chuck power supply 11 has a positive high-voltage output port HV+ and a negative high-voltage output port HV-. The positive voltage output from the positive high-voltage output port HV+ and the negative voltage output from the negative high-voltage output port HV- are filtered by a filter circuit 10 and then transmitted to the first electrode 7 and the second electrode 8, respectively.

[0030] When a positive voltage is applied to the first electrode 7 and a negative voltage is applied to the second electrode 8, the electrostatic chuck generates an electrostatic attraction that can hold and fix the wafer 3, preventing refrigerant gas from leaking from below the wafer 3. When a negative voltage is applied to the first electrode 7 and a positive voltage is applied to the second electrode 8, the electrostatic chuck generates an opposite electrostatic attraction to neutralize the charge, thereby separating or desorbing the wafer 3 from the electrostatic chuck. However, with the development of semiconductor technology, under certain process conditions, it is necessary to apply either a positive or a negative voltage to both the first electrode 7 and the second electrode 8. In other words, the current electrostatic chuck power supply 11 cannot meet the process requirements of providing the above four voltage combinations to the first electrode 7 and the second electrode 8 in the electrostatic chuck.

[0031] As shown in Figure 2, although two electrostatic chuck power supplies 11 can provide the above four voltage combinations, this is not only costly, but also requires the controller software to input two control signals to each of the two electrostatic chuck power supplies 11 to control the output of the corresponding voltage combinations. For example, if control signals are input to each of the two electrostatic chuck power supplies 11 to control their output of positive voltage, then both electrostatic chuck power supplies 11 will output positive voltage.

[0032] However, this control method has high requirements for the timing of the two control signals, and the control software is prone to inconsistencies in the timing of the two control signals due to external interference. This can easily lead to both electrostatic chuck power supplies 11 simultaneously outputting positive and negative voltages to the same electrostatic chuck electrode, which can cause short circuits in the electrostatic chuck power supply 11 and damage to the electrostatic chuck. In other words, the reliability of interlocking positive and negative voltages through control software is poor, which can easily lead to poor stability of the electrostatic chuck power supply.

[0033] Based on this, this application discloses an electrostatic chuck power supply, which outputs two control signals through a voltage control circuit and generates four switching signals based on the two control signals through an interlock circuit. The four switching signals control the outputs of two switches receiving positive voltage and two switches receiving negative voltage, respectively. Not only can a single electrostatic chuck power supply provide the above four voltage combinations, but the reliability of positive and negative voltage interlocking can also be improved through the hardware interlock circuit.

[0034] As one embodiment of the content disclosed in this application, Figure 3 is a schematic diagram of the structure of an electrostatic chuck power supply disclosed in an embodiment of this application. The electrostatic chuck power supply includes a voltage control circuit 30, an interlock circuit 31, a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a first power output terminal HVout1, and a second power output terminal HVout2.

[0035] The voltage control circuit 30 is used to generate and output a first voltage and a second voltage according to the received first instruction; and to generate and output a first control signal B1 and a second control signal B2 according to the received second instruction. The first voltage and the second voltage are either a positive voltage HV+ or a negative voltage HV-. That is, the first voltage can be positive HV+ and the second voltage can be negative HV-, or vice versa.

[0036] Interlock circuit 31 is connected to voltage control circuit 30 and is used to receive first control signal B1 and second control signal B2. Based on the first control signal B1 and second control signal B2, it generates first switch signal X1 to fourth switch signal X4 and transmits first switch signal X1 to fourth switch signal X4 to the control terminals of first switch K1 to fourth switch K4 respectively to control the output state and interlock state of first switch K1 to fourth switch K4.

[0037] The input terminals of both the first switch K1 and the second switch K2 are used to receive the first voltage. The output terminal of the first switch K1 is connected to the first power output terminal HVout1, and the output terminal of the second switch K2 is connected to the second power output terminal HVout2. The input terminals of both the third switch K3 and the fourth switch K4 are used to receive the second voltage. The output terminal of the third switch K3 is connected to the first power output terminal HVout1, and the output terminal of the fourth switch K4 is connected to the second power output terminal HVout2.

[0038] The first switch signal X1 to the fourth switch signal X4 are used to control the first switch K1 to output a first voltage to the first power output terminal HVout1 and the fourth switch K4 to output a second voltage to the second power output terminal HVout2, or to control the second switch K2 to output a first voltage to the second power output terminal HVout2 and the third switch K3 to output a second voltage to the first power output terminal HVout1, or to control the first switch K1 and the second switch K2 to output the first voltage to the first power output terminal HVout1 and the second power output terminal HVout2 respectively, or to control the third switch K3 and the fourth switch K4 to output the second voltage to the first power output terminal HVout1 and the second power output terminal HVout2 respectively, and to control the first switch K1 and the third switch K3 to not output at the same time and the second switch K2 and the fourth switch K4 to not output at the same time, so that the first switch K1 and the third switch K3 are in an interlocked state, and the second switch K2 and the fourth switch K4 are in an interlocked state.

[0039] Taking a scenario where the first voltage is positive (HV+), the second voltage is negative (HV-), the first power output terminal (HVout1) is connected to the first electrode of the electrostatic chuck, and the second power output terminal (HVout2) is connected to the second electrode of the electrostatic chuck, it is possible to control the first switch K1 to output a positive voltage (HV+) to the first electrode and the fourth switch K4 to output a negative voltage (HV-) to the second electrode; or, control the second switch K2 to output a positive voltage (HV+) to the second electrode and the third switch K3 to output a negative voltage (HV-) to the first electrode; or, control the first switch K1 and the second switch K2 to output positive voltages (HV+) to the first electrode and the second electrode, respectively; or, control the third switch K3 and the fourth switch K4 to output negative voltages (HV-) to the first electrode and the second electrode, respectively. Thus, a single electrostatic chuck power supply can provide the above four voltage combinations to the first and second electrodes of the electrostatic chuck.

[0040] Because the first switch signal X1 to the fourth switch signal X4 can also control the first switch K1 and the third switch K3 to not output at the same time, and the second switch K2 and the fourth switch K4 to not output at the same time, that is, the first switch K1 and the third switch K3 are in an interlocked state, and the second switch K2 and the fourth switch K4 are in an interlocked state, it is possible to control the first switch K1 and the third switch K3 to not output positive voltage HV+ and negative voltage HV- to the first electrode at the same time, and to control the second switch K2 and the fourth switch K4 to not output positive voltage HV+ and negative voltage HV- to the second electrode at the same time. This can avoid the problem of short circuit of the electrostatic chuck power supply and damage to the electrostatic chuck caused by the positive voltage HV+ and the negative voltage HV- being transmitted to the same power output terminal and the same electrostatic chuck electrode at the same time.

[0041] Furthermore, the interlock circuit in this embodiment is a hardware circuit structure, so it is more reliable and the electrostatic chuck power supply is more stable compared to control software.

[0042] In some embodiments of this application, the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 can all be MOSFETs. The first switch signal X1 to the fourth switch signal X4 control the switching states of the first switch K1 to the fourth switch K4, thereby controlling the output states and interlocking states of the first switch K1 to the fourth switch K4.

[0043] Specifically, the first switch signal X1 controls the first switch K1 to open or close, the second switch signal X2 controls the second switch K2 to open or close, the third switch signal X3 controls the third switch K3 to open or close, and the fourth switch signal X4 controls the fourth switch K4 to open or close. When the first switch K1 is open, it outputs a first voltage to the first power output terminal HVout1; when the second switch K2 is open, it outputs a first voltage to the second power output terminal HVout2; when the third switch K3 is open, it outputs a second voltage to the first power output terminal HVout1; and when the fourth switch K4 is open, it outputs a second voltage to the second power output terminal HVout2.

[0044] Furthermore, when the first switch signal X1 controls the first switch K1 to open, the third switch signal X3 controls the third switch K3 to close; when the third switch signal X3 controls the third switch K3 to open, the first switch signal X1 controls the first switch K1 to close, thus interlocking the first switch K1 and the third switch K3. When the second switch signal X2 controls the second switch K2 to open, the fourth switch signal X4 controls the fourth switch K4 to close; when the fourth switch signal X4 controls the fourth switch K4 to open, the second switch signal X2 controls the second switch K2 to close, thus interlocking the second switch K2 and the fourth switch K4.

[0045] Of course, this application is not limited to this. In other embodiments, the first switch K1, the second switch K2, the third switch K3 and the fourth switch K4 may be other types of switches, which will not be described in detail here.

[0046] In some embodiments of this application, as shown in FIG4, the voltage control circuit 30 includes a control circuit 301 and a boost circuit 302.

[0047] The control circuit 301 is used to generate a control voltage U1 according to the first instruction and output the control voltage U1 to the boost circuit 302, generate a first control signal B1 and a second control signal B2 according to the second instruction, and output the first control signal B1 and the second control signal B2 to the interlock circuit 31.

[0048] The boost circuit 302 is used to boost the control voltage U1, generate a first voltage and a second voltage based on the boosted control voltage U1, and transmit the first voltage to the input terminals of the first switch K1 and the second switch K2, and transmit the second voltage to the input terminals of the third switch K3 and the fourth switch K4.

[0049] In some embodiments of this application, the first and second instructions are sent by the host computer of the semiconductor process equipment where the electrostatic chuck power supply is located. For example, after the host computer generates the first or second instruction based on user settings, it sends the first or second instruction to the slave computer of the semiconductor process equipment, which then sends it to the voltage control circuit 30 or the control circuit 301. Of course, this application is not limited to this. In other embodiments, the first and second instructions can also be sent by the test tool of the semiconductor process equipment where the electrostatic chuck power supply is located, which will not be elaborated here.

[0050] In some embodiments of this application, the boost circuit 302 can boost the control voltage U1 using a transformer, generate a first voltage (such as a positive voltage) based on the boosted control voltage U1 using a positive voltage generation circuit, and generate a second voltage (such as a negative voltage) based on the boosted control voltage U1 using a negative voltage generation circuit. Of course, this application is not limited to this; in other embodiments, the boost circuit 302 can also boost the voltage and generate the first and second voltages in other ways, which will not be elaborated here.

[0051] In some embodiments of this application, as shown in FIG5, the second instruction includes a first indication signal Y1, a second indication signal Y2, a third indication signal Y3, and a fourth indication signal Y4. The control circuit 301 includes a logic control circuit 3010, which is used to generate a first control signal B1 and a second control signal B2 according to the first indication signal Y1, the second indication signal Y2, the third indication signal Y3, and the fourth indication signal Y4.

[0052] Specifically, if only one of the first indication signal Y1, second indication signal Y2, third indication signal Y3, and fourth indication signal Y4 is a first-level signal, then one of the first control signal B1 and the second control signal B2 is a first-level signal and the other is a second-level signal; or both the first control signal B1 and the second control signal B2 are either first-level signals or second-level signals. If at least two of the first indication signal Y1, second indication signal Y2, third indication signal Y3, and fourth indication signal Y4 are first-level signals, then both the first control signal B1 and the second control signal B2 are second-level signals. In this case, one of the first-level signal and the second-level signal is a high-level signal and the other is a low-level signal.

[0053] Table 1

[0054] Taking a high-level signal as the first level signal and a low-level signal as an example, referring to Table 1, where 0 represents a low-level signal and 1 represents a high-level signal: When the first indicator signal Y1 is 1, and the second, third, and fourth indicator signals Y3 are all 0, the first control signal B1 is 0, and the second control signal B2 is 0. When the second indicator signal Y2 is 1, and the first, third, and fourth indicator signals Y3 are all 0, the first control signal B1 is 1, and the second control signal B2 is 1. When the third indicator signal Y3 is 1, and the first, second, and fourth indicator signals Y1 and Y2 are all 0, the first control signal B1 is 0, and the second control signal B2 is 1. When the fourth indicator signal Y4 is 1, and the first, second, and third indicator signals Y1 and Y2 are all 0, the first control signal B1 is 1, and the second control signal B2 is 0. When at least two of the first indication signal Y1, the second indication signal Y2, the third indication signal Y3, and the fourth indication signal Y4 are 1, the first control signal B1 is 0 and the second control signal B2 is 0. In Table 1, XXXX in the last row represents the case where at least two of the first indication signal Y1, the second indication signal Y2, the third indication signal Y3, and the fourth indication signal Y4 are 1.

[0055] In some embodiments of this application, as shown in FIG6, the logic control circuit 3010 includes a third NOT gate F3, a fourth NOT gate F4, a fifth NOT gate F5, a sixth NOT gate F6, a first AND gate A1, a second AND gate A2, a third AND gate A3, a fifth OR gate R5, and a sixth OR gate R6.

[0056] The third NOT gate F3 receives the first indication signal Y1 at its input, and its output is connected to the first inputs of the first AND gates A1, A2, and A3. The fourth NOT gate F4 receives the second indication signal Y2 at its input, and its output is connected to the second inputs of the second AND gates A2 and A3. The second input of the first AND gate A1 receives the second indication signal Y2.

[0057] The input of the fifth NOT gate F5 is used to receive the third indication signal Y3, and the output of the fifth NOT gate F5 is connected to the third input of the first AND gate A1 and the second AND gate A2. The third input of the third AND gate A3 is used to receive the third indication signal Y3. The input of the sixth NOT gate F6 is used to receive the fourth indication signal Y4, and the output of the sixth NOT gate F6 is connected to the fourth input of the first AND gate A1 and the third AND gate A3. The fourth input of the second AND gate A2 is used to receive the fourth indication signal Y4.

[0058] The output of the first AND gate A1 is connected to the first input of the fifth OR gate R5. The output of the second AND gate A2 is connected to the second input of the fifth OR gate R5. The output of the first AND gate A1 is also connected to the first input of the sixth OR gate R6. The output of the third AND gate A3 is connected to the second input of the sixth OR gate R6. The output of the fifth OR gate R5 is used to output the first control signal B1, and the output of the sixth OR gate R6 is used to output the second control signal B2.

[0059] Similarly, taking the first level signal as high and the second level signal as low as an example, referring to Table 1, when the first indicator signal Y1 is 1, and the second indicator signal Y2, the third indicator signal Y3, and the fourth indicator signal Y4 are all 0, the third NOT gate F3 outputs 0, the fourth NOT gate F4 outputs 1, the fifth NOT gate F5 outputs 1, the sixth NOT gate F6 outputs 1, the first AND gate A1 outputs 0, the second AND gate A2 outputs 0, the third AND gate A3 outputs 0, the first control signal B1 output by the fifth OR gate R5 is 0, and the second control signal B2 output by the sixth OR gate R6 is 0.

[0060] When the second indicator signal Y2 is 1, and the first indicator signal Y1, the third indicator signal Y3, and the fourth indicator signal Y4 are all 0, the third NOT gate F3 outputs 1, the fourth NOT gate F4 outputs 0, the fifth NOT gate F5 outputs 1, the sixth NOT gate F6 outputs 1, the first AND gate A1 outputs 1, the second AND gate A2 outputs 0, the third AND gate A3 outputs 0, the first control signal B1 output by the fifth OR gate R5 is 1, and the second control signal B2 output by the sixth OR gate R6 is 1.

[0061] When the third indicator signal Y3 is 1, and the first indicator signal Y1, the second indicator signal Y2, and the fourth indicator signal Y4 are all 0, the third NOT gate F3 outputs 1, the fourth NOT gate F4 outputs 1, the fifth NOT gate F5 outputs 0, the sixth NOT gate F6 outputs 1, the first AND gate A1 outputs 0, the second AND gate A2 outputs 0, the third AND gate A3 outputs 1, the first control signal B1 output by the fifth OR gate R5 is 0, and the second control signal B2 output by the sixth OR gate R6 is 1.

[0062] When the fourth indicator signal Y4 is 1, and the first indicator signal Y1, the second indicator signal Y2, and the third indicator signal Y3 are all 0, the third NOT gate F3 outputs 1, the fourth NOT gate F4 outputs 1, the fifth NOT gate F5 outputs 1, the sixth NOT gate F6 outputs 0, the first AND gate A1 outputs 0, the second AND gate A2 outputs 1, the third AND gate A3 outputs 0, the first control signal B1 output by the fifth OR gate R5 is 1, and the second control signal B2 output by the sixth OR gate R6 is 0.

[0063] When the first indicator signal Y1 and the second indicator signal Y2 are 1, and the third indicator signal Y3 and the fourth indicator signal Y4 are 0, the third NOT gate F3 outputs 0, the fourth NOT gate F4 outputs 0, the fifth NOT gate F5 outputs 1, the sixth NOT gate F6 outputs 1, the first AND gate A1 outputs 0, the second AND gate A2 outputs 0, the third AND gate A3 outputs 0, the fifth OR gate R5 outputs the first control signal B1 as 0, and the sixth OR gate R6 outputs the second control signal B2 as 0. The same applies to the other cases where at least two of the first indicator signal Y1, the second indicator signal Y2, the third indicator signal Y3, and the fourth indicator signal Y4 are 1, and will not be repeated here.

[0064] It should be noted that the logic control circuit 3010 in this application embodiment is not limited to the structure shown in FIG6. Other logic control circuits 3010 can also be applied to this application embodiment if they can output corresponding first control signal B1 and second control signal B2 based on the first indication signal Y1 to the fourth indication signal Y1 mentioned above.

[0065] In some embodiments of this application, as shown in FIG7, the interlock circuit 31 includes a first interlock circuit 311 and a second interlock circuit 312. The first interlock circuit 311 is used to generate a first switch signal X1 and a third switch signal X3 according to a first control signal B1 and a first enable signal E1. The first enable signal E1 is used to control the enable state of the first interlock circuit 311. The second interlock circuit 312 is used to generate a second switch signal X2 and a fourth switch signal X4 according to a second control signal B2 and a second enable signal E2. The second enable signal E2 is used to control the enable state of the second interlock circuit 312. The first enable signal E1 and the second enable signal E2 can be provided by the voltage control circuit 30 or by a controller that controls the power supply of the electrostatic chuck.

[0066] Specifically, when the first enable signal E1 controls the first interlock circuit 311 to be in the enabled state, the first switch signal X1 and the third switch signal X3 control the first switch K1 and the third switch K3 to not output voltage simultaneously. That is, one of the first switch K1 and the third switch K3 outputs voltage while the other does not, so as to prevent the first switch K1 and the third switch K3 from simultaneously outputting positive voltage HV+ and negative voltage HV- to the same power output terminal and the same electrostatic chuck electrode. When the first enable signal E1 controls the first interlock circuit 311 to be in the disabled state, the first switch signal X1 and the third switch signal X3 control the first switch K1 and the third switch K3 to not output voltage.

[0067] When the second enable signal E2 controls the second interlock circuit 312 to be in the enabled state, the second switch signal X2 and the fourth switch signal X4 control the second switch K2 and the fourth switch K4 to not output voltage simultaneously. That is, one of the second switch K2 and the fourth switch K4 outputs voltage while the other does not, to prevent the second switch K2 and the fourth switch K4 from simultaneously outputting positive voltage HV+ and negative voltage HV- to the same power output terminal and the same electrostatic chuck electrode. When the second enable signal E2 controls the second interlock circuit 312 to be in the disabled state, the second switch signal X2 and the fourth switch signal X4 control the second switch K2 and the fourth switch K4 to not output voltage.

[0068] Based on this, in some embodiments of this application, the first switch K1 and the third switch K3 are MOS transistors of the same type. For example, both the first switch K1 and the third switch K3 are PMOS transistors, or both the first switch K1 and the third switch K3 are NMOS transistors. When the first enable signal E1 is a first-level signal and the first control signal B1 is a first-level signal, the first interlock circuit 311 is in an enabled state, the first switch signal X1 is a first-level signal, and the third switch signal X2 is a second-level signal. When the first enable signal E1 is a first-level signal and the first control signal B1 is a second-level signal, the first interlock circuit 311 is in an enabled state, the first switch signal X1 is a second-level signal, and the third switch signal X3 is a first-level signal. When the first enable signal E1 is a second-level signal and the first interlock circuit 312 is in a disabled state, both the first switch signal X1 and the third switch signal X3 are second-level signals. In this configuration, one of the first-level signal and the second-level signal is a high-level signal, and the other is a low-level signal.

[0069] The second switch K2 and the fourth switch K4 are the same type of MOSFET, for example, both second switch K2 and fourth switch K4 are PMOS transistors, or both second switch K2 and fourth switch K4 are NMOS transistors. Furthermore, when the second enable signal E2 and the second control signal B2 are both at a first level, the second interlock circuit 312 is enabled, the second switch signal X2 is at a first level, and the fourth switch signal X4 is at a second level. When the second enable signal E2 and the second control signal B2 are both at a second level, the second interlock circuit 312 is enabled, the second switch signal X2 is at a second level, and the fourth switch signal X4 is at a first level. When the second enable signal E2 is at a second level, the second interlock circuit 312 is disabled, and both the second switch signal X2 and the fourth switch signal X4 are at a second level. In this configuration, one of the first level signal and the other of the second level signal is a high-level signal and the other is a low-level signal.

[0070] In some embodiments of this application, as shown in FIG8, the first interlock circuit 311 includes a first NOT gate F1, a first OR gate R1, and a second OR gate R2. The second interlock circuit 312 includes a second NOT gate F2, a third OR gate R3, and a fourth OR gate R4.

[0071] In this configuration, the input of the first NOT gate F1 receives the first control signal B1, and the output of the first NOT gate F1 is connected to the first input of the first OR gate R1. The first NOT gate F1 transmits the inverted signal of the first control signal B1 to the first OR gate R1. The second input of the first OR gate R1 receives the first enable signal E1, and the first OR gate R1 performs a logical OR operation on the inverted signal of the first control signal B1 and the first enable signal E1, outputting the result as the first switch signal X1.

[0072] The first input of the second OR gate R2 is connected to the input of the first NOT gate F1 to receive the first control signal B1. The second input of the second OR gate R2 is connected to the second input of the first OR gate R1 to receive the first enable signal E1. The second OR gate R2 performs a logical OR operation on the first control signal B1 and the first enable signal E1, and outputs the result as the third switch signal X3.

[0073] The input of the second NOT gate F2 is used to receive the second control signal B2. The output of the second NOT gate F2 is connected to the first input of the third OR gate R3. The second NOT gate F2 is used to transmit the inverted signal of the second control signal B2 to the third OR gate R3. The second input of the third OR gate R3 is used to receive the second enable signal E2. The third OR gate R3 is used to perform a logical OR operation on the inverted signal of the second control signal B2 and the second enable signal E2, and outputs the result as the second switch signal X2.

[0074] The first input of the fourth OR gate R4 is connected to the input of the second NOT gate F2 to receive the second control signal B2. The second input of the fourth OR gate R4 is connected to the first input of the third OR gate R3 to receive the second enable signal E2. The fourth OR gate R4 performs a logical OR operation on the second control signal B2 and the second enable signal E2, and outputs the result as the fourth switch signal X4.

[0075] Understandably, because interlock circuits are hardware circuit structures composed of logic gates, they are not easily affected by external interference. Therefore, compared to control software, interlock circuits have higher reliability. It should be noted that the interlock circuit 31 in this embodiment includes, but is not limited to, the structure shown in Figure 8.

[0076] Taking a scenario where the first switch K1, the third switch K3, the second switch K2, and the fourth switch K4 are all PMOS transistors as an example, referring to Table 2, when the first enable signal E1 is 0 and the first control signal B1 is 0, the first interlock circuit 311 is enabled, the first NOT gate F1 outputs 1, the first switch signal X1 output by the first OR gate R1 is 1, the third switch signal X2 output by the second OR gate R2 is 0, the first switch K1 is off, the third switch K3 is on, and a second voltage, such as a negative voltage HV-, is output to the first power supply output terminal HVout1. When the first enable signal E1 is 0 and the first control signal B1 is 1, the first interlock circuit 311 is enabled, the first NOT gate F1 outputs 0, the first switch signal X1 output by the first OR gate R1 is 0, the third switch signal X3 output by the second OR gate R2 is 1, the first switch K1 is on, the third switch K3 is off, and a first voltage, such as a positive voltage HV+, is output to the first power supply output terminal HVout1. When the first enable signal E1 is 1, the first interlock circuit 311 is in the disabled state. Regardless of whether the first control signal B1 is 0 or 1 (X in Table 2 indicates whether the first control signal B1 is 0 or 1), the first switch signal X1 and the third switch signal X3 are both 1, and the first switch K1 and the third switch K3 are both turned off.

[0077] Referring to Table 3, when the second enable signal E2 is 0 and the second control signal B2 is 0, the second interlock circuit 312 is enabled. The second NOT gate F2 outputs 1, the second switch signal X2 output by the third OR gate R3 is 1, and the fourth switch signal X4 output by the fourth OR gate R4 is 0. The second switch K2 is off and the fourth switch K4 is on, outputting a second voltage, such as a negative voltage HV-, to the second power supply output terminal HVout2. When the second enable signal E2 is 0 and the second control signal B2 is 1, the second interlock circuit 312 is enabled. The second NOT gate F2 outputs 0, the second switch signal X2 output by the third OR gate R3 is 0, and the fourth switch signal X4 output by the fourth OR gate R4 is 1. The second switch K2 is on and the fourth switch K4 is off, outputting a first voltage, such as a positive voltage HV+, to the second power supply output terminal HVout2. When the second enable signal E2 is 1, the second interlock circuit 312 is in a disabled state. Regardless of whether the second control signal B2 is 1 or 0 (X in Table 3 indicates whether the second control signal B2 is 0 or 1), the second switch signal X2 and the fourth switch signal X4 are both 1, and the second switch K2 and the fourth switch K4 are both turned off. Here, X can be 0 or 1.

[0078] Table 2

[0079] Table 3

[0080] Referring to Tables 1, 2, and 3, when the first indicator signal Y1 is 1 and the second, third, and fourth indicator signals Y2 and Y3 are all 0, the first and second control signals B1 and B2 are both 0. When the first enable signal E1 is 0 and the second enable signal E2 is 0, the first switch signal X1 is 1, the second switch signal X2 is 1, the third switch signal X3 is 0, and the fourth switch signal X4 is 0. The third and fourth switches K3 are turned on, and the first and second switches K2 are turned off. The third switch K3 outputs a second voltage, such as a negative voltage HV-, to the first power output terminal HVout1, and the fourth switch K4 outputs a second voltage, such as a negative voltage HV-, to the second power output terminal HVout2.

[0081] When the second indicator signal Y2 is 1, and the first indicator signal Y1, the third indicator signal Y3, and the fourth indicator signal Y4 are all 0, the first control signal B1 and the second control signal B2 are both 1. When the first enable signal E1 is 0 and the second enable signal E2 is 0, the first switch signal X1 is 0, the second switch signal X2 is 0, the third switch signal X3 is 1, and the fourth switch signal X4 is 1. The first switch K1 and the second switch K2 are turned on, and the third switch K3 and the fourth switch K4 are turned off. The first switch K1 outputs a first voltage, such as a positive voltage HV+, to the first power output terminal HVout1, and the second switch K2 outputs a first voltage, such as a positive voltage HV+, to the second power output terminal HVout2.

[0082] When the third indicator signal Y3 is 1, and the first indicator signal Y1, the second indicator signal Y2, and the fourth indicator signal Y4 are all 0, the first control signal B1 is 0 and the second control signal B2 is 1. When the first enable signal E1 is 0 and the second enable signal E2 is 0, the first switch signal X1 is 1, the second switch signal X2 is 0, the third switch signal X3 is 0, and the fourth switch signal X4 is 1. The second switch K2 and the third switch K3 are turned on, and the first switch K1 and the fourth switch K4 are turned off. The second switch K2 outputs the first voltage, such as a positive voltage HV+, to the second power output terminal HVout2, and the third switch K3 outputs the second voltage, such as a negative voltage HV-, to the first power output terminal HVout1.

[0083] When the fourth indicator signal Y4 is 1, and the first indicator signal Y1, the second indicator signal Y2, and the third indicator signal Y3 are all 0, the first control signal B1 is 1, and the second control signal B2 is 0. When the first enable signal E1 is 0 and the second enable signal E2 is 0, the first switch signal X1 is 0, the second switch signal X2 is 1, the third switch signal X3 is 1, and the fourth switch signal X4 is 0. The first switch K1 and the fourth switch K4 are turned on, and the second switch K2 and the third switch K3 are turned off. The first switch K1 outputs a first voltage, such as a positive voltage HV+, to the first power output terminal HVout1, and the fourth switch K4 outputs a second voltage, such as a negative voltage HV-, to the second power output terminal HVout2.

[0084] In some embodiments of this application, the second input terminal of the first OR gate R1 may be grounded to make the first enable signal E1 a low-level signal 0, and the second input terminal of the third OR gate R3 may be grounded to make the second enable signal E2 a low-level signal 0. Of course, this application is not limited to this. In other embodiments, the voltage control circuit 30 may provide the first enable signal E1 and the second enable signal E2.

[0085] As one embodiment of the disclosure in this application, an embodiment of this application discloses a semiconductor process apparatus, as shown in FIG9, including an electrostatic chuck and an electrostatic chuck power supply as disclosed in any of the above embodiments. The electrostatic chuck includes at least a first electrode 7 and a second electrode 8, which are respectively connected to a first power supply output terminal HVout1 and a second power supply output terminal HVout2. Specifically, the first electrode 7 and the second electrode 8 can be connected to the first power supply output terminal HVout1 and the second power supply output terminal HVout2 through a filter circuit 10, respectively.

[0086] Based on this, a positive voltage can be input to the first electrode 7 and a negative voltage to the second electrode 8 via an electrostatic chuck power supply, or a negative voltage can be input to the first electrode 7 and a positive voltage to the second electrode 8, or a positive voltage can be input to both the first electrode 7 and the second electrode 8, or a negative voltage can be input to both the first electrode 7 and the second electrode 8.

[0087] As shown in Figures 1 and 9, the semiconductor process equipment may also include a plasma generation system 1. This plasma generation system 1 generally includes an RF coil, an upper matching unit, and an upper RF power supply. The high-frequency magnetic field generated by the system excites the process gas entering the process chamber 9 into plasma 2. The lower RF power supply 15 generates a plasma sheath layer 16 on the upper surface of the wafer 3 through the high-frequency magnetic field generated by the lower matching unit 14. The voltage difference (DC self-bias) between the plasma sheath layer 16 and the wafer 3 forms an electric field, attracting various charged particles in the plasma 2 to perform deposition or etching processes on the surface of the wafer 3.

[0088] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above embodiments are merely illustrative of several implementation methods described in detail, but they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. An electrostatic chuck power supply, comprising: The voltage control circuit, the interlocking circuit, the first switch, the second switch, the third switch, the fourth switch, the first power output terminal and the second power output terminal are comprised; The voltage control circuit is configured to generate and output a first voltage and a second voltage according to a received first instruction, and generate and output a first control signal and a second control signal according to a received second instruction; one of the first voltage and the second voltage is a positive voltage, and the other is a negative voltage; The interlocking circuit is connected with the voltage control circuit, configured to receive the first control signal and the second control signal, generate a first switch signal to a fourth switch signal according to the first control signal and the second control signal, and transmit the first switch signal to the fourth switch signal to control terminals of the first switch to the fourth switch respectively, so as to control output states and interlocking states of the first switch to the fourth switch; The input terminals of the first switch and the second switch are configured to receive the first voltage, the output terminal of the first switch is connected with the first power output terminal, and the output terminal of the second switch is connected with the second power output terminal; the input terminals of the third switch and the fourth switch are configured to receive the second voltage, the output terminal of the third switch is connected with the first power output terminal, and the output terminal of the fourth switch is connected with the second power output terminal; The first switch signal to the fourth switch signal are configured to control the first switch to output the first voltage to the first power output terminal and the fourth switch to output the second voltage to the second power output terminal, or control the second switch to output the first voltage to the second power output terminal and the third switch to output the second voltage to the first power output terminal, or control the first switch and the second switch to output the first voltage to the first power output terminal and the second power output terminal respectively, or control the third switch and the fourth switch to output the second voltage to the first power output terminal and the second power output terminal respectively, and control the first switch and the third switch not to output voltage at the same time and the second switch and the fourth switch not to output voltage at the same time, so that the first switch and the third switch are in the interlocking state, and the second switch and the fourth switch are in the interlocking state.

2. The electrostatic chuck power supply of claim 1, wherein, The interlocking circuit comprises a first interlocking circuit and a second interlocking circuit; The first interlocking circuit is configured to generate the first switch signal and the third switch signal according to the first control signal and a first enable signal; The first enable signal is configured to control an enable state of the first interlocking circuit; The second interlocking circuit is configured to generate the second switch signal and the fourth switch signal according to the second control signal and a second enable signal; and the second enable signal is configured to control an enable state of the second interlocking circuit. Wherein, when the first enable signal controls the first interlocking circuit to be in the enabled state, the first switch signal and the third switch signal control the first switch and the third switch to output voltage at different times; when the second enable signal controls the second interlocking circuit to be in the enabled state, the second switch signal and the fourth switch signal control the second switch and the fourth switch to output voltage at different times.

3. The electrostatic chuck power supply of claim 2, wherein, The first switch and the third switch are MOS tubes of the same type, when the first enable signal is a first level signal and the first control signal is a first level signal, the first interlocking circuit is in the enabled state, the first switch signal is a first level signal and the third switch signal is a second level signal; When the first enable signal is a first level signal and the first control signal is a second level signal, the first interlocking circuit is in the enabled state, the first switch signal is a second level signal and the third switch signal is a first level signal; And / or, The second switch and the fourth switch are MOS tubes of the same type, when the second enable signal is a first level signal and the second control signal is a first level signal, the second interlocking circuit is in the enabled state, the second switch signal is a first level signal and the fourth switch signal is a second level signal; When the second enable signal is a first level signal and the second control signal is a second level signal, the second interlocking circuit is in the enabled state, the second switch signal is a second level signal and the fourth switch signal is a first level signal; Wherein, one of the first level signal and the second level signal is a high level signal and the other is a low level signal.

4. The electrostatic chuck power supply of claim 2 or 3, wherein, The first interlocking circuit comprises a first NOT gate, a first OR gate and a second OR gate; The input end of the first NOT gate is used for receiving the first control signal, the output end of the first NOT gate is connected with the first input end of the first OR gate, and the first NOT gate is used for transmitting the inverse signal of the first control signal to the first OR gate; the second input end of the first OR gate is used for receiving the first enable signal, and the first OR gate is used for performing logical or operation on the inverse signal of the first control signal and the first enable signal and outputting the operation result as the first switch signal; The first input end of the second OR gate is connected with the input end of the first NOT gate and is used for receiving the first control signal; the second input end of the second OR gate is connected with the second input end of the first OR gate and is used for receiving the first enable signal; and the second OR gate is used for performing logical or operation on the first control signal and the first enable signal and outputting the operation result as the third switch signal.

5. The electrostatic chuck power supply of claim 2 or 3, wherein, The second interlocking circuit comprises a second NOT gate, a third OR gate and a fourth OR gate; An input end of the second NOT gate is configured to receive the second control signal, an output end of the second NOT gate is connected with a first input end of the third OR gate, and the second NOT gate is configured to transmit an inverse signal of the second control signal to the third OR gate; a second input end of the third OR gate is configured to receive the second enable signal, and the third OR gate is configured to perform logical OR operation on the inverse signal of the second control signal and the second enable signal, and output an operation result as the second switch signal. A first input end of the fourth OR gate is connected with the input end of the second NOT gate and configured to receive the second control signal; a second input end of the fourth OR gate is connected with the first input end of the third OR gate and configured to receive the second enable signal; and the fourth OR gate is configured to perform logical OR operation on the second control signal and the second enable signal, and output an operation result as the fourth switch signal.

6. The electrostatic chuck power supply of claim 1, wherein, The voltage control circuit comprises a control circuit and a boost circuit; The control circuit is configured to generate a control voltage according to the first instruction, output the control voltage to the boost circuit, generate a first control signal and a second control signal according to the second instruction, and output the first control signal and the second control signal to the interlocking circuit; The boost circuit is configured to boost the control voltage, generate the first voltage and the second voltage according to the boosted control voltage, and transmit the first voltage to input ends of the first switch and the second switch, and transmit the second voltage to input ends of the third switch and the fourth switch.

7. The electrostatic chuck power supply of claim 6, wherein, The second instruction comprises a first indication signal, a second indication signal, a third indication signal and a fourth indication signal; the control circuit comprises a logic control circuit, and the logic control circuit is configured to generate the first control signal and the second control signal according to the first indication signal, the second indication signal, the third indication signal and the fourth indication signal; In a case where only one of the first indication signal, the second indication signal, the third indication signal and the fourth indication signal is a first level signal, one of the first control signal and the second control signal is the first level signal, and the other is a second level signal, or the first control signal and the second control signal are both the first level signal or the second level signal; In a case where at least two of the first indication signal, the second indication signal, the third indication signal and the fourth indication signal are the first level signal, the first control signal and the second control signal are both the second level signal; wherein one of the first level signal and the second level signal is a high level signal, and the other is a low level signal.

8. The electrostatic chuck power supply of claim 7, wherein, The logic control circuit comprises a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a first AND gate, a second AND gate, a third AND gate, a fifth OR gate and a sixth OR gate; An input end of the third NOT gate is configured to receive the first indication signal, and an output end of the third NOT gate is connected with first input ends of the first AND gate, the second AND gate and the third AND gate. An input end of the fourth NOT gate is configured to receive the second indication signal, and an output end of the fourth NOT gate is connected with second input ends of the second AND gate and the third AND gate; a second input end of the first AND gate is configured to receive the second indication signal; An input end of the fifth NOT gate is configured to receive the third indication signal, and an output end of the fifth NOT gate is connected with third input ends of the first AND gate and the second AND gate; a third input end of the third AND gate is configured to receive the third indication signal; An input end of the sixth NOT gate is configured to receive the fourth indication signal, and an output end of the sixth NOT gate is connected with fourth input ends of the first AND gate and the third AND gate; a fourth input end of the second AND gate is configured to receive the fourth indication signal; An output end of the first AND gate is connected with a first input end of the fifth OR gate, an output end of the second AND gate is connected with a second input end of the fifth OR gate, the output end of the first AND gate is also connected with a first input end of the sixth OR gate, and an output end of the third AND gate is connected with a second input end of the sixth OR gate; an output end of the fifth OR gate is configured to output the first control signal, and an output end of the sixth OR gate is configured to output the second control signal.

9. The electrostatic chuck power supply of claim 1, wherein, The first instruction and the second instruction are sent by a host computer of a semiconductor process equipment where the electrostatic chuck power supply is located.

10. A semiconductor process apparatus, characterized by, The semiconductor process equipment comprises an electrostatic chuck and an electrostatic chuck power supply according to any one of claims 1-9, wherein the electrostatic chuck comprises at least a first electrode and a second electrode, and the first electrode and the second electrode are connected with the first power supply output end and the second power supply output end, respectively.

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