Semiconductor device

Abstract

This semiconductor device comprises: a first inverter in which input and output are respectively connected to first and second nodes; a second inverter in which input and output are respectively connected to the second and first nodes; a first transistor of a first conductivity type; a first capacitor; a second transistor of a second conductivity type; and a second capacitor. At least a section of the first transistor and of the first capacitor are disposed so as to overlap each other in plan view. Alternatively, at least a section of the second transistor and of the second capacitor are disposed so as to overlap each other in plan view. Due to this configuration, it is possible to efficiently design the layout of elements in an ESD protection circuit, and to suppress an increase in layout size.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] In order to protect elements from damage due to electrostatic discharge (ESD) that occurs when assembling a semiconductor device in the form of a chip into a package or when handling the semiconductor device assembled in a package, a dedicated ESD protection circuit is sometimes provided between a power supply terminal and a ground terminal of the semiconductor device. A CFET (Complementary Field Effect Transistor) formed by stacking multiple transistors is known.

[0003] US Patent Application Publication No. 2022 / 0102479 US Patent Application Publication No. 2010 / 0142105 US Patent No. 7,969,699 US Patent No. 8,339,756 US Patent Application Publication No. 2022 / 0344263

[0004] In a semiconductor device incorporating a CFET, no detailed study has been made on how to form an ESD protection circuit using the CFET.

[0005] The present invention has been made in view of the above points, and has as its object to efficiently design the layout of elements in an ESD protection circuit and to suppress an increase in layout size.

[0006] In one aspect of the present invention, a semiconductor device includes a first power supply line, a second power supply line, a first inverter provided between the first power supply line and the second power supply line, the first inverter having an input connected to a first node and an output connected to a second node, a second inverter provided between the first power supply line and the second power supply line, the second inverter having an input connected to the second node and an output connected to the first node, a first transistor of a first conductivity type provided between the first power supply line and the second power supply line, the first transistor having an input connected to the second node, a first capacitor provided between the second node and the first power supply line, a second transistor of a second conductivity type different from the first conductivity type provided between the first power supply line and the second power supply line, the second transistor having an input connected to the first node, and a second capacitor provided between the first node and the second power supply line, wherein at least a portion of the first transistor and the first capacitor are arranged to overlap in a planar view, or at least a portion of the second transistor and the second capacitor are arranged to overlap in a planar view.

[0007] According to the disclosed technology, it is possible to efficiently design the layout of elements in an ESD protection circuit, and to suppress an increase in layout size.

[0008] 4. FIG. 5 is a circuit diagram showing an example of an ESD protection circuit applied to various embodiments described in FIG. 3 and subsequent figures. FIG. 6 is an explanatory diagram showing a legend for circuit elements of the circuit in the plan views shown in FIG. 3 and subsequent figures. FIG. 7 is a perspective view showing an example of a layout of the ESD protection circuit in the first embodiment. FIG. 8 is a plan view showing an example of a layout of a bottom layer formed on the surface of a substrate in the ESD protection circuit of FIG. 3. FIG. 9 is a plan view showing an example of a layout of a top layer formed on the circuit of the bottom layer of FIG. 4 in the ESD protection circuit of FIG. 3. FIG. 10 is a plan view showing an example of a resistor mounted in the ESD protection circuit of FIG. 1. FIG. 11 is a cross-sectional view showing an example of a cross section taken along line X1-X1' in FIGS. 3 and 4. FIG. 12 is a cross-sectional view showing another example of a cross section taken along line X1-X1' in FIGS. 3 and 4. FIG. 13 is a cross-sectional view showing an example of a cross section taken along line Y1-Y1' in FIGS. 3 and 4. FIG. 14 is a cross-sectional view showing a modified example of the cross section taken along line Y1-Y1' in FIGS. 3 and 4. FIG. 15 is a plan view showing a modified example of the ESD protection circuit ESDC shown in FIG. 1. FIG. 16 is a perspective view showing an example of a layout of the ESD protection circuit in the second embodiment. 14 is a plan view showing an example of a layout of a bottom layer formed on the surface of a substrate in the ESD protection circuit of Fig. 12. FIG. 15 is a plan view showing an example of a layout of a top layer formed on the circuit of the bottom layer of Fig. 13 in the ESD protection circuit of Fig. 12. FIG. 16 is a cross-sectional view showing an example of a cross section taken along line X2-X2' in Fig. 13 and Fig. 14. FIG. 17 is a cross-sectional view showing an example of a cross section taken along line Y2-Y2' in Fig. 13 and Fig. 14.

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line or a signal terminal. A symbol indicating a power supply voltage is also used to indicate a power supply line or a power supply terminal to which the power supply voltage is supplied.

[0010] Fig. 1 shows an example of an ESD protection circuit that is applied to various embodiments described in Fig. 3 and subsequent figures. The ESD protection circuit ESDC shown in Fig. 1 is mounted on a semiconductor device and includes a resistor bigN_R, an inverter bigN_inv, a capacitor bigP_C, a transistor bigN, a resistor bigP_R, an inverter bigP_inv, a capacitor bigN_C, and a transistor bigP.

[0011] The inverter bigP_inv is an example of either a first inverter or a second inverter, and the inverter bigN_inv is an example of the other of the first inverter or the second inverter. The transistor bigN is an example of either a first transistor or a second transistor, and the transistor bigP is an example of the other of the first transistor or the second transistor. The capacitance bigP_C is an example of either a first capacitance or a second capacitance, and the capacitance bigN_C is an example of the other of the first capacitance or the second capacitance. The resistor bigN_R is an example of either a first resistor or a second resistor, and the resistor bigP_R is an example of the other of the first resistor or the second resistor.

[0012] The PMOS transistor PM1 of the inverter bigN_inv has a gate electrode connected to the node netA, a source connected to the power supply line VDD, and a drain connected to the node netB. The NMOS transistor NM1 of the inverter bigN_inv has a gate electrode connected to the node netA, a source connected to the ground line VSS, and a drain connected to the node netB.

[0013] The power supply line VDD is an example of either a first power supply line or a second power supply line, and the ground line VSS is an example of the other of the first power supply line or the second power supply line. The node netA is an example of either a first node or a second node, and the node netB is an example of the other of the first node or the second node.

[0014] The PMOS transistor PM3 of the inverter bigP_inv has a gate electrode connected to the node netB, a source connected to the power supply line VDD, and a drain connected to the node netA. The NMOS transistor NM3 of the inverter bigP_inv has a gate electrode connected to the node netB, a source connected to the ground line VSS, and a drain connected to the node netA. That is, the output of the inverter bigN_inv is connected to the input of the inverter bigP_inv via the node netB, and the output of the inverter bigP_inv is connected to the input of the inverter bigN_inv via the node netA.

[0015] One end and the other end of the resistor bigN_R are connected to the node netA and the power supply line VDD, respectively. One end and the other end of the resistor bigP_R are connected to the node netB and the ground line VSS, respectively. The gate, source, and drain of the transistor bigN (NMOS transistor NM2) are connected to the node netB, the ground line VSS, and the power supply line VDD, respectively. The gate, source, and drain of the transistor bigP (PMOS transistor PM4) are connected to the node netA, the power supply line VDD, and the ground line VSS, respectively.

[0016] The capacitance bigP_C is formed, for example, by the gate insulating film of the PMOS transistor PM2. The gate of the PMOS transistor PM2 is connected to the net netB, and the source and drain of the PMOS transistor PM2 are connected to the power supply line VDD. The capacitance bigN_C is formed, for example, by the gate insulating film of the NMOS transistor NM4. The gate of the NMOS transistor NM4 is connected to the net netA, and the source and drain of the NMOS transistor NM4 are connected to the ground line VSS.

[0017] The PMOS transistors PM1-PM4 are an example of one of the first conductivity type and the second conductivity type, and the NMOS transistors NM1-NM4 are an example of the other of the first conductivity type and the second conductivity type.

[0018] Fig. 2 shows an example of the legend for circuit elements in the plan views shown in Fig. 3 and subsequent figures. In the plan views shown in Fig. 4 and subsequent figures, a wiring formed in a bottom layer BTM on a semiconductor substrate is referred to as a bottom wiring BTMW, and a wiring formed in a top layer TOP located above the bottom layer BTM is referred to as a top wiring TOPW. A wiring formed in a wiring layer FS1 provided above the top layer TOP is referred to as a wiring FS1, and a wiring formed in a wiring layer FS2 provided above the wiring layer FS1 is referred to as a wiring FS2.

[0019] In the plan views shown in Figure 4 and subsequent figures, vias hidden by wiring or semiconductor layers arranged above may be shown with the wiring or semiconductor layers shown transparently. Wiring FS1 is shown with a bold frame, and elements arranged on the semiconductor substrate side of wiring FS1 are shown transparently. Wiring FS2 is shown with a bold solid line.

[0020] 3 shows an example of the layout of the ESD protection circuit ESDC in the first embodiment. In FIG. 3, an interlayer insulating film is omitted, and the substrate SUB is simply indicated by a thick dashed line. The ESD protection circuit ESDC extends in the Y direction and has a ground line VSS and a power supply line VDD arranged in the X direction. For example, the ground line VSS is arranged at both ends in the X direction in the region where the ESD protection circuit ESDC is formed, and the power supply line VDD is arranged in the center in the X direction in the region where the ESD protection circuit ESDC is formed.

[0021] For example, the power supply line VDD and the ground line VSS may be formed as buried wiring BPR (Buried Power Rail) provided in the semiconductor substrate. Alternatively, the power supply line VDD and the ground line VSS may be formed as wiring in a wiring layer BS (Back Side) provided on the back side of the substrate SUB. In the first embodiment, an example is shown in which the power supply line VDD and the ground line VSS are formed by buried wiring BPR, except for FIG. 8 .

[0022] For example, on the substrate SUB, a CFET is formed by a transistor provided in a bottom layer BTM located closer to the substrate SUB and a transistor provided in a top layer TOP located farther from the substrate SUB. Fig. 3 shows an example in which a PMOS transistor is formed in the bottom layer BTM and an NMOS transistor is formed in the top layer TOP. Alternatively, an NMOS transistor may be formed in the bottom layer BTM and a PMOS transistor may be formed in the top layer TOP.

[0023] The PMOS transistor of the bottom layer BTM has a P-type semiconductor layer Pdiff which is a source S or a drain D, a gate electrode GT, and a nanosheet NS(BTM) which electrically connects the P-type semiconductor layers Pdiff arranged side by side in the Y direction via the gate electrode GT. The semiconductor layer Pdiff of the bottom layer BTM is connected to the bottom wiring BTMW. The nanosheet NS(BTM) is provided so as to penetrate the gate electrode GT.

[0024] The NMOS transistor in the top layer TOP has an N-type semiconductor layer Ndiff that is a source or drain, a gate electrode GT, and a nanosheet NS(TOP) that electrically connects the semiconductor layers Ndiff arranged side by side in the Y direction via the gate electrode GT. The semiconductor layer Ndiff in the top layer TOP is connected to a top wiring TOPW. The nanosheet NS(TOP) is provided so as to penetrate the gate electrode GT.

[0025] The gate electrode GT of the CFET is provided to cover both the nanosheet NS (TOP) of the top layer TOP and the nanosheet NS (BTM) of the bottom layer BTM. Within the gate electrode GT, a gate insulating film (not shown) is formed around the nanosheet NS. The nanosheet NS and the gate electrode GT are electrically isolated by the gate insulating film.

[0026] The PMOS and NMOS transistors of the ESD protection circuit ESDC are disposed on the substrate SUB between two buried wirings BPR in plan view. That is, the PMOS and NMOS transistors of the ESD protection circuit ESDC are disposed at positions shifted in the X direction with respect to the buried wirings BPR in plan view.

[0027] For example, two wiring layers sequentially provided above the CFET are formed with a wiring FS1 extending in the Y direction and a wiring FS2 extending in the X direction. The wirings FS1 and FS2 can be connected to the gate electrode GT, the top wiring TOPW, the bottom wiring BTMW, and the semiconductor layer Ndiff of the top layer TOP through vias VIA. The top wiring TOPW and the bottom wiring BTMW can be connected to each other through vias VIA. Furthermore, the bottom wiring BTMW and the top wiring TOPW can be connected to the buried wiring BPR through vias VIA.

[0028] The bottom wiring BTMW and the top wiring TOPW may be connected to the BS wiring via a via VIA such as a TSV (Through Silicon Via). The resistors bigN_R and bigP_R, not shown, may be formed in the same layer as the wiring FS1 or wiring FS2, or in a wiring layer above the wiring layer in which the wiring FS2 is formed. For example, the resistors bigN_R and bigP_R may be formed by multiple layers of wiring arranged in a zigzag pattern and vias that connect the multiple layers of wiring to each other.

[0029] 4 shows an example of the layout of the bottom layer BTM formed on the surface of the substrate in the ESD protection circuit ESDC of FIG. 3. The PMOS transistor is formed between the power supply line VDD and the ground line VSS of the BPR layer extending in the Y direction. In FIG. 4 and subsequent figures, the symbols in parentheses following the names of various wirings, various vias, and various semiconductor layers indicate the names of the wirings, nodes, or power supplies to which they are connected. Note that the power supply line VDD and the ground line VSS may be provided using the wiring layer BS provided on the back side of the substrate SUB.

[0030] 4, the PMOS transistor of the inverter bigN_inv and the PMOS transistor forming the capacitance bigP_C are arranged side by side in the Y direction between the ground line VSS on the left side and the power line VDD in the center. The PMOS transistor of the inverter bigN_inv and the PMOS transistor forming the capacitance bigP_C are arranged in positions that do not overlap with the vias VIA (BTMW-BPR) and VIA (TOPW-BPR) connected to the power line VDD (BPR) and the ground line VSS (BPR) in a planar view. The semiconductor layer Pdiff (VDD), which is the source of the PMOS transistor of the inverter bigN_inv, is connected to the power line VDD in the BPR layer via the bottom wiring BTMW and the via VIA (BTMW-BPR), which are arranged in the same layer as the semiconductor layer Pdiff.

[0031] The semiconductor layer Pdiff (netB) which is the drain of the PMOS transistor of the inverter bigN_inv is connected to the semiconductor layer Ndiff (netB) which is the drain of the NMOS transistor of the inverter bigN_inv shown in FIG. 5 via the bottom wiring BTMW and the via VIA (BTMW-TOPW).

[0032] The PMOS transistor of the inverter bigN_inv and the PMOS transistor of the inverter bigP_inv are an example of a third transistor. The gate electrode GT of the inverter bigN_inv and the gate electrode GT of the inverter bigP_inv are an example of a second gate electrode. The semiconductor layer Pdiff(VDD) of the inverter bigN_inv and the semiconductor layer Pdiff(VDD) of the inverter bigP_inv are an example of either a fifth semiconductor layer or a sixth semiconductor layer. The semiconductor layer Pdiff(netB) of the inverter bigN_inv and the semiconductor layer Pdiff(netA) of the inverter bigP_inv are an example of the other of the fifth semiconductor layer or the sixth semiconductor layer.

[0033] The three semiconductor layers Pdiff(VDD) that are the sources / drains of the PMOS transistors that form the capacitance bigP_C are connected to the power supply line VDD of the BPR layer via the bottom wiring BTMW and via VIA (BTMW-BPR), respectively. The semiconductor layer Pdiff(VDD) of the capacitance bigP_C adjacent to the inverter bigN_inv is provided integrally with the semiconductor layer Pdiff(VDD) of the inverter bigN_inv.

[0034] The semiconductor layer Pdiff(VDD) of the PMOS transistor that forms the capacitance bigP_C is an example of a first semiconductor layer or a second semiconductor layer. The gate electrode GT of the PMOS transistor that forms the capacitance bigP_C is an example of a first gate electrode.

[0035] The power supply line VDD of the BPR layer connected to the bottom wiring BTMW through a via VIA (BTMW-BPR) may be further connected to the top wiring TOPW in FIG. 5 through a via VIA (BTMW-TOPW).

[0036] 4, the PMOS transistor of the inverter bigP_inv and the transistor bigP are arranged side by side in the Y direction between the ground line VSS on the right side and the power supply line VDD in the center. The semiconductor layer Pdiff (VDD), which is the source of the PMOS transistor of the inverter bigP_inv, is connected to the power supply line VDD of the BPR layer through the bottom wiring BTMW and the via VIA (BTMW-BPR).

[0037] The semiconductor layer Pdiff (netA), which is the drain of the PMOS transistor of the inverter bigP_inv, is connected to the semiconductor layer Ndiff (netA), which is the drain of the NMOS transistor of the inverter bigP_inv shown in FIG. 5, via the bottom wiring BTMW and the via VIA (BTMW-TOPW).

[0038] The two semiconductor layers Pdiff(VDD) that are the sources of the transistor bigP are connected to the power supply line VDD of the BPR layer via the bottom wiring BTMW and the via VIA (BTMW-BPR), respectively. The semiconductor layer Pdiff(VSS) that is the drain of the transistor bigP is connected to the ground line VSS of the BPR layer via the bottom wiring BTMW and the via VIA (BTMW-BPR). The semiconductor layer Pdiff(VDD) of the transistor bigP adjacent to the inverter bigP_inv is provided integrally with the semiconductor layer Pdiff(VDD) of the inverter bigP_inv.

[0039] The semiconductor layer Pdiff(VDD) of the transistor bigP is an example of either the first semiconductor layer or the second semiconductor layer, and the semiconductor layer Pdiff(VSS) of the transistor bigP is an example of the other of the first semiconductor layer or the second semiconductor layer. The gate electrode GT of the transistor bigP is an example of the first gate electrode.

[0040] Fig. 5 shows an example of the layout of the top layer TOP formed on the circuit of the bottom layer BTM in Fig. 4 in the ESD protection circuit ESDC in Fig. 3. The NMOS transistor is formed between the ground line VSS and the power supply line VDD of the BPR layer extending in the Y direction.

[0041] 5, the NMOS transistor of the inverter bigN_inv and the transistor bigN are arranged side by side in the Y direction between the ground line VSS on the left side and the power supply line VDD in the center. The semiconductor layer Ndiff (VSS), which is the source of the NMOS transistor of the inverter bigN_inv, is connected to the ground line VSS of the BPR layer through the top wiring TOPW and the via VIA (TOPW-BPR).

[0042] The semiconductor layer Ndiff (netB), which is the drain of the NMOS transistor of the inverter bigN_inv, is connected to the drain of the PMOS transistor of the inverter bigN_inv in Fig. 4 via the top wiring TOPW (netB) and via VIA (BTMW-TOPW). The top wiring TOPW (netB) is connected to wiring FS2 (netB) via via VIA (FS1-TOPW), wiring FS1 (netB), and via VIA (FS1-FS2), and is further connected to wiring FS1 (netB) extending in the Y direction via via VIA (FS1-FS2).

[0043] The gate electrode GT (netA) of the NMOS transistor of the inverter bigN_inv is connected to one side of the wiring FS1 (netA) extending in the Y direction through a via VIA (FS1-GT), and is further connected to the other side of the wiring FS1 (netA) extending in the Y direction through a via VIA (FS1-FS2), a wiring FS2 (netA), and a via VIA (FS1-FS2).

[0044] The NMOS transistor of the inverter bigN_inv and the NMOS transistor of the inverter bigP_inv are an example of a fourth transistor. The semiconductor layer Ndiff(VSS) of the inverter bigN_inv and the semiconductor layer Ndiff(VSS) of the inverter bigP_inv are an example of either a seventh semiconductor layer or an eighth semiconductor layer, and the semiconductor layer Ndiff(netB) of the inverter bigN_inv and the semiconductor layer Ndiff(netA) of the inverter bigP_inv are an example of the other of the seventh semiconductor layer or the eighth semiconductor layer.

[0045] The semiconductor layer Ndiff (VSS) which is the source of the transistor bigN (NMOS transistor) is connected to the ground line VSS of the BPR layer through the top wiring TOPW (VSS) and the via VIA (TOPW-BPR). The semiconductor layer Ndiff (VSS) of the transistor bigN (NMOS transistor) adjacent to the inverter bigN_inv is provided integrally with the semiconductor layer Ndiff (VSS) of the inverter bigN_inv.

[0046] The semiconductor layer Ndiff (VDD), which is the drain of the transistor bigN (NMOS transistor), is connected to the power supply line VDD of the BPR layer via the top wiring TOPW (VDD), via VIA (BTMW-TOPW), and the bottom wiring BTMW (VDD) and via VIA (BTMW-BPR) in Figure 4. The gate electrode GT (netB) of the transistor bigN (NMOS transistor) is connected to the wiring FS1 (netB) extending in the Y direction via a via VIA (FS1-GT).

[0047] The semiconductor layer Ndiff(VSS) of the transistor bigN is an example of one of the third semiconductor layer and the fourth semiconductor layer, and the semiconductor layer Ndiff(VDD) of the transistor bigN is an example of the other of the third semiconductor layer and the fourth semiconductor layer. The gate electrode GT of the transistor bigN is an example of a first gate electrode shared with the capacitor bigP_C in FIG. 4.

[0048] 5, the NMOS transistor of the inverter bigP_inv and the NMOS transistor that forms the capacitance bigN_C are arranged side by side in the Y direction between the ground line VSS on the right side and the power supply line VDD in the center. The semiconductor layer Ndiff (VSS), which is the source of the NMOS transistor of the inverter bigP_inv, is connected to the ground line VSS of the BPR layer through the top wiring TOPW (VSS) and the via VIA (TOPW-BPR).

[0049] The semiconductor layer Ndiff (netA), which is the drain of the NMOS transistor of the inverter bigP_inv, is connected to the drain of the PMOS transistor of the inverter bigP_inv shown in Fig. 4 via the bottom wiring BTMW (netA) and via VIA (BTMW-TOPW). The top wiring TOPW (netA) is connected to wiring FS2 (netA) via via VIA (FS1-TOPW), wiring FS1 (netA), and via VIA (FS1-FS2), and is further connected to wiring FS1 (netA) extending in the Y direction via via VIA (FS1-FS2).

[0050] The gate electrode GT (netB) of the NMOS transistor of the inverter bigP_inv is connected to one side of the wiring FS1 (netB) extending in the Y direction through a via VIA (FS1-GT), and is further connected to the other side of the wiring FS1 (netB) extending in the Y direction through a via VIA (FS1-FS2), a wiring FS2 (netB), and a via VIA (FS1-FS2).

[0051] The semiconductor layer Ndiff(VSS) of the NMOS transistor forming the capacitance bigN_C is connected to the ground line VSS of the BPR layer via the top wiring TOPW and the via VIA (TOPW-BPR). Alternatively, the semiconductor layer Ndiff(VSS) of the NMOS transistor forming the capacitance bigN_C is connected to the ground line VSS of the BPR layer via the top wiring TOPW, the via VIA (BTMW-TOPW), and the bottom wiring BTMW(VSS) and the via VIA (BTMW-BPR) in FIG. 4. The semiconductor layer Ndiff(VSS) of the capacitance bigN_C adjacent to the inverter bigP_inv is provided integrally with the semiconductor layer Pdiff(VSS) of the inverter bigP_inv.

[0052] The semiconductor layer Ndiff(VSS) of the NMOS transistor forming the capacitance bigN_C is an example of the third semiconductor layer and the fourth semiconductor layer. The gate electrode GT of the NMOS transistor forming the capacitance bigN_C is an example of the first gate electrode shared with the transistor bigP in FIG.

[0053] 4 and 5, the capacitor bigP_C and the transistor bigN (NMOS transistor) are arranged to overlap each other in a planar view, and the transistor bigP (PMOS transistor) and the capacitor bigN_C are arranged to overlap each other in a planar view. This allows one CFET to be used as two functional elements, enabling the layout design of elements in the ESD protection circuit ESDC to be efficient, and suppressing an increase in layout size.

[0054] 6 shows an example of a resistor mounted in the ESD protection circuit ESDC of FIG. 1. For example, the resistor bigN_R or the resistor bigP_R has a plurality of wires W1 extending in the Y direction and arranged side by side in the X direction, and a plurality of wires W2 extending in the X direction and arranged repeatedly at both ends of the wires W1 in the Y direction. One end or the other end in the Y direction of two adjacent wires W1 is alternately connected to the wire W2 via a via VIA. This forms a zigzag-shaped resistor bigN_R or resistor bigP_R.

[0055] The resistor bigN_R or the resistor bigP_R may be formed by a wire W1 extending in the X direction and a wire W2 extending in the Y direction. The resistor bigN_R or the resistor bigP_R may be formed in a shape other than a zigzag wiring shape, or may be formed in a zigzag shape by one wire W1 (or W2) having a repeatedly bent shape.

[0056] The resistor bigN_R or the resistor bigP_R may be formed using the wirings W1 and W2 in the wiring layer above the inverters bigN_inv and bigP_inv or the wiring layer above the capacitors bigN_C and bigP_C. Furthermore, the resistor bigN_R or the resistor bigP_R may be formed using a conductor in the same layer as the gate electrode GT.

[0057] 7 shows an example of a cross section taken along line X1-X1' in Figures 3 and 4. The transistors bigP and bigN, the capacitors bigP_C and bigN_C, and the inverters bigN_inv and bigP_inv (not shown) are formed on the front surface side of the substrate SUB. The power supply line VDD (BPR) and the ground line VSS (BPR) are formed on the substrate SUB.

[0058] For example, the semiconductor layer Ndiff(VDD) of the transistor bigN and the semiconductor layer Pdiff(VDD) of the capacitance bigP_C are connected to each other via the top wiring TOPW(VDD), via VIA(BTMW-TOPW) and bottom wiring BTMW(VDD), and are further connected to the power supply line VDD(BPR) formed on the substrate SUB via the via VIA(BTMW-BPR).

[0059] Similarly, the semiconductor layer Ndiff (VSS) of the capacitor bigN_C and the semiconductor layer Pdiff (VSS) of the transistor bigP are connected to each other via the top wiring TOPW (VSS), the via VIA (BTMW-TOPW) and the bottom wiring BTMW (VSS), and are further connected to the ground line VSS (BPR) formed on the substrate SUB via the via VIA (BTMW-BPR).

[0060] Fig. 8 shows another example of a cross section taken along line X1-X1' in Fig. 3 and Fig. 4. In Fig. 8, the power supply line VDD and the ground line VSS are formed on the back surface (BS) side of the substrate SUB, not on the BPR layer in Fig. 8. In this case, the via VIA (BTMW-BS) connecting the bottom wiring BTMW and the wiring BS may be a TSV.

[0061] 9 shows an example of a cross section taken along line Y1-Y1' in FIGS. 3 and 4. The gate electrode GT (netA) on the right side of FIG. 9 is provided in common with the PMOS transistor and NMOS transistor of the inverter bigN_inv. The PMOS transistor of the inverter bigN_inv and the PMOS transistor of the capacitor bigP_C share the semiconductor layer Pdiff (VDD). Similarly, the NMOS transistor of the inverter bigN_inv and the NMOS transistor of the transistor bigN share the semiconductor layer Ndiff (VSS).

[0062] The gate electrode GT (netB) common to the transistor bigN and the capacitor bigP_C is connected to a wiring FS1 (netB) extending in the Y direction through a via VIA (FS1-GT). The wiring FS1 (netB) extending in the Y direction is connected to a wiring FS2 (netB) extending in the X direction through a via VIA (FS1-FS2), and is connected to another wiring FS1 (netB) extending in the Y direction in a cross section different from that shown in FIG.

[0063] 10 shows a modified example of the cross section taken along line Y1-Y1' in FIGS. 3 and 4. Detailed description of elements similar to those in FIG. 9 will be omitted. In the cross section shown in FIG. 10, part or all of the capacitance bigP_C of the bottom layer BTM in FIG. 9 is replaced with a dummy transistor DMY.

[0064] In the example shown in Figure 10, one PMOS transistor of the capacitor bigP_C shown in Figure 9 is replaced with a dummy transistor DMY. That is, as shown in Figures 10 and 9, the transistor bigN and part or all of the capacitor bigP_C are arranged to overlap in a planar view. Note that, although not shown, part or all of the capacitor bigN_C in Figure 5 may be replaced with a dummy transistor DMY. That is, the transistor bigP and part or all of the capacitor bigN_C may be arranged to overlap in a planar view.

[0065] Depending on the required specifications of the ESD protection circuit ESDC, the size of the capacitance bigP_C may be smaller than the size of the transistor bigN, and the size of the capacitance bigN_C may be smaller than the size of the transistor bigP. In such cases, part or all of the capacitance bigP_C may be replaced with a dummy transistor DMY at a position overlapping with the transistor bigN in a planar view. Similarly, part or all of the capacitance bigN_C may be replaced with a dummy transistor DMY at a position overlapping with the transistor bigP in a planar view.

[0066] This makes it possible to easily change the size ratio between the transistor bigN and the capacitance bigP_C, and the size ratio between the transistor bigP and the capacitance bigN_C, thereby enabling the ESD protection circuit ESDC to be designed efficiently.

[0067] 11 shows a modified example of the ESD protection circuit ESDC shown in FIG. 1. In FIG. 11, the capacitance bigP_C and the transistor bigP formed in the bottom layer BTM are expanded in the Y direction compared to FIG. 4. The number of gate electrodes GT of the capacitance bigP_C is greater than the number of gate electrodes GT of the inverter bigN_inv, and the number of gate electrodes GT of the transistor bigP is greater than the number of gate electrodes GT of the inverter bigP_inv. For example, the number of transistors (the number of gate electrodes GT) of each of the capacitance bigP_C and the transistor bigP in FIG. 11 is increased from two in FIG. 4 to six.

[0068] As shown in FIG. 11 , by expanding the capacitance bigP_C and the transistor bigP in the Y direction, it is possible to easily determine the layout configuration of the circuit according to the required electrical specifications of the ESD protection circuit ESDC, and it is possible to efficiently design the ESD protection circuit ESDC.

[0069] 11, the transistor bigN and the capacitor bigN_C formed in the top layer TOP in FIG. 5 can be expanded in the Y direction, and the ESD protection circuit ESDC can be designed efficiently. In this case, the number of gate electrodes GT of the transistor bigN is greater than the number of gate electrodes GT of the inverter bigN_inv, and the number of gate electrodes GT of the capacitor bigN_C is greater than the number of gate electrodes GT of the inverter bigP_inv.

[0070] As described above, in the first embodiment, in the ESD protection circuit ESDC having a CFET structure, the capacitor bigP_C and the transistor bigN are arranged to overlap in a planar view, and the transistor bigP and the capacitor bigN_C are arranged to overlap in a planar view. This allows one CFET to be used as two functional elements. As a result, the elements in the ESD protection circuit ESDC can be efficiently designed in a layout, and an increase in layout size can be suppressed.

[0071] By replacing part or all of the capacitance bigP_C with a dummy transistor DMY at a position overlapping with the transistor bigN in a plan view, the size ratio between the transistor bigN and the capacitance bigP_C can be easily changed. Also, by replacing part or all of the capacitance bigN_C with a dummy transistor DMY at a position overlapping with the transistor bigP in a plan view, the size ratio between the transistor bigP and the capacitance bigN_C can be easily changed. As a result, the ESD protection circuit ESDC can be designed efficiently.

[0072] By expanding the capacitance bigP_C and the transistor bigP in the Y direction, it is possible to easily determine the layout configuration of the circuit according to the required electrical specifications of the ESD protection circuit ESDC. Similarly, by expanding the transistor bigN and the capacitance bigN_C in the Y direction, it is possible to easily determine the layout configuration of the circuit according to the required electrical specifications of the ESD protection circuit ESDC. As a result, it is possible to efficiently design the ESD protection circuit ESDC.

[0073] Second Embodiment Fig. 12 shows an example of the layout of an ESD protection circuit according to a second embodiment. Elements similar to those in Fig. 3 are given the same reference numerals, and detailed description thereof will be omitted.

[0074] 12, the ground lines VSS and power supply lines VDD are formed using a wiring layer BS provided on the back surface of the substrate SUB. Ground lines VSS are arranged at both ends and in the center in the X direction, and power supply lines VDD are arranged between the ground lines VSS at both ends and in the center in the X direction, at positions that overlap each CFET in plan view. That is, the ESD protection circuit ESDC has ground lines VSS and power supply lines VDD that are alternately arranged in the X direction.

[0075] In the PMOS transistor of the bottom layer BTM, a semiconductor layer Pdiff to which a power supply voltage VDD is supplied is connected to a power supply line VDD (BS) that overlaps the semiconductor layer Pdiff in a planar view through a via VIA (Pdiff-BS) such as a TSV. The capacitors bigP_C, bigN_C, transistors bigP, bigN, inverter bigN_inv, and inverter bigP_inv mounted in the ESD protection circuit ESDC are the same as those in the first embodiment, except that the positions of some of the connected wiring and vias are different.

[0076] Fig. 13 shows an example of the layout of the bottom layer BTM formed on the surface of the substrate in the ESD protection circuit ESDC of Fig. 12. The same elements as in Fig. 4 are given the same reference numerals, and detailed description thereof will be omitted. The layout of the capacitor bigP_C, the transistor bigP, and the PMOS transistors of the inverters bigN_inv and bigP_inv is the same as in Fig. 4.

[0077] In the ESD protection circuit ESDC of the second embodiment, a power supply line VDD (BS) is arranged below the CFET, and a semiconductor layer Pdiff, which is the source of a PMOS transistor arranged in the bottom layer BTM, is provided at a position overlapping in plan view with a via VIA (Pdiff-BS) connected to the power supply line VDD (BS).

[0078] The source / drain of the PMOS transistor forming the capacitance bigP_C, the source of the transistor bigP, the source of the PMOS transistor of the inverter bigN_inv, and the source of the PMOS transistor of the inverter bigP_inv are each connected to the power supply line VDD (BS) through a via VIA (Pdiff-BS). This allows the semiconductor layer Pdiff of the PMOS transistor arranged in the bottom layer BTM to be connected to the power supply line VDD (BS) through the via VIA (Pdiff-BS) without using the bottom wiring BTMW.

[0079] The supply of the power supply voltage VDD to the top wiring TOPW (VDD) (not shown) is performed via the power supply line VDD (BS), the via VIA (Pdiff-BS), the semiconductor layer Pdiff (VDD), the bottom wiring BTMW (VDD), and the via VIA (BTMW-TOPW). The supply of the ground voltage VSS to the top wiring TOPW (VSS) (not shown) is performed via the ground line VSS (BS) and the via VIA (TOPW-BS), or via the ground line VSS (BS), the via VIA (BTMW-BS), the bottom wiring BTMW (VSS), and the via VIA (BTMW-TOPW).

[0080] By arranging the power supply line VDD at a position overlapping the PMOS transistor in a plan view and connecting the PMOS transistor and the power supply line with a via VIA (Pdiff-BS) such as a TSV without using bottom wiring BTMW, the layout density of the power supply line VDD (BS) and ground line VSS (BS) formed on the back surface of the substrate SUB can be made higher than in Fig. 4. This makes it possible to reduce the circuit area of ​​the ESD protection circuit ESDC.

[0081] 11, in the second embodiment, the capacitor bigP_C and the transistor bigP formed in the bottom layer BTM may be extended in the Y direction, which makes it possible to easily determine the layout configuration of the circuit according to the required electrical specifications of the ESD protection circuit ESDC, and to efficiently design the ESD protection circuit ESDC.

[0082] Furthermore, when an NMOS transistor is formed in the bottom layer BTM, a ground line VSS may be arranged at a position overlapping the NMOS transistor in a plan view, and the semiconductor layer Ndiff of the NMOS transistor and the ground line VSS (BS) may be connected through a via VIA (Ndiff-BS) without using the bottom wiring BTMW. In this case as well, the arrangement density of the power supply line VDD (BS) and the ground line VSS (BS) formed on the back surface of the substrate SUB can be made higher than in Figure 4, and the circuit area of ​​the ESD protection circuit ESDC can be reduced.

[0083] Fig. 14 shows an example of the layout of the top layer TOP formed on the circuit of the bottom layer BTM of Fig. 13 in the ESD protection circuit of Fig. 12. The same elements as in Fig. 5 are given the same reference numerals, and detailed description will be omitted. The arrangement of the transistor bigN, the capacitance bigN_C, and the NMOS transistors of the inverters bigN_inv and bigP_inv is the same as in Fig. 5.

[0084] For example, the semiconductor layer Ndiff (netB), which is the drain of the NMOS transistor of the inverter bigN_inv, is connected to the wiring FS1 (netB) extending in the Y direction via the top wiring TOPW (netB), the via VIA (FS2-TOPW), the wiring FS2 (netB), and the via VIA (FS1-FS2). Similarly, the semiconductor layer Ndiff (netA), which is the drain of the NMOS transistor of the inverter bigP_inv, is connected to the wiring FS1 (netA) extending in the Y direction via the top wiring TOPW (netA), the via VIA (FS2-TOPW), the wiring FS2 (netA), and the via VIA (FS1-FS2).

[0085] Note that the ground voltage VSS is supplied to the top layer TOP from the ground line VSS(BS) in the center of Fig. 14, but may also be supplied from the ground lines VSS(BS) on both sides of Fig. 14. Also, the transistor bigN and the capacitor bigN_C formed in the top layer TOP may be extended in the Y direction. This makes it possible to easily determine the layout configuration of the circuit according to the required electrical specifications of the ESD protection circuit ESDC, and to efficiently design the ESD protection circuit ESDC.

[0086] Figure 15 shows an example of a cross section taken along line X2-X2' in Figures 13 and 14. Elements similar to those in Figure 8 are given the same reference numerals, and detailed descriptions will be omitted. The arrangement of capacitors bigP_C, bigN_C and transistors bigP, bigN is the same as in Figure 8.

[0087] 15 is similar to FIG. 8 except that the supply path of the power supply voltage VDD to the transistor bigN and the capacitor bigP_C and the supply path of the ground voltage VSS to the capacitor bigN_C and the transistor bigP are different from those in FIG.

[0088] Fig. 16 shows an example of a cross section taken along line Y2-Y2' in Fig. 13 and Fig. 14. The same elements as in Fig. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted. The arrangement of the capacitor bigP_C, the transistor bigN, and the inverter bigN_inv is the same as in Fig. 9.

[0089] In the second embodiment, the power supply line VDD (BS) is arranged at a position overlapping each transistor in a plan view. Therefore, for example, the semiconductor layer Pdiff (VDD) of the capacitor bigP_C and the semiconductor layer Pdiff (VDD) of the PMOS transistor of the inverter bigN_inv are connected to the power supply line VDD (BS) through a via VIA (Pdiff-BS).

[0090] As described above, the second embodiment can also achieve the same effects as the first embodiment. For example, in an ESD protection circuit ESDC having a CFET structure, one CFET can be used as two functional elements, allowing for an efficient layout design of elements in the ESD protection circuit ESDC. As a result, an increase in layout size can be suppressed.

[0091] Furthermore, in the second embodiment, by arranging the power supply line VDD at a position overlapping the PMOS transistor in a plan view, the PMOS transistor and the power supply line can be connected by a via VIA (Pdiff-BS) such as a TSV without using a bottom wiring BTMW. This makes it possible to increase the arrangement density of the power supply line VDD and the ground line VSS formed on the back surface of the substrate SUB compared to FIG. 4, and to reduce the circuit area of ​​the ESD protection circuit ESDC.

[0092] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0093] bigN transistor bigN_C capacitance bigN_inv inverter bigN_R resistance bigP transistor bigP_C capacitance bigP_inv inverter bigP_R resistance BPR buried wiring BS wiring layer BTM bottom layer BTMW bottom wiring DMY dummy transistor ESDC ESD protection circuit FS1 wiring, wiring layer FS2 wiring, wiring layer GT gate electrode Ndiff semiconductor layer netA, netB node NM, NM1, NM2, NM3, NM4 NMOS transistor NS nanosheet Pdiff semiconductor layer PM, PM1, PM2, PM3, PM4 PMOS transistor SUB substrate TOP top layer TOPW top wiring VDD Power line, power supply voltage VIA Via VSS Ground line, ground voltage W1, W2 Wiring

Claims

1. A semiconductor device comprising: a first power supply line; a second power supply line; a first inverter provided between the first power supply line and the second power supply line, the input connected to a first node and the output connected to a second node; a second inverter provided between the first power supply line and the second power supply line, the input connected to the second node and the output connected to the first node; a first transistor of a first conductivity type provided between the first power supply line and the second power supply line, the input connected to the second node; a first capacitor provided between the second node and the first power supply line; a second transistor of a second conductivity type different from the first conductivity type provided between the first power supply line and the second power supply line, the input connected to the first node; and a second capacitor provided between the first node and the second power supply line, wherein at least a portion of the first transistor and the first capacitor are arranged to overlap in a planar view, or at least a portion of the second transistor and the second capacitor are arranged to overlap in a planar view.

2. The semiconductor device according to claim 1, wherein the first capacitor has a first semiconductor layer, a second semiconductor layer, and a first gate electrode provided on a substrate, and the first transistor has a third semiconductor layer, a fourth semiconductor layer, and the first gate electrode provided on the first semiconductor layer and the second semiconductor layer.

3. The semiconductor device according to claim 2, wherein the first inverter comprises a third transistor having a fifth semiconductor layer, a sixth semiconductor layer, and a second gate electrode on the substrate, and a fourth transistor having a seventh semiconductor layer, an eighth semiconductor layer, and the second gate electrode provided on the fifth semiconductor layer and the sixth semiconductor layer, and the number of the first gate electrodes is greater than the number of the second gate electrodes.

4. The semiconductor device according to claim 3, wherein one of the first semiconductor layer or the second semiconductor layer is provided integrally with one of the fifth semiconductor layer or the sixth semiconductor layer, and one of the third semiconductor layer or the fourth semiconductor layer is provided integrally with one of the seventh semiconductor layer or the eighth semiconductor layer.

5. The semiconductor device according to claim 1, wherein the second transistor has a first semiconductor layer, a second semiconductor layer, and a first gate electrode provided on a substrate, and the second capacitor has a third semiconductor layer, a fourth semiconductor layer, and the first gate electrode provided on the first semiconductor layer and the second semiconductor layer.

6. The semiconductor device according to claim 5, wherein the second inverter comprises a third transistor having a fifth semiconductor layer, a sixth semiconductor layer, and a second gate electrode on the substrate, and a fourth transistor having a seventh semiconductor layer, an eighth semiconductor layer, and the second gate electrode provided on the fifth semiconductor layer and the sixth semiconductor layer, and the number of the first gate electrodes is greater than the number of the second gate electrodes.

7. The semiconductor device according to claim 6, wherein one of the first semiconductor layer or the second semiconductor layer is provided integrally with one of the fifth semiconductor layer or the sixth semiconductor layer, and one of the third semiconductor layer or the fourth semiconductor layer is provided integrally with one of the seventh semiconductor layer or the eighth semiconductor layer.

8. A semiconductor device according to any one of claims 1 to 7, wherein the first inverter, the second inverter, the first transistor, the first capacitor, the second transistor, and the second capacitor are formed on the front surface side of a substrate, and the first power supply line and the second power supply line are formed on the substrate.

9. A semiconductor device according to any one of claims 1 to 7, wherein the first inverter, the second inverter, the first transistor, the first capacitor, the second transistor, and the second capacitor are formed on the front surface side of a substrate, and the first power supply line and the second power supply line are formed on the back surface side of the substrate.

10. A semiconductor device according to any one of claims 2 to 7, wherein the first power supply line and the second power supply line are formed on the back surface side of the substrate, at least one of the first semiconductor layer and the second semiconductor layer is provided in a position that does not overlap in a planar view with a via that penetrates the substrate, and at least one of the first power supply line and the second power supply line is connected to at least one of the first semiconductor layer and the second semiconductor layer via the via and wiring provided in the same layer as the first semiconductor layer and the second semiconductor layer.

11. The semiconductor device according to any one of claims 3, 4, 6 and 7, wherein the first power supply line and the second power supply line are formed on the back surface side of the substrate, at least one of the fifth semiconductor layer and the sixth semiconductor layer is provided at a position that does not overlap in a planar view with a via that penetrates the substrate, and at least one of the first power supply line and the second power supply line is connected to at least one of the fifth semiconductor layer and the sixth semiconductor layer via the via and wiring provided in the same layer as the fifth semiconductor layer and the sixth semiconductor layer.

12. A semiconductor device according to any one of claims 2 to 7, wherein the first power supply line and the second power supply line are formed on the back surface side of the substrate, at least one of the first semiconductor layer and the second semiconductor layer is provided in a position that overlaps in a planar view with a via that penetrates the substrate, and at least one of the first power supply line and the second power supply line is connected to at least one of the first semiconductor layer and the second semiconductor layer through the via.

13. A semiconductor device according to any one of claims 3, 4, 6 and 7, wherein the first power supply line and the second power supply line are formed on the back surface side of the substrate, at least one of the fifth semiconductor layer and the sixth semiconductor layer is provided at a position overlapping in a planar view with a via that penetrates the substrate, and at least one of the first power supply line and the second power supply line is connected to at least one of the fifth semiconductor layer and the sixth semiconductor layer through the via.

14. The semiconductor device according to any one of claims 1 to 7, comprising: a first resistor provided between the first power supply line and the first node; and a second resistor provided between the second power supply line and the second node.

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