Semiconductor device

Abstract

This semiconductor device includes: a first wiring layer which is formed on a front surface or a rear surface of a substrate; first and second power supply lines; an inverter which is located between the first and second power supply lines; a capacitor which is located between the first power supply line and an input of the inverter; a resistor which is located between the second power supply line and an input of the inverter; and a thin film transistor which is located between the first and second power supply lines and is connected to an output of the inverter, the thin film transistor being formed on the first wiring layer. This makes it possible to appropriately form an ESD protection circuit by using TFT.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] BACKGROUND ART Semiconductor devices are known that include an electrostatic discharge (ESD) protection circuit that prevents damage to elements due to electrostatic discharge (ESD). Techniques for forming transistors such as thin film transistors (TFTs) on wiring layers are known.

[0003] U.S. Patent No. 10,304,821 U.S. Patent No. 9,530,769 U.S. Patent Application Publication No. 2022 / 0271026 U.S. Patent No. 1,621,556

[0004] In semiconductor devices incorporating thin film transistors, no detailed study has been made on how to form an ESD protection circuit using thin film transistors.

[0005] The present invention has been made in view of the above points, and has as its object to appropriately form an ESD protection circuit using thin film transistors.

[0006] In one aspect of the present invention, a semiconductor device includes a substrate, a first wiring layer formed on a front or back surface of the substrate, a first power supply line, a second power supply line, an inverter arranged between the first power supply line and the second power supply line, a capacitor arranged between the first power supply line and the input of the inverter, a resistor arranged between the second power supply line and the input of the inverter, and a thin film transistor arranged between the first power supply line and the second power supply line and connected to the output of the inverter, wherein the thin film transistor is formed in the first wiring layer.

[0007] According to the disclosed technology, an ESD protection circuit can be appropriately formed using thin film transistors.

[0008] 9 is a circuit diagram showing an example of an ESD protection circuit. It is an explanatory diagram showing a legend for circuit elements of the circuits shown in FIG. 3 and subsequent figures. It is an exploded plan view showing an example of a circuit layout of an ESD protection circuit formed in a semiconductor device according to a first embodiment. It is a cross-sectional view showing an example of a cross section taken along line X1-X1' and line X2-X2' in FIG. 3. It is a plan view showing an example of a resistor and a capacitor mounted in the ESD protection circuit of FIG. 1. It is a cross-sectional view showing an example of a cross-sectional structure of a TFT operating as a PMOS transistor or an NMOS transistor in FIG. 1. It is a plan view showing a first modified example of the circuit layout of the ESD protection circuit formed in the semiconductor device according to the first embodiment. It is a plan view showing a second modified example of the circuit layout of the ESD protection circuit formed in the semiconductor device according to the first embodiment. It is a plan view showing an example of a circuit layout of an inverter in an ESD protection circuit formed in a semiconductor device according to a second embodiment. It is a cross-sectional view showing an example of a cross section taken along line X3-X3' and line X4-X4' in FIG. It is an exploded plan view showing an example of a circuit layout of an ESD protection circuit formed in a semiconductor device according to a third embodiment. 12A and 12B are cross-sectional views showing examples of cross sections taken along lines X5-X5' and X6-X6' in FIG. 11.

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line or a signal terminal. A symbol indicating a power supply potential is also used to indicate a power supply line or a power supply terminal to which the power supply potential is supplied.

[0010] First Embodiment Fig. 1 shows an example of an ESD protection circuit. The ESD protection circuit ESDC1 shown in Fig. 1 includes a capacitor C1, a resistor R1, an inverter IV1, and a PMOS transistor PM1. The capacitor C1 and the resistor R1 are connected in series between a power supply line VDD and a ground line VSS, and function as an RC time constant circuit. The inverter IV1 has an input IN connected to one end of the capacitor C1 and one end of the resistor R1, and an output OUT connected to the gate of the PMOS transistor PM1. The source and substrate of the PMOS transistor PM1 are connected to the power supply line VDD, and the drain is connected to the ground line VSS.

[0011] In the ESD protection circuit ESDC1, during system operation of the semiconductor device, the input IN of the inverter IV1 is pulled down to a low level via the resistor R1, and the output OUT of the inverter IV1 outputs a high level. The PMOS transistor PM1 receives a high level at its gate and is turned off.

[0012] During an ESD event in which a positive ESD voltage is applied between the power supply line VDD and the ground line VSS, the inverter IV1 receives a high level at the input IN due to the coupling action of the capacitor C1 and outputs a low level from the output OUT. The PMOS transistor PM1 receives a high level at its source and a low level at its gate, turning on and allowing an ESD current to flow from the power supply line VDD to the ground line VSS. The power supply line VDD of the ESD protection circuit ESDC1 is an example of a first power supply line, and the ground line VSS of the ESD protection circuit ESDC1 is an example of a second power supply line.

[0013] The ESD protection circuit ESDC2 includes a resistor R1, a capacitor C1, an inverter IV1, and an NMOS transistor NM1. The resistor R1 and the capacitor C1 are connected in series between the power supply line VDD and the ground line VSS, and function as an RC time constant circuit. The inverter IV1 has an input IN connected to one end of the resistor R1 and one end of the capacitor C1, and an output OUT connected to the gate of the NMOS transistor NM1. The NMOS transistor NM1 has a drain connected to the power supply line VDD, and a source and a substrate connected to the ground line VSS.

[0014] In the ESD protection circuit ESDC2, during system operation of the semiconductor device, the input IN of the inverter IV1 is pulled up to a high level via the resistor R1, and the output OUT of the inverter IV1 outputs a low level. The NMOS transistor NM1 receives a low level at its gate and turns off. During an ESD event in which a positive ESD voltage is applied between the power supply line VDD and the ground line VSS, the input IN of the inverter IV1 is considered to be a low level due to the RC time constant formed by the resistor R1 and the capacitor C1, and the output OUT of the inverter IV1 outputs a high level. The NMOS transistor NM1 receives a low level at its source and a high level at its gate and turns on, causing an ESD current to flow from the power supply line VDD to the ground line VSS. The ground line VSS of the ESD protection circuit ESDC2 is an example of a first power supply line, and the power supply line VDD of the ESD protection circuit ESDC1 is an example of a second power supply line.

[0015] Although an example of the circuit layout of the ESD protection circuit ESDC1 including the PMOS transistor PM1 will be described below, it may also be applied to the circuit layout of the ESD protection circuit ESDC2 including the NMOS transistor NM1. In this case, the polarity of the semiconductor layer of the NMOS transistor NM1 is opposite to that of the semiconductor layer of the PMOS transistor PM1.

[0016] Fig. 2 shows a legend for the circuit elements of the circuits shown in Fig. 3 and subsequent figures. For ease of understanding, Fig. 2 shows the shapes of the elements used in each of four layers (layer A, layer B, layer C, and layer D). For example, layers A to D may be arranged in this order on the front surface side of the substrate.

[0017] For example, the inverter IV1 in FIG. 1 may be formed on the A layer. The A layer is provided with a fin FIN, a gate electrode GT, a local wiring LI, a via VA1, and a wiring WA1 arranged from the side closest to a substrate such as a silicon substrate. Furthermore, the A layer may be provided with a via VA2 connected to the wiring WA1 and a wiring WA2 connected to the via VA2. In this case, the via VA2 may be a TSV (Through Silicon Via) that penetrates the substrate. The inverter IV1 on the A layer may be formed by a thin film transistor (hereinafter, referred to as a TFT).

[0018] On layer B, from the side closest to the substrate, via VB1, wiring WB1, via VB2, and wiring WB2 are arranged. For example, resistor R1 in FIG. 1 may be formed on layer B. In this case, a region Res for forming resistor R1 is provided on layer B.

[0019] In the C layer, from the side closest to the substrate, a via VC1, a wiring WC1, a via VC2, and a wiring WC2 are arranged. For example, the PMOS transistor PM1 or the NMOS transistor NM1 in FIG. 1 may be formed by a TFT in the C layer. In this case, a gate electrode GT (TFT), a semiconductor layer SEML (TFT), and a gate insulating film GINS (TFT) for the TFT are arranged in the C layer.

[0020] In layer D, from the side closest to the substrate, via VD1, wiring WD1, via VD2, and wiring WD2 are arranged. For example, layer D may have capacitance C1 of FIG. 1 formed therein. In this case, layer D has an area Cap for forming capacitance C1.

[0021] 3 shows an example of a circuit layout of an ESD protection circuit formed in the semiconductor device according to the first embodiment. The layouts of layers A to D are shown in FIG. The dashed rectangles extending in the X direction shown in layers B, C, and D indicate wiring WA1 on layer A. Note that in FIG. 3, to make the vias easier to understand, vias located below wiring are positioned above the wiring.

[0022] In layer A, the channels below the source S, drain D, and gate electrode GT of each of the PMOS transistor and NMOS transistor of inverter IV1 are formed by fins FIN extending in the X direction. The source S and drain D are connected to the channels via the fins FIN.

[0023] The PMOS transistor (hereinafter referred to as PMOS) of the inverter IV1 has a source S connected to the power supply line VDD (WA1) via the local wiring LI and the via VA1, and a drain D connected to the output OUT (WA1) via the local wiring LI and the via VA1. The NMOS transistor (hereinafter referred to as NMOS) of the inverter IV1 has a source S connected to the ground line VSS (WA1) via the local wiring LI and the via VA1, and a drain D connected to the output OUT (WA1) via the local wiring LI and the via VA1.

[0024] The gate electrode GT of the inverter IV1 is connected to the input IN (WA1) through a via VA1. Note that another inverter, another PMOS, or another NMOS may be formed adjacent to the region where the inverter IV1 is formed on the A layer.

[0025] In the B layer, a meandering wiring is formed in the region Res where the resistor R1 is formed, and is shown in Fig. 3 as a rectangular frame with dashed lines. One end of the wiring for the resistor R1 in the region Res is connected to via VB2, wiring WB2, via VB2, wiring WB1, and via VB1, and the via VB1 is further connected to the input IN (WA1). The other end of the wiring for the resistor R1 in the region Res is connected to via VB2, wiring WB2, via VB2, wiring WB1, and via VB1, and the via VB1 is further connected to the ground line VSS (WA1).

[0026] The size of the PMOS (TFT) provided in the C layer for discharge during an ESD event is larger than the size of the PMOS of the inverter IV1, and is therefore indicated as big-PMOS in Fig. 3. The C layer in which the big-PMOS is formed is an example of a first wiring layer.

[0027] In layer C, the source S (semiconductor layer SEML) of the PMOS (TFT) is connected to via VC2, wiring WC2, via VC2, wiring WC1, and via VC1. Furthermore, via VC1 is connected to the ground line VSS (WA1) via wiring WB2, via VB2, wiring WB1, and via VB1 (not shown).

[0028] The drain D (semiconductor layer SEML) of the PMOS (TFT) is connected to the via VC2, the wiring WC2, the via VC2, the wiring WC1, and the via VC1. Furthermore, the via VC1 is connected to the power supply line VDD (WA1) through the wiring WB2, the via VB2, the wiring WB1, and the via VB1 (not shown).

[0029] The gate electrode GT of the PMOS (TFT) is connected to the via VC2, the wiring WC2, the via VC2, the wiring WC1, and the via VC1. Furthermore, the via VC1 is connected to the output OUT (WA1) through the wiring WB2, the via VB2, the wiring WB1, and the via VB1 (not shown).

[0030] In the D layer, in the area Cap where the capacitance C1 is formed, for example, comb-shaped wiring is formed, which is indicated by a rectangular frame of two-dot chain lines in Fig. 3. One end of the wiring for the capacitance C1 in the area Cap is connected to via VD2, wiring WD2, via VD2, wiring WD1, and via VD1. Furthermore, via VD1 is connected to the input IN (WA1) via wiring WC2, via VC2, wiring WC1, via VC1, wiring WB2, via VB2, wiring WB1, and via VB1 (not shown).

[0031] The other end of the wiring for the capacitance C1 in the region Cap is connected to the via VD1 via the via VD2, the wiring WD2, the via VD2, and the wiring WD1. Furthermore, the via VD1 is connected to the power supply line VDD (WA1) via the wiring WC2, the via VC2, the wiring WC1, the via VC1, the wiring WB2, the via VB2, the wiring WB1, and the via VB1 (not shown).

[0032] 4 shows an example of a cross section taken along line X1-X1' and line X2-X2' in FIG. 3. In the example shown in FIG. 4, layers A, B, C, and D are arranged in this order on the front surface side of the substrate SUB. An input IN (WA1) connected to a gate electrode GT of the inverter IV1 is connected to one end of a resistor R1 and one end of a capacitor C1 through various vias and wiring from layers A to D. An output OUT (WA1) connected to a drain D of the inverter IV1 is connected to the gate electrode GT of the big-PMOS through various vias and wiring from layers A to C.

[0033] By forming the big-PMOS using TFTs, it is possible to reduce the number of transistors formed on the substrate SUB, and the size of the ESD protection circuit ESDC1 can be made smaller than when the big-PMOS is formed on the substrate SUB using fins, etc. Note that the B layer, C layer, and D layer on the A layer may be arranged in an order different from that shown in FIG.

[0034] Fig. 5 shows an example of the resistor R1 and the capacitor C1 mounted in the ESD protection circuit of Fig. 1. Note that the resistor R1 and the capacitor C1 shown in Fig. 5 and modified examples of the resistor R1 and the capacitor C1 described below may be applied to modified examples of the ESD protection circuit and other embodiments described later.

[0035] For example, the resistor R1 has a plurality of wirings WB1 extending in the Y direction and arranged side by side in the X direction within the region Res. For example, the wirings WB1 arranged at one end in the X direction are connected to the input IN, and the wirings WB1 arranged at the other end in the X direction are connected to the ground line VSS.

[0036] The resistor R1 has a plurality of wires WB2 arranged repeatedly and extending in the X direction at both ends of the wire WB1 in the Y direction within the region Res. The zigzag resistor R1 is formed by alternately connecting one end or the other end of two adjacent wires WB1 in the Y direction to the wire WB2 via vias VB2.

[0037] The resistor R1 may be formed by a wire WB1 extending in the X direction and a wire WB2 extending in the Y direction. The resistor R1 may be formed in a shape other than a zigzag wiring shape, or may be formed in a zigzag shape by one wire WB1 (or WB2) having a repeatedly bent shape.

[0038] For example, the capacitor C1 has a plurality of wirings WD1 extending in the Y direction and arranged side by side in the X direction. For example, the odd-numbered wirings WD1 from the left side of FIG. 5 are connected to the input IN, and the even-numbered wirings WD1 from the left side of FIG. 5 are connected to the power supply line VDD. The capacitor C1 also has comb-shaped wirings WD2(1) whose teeth protrude in the Y direction and are arranged so as to overlap the odd-numbered wirings WD1 in a planar view, and comb-shaped wirings WD2(2) whose teeth protrude in the direction opposite to the Y direction and are arranged so as to overlap the even-numbered wirings WD1 in a planar view. The comb teeth of the wirings WD2(1) and WD(2) are arranged so as to interdigitate with each other at a predetermined interval.

[0039] The even-numbered wirings WD1 from the left are connected to the first wiring WD2 through vias VD2 at one end in the Y direction, and the odd-numbered wirings WD1 from the left are connected to the second wiring WD2 through vias VD2 at the other end in the Y direction. As a result, capacitances C1 are formed between adjacent wirings WD1, between the comb teeth of a pair of adjacent wirings WD2, and between the wirings WD1 and WD2 that overlap in plan view.

[0040] Note that a plurality of wirings WD1 may be connected to one of the power supply line VDD or the input IN, and a plurality of wirings WD2 may be connected to the other of the power supply line VDD or the input IN, with a capacitance C1 formed by the opposing portions of the wirings WD1 and WD2. Alternatively, a plurality of wirings WD1 may be alternately connected to the input IN and the power supply line VDD, with a capacitance C1 formed between adjacent wirings WD1. In this case, a pair of comb-like wirings WD1 whose comb teeth interdigitate with each other may be formed. Furthermore, a plurality of wirings WD2 may be alternately connected to the input IN and the power supply line VDD, with a capacitance C1 formed between adjacent wirings WD2. In this case, a pair of comb-like wirings WD2 whose comb teeth interdigitate with each other may be formed.

[0041] Fig. 6 shows an example of a cross-sectional structure of a TFT that operates as the PMOS transistor PM1 or the NMOS transistor NM1 in Fig. 1. Note that the cross-sectional structure of a TFT that operates as the NMOS transistor NM1 in Fig. 1 can be shown by interchanging the source and drain of the semiconductor layer SEML in Fig. 6.

[0042] Fig. 6(a) shows an example of a TFT formed using two wiring layers Top and 2nd. Figs. 6(b) to 6(e) show examples of a TFT formed using three wiring layers Top, 2nd, and 3rd. In Figs. 6(b) to 6(e), vias and wiring connected to the gate electrode GT are omitted. Note that the cross-sectional structures of the TFTs shown in Figs. 6(a) to 6(e) are examples, and the TFT may be formed using various structures formed in the wiring layers.

[0043] The source S and drain D of the TFT shown in FIG. 6A are formed by a semiconductor layer SEML disposed on an insulating film INS. The source S and drain D are connected to a power supply line VDD and a ground line VSS formed in the wiring layer Top through vias VIA, respectively. The semiconductor layer SEML is made of, for example, IGZO (In, Ga, Zn, O) or graphene. The gate electrode GT of the TFT is formed on the semiconductor layer SEML via a gate insulating film GINS. For example, the TFT shown in FIG. 6A may be formed as a TFT in the C layer of FIGS. 3 and 4 .

[0044] 6B, the semiconductor layer SEML of the TFT is formed between the wiring layers 2nd and 3rd. The gate insulating film GINS and gate electrode GT of the TFT are sequentially formed on the semiconductor layer SEML. The source S and drain D of the semiconductor layer SEML are connected to the wiring of the wiring layer 2nd through vias VIA, and are further connected to the power supply line VDD and ground line VSS formed in the wiring layer Top through vias VIA.

[0045] 6C, the semiconductor layer SEML of the TFT is formed below the wiring layer 3rd. The gate insulating film GINS and gate electrode GT of the TFT are sequentially formed on the semiconductor layer SEML. The source S and drain D of the semiconductor layer SEML are connected to the wiring of the wiring layer 3rd through vias VIA, and are further connected to the power supply line VDD and ground line VSS formed in the wiring layer 2nd or the wiring layer TOP through vias VIA.

[0046] The semiconductor layer SEML of the TFT shown in Figures 6(d) and (e) is formed at the same position in the Z direction as the wiring of the wiring layer 2nd. A gate insulating film GINS and a gate electrode GT are sequentially formed on the lower surface of the semiconductor layer SEML. The source S and drain D of the semiconductor layer SEML of the TFT shown in Figure 6(d) are directly connected to the wiring of the wiring layer 2nd, and are connected to the power supply line VDD and the ground line VSS formed in the wiring layer Top through vias VIA. The source S and drain D of the semiconductor layer SEML of the TFT shown in Figure 6(e) are connected to the power supply line VDD and the ground line VSS of the wiring layers Top and 3rd through vias VIA.

[0047] 7 shows a first modified example of the circuit layout of the ESD protection circuit ESDC1 formed in the semiconductor device of the first embodiment. The same elements as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. In the ESD protection circuit ESDC1 of FIG. 1, FIG. 7 is the same as FIG. 3 except that the layout of layer A differs from the layout of layer A in FIG. 3 and does not have layer D in which capacitance C1 is formed in FIG. 3. The layouts of layers B and C (not shown) are the same as the layouts of layers B and C in FIG. 3, respectively.

[0048] In FIG. 7, the capacitor C1 is formed in the A layer using the gate insulating film of a transistor. The region Cap in which the capacitor C1 is formed is disposed adjacent to the region in which the inverter IV1 is formed. One end of the capacitor C1, the source S / drain D, is connected to the input IN (WA1) through a via VA1. The other end of the capacitor C1, the gate electrode GT, is connected to the power supply line VDD (WA1) through a via VA1. By forming the capacitor C1 in the A layer using the gate insulating film of a transistor, it is possible to omit the formation of the D layer shown in FIG. 3, or to omit forming the capacitor C1 in the D layer.

[0049] 8 shows a second modified example of the circuit layout of the ESD protection circuit ESDC1 formed in the semiconductor device of the first embodiment. The same elements as those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. In the ESD protection circuit ESDC1 of FIG. 1, FIG. 8 is the same as FIG. 3 except that the layout of layer A differs from the layout of layer A in FIG. 3 and does not include layer B in which resistor R1 is formed in FIG. 3. The layouts of layers C and D, not shown, are the same as the layouts of layers C and D, respectively, in FIG. 3.

[0050] In FIG. 8 , resistor R1 is formed in layer A using the gate electrode material of a transistor. The region Res where resistor R1 is formed is located adjacent to the region where inverter IV1 is formed. The resistor is formed in a zigzag shape by connecting both ends of each of a plurality of wirings WA1 extending in the X direction to wiring for gate electrodes GT extending in the Y direction via vias VA1. One end of resistor R1 is connected to input IN (WA1) via via VA1. The other end of resistor R1 is connected to ground line VSS (WA1) via via VA1. The zigzag shape may also be formed by wiring for gate electrodes GT having a repeatedly bent shape.

[0051] By forming the resistor R1 in the layer A using the gate electrode material of the transistor, it is possible to omit forming the layer B shown in Fig. 3 or to omit forming the resistor R1 in the layer B. Note that by combining Fig. 7 and Fig. 8, the capacitor C1 and the resistor R1 may be formed in the layer A using the transistor structure.

[0052] As described above, in the first embodiment, by forming the big-PMOS using TFTs, it is possible to reduce the number of transistors formed on the substrate SUB, and the size of the ESD protection circuit ESDC1 can be reduced compared to when the big-PMOS is formed on the substrate SUB using fins FIN or the like. Also, by arranging the inverter IV1, resistor R1, capacitor C1, and big-PMOS (TFT) so that they overlap in a planar view, it is possible to reduce the size of the ESD protection circuit ESDC1 compared to when they are not arranged so that they overlap in a planar view. As a result, the ESD protection circuit ESDC1 can be appropriately formed using TFTs.

[0053] For example, in Fig. 7, by forming capacitance C1 in layer A using the gate insulating film of a transistor, it is possible to omit the formation of layer D shown in Fig. 3, or to omit forming capacitance C1 in layer D. For example, in Fig. 8, by forming resistor R1 in layer A using the gate electrode material of a transistor, it is possible to omit the formation of layer B shown in Fig. 3, or to omit forming resistor R1 in layer B.

[0054] Second Embodiment Figure 9 shows an example of the circuit layout of an inverter IV1 in an ESD protection circuit ESDC1 formed in a semiconductor device according to a second embodiment. The same elements as those in Figure 3 are designated by the same reference numerals, and detailed description thereof will be omitted. Figure 9 is the same as Figure 3 except that in the ESD protection circuit ESDC1 of Figure 1, the PMOS and NMOS of the inverter IV1 in layer A are formed of TFTs, and layer A is formed on the back surface side of the substrate SUB. The layouts of layers B, C, and D are the same as those of layers B, C, and D in Figure 3, respectively.

[0055] The source S of the PMOS is connected to a power supply line VDD (WA2) formed on the surface side of the substrate SUB via a via VA1, a wiring WA1 extending in the X direction, and a via VA2 (e.g., a TSV) penetrating the substrate SUB. The source S of the NMOS is connected to a ground line VSS (WA2) formed on the surface side of the substrate SUB via a via VA1, a wiring WA1 extending in the X direction, and a via VA2.

[0056] The drain D of the PMOS and the drain D of the NMOS are connected to an output OUT (WA2) formed on the surface side of the substrate SUB via a via VA1, a wiring WA1 extending in the X direction, and a via VA2. The gate electrode GT of the PMOS and the gate electrode GT of the NMOS are connected to an input IN (WA2) formed on the surface side of the substrate SUB via a via VA1, a wiring WA1 extending in the X direction, and a via VA2.

[0057] Fig. 10 shows an example of a cross section taken along the lines X3-X3' and X4-X4' in Fig. 9. Elements similar to those in Fig. 4 are given the same reference numerals, and detailed description thereof will be omitted.

[0058] In the cross section taken along line X3-X3', the gates of the PMOS (TFT) and NMOS (TFT) located on the back side of the substrate SUB are connected to an input IN (WA2) on the front side of the substrate SUB via a via VA1, wiring WA1, and via VA2. The input IN (WA2) is further connected to one end of a resistor R1 via a via VB1, wiring WB1, via VB2, and wiring WB2 on layer B. The input IN (WA2) is further connected to one end of a capacitor C1 via a via VC1, wiring WC1, via VC2, and wiring WC2 on layer C and a via VD1, wiring WD1, via VD2, and wiring WD2 on layer D.

[0059] In the cross section along line X4-X4', the drains D of the PMOS (TFT) and NMOS (TFT) are connected to an output OUT (WA2) on the front side of the substrate SUB via a via VA1, wiring WA1, and via VA2. The output OUT (WA2) is further connected to a gate electrode GT of the big-PMOS (TFT) via a via VB1, wiring WB1, via VB2, and wiring WB2 in layer B and a via VC1, wiring WC1, via VC2, and wiring WC2 in layer C. In layer A, the region where inverter IV1 is formed by TFTs is an example of a second wiring layer.

[0060] 9 and 10, by forming not only the big-PMOS but also the inverter IV1 using TFTs, the number of transistors formed on the substrate SUB can be reduced, and as a result, the element area of ​​the ESD protection circuit ESDC1 can be reduced.

[0061] Note that, similar to the layer A in Fig. 4, transistors of another circuit may be arranged on the substrate SUB at a position overlapping in plan view with the inverter IV1 formed on the back surface of the substrate SUB. Also, as in the first and second modified examples of the first embodiment shown in Figs. 7 and 8, one or both of the resistor R1 and the capacitor C1 may be formed using a transistor structure. In this case, one or both of the resistor R1 and the capacitor C1 may be arranged on the front surface side of the substrate SUB at a position overlapping in plan view with the inverter IV1, similar to the layer A in Fig. 7 or 8.

[0062] As described above, the second embodiment can also achieve the same effects as the above-described embodiments. For example, by forming the big-PMOS using TFTs, the number of transistors formed on the substrate SUB can be reduced, and the size of the ESD protection circuit ESDC1 can be made smaller than when the big-PMOS is formed on the substrate SUB using fins FIN or the like. Furthermore, by arranging the inverter IV1, resistor R1, capacitor C1, and big-PMOS (TFT) so that they overlap in a planar view, the size of the ESD protection circuit ESDC1 can be made smaller than when they are not arranged so that they overlap in a planar view. As a result, the ESD protection circuit ESDC1 can be appropriately formed using TFTs.

[0063] Furthermore, in the second embodiment, not only the big-PMOS but also the inverter IV1 is formed using TFTs, thereby reducing the number of transistors formed on the substrate SUB, and as a result, the element area of ​​the ESD protection circuit ESDC1 can be reduced.

[0064] Third Embodiment Fig. 11 shows an example of a circuit layout of an ESD protection circuit formed in a semiconductor device according to a third embodiment. Elements similar to those in Figs. 3 and 9 are given the same reference numerals, and detailed descriptions thereof will be omitted. Fig. 11 is the same as Fig. 3 except that in the ESD protection circuit ESDC1 of Fig. 1, layers B, C, and D are formed on the back surface side of the substrate SUB.

[0065] The layout of layer A is the same as that of layer A in Fig. 3, except that it has vias VA2 such as TSVs that connect the input IN and output OUT to the back side of the substrate SUB. The power supply line VDD (WA1) and ground line VSS (WA1) of layer A are also connected to the power supply line VDD and ground line VSS on the back side of the substrate SUB, respectively, through vias VA2 formed in an area not shown.

[0066] The layout of layer B is the same as the layout of layer B in Figure 3 except that via VB1 and wiring WB1 are not formed. The layout of layer C is the same as the layout of layer C in Figure 3. The layout of layer D is the same as the layout of layer D in Figure 3.

[0067] Fig. 12 shows an example of a cross section taken along the X5-X5' line and the X6-X6' line in Fig. 11. In Fig. 12, a capacitance C1 of the D layer, a big-PMOS of the C layer, and a resistance R1 of the B layer are formed on the back surface of the substrate SUB in this order, starting from the position closest to the substrate SUB. Note that the order of the D layer, C layer, and B layer formed on the back surface of the substrate SUB is not limited to the order shown in Fig. 12. Furthermore, one or both of the D layer and the B layer may be formed on the front surface of the substrate SUB.

[0068] Furthermore, the inverter IV1 in the layer A, the resistor R1 in the layer B, the big-PMOS in the layer C, and the capacitor C1 in the layer D may all be formed on the back surface side of the substrate SUB. In this case, the inverter IV1 in the layer A is preferably formed of a TFT, as in the second embodiment shown in FIGS.

[0069] As described above, the third embodiment can also achieve the same effects as the above-described embodiments. For example, by forming the big-PMOS using TFTs, the number of transistors formed on the substrate SUB can be reduced, and the size of the ESD protection circuit ESDC1 can be made smaller than when the big-PMOS is formed on the substrate SUB using fins FIN or the like. Furthermore, by arranging the inverter IV1, resistor R1, capacitor C1, and big-PMOS (TFT) so that they overlap in a planar view, the size of the ESD protection circuit ESDC1 can be made smaller than when they are not arranged so that they overlap in a planar view. As a result, the ESD protection circuit ESDC1 can be appropriately formed using TFTs.

[0070] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0071] 2nd wiring layer 3rd wiring layer big-PMOS ESD discharge transistor C1 Capacitance Cap Region D Drain ESDC1, ESDC2 ESD protection circuit FIN Fin GINS Gate insulating film GT Gate electrode IN Input INS Insulating film IV1 Inverter LI Local wiring NM1 NMOS transistor OUT Output PM1 PMOS transistor R1 Resistor Res Region S Source SEML Semiconductor layer SUB Substrate Top wiring layer VA1, VA2, VB1, VB2 Vias VC1, VC2, VD1, VD2 Vias VDD Power supply line VIA Via VSS Ground line WA1, WA2, WB1, WB2 Wiring WC1, WC2, WD1, WD2 Wiring WD2 First wiring, second wiring

Claims

1. A semiconductor device comprising: a substrate; a first wiring layer formed on the front or back surface of the substrate; a first power supply line; a second power supply line; an inverter arranged between the first power supply line and the second power supply line; a capacitor arranged between the first power supply line and the input of the inverter; a resistor arranged between the second power supply line and the input of the inverter; and a thin film transistor arranged between the first power supply line and the second power supply line and connected to the output of the inverter, wherein the thin film transistor is formed in the first wiring layer.

2. The semiconductor device according to claim 1, wherein the inverter, the resistor, the capacitor, and the thin film transistor are arranged to overlap each other in a plan view.

3. The semiconductor device according to claim 1, wherein the first wiring layer is formed on the front surface side of the substrate.

4. The semiconductor device according to claim 3, wherein the inverter, the resistor, and the capacitor are formed on the front surface side of the substrate.

5. The semiconductor device according to claim 4, wherein one or both of the resistor and the capacitor are formed in the same layer as the inverter.

6. The semiconductor device according to claim 1 or 2, further comprising a second wiring layer formed on the back surface of the substrate, and the inverter is formed as a thin film transistor in the second wiring layer.

7. The semiconductor device according to claim 1 or 2, wherein the first wiring layer is formed on the back surface side of the substrate.

8. The semiconductor device according to claim 7, further comprising fins formed on the surface of the substrate, and the inverter is formed by a transistor having the fins as a source and a drain.

9. The semiconductor device according to claim 1 or 2, wherein the thin film transistor is a PMOS transistor, the first power supply line is a power supply line, and the second power supply line is a ground line.

10. The semiconductor device according to claim 1 or 2, wherein the thin film transistor is an NMOS transistor, the first power supply line is a ground line, and the second power supply line is a power supply line.

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