Semiconductor module

Abstract

A semiconductor module including: a first semiconductor chip that includes a first surface parallel to a first direction and a second direction intersecting the first direction, a second surface on the opposite side from the first surface, and a plurality of second inductor groups separated from the first surface and provided on the first surface side; and a layered memory chip that includes a bottom surface parallel to the first surface, a plurality of IC chips provided on the first surface such that the bottom surface and the first surface are facing, and a plurality of first inductors separated from the bottom surface and provided to the plurality of IC chips, wherein the second inductor groups include a plurality of second inductors, and one first inductor among the plurality of first inductors communicates in a contactless manner with one second inductor among the plurality of second inductors, said one second inductor having been matched with the one first inductor.

Description

Semiconductor Module

[0001] One embodiment of the present invention relates to a semiconductor module.

[0002] In recent years, electronic computers in data centers and the like include semiconductor modules in which a stacked memory chip in which multiple memory chips are stacked, multiple IC (Integrated Circuit) chips including an arithmetic processing circuit, and the like are mounted on a single package substrate. The semiconductor modules enable electronic computers to increase memory capacity and process large amounts of data in data communications between each IC chip and each memory chip.

[0003] For example, Patent Documents 1 to 4 and Non-Patent Document 3 disclose examples of stacked chips in which multiple chips are stacked, or methods for mounting stacked chips. Also, Patent Documents 2, 3, 5, and 6 and Non-Patent Documents 1 and 2 disclose techniques for performing contactless communication between two chips. Furthermore, Patent Documents 1 to 4 and Non-Patent Documents 3 to 5 disclose techniques for forming wiring on the sidewalls of stacked chips as examples of methods for mounting stacked chips.

[0004] Japanese Patent Publication No. 3-501428 International Publication No. 2021 / 095083 International Publication No. 2021 / 199447 Japanese Patent Application Laid-Open No. 2012-156478 Japanese Patent Application Laid-Open No. 2017-069456 Japanese Patent Application Laid-Open No. 2015-103684

[0005] Kadomoto et al. , “WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers,” ICCD 2019. Hasegawa et al. , “A 1 Tb / s / mm2 Inductive-Coupling Side-by-Side Chip Link,” ESSCIRC 2016. A. Agnesina et al. , “A Novel 3D DRAM Memory Cube Architecture for Space Applications,” 2018 55th ACM / ESDA / IEEE Design Automation Conference (DAC), 2018, pp. 1-6, doi: 10.1109 / DAC. 2018.8465911. R. W. Johnson, “3-D Packaging: A Technology Review,” pp. 1-70, 23 Jun 2005. https: / / nepp. nasa. gov / doculoads / EA7E7EA1-BD30-4DA4-BD615FEA1A7F5AE9 / 3D%20Packaging%20Report%20071805. pdfR. M. Lea et al. , “3-D Stacked Chip Packaging Solution for Miniaturized Massively Parallel Processing,” IEEE Trans. Adv Packag. , 22 (3), Aug 1999.

[0006] For example, the semiconductor modules disclosed in Patent Documents 1 to 6 and Non-Patent Documents 1 to 5 make it possible to mount a stacked memory chip in which multiple memory chips are stacked, and multiple IC chips including an arithmetic processing circuit, on a single package substrate, and also make it possible to perform contactless communication (e.g., wireless communication, inductor communication) between an inductor formed on the stacked memory chip and an inductor formed on an IC chip. However, for example, if the positions of the inductors facing each other are misaligned, signal loss occurs in the inductor communication.

[0007] In view of such problems, one embodiment of the present invention aims to provide a semiconductor module that can suppress deterioration in the quality of inductor communication.

[0008] A semiconductor module according to one embodiment of the present invention includes: a first semiconductor chip including a first surface parallel to a first direction and a second direction intersecting the first direction, a second surface opposite the first surface, and a group of multiple second inductors spaced apart from the first surface and provided on the first surface side; and a stacked memory chip including a bottom surface parallel to the first surface, multiple IC chips provided on the first surface so that the bottom surface and the first surface face each other, and multiple first inductors provided on the multiple IC chips spaced apart from the bottom surface, wherein the group of second inductors includes multiple second inductors, and one first inductor of the multiple first inductors communicates contactlessly with one second inductor of the multiple second inductors that is matched to the one first inductor.

[0009] The plurality of second inductors may include an inductor positioned at a position shifted in the first direction from the position of a reference inductor among the plurality of second inductors by an inductor diameter / n (n is an integer greater than or equal to 2) of the second inductor.

[0010] The plurality of second inductors may include an inductor that is arranged at a position shifted in the second direction by an inductor diameter / n of the second inductor with respect to a position of a reference inductor among the plurality of second inductors.

[0011] The plurality of first inductors may include an inductor that is arranged at a position shifted in the second direction by an inductor diameter / n of the first inductor with respect to a position of a reference inductor among the plurality of first inductors.

[0012] The plurality of first inductors may include an inductor that is arranged at a position shifted in the first direction from a position of a reference inductor among the plurality of first inductors by an inductor diameter / n of the first inductor.

[0013] The n may be 2, the n may be 3, or the n may be 7.

[0014] The plurality of IC chips may be stacked along the first direction.

[0015] The plurality of IC chips may be stacked along the second direction.

[0016] The first inductor may include a first wiring, and the second inductor may include a wiring different from the first wiring, and the wiring may have a line width greater than the line width of the first wiring.

[0017] The semiconductor module may further include a second semiconductor chip electrically connected to the first semiconductor chip on the second surface side, and the second semiconductor chip may include a configuration for controlling the contactless communication.

[0018] The second semiconductor chip may include a determination circuit that determines whether the one first inductor is matched with the one second inductor.

[0019] The second semiconductor chip may include a path-failure map generation circuit that uses the judgment result determined by the judgment circuit to generate a path-failure map indicating whether the one first inductor is matched or not matched with the one second inductor, and a table that stores the path-failure map.

[0020] 5 is a perspective view showing the configuration of a semiconductor module according to a first embodiment of the present invention. FIG. 6 is an end view showing the end cross-sectional structure of the semiconductor module taken along line A1-A2 shown in FIG. 1. FIG. 7 is a plan view showing a plurality of inductor groups included in a stacked memory chip included in the semiconductor module according to the first embodiment of the present invention. FIG. 8 is a plan view showing a plurality of inductor groups included in a (Through Chip Interface-IO (TCI-IO)) chip included in the semiconductor module according to the first embodiment of the present invention. FIG. 9 is a plan view showing the inductor groups shown in FIGS. 3 and 4. FIG. 10 is a plan view and a perspective view showing an enlarged portion of the inductor shown in FIG. 11. FIG. 12 is a block diagram showing the configuration of a memory module according to a first embodiment of the present invention. FIG. 13 is an end view showing the end cross-sectional structure of a stacked memory chip according to the first embodiment of the present invention. FIG. 14 is an end view showing an end cross-sectional structure of a stacked memory chip according to the first embodiment of the present invention. FIG. 15 is an end view showing an enlarged portion of the end cross-sectional structure of an IC chip according to the first embodiment of the present invention. FIG. 16 is a plan view showing a plurality of inductors included in a stacked memory chip included in a semiconductor module according to a second embodiment of the present invention. FIG. 17 is a plan view showing a plurality of inductors included in a TCI-IO chip included in a semiconductor module according to the second embodiment of the present invention. 12 or 13. FIG. 14 is a plan view showing a plurality of inductors included in a stacked memory chip included in a semiconductor module according to a third embodiment of the present invention. FIG. 15 is a plan view showing a portion of the inductor shown in FIG. 15. FIG. 16 is a plan view showing a group of inductors included in a TCI-IO chip included in a semiconductor module according to a third embodiment of the present invention. FIG. 17 is a plan view showing a portion of the group of inductors shown in FIG. 17. FIG. 18 is a plan view showing a plurality of inductors included in a TCI-IO chip included in a semiconductor module according to a fourth embodiment of the present invention. FIG. 19 is a plan view showing a plurality of inductors included in a stacked memory chip included in a semiconductor module according to a fifth embodiment of the present invention. FIG. 20 is a plan view showing a portion of a plurality of inductors included in a semiconductor module according to a sixth embodiment of the present invention.13 is a flowchart illustrating an example of an inductor communication method for a semiconductor module according to a seventh embodiment of the present invention.

[0021] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the following exemplary embodiments. For clarity of explanation, the drawings may show schematic representations of the width, thickness, shape, etc. of each part compared to the actual form. However, these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals (or reference numerals with a, b, etc. suffixed thereto), and detailed descriptions may be omitted as appropriate. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element and have no further meaning unless otherwise specified.

[0022] In one embodiment of the present invention, when a component or region is said to be "on (or under)" another component or region, unless otherwise specified, this includes not only the case where it is directly above (or directly under) the other component or region, but also the case where it is above (or under) the other component or region, i.e., the case where another component is included between the component or region and above (or under) the other component or region.

[0023] In one embodiment of the present invention, the first direction D1 intersects with the second direction D2, and the third direction D3 intersects with the first direction D1 and the second direction D2 (D1D2 plane).

[0024] In one embodiment of the present invention, when the expressions "identical" and "matching" are used, the expressions "identical" and "matching" may include a tolerance within the design range. In addition, in one embodiment of the present invention, when a tolerance within the design range is included, the expressions "approximately identical" and "approximately matching" may be used.

[0025] First Embodiment A semiconductor module 10 according to a first embodiment will be described with reference to FIGS.

[0026] <1-1. Overview of Semiconductor Module 10> First, an overview of the semiconductor module 10 will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a perspective view showing the configuration of the semiconductor module 10. Fig. 2 is an end view showing the cross-sectional structure of the end of the semiconductor module 10 taken along A1-A2 shown in Fig. 1.

[0027] 1 or 2, the semiconductor module 10 includes stacked memory chips 100, TCI-IO chips 300, logic chips 200, and an adhesive layer 400. The semiconductor module 10 may also include a bump layer 500 and a substrate 600. For example, the stacked memory chips 100 may be referred to as a semiconductor cube, the TCI-IO chips 300 may be referred to as a first semiconductor chip, and the logic chip 200 may be referred to as a second semiconductor chip.

[0028] The stacked memory chip 100 includes an inductor layer 170 including a plurality of inductor groups 171, a first outermost surface (first surface 146) which are the two outermost surfaces in the third direction D3, and a second outermost surface (second surface 148) opposite the first outermost surface, a third outermost surface (third surface 145) which are the two outermost surfaces in the second direction D2 and are parallel to the third direction D3 and the first direction D1, and a fourth outermost surface (fourth surface 147) opposite the third outermost surface, and a fifth outermost surface (fifth surface 142) which are the two outermost surfaces in the first direction D1 and are parallel to the third direction D3 and the second direction D2, and a sixth outermost surface (sixth surface 144) opposite the fifth outermost surface. The first surface 146 and the second surface 148 are adjacent to the third surface 145, the fourth surface 147, the fifth surface 142, and the sixth surface 144, and are perpendicular to the third surface 145, the fourth surface 147, the fifth surface 142, and the sixth surface 144. The third surface 145 and the fourth surface 147 are adjacent to the fifth surface 142 and the sixth surface 144, and are perpendicular to the fifth surface 142 and the sixth surface 144.

[0029] The stacked memory chip 100 includes a configuration in which multiple IC chips 110 (see FIGS. 8 to 10 ) are stacked (bonded) in a first direction D1 or a third direction D3. An inductor layer 170 including multiple inductor groups 171 may be provided within one memory chip or across multiple memory chips. The multiple inductor groups 171 are arranged in a matrix along the first direction D1 and the second direction D2 parallel to the first surface 146 (see FIG. 3 ), and are spaced apart from the first surface 146. The first surface 146 is the bottom surface of the stacked memory chip 100 and is the surface that contacts the adhesive layer 400. The first surface 146 is positioned to face the first surface 302 of the TCI-IO chip 300, and the stacked memory chip 100 is disposed on the first surface 302 of the TCI-IO chip 300.

[0030] For example, techniques such as fusion bonding and silicon direct bonding (SDB) can be used to stack (bond) the IC chips 110 together. Fusion bonding and silicon direct bonding are well known techniques in the relevant technical field, and detailed explanations thereof will be omitted here.

[0031] The TCI-IO chip 300 includes an inductor layer 370 including a plurality of inductor groups 371, a first surface 302, and a second surface 304. The first surface 302 and the second surface 304 are parallel to the first direction D1 and the second direction D2. The second surface 304 is positioned to face the first surface 202 of the logic chip 200 and is in contact with the first surface 202 of the logic chip 200. The first surface 302 is in contact with the adhesive layer 400 and is positioned to face the first surface 146 of the stacked memory chip 100.

[0032] The TCI-IO chip 300 also includes an IC chip 110n+8. For example, the IC chip 110n+8 includes an inductor layer 370, which includes a wiring layer 150 (see FIG. 10 ). The inductor layer 370 is provided on the first surface 302 side, and a plurality of inductor groups 371 are arranged in a matrix along the first direction D1 and the second direction D2 parallel to the first surface 302 (see FIG. 4 ), and are also arranged at a distance from the first surface 302.

[0033] The logic chip 200 includes a first surface 202 and a second surface 204. The first surface 202 and the second surface 204 are surfaces parallel to the first direction D1 and the second direction D2. As described above, the first surface 202 is positioned opposite the second surface 304 of the TCI-IO chip 300, and the logic chip 200 is stacked (bonded) to the second surface 304 of the TCI-IO chip 300. The logic chip 200 also includes an IC chip 110n+9. For example, the IC chip 110n+9 includes a wiring layer 150 (see FIG. 10 ), and the wiring of the wiring layer 150 serves as an electrode and is electrically connected to the bumps 52 included in the bump layer 500.

[0034] IC chip 110n+8 and IC chip 110n+9 may be a single IC chip. That is, a single IC chip may be a chip that integrates the configuration of TCI-IO chip 300 and the configuration of logic chip 200, and may have the functions of TCI-IO chip 300 and logic chip 200.

[0035] As described above, the adhesive layer 400 is disposed between the stacked memory chips 100 and the TCI-IO chips 300, and bonds the stacked memory chips 100 and the TCI-IO chips 300. The adhesive layer 400 may be, for example, an adhesive containing an epoxy resin or an acrylic polymer, a die bonding film (DBF) containing an epoxy resin or an acrylic polymer, or an adhesive film such as a die attached film (DAF).

[0036] The substrate 600 includes a multilayer wiring structure (not shown) in which wiring and insulating layers are alternately stacked, a first surface 602, and a second surface 604. For example, the multilayer wiring structure includes electrodes 62 exposed on the first surface 602. The electrodes 62 are electrically connected to the bumps 52, and the semiconductor module 10 is electrically connected to the substrate 600. For example, the semiconductor module 10 is connected to an external substrate, an external circuit, etc. via the substrate 600, and various control signals, power supply voltages, etc. are supplied to the semiconductor module 10 from the external substrate and the external circuit.

[0037] As will be described in detail later, the multiple inductor groups 171 are arranged parallel to and facing the multiple inductor groups 371. Each of the multiple inductor groups 171 includes multiple inductors 71 ( FIG. 5 ) that are arranged at offset positions, and each of the multiple inductor groups 371 includes multiple inductors 71 ( FIG. 5 ) that are arranged at offset positions. In the semiconductor module 10, one inductor group 171 and one inductor group 371 that face each other are magnetically coupled, thereby enabling one-to-one, non-contact communication between the inductors 71 included in the inductor group 171 and the inductors 71 included in the inductor group 371. For example, communication between inductors that occurs due to magnetic field coupling is called inductor communication, signal communication, data communication, etc. Even if the stacked memory chip 100 is attached to the TCI-IO chip 300 in a position that is shifted from its original position relative to the TCI-IO chip 300, any one of the multiple inductors 71 in the inductor group 171 can be matched (aligned) with any one of the multiple inductors 71 in the inductor group 371. As a result, the inductor group 171 in the semiconductor module 10 can be prevented from being misaligned with the inductor group 371, and the semiconductor module 10 can therefore reduce signal loss in the inductor communication. In other words, the semiconductor module 10 can reduce degradation in the quality of inductor communication.

[0038] <1-2. Overview of Inductors> Next, an overview of the inductors will be described with reference to FIGS. 3 to 6. FIG. 3 is a plan view showing a plurality of inductor groups 171 included in the stacked memory chip 100. FIG. 4 is a plan view showing a plurality of inductor groups 371 included in the TCI-IO chip 300 included in the semiconductor module 10. FIG. 5 is a plan view showing the inductor groups 171 and 371 shown in FIGS. 3 and 4. FIG. 6 is an enlarged plan view and perspective view of a portion of the inductor 71 shown in FIG. 5. Configurations that are the same as or similar to those in FIGS. 1 and 2 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 and 2 may be omitted.

[0039] 3 is a plan view of the multiple inductor groups 171 as seen from the first surface 146 side. For convenience of explanation, the multiple inductor groups 171 appear to be the same as the first surface 146, but as shown in FIG. 2, the multiple inductor groups 171 are actually separated from the first surface 146. FIG. 4 is a plan view of the multiple inductor groups 371 and the multiple TCI-IOs 312 as seen from the first surface 302 side. For convenience of explanation, the multiple inductor groups 371 and the multiple TCI-IOs 312 appear to be the same as the first surface 302, but as shown in FIG. 2, the multiple inductor groups 371 are actually separated from the first surface 302. As will be described in detail later, the multiple TCI-IOs 312 are electrically connected to the multiple inductors 71 in the multiple inductor groups 371 (see FIG. 7).

[0040] First, we will explain the inductor group 171 included in the stacked memory chip 100. As explained in "1-1. Overview of the Semiconductor Module 10," the stacked memory chip 100 includes a plurality of inductor groups 171 that are provided parallel to and spaced apart from the first surface 146 that is parallel to the first direction D1 and the second direction D2.

[0041] 3, the multiple inductor groups 171 include an inductor group 171A and an inductor group 171B. The multiple inductor groups 171 are arranged in a matrix along a first direction D1 and a second direction D2. For example, the multiple inductor groups 171 are arranged at a distance PH in the first direction D1 and at a distance PV in the second direction D2.

[0042] 5, one inductor group 171 includes inductors 71A, 71B, 71C, 71D, 71E, 71F, 71G, 71H, 71J, and 71K. Since each of the inductors 71A, 71B, 71C, 71D, 71E, 71F, 71G, 71H, 71J, and 71K has the same configuration, the configuration of the inductor 71 will be described using one inductor 71A as an example.

[0043] For example, as shown in FIG. 6 , the inductor 71 includes terminal A, terminal B, first wirings 11, 12, and 13, second wirings 31 and 32, and vias 21, 22, 23, and 24. Also, as shown in FIGS. 5 and 6 , for example, the inductor 71 is a single-turn coil having terminals A and B at both ends. Also, as shown in FIGS. 5 and 6 , for example, the shape of the inductor 71 is rectangular in plan view. For example, the length of each of the first wirings 11, 12, and 13 is length L1, and the length of each of the second wirings 31 and 32 is length L2. The length of the diagonal of the rectangular shape of the inductor 71 is length DL. The multiple dashed lines parallel to the extension directions of the first wirings 11, 12, and 13 and the second wirings 31 and 32 in the perspective view of FIG. 6 are imaginary lines to make the structure of the inductor 71 easier to see. The diameter of the inductor 71 (inductor diameter) may be length L1, length L2, or length DL. Furthermore, length L1 may be the same as or different from length L2. The diameter of the inductor 71 (inductor diameter) may be selected appropriately based on the application, specifications, etc. of the semiconductor module 10.

[0044] The terminals A, B, the first wirings 11, 12, and 13, and the second wirings 31 and 32 intersect with each other and are formed in different layers, and the vias 21, 22, 23, and 24 are formed in a layer between the layer on which the terminals A, B, the first wirings 11, 12, and 13 are formed and the layer on which the second wirings 31 and 32 are formed. For example, the second wirings 31 and 32 are formed along the second direction D2 in a layer including the wiring 178 shown in FIG. 10 , the terminals A, B, the first wirings 11, 12, and 13 are formed along the first direction D1 in a layer including the wiring 180 shown in FIG. 10 , and the vias 21, 22, 23, and 24 are formed along the third direction D3 in a layer including the via 180A shown in FIG. 10 .

[0045] The first wiring 11 extends in the first direction D1, one end of the first wiring 11 is electrically connected to the terminal A, and the other end of the first wiring 11 is electrically connected to one end of the via 21. The second wiring 31 extends in the second direction D2, one end of the second wiring 31 is electrically connected to the other end of the via 21, and the other end of the second wiring 31 is electrically connected to one end of the via 22. The first wiring 12 extends in the first direction D1, one end of the first wiring 12 is electrically connected to the other end of the via 22, and the other end of the first wiring 12 is electrically connected to one end of the via 23. The second wiring 32 extends in the second direction D2, one end of the second wiring 32 is electrically connected to the other end of the via 23, and the other end of the second wiring 32 is electrically connected to one end of the via 24. The first wiring 13 extends in the first direction D1, one end of the first wiring 13 is electrically connected to the other end of the via 24, and the other end of the first wiring 13 is electrically connected to the terminal B.

[0046] As described above, the inductor 71 is formed by alternately connecting first wirings formed along the first direction D1 and second wirings formed along the second direction D2 via vias. Because the layer including the first wirings formed along the first direction D1 is different from the layer including the second wirings formed along the second direction D2, the first wirings can intersect (overlap) with the second wirings. Therefore, the inductors 71A, 71B, 71C, 71D, 71E, 71F, 71G, 71H, 71J, and 71K can intersect (overlap), and therefore the positions of the inductors 71A, 71B, 71C, 71D, 71E, 71F, 71G, 71H, 71J, and 71K can be shifted from one another.

[0047] For example, the positional relationship between inductors 71A, 71B, 71C, 71D, 71E, 71F, 71G, 71H, 71J, and 71K will be described using FIG. 5 as an example. Inductor 71B is arranged offset by a length L2 / n from inductor 71A along the second direction D2. Inductor 71C is arranged offset by a length L2 / n from inductor 71B along the second direction D2. Inductor 71D is arranged offset by a length L2 / n from inductor 71C along the first direction D1. Inductor 71E is arranged offset by a length L2 / n from inductor 71D along the first direction D1. Inductor 71G is arranged offset by a length L2 / n from inductor 71F along the second direction D2. Inductor 71H is arranged offset by a length L2 / n from inductor 71G along the second direction D2. Inductor 71J is arranged with a length L2 / n offset from inductor 71H along the first direction D1. Inductor 71K is arranged with a length L2 / n offset from inductor 71J along the first direction D1, where n is an integer equal to or greater than 2. Note that the inductors arranged in the first direction D1 may be arranged with a length L1 / n offset, and the inductors arranged in the second direction D2 may be arranged with a length L1 / n offset.

[0048] Furthermore, for example, in order to prevent adjacent inductors in the same direction from shorting out, adjacent inductors in the same direction are arranged with a shift in a direction different from the same direction to an extent that a short circuit does not occur. For example, in order to prevent adjacent inductors in the first direction D1 from shorting out, adjacent inductors in the second direction D2 are arranged with a slight shift in the first direction D1. For example, in order to prevent adjacent inductors in the second direction D2 from shorting out, adjacent inductors in the first direction D1 are arranged with a slight shift in the first direction D1. For example, the slight shift may be 1 / 100 or more and 1 / 10 or less of the length L1, the length L2, or the length DL.

[0049] For example, in the inductor group 171 shown in FIG. 5, the number n is 3, and the multiple inductors 71 are arranged so as to be offset by 1 / 3 of the length L2 along the first direction D1 and the second direction D2.

[0050] Next, we will explain the inductor group 371 included in the TCI-IO chip 300. As explained in "1-1. Overview of Semiconductor Module 10," the TCI-IO chip 300 includes a plurality of inductor groups 371 that are arranged parallel to and spaced apart from a first surface 302 that is parallel to the first direction D1 and the second direction D2.

[0051] 4, the inductor groups 371 include an inductor group 371A and an inductor group 371B. The inductor groups 371 are arranged in a matrix along the first direction D1 and the second direction D2. For example, like the inductor groups 171, the inductor groups 371 are arranged at a distance PH in the first direction D1 and at a distance PV in the second direction D2.

[0052] 5 and 6, similar to the multiple inductor groups 171. That is, similar to the multiple inductor groups 171, each inductor group 371 includes inductors 71A, 71B, 71C, 71D, 71E, 71F, 71G, 71H, 71J, and 71K. Each of the inductors 71A, 71B, 71C, 71D, 71E, 71F, 71G, 71H, 71J, and 71K has the same configuration (inductor 71). Therefore, detailed description of the inductor 71 will be omitted here. Similar to the single inductor group 171, the inductors 71A, 71B, 71C, 71D, 71E, 71F, 71G, 71H, 71J, and 71K included in the single inductor group 371 can be positioned so as to be offset from one another.

[0053] Although not shown in the drawings, for example, the line width of the first wirings 11, 12, and 13 and the line width of the second wirings 31 and 32 of the inductors 71 included in the multiple inductor groups 371 are thicker than the line width of the first wirings 11, 12, and 13 and the line width of the second wirings 31 and 32 of the inductors 71 included in the multiple inductor groups 171. As a result, even if the position of the inductor group 171 is shifted with respect to the position of the inductor group 371, the multiple inductor groups 171 can overlap with the inductor group 371, and therefore the semiconductor module 10 can suppress signal loss in inductor communication between the inductor group 171 and the inductor group 371.

[0054] When the stacked memory chip 100 is stacked on the TCI-IO chip 300, the multiple inductor groups 171 are arranged parallel to and facing the multiple inductor groups 371. That is, each of the multiple inductor groups 171 overlaps with an inductor group 371 that is arranged parallel to and facing each other among the multiple inductor groups 371. As a result, one inductor group 171 and one inductor group 371 that face each other are magnetically coupled, allowing one inductor 71 included in the inductor group 171 and one inductor 71 included in the inductor group 371 to communicate one-to-one and contactlessly. For example, the inductor group 171A overlaps with the inductor group 371A, and the inductor group 171B overlaps with the inductor group 371B. For example, even if the inductor group 171A and the inductor group 371A are misaligned, the multiple inductors 71 included in the inductor group 171A can suppress the misalignment of the inductor group 171A, and the multiple inductors 71 included in the inductor group 371B can suppress the misalignment of the inductor group 371B in the first direction D1 and the second direction D2, so that the semiconductor module 10 can suppress signal loss in the inductor communication. In other words, the semiconductor module 10 can suppress deterioration in the quality of inductor communication.

[0055] <1-3. Functional Block Configuration of Semiconductor Module 10> Next, the functional block configuration of the semiconductor module 10 will be described with reference to Fig. 7. Fig. 7 is a block diagram showing the functional block configuration of the semiconductor module 10. Configurations that are the same as or similar to those in Figs. 1 to 6 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 6 may be omitted.

[0056] The semiconductor module 10 includes a stacked memory chip 100 , a TCI-IO chip 300 and a logic chip 200 .

[0057] The stacked memory chip 100 includes a plurality of TCI-IOs 112 and a plurality of memory modules 111. The plurality of TCI-IOs 112 are electrically connected to the memory modules 111. For example, the stacked memory chip 100 includes a function of storing received data and a function of transmitting the stored data.

[0058] The TCI-IO 112 includes an inductor group 171A (e.g., 171B, 171B) including a plurality of inductors 71 (e.g., 71A, ... 71K), a transmitting / receiving circuit 114, and a parallel-serial conversion circuit 113. The inductors 71 are electrically connected to the transmitting / receiving circuit 114 using terminals A and B. The transmitting / receiving circuit 114 is electrically connected to the parallel-serial conversion circuit 113. The parallel-serial conversion circuit 113 is electrically connected to the memory module 111.

[0059] The inductor 71 of the stacked memory chip 100 has the function of performing contactless inductor communication with the inductor 71 of the TCI-IO chip 300 .

[0060] For example, the transmitter / receiver circuit 114 has a function of amplifying signals (e.g., control signals and data signals) received by the inductors 71 of the stacked memory chips 100, and a function of removing noise from the received signals (e.g., control signals and data signals). Furthermore, for example, the transmitter / receiver circuit 114 has a function of transmitting desired signals (e.g., control signals and data signals) converted using the parallel-to-serial conversion circuit 113 over radio waves. The signals received by the inductors 71 of the stacked memory chips 100 include multiple parallel signals (parallel signals) from the inductors 71 of the TCI-IO chip 300. The desired signals include multiple parallel signals (parallel signals) from the memory modules 111.

[0061] For example, in step 1, the parallel-serial conversion circuit 113 performs parallel-to-serial conversion on a large number of parallel signals from the TCI-IO chip 300 to convert them into serial signals (serial signals). The serial signals are transferred at high speed using a single signal path (wiring). In step 2, the parallel-serial conversion circuit 113 performs serial-to-parallel conversion on the serial signals immediately before the memory module 111 to return them to a large number of parallel signals, and then transmits the large number of parallel signals to the memory module 111. For example, when transmitting signals (e.g., control signals and data signals) from the memory module 111 to the TCI-IO chip 300, the parallel-serial conversion circuit 113 performs step 1 following step 2. The parallel-serial conversion circuit 113 is called, for example, a SerDes circuit (Serialize and Deserialize Circuit).

[0062] For example, the memory module 111 includes a plurality of memory cell arrays (not shown). The memory module 111 has a function of generating a plurality of parallel signals to be transmitted and a function of controlling a plurality of received parallel signals and storing them in a memory cell array (not shown) included in the memory module 111. For example, each of the plurality of memory cell arrays is a static random access memory (SRAM), and each of the plurality of memory cells is an SRAM cell. For example, the plurality of memory cell arrays and the plurality of memory cells may be memory cell arrays and memory cells other than SRAM, such as a magnetoresistive random access memory (MRAM) and MRAM cells.

[0063] The TCI-IO chip 300 includes a plurality of TCI-IOs 312. The plurality of TCI-IOs 312 are electrically connected to the logic chip 200.

[0064] The TCI-IO 312 includes an inductor group 371A (e.g., 371B, 371B) including a plurality of inductors 71 (e.g., 71A, ... 71K), a transmitting / receiving circuit 314, and a parallel-serial conversion circuit 313. The inductors 71 included in the inductor group 371A are electrically connected to the transmitting / receiving circuit 314 using terminals A and B. The transmitting / receiving circuit 314 is electrically connected to the parallel-serial conversion circuit 313. For example, the parallel-serial conversion circuit 313 is electrically connected to the logic chip 200 (logic module 211).

[0065] The configurations and functions of the inductor 71, the transmitter / receiver circuit 314, and the parallel-serial conversion circuit 313 included in the inductor group 371A are similar to the configurations and functions of the inductor 71, the transmitter / receiver circuit 114, and the parallel-serial conversion circuit 113 included in the inductor group 171A.

[0066] The logic chip 200 includes a logic module 211. The logic chip 200 may include multiple logic modules 211. The logic module 211 is electrically connected to multiple TCI-IOs 312.

[0067] For example, the logic chip 200 may include a plurality of dynamic random access memory (DRAM) interfaces (not shown) and a plurality of external I / Os (not shown).

[0068] The logic module 211 has a function for controlling the transmission of signals (data) to a plurality of TCI-IOs 312, or the reception of signals (data) from a plurality of TCI-IOs 312. The logic module 211 also has a function for driving the memory module 111 in the IC chip 110. The logic module 211 is supplied with voltages VDD, VSS, and the like from an external circuit, receives a control program stored in a DRAM module from the DRAM module, and executes the processing of the control program. For example, the logic module 211 may include an arithmetic circuit such as a CPU (Central Processing Unit), and transmit a signal for driving the memory module 111 via the TCI-IO 312.

[0069] For example, the DRAMIO is electrically connected to a DRAM module (not shown) electrically connected on the substrate 600, and has a function of transmitting and receiving signals between the DRAM module and the logic chip 200. For example, the external IO is electrically connected to the logic chip 200 and an external circuit (not shown, for example, a power supply circuit), and has a function of transmitting and receiving signals between the external circuit and the logic chip 200.

[0070] <1-4. Configuration of Stacked Memory Chip 100> Next, the configuration of the stacked memory chip 100 will be described with reference to Figures 8 and 9. Figures 8 and 9 are end views showing the cross-sectional structure of the end of the stacked memory chip 100. Configurations that are the same as or similar to those in Figures 1 to 7 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figures 1 to 7 may be omitted.

[0071] 8, the stacked memory chip 100 includes a configuration in which a plurality of IC chips 110 are stacked in a first direction D1. That is, the stacked memory chip 100 shown in FIG. 8 is stacked such that the plurality of IC chips 110 are arranged perpendicular to the first surface 302 of the TCI-IO chip 300 along the third direction.

[0072] Each of the multiple IC chips 110 includes multiple inductor groups 171 and has a similar configuration. The inductor layer 170 includes multiple inductor groups 171. For example, the stacked memory chip 100 includes a configuration in which seven IC chips 110 (110n+1 to 110n+7) are stacked in a first direction D1. For example, the IC chip 110n+2 is adjacent to and electrically connected to the IC chip 110n+1. Furthermore, for example, the IC chips 110n+2 to 110n+7 are electrically connected to adjacent IC chips, similar to the IC chips 110n+2 and 110n+1. As described above, for example, the IC chips 110 (110n+1 to 110n+7) are electrically connected using fusion bonding.

[0073] The number of layers of the stacked memory chips 100 is just an example, and the number of layers of the stacked memory chips 100 is not limited to 8. The number of layers of the stacked memory chips 100 may be selected appropriately based on the application, specifications, etc. of the semiconductor module 10.

[0074] 9, the stacked memory chip 100 may include a configuration in which multiple IC chips 110 (110n+1 and 110n+2) are stacked in a third direction D3. The stacked memory chips 100 shown in FIG. 9 are stacked parallel to the first surface 302 of the TCI-IO chip 300 along the third direction. In the stacked memory chip 100 shown in FIG. 9, the IC chip 110n+1 includes an inductor layer 170. That is, one IC chip 110 includes multiple inductor groups 171.

[0075] When the multiple IC chips 110 are not distinguished from one another, the IC chip is expressed as IC chip 110. When the multiple IC chips 110 are distinguished from one another, the IC chip is expressed as IC chip 110n, IC chip 110n+1, IC chip 110n+2, etc.

[0076] <1-5. Overview of IC Chip 110> Next, an overview of the IC chip 110 will be described with reference to Fig. 10. Fig. 10 is an end view showing an enlarged portion of the end cross-sectional structure of the IC chip 110. Configurations that are the same as or similar to those in Figs. 1 to 9 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 9 may be omitted.

[0077] 10 , the IC chip 110 includes a first surface 102 parallel to the second direction D2 and the first direction D1, a second surface 104 opposite the first surface 102 in the third direction D3, a transistor layer 130, and a wiring layer 150. The first surface 102 is the surface opposite the surface on which the wiring layer 150 is disposed relative to the transistor layer 130, and the second surface 104 is the surface opposite the surface on which the wiring layer 150 is disposed relative to the transistor layer 130.

[0078] For example, the transistor layer 130 includes a semiconductor substrate 173, an isolation region 174, an activation region 175, a transistor 176, an insulating layer 177, and a portion of a wiring 178. For example, the semiconductor substrate 173 is a Si substrate or Si-wafer, and is called a semiconductor substrate. Note that a through electrode 131 that penetrates the semiconductor substrate 173 and the isolation region 174 may be provided.

[0079] For example, the wiring layer 150 includes a multilayer wiring structure in which wirings and insulating layers are alternately stacked. For example, the wiring layer 150 includes a part of the wiring 178, an insulating layer 179, a via 180A, a wiring 180, an insulating layer 181, an insulating layer 182, and a wiring 183. The wiring 183 may be a through electrode.

[0080] For example, the wiring 178 is provided to penetrate the insulating layer 177 and is electrically connected to the source or drain of the transistor 176. The via 180A is provided in the insulating layer 179 and is electrically connected to the wiring 178. The wiring 180 is electrically connected to the via 180A and also to the wiring 178. The wiring 183 is electrically connected to the wiring 180.

[0081] As described above, for example, the inductor layer 170 includes the wiring layer 150, and the inductor group 171 is formed using the wiring 180, the via 180A, and the wiring 178. For example, the terminal A, the terminal B, the first wirings 11, 12, and 13 are formed using the wiring 180, the second wirings 31 and 32 are formed using the wiring 178, and the vias 22 to 24 are formed using the via 180A.

[0082] The transmitter / receiver circuit 114, the parallel-serial conversion circuit 113, and the memory module 111 are formed using wiring 178, wiring 180, via 180A, wiring 183, and transistor 176. The wiring connections shown in Fig. 10 are merely an example, and the wiring connections are not limited to the configuration shown in Fig. 10. The wiring connections can be changed as appropriate based on the application or specifications of the semiconductor module 10.

[0083] 8 may be bonded so that their first surfaces 102 face each other. That is, the through electrodes 131 exposed on their first surfaces 102 may be electrically connected to each other.

[0084] Furthermore, for example, IC chip 110n+8 of TCI-IO chip 300 and IC chip 110n+9 of logic chip 200 may be bonded together such that second surface 104 of IC chip 110n+8 faces first surface 102 of IC chip 110n+9. That is, wiring 183 exposed on second surface 104 may be electrically connected to through electrode 131 exposed on first surface 102.

[0085] In addition, the outermost IC chip 110 does not have either the through electrodes 131 exposed on the first surface 102 or the wiring 183 exposed on the second surface 104 formed thereon.

[0086] Second Embodiment A semiconductor module 10A according to a second embodiment will be described with reference to FIGS. 11 to 14. FIG. 11 is a plan view showing a plurality of inductors 71 included in a stacked memory chip 100A included in the semiconductor module 10A. FIGS. 12 and 13 are plan views showing a plurality of inductors 71 included in a TCI-IO chip 300A included in the semiconductor module 10A. FIG. 14 is an enlarged plan view of a portion of the inductor shown in FIG. 12 or 13. Configurations that are the same as or similar to those in FIGS. 1 to 10 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 10 may be omitted.

[0087] 3, the stacked memory chip 100A shown in Fig. 11 is a plan view of the inductors 71 as seen from the first surface 146 side, and for convenience of explanation, the multiple inductors 71 appear to be the same as the first surface 146, but the multiple inductors 71 are actually separated from the first surface 146 like the inductor group 171 shown in Fig. 2. Also, the TCI-IO chip 300A shown in Figs. 12 and 13 omits the multiple TCI-IOs 312 in the TCI-IO chip 300 shown in Fig. 4. 12 and 13 are plan views of the TCI-IO chip 300A shown in Fig. 12 and 13, similar to the TCI-IO chip 300 shown in Fig. 4, in which the multiple inductors 71 and the like are viewed from the first surface 302 side, and for convenience of explanation, the multiple inductors 71 and the like appear to be the same as the first surface 302, but the multiple inductors 71 are actually separated from the first surface 302 like the inductor group 371 shown in Fig. 2. Furthermore, although not shown in the drawings, the multiple TCI-IO chips 312 are electrically connected to the multiple inductors 71, the multiple inductors 71HSH, the multiple inductors 71VSH, and the multiple inductors 71 in the multiple inductors 71DSH.

[0088] The semiconductor module 10A differs from the semiconductor module 10 in the following configurations (1) and (2): (1) The inductor group 171 including the multiple inductors 71 in the stacked memory chip 100 of the semiconductor module 10 is replaced with the inductor 71 of the stacked memory chip 100A. In other words, the inductor group 171 including the multiple inductors 71 is replaced with a single inductor 71. (2) The TCI-IO chip 300A includes multiple inductors 71, multiple inductors 71HSH, multiple inductors 71VSH, and multiple inductors 71DSH. The inductor 71HSH is disposed at a position shifted from the inductor 71 along the first direction D1 by a length (L1 / 2) that is half the coil diameter L1 using the position of the inductor 71 as a reference, the inductor 71VSH is disposed at a position shifted from the inductor 71 along the second direction D2 by a length (L2 / 2) that is half the coil diameter L2 using the position of the inductor 71 as a reference, and the inductor 71DSH is disposed at a position shifted from the inductor 71 along the diagonal direction by a length (L2 / 2) that is half the coil diameter L2 using the position of the inductor 71 as a reference. That is, the inductors disposed shifted in the second direction D2 and the diagonal direction using the position of the inductor 71 as a reference have a value n of 2 in L2 / n, and the inductors disposed shifted in the first direction D1 using the position of the inductor 71 as a reference have a value n of 2 in L1 / n.

[0089] The configurations of the semiconductor module 10A other than those shown in (1) and (2) are the same as those of the semiconductor module 10. Therefore, here, configurations that are the same as or similar to those of the semiconductor module 10 will be described as necessary, and descriptions of configurations that are the same as or similar to those of the semiconductor module 10 may be omitted.

[0090] The semiconductor module 10A includes a stacked memory chip 100A, a TCI-IO chip 300A, a logic chip 200, and an adhesive layer 400. The semiconductor module 10A may include a bump layer 500 and a substrate 600, similar to the semiconductor module 10. The logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 are similar to the logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 included in the semiconductor module 10. A detailed description of the logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 will be omitted here.

[0091] 11, the multiple inductors 71 included in the stacked memory chip 100A are arranged in a matrix along the first direction D1 and the second direction D2. For example, the multiple inductors 71 are arranged at a distance PH in the first direction D1 and at a distance PV in the second direction D2.

[0092] 12, the multiple inductors 71 included in the TCI-IO chip 300A are arranged in a matrix along the first direction D1 and the second direction D2. For example, the multiple inductors 71 are arranged at a distance PH in the first direction D1 and at a distance PV in the second direction D2.

[0093] For ease of explanation and to make the drawings easier to understand, the inductors shown in FIG. 12 omit the multiple inductors 71HSH, the multiple inductors 71VSH, and the multiple inductors 71DSH shown in FIG. 13, and the inductors shown in FIG. 13 omit the multiple inductors 71 shown in FIG. 12.

[0094] 13 , the multiple inductors 71HSH, the multiple inductors 71VSH, and the multiple inductors 71DSH are arranged in a matrix along the first direction D1 and the second direction D2, respectively. Although not shown, the multiple inductors 71 are arranged at a distance PH in the first direction D1 and at a distance PV in the second direction D2, and therefore the multiple inductors 71HSH, the multiple inductors 71VSH, and the multiple inductors 71DSH, which are arranged at positions shifted with respect to the multiple inductors 71, are arranged at a distance PH in the first direction D1 and at a distance PV in the second direction D2.

[0095] 14 is an enlarged plan view of the inductor 71, the inductor 71HSH, the inductor VSH, and the inductor DSH shown in FIG. 12 or 13. The inductor 71HSH is disposed at a position offset by a length L1 / 2 from the inductor 71 along the first direction D1. The inductor 71VSH is disposed at a position offset by a length L2 / 2 from the inductor 71 along the second direction D2. The inductor 71DSH is disposed at a position offset by a length L2 / 2 from the inductor 71 along the diagonal direction. For example, the diagonal direction is parallel to a line connecting the via 22 and the via 24 in a plan view along the first direction D1 and the second direction D2.

[0096] In the semiconductor module 10A, the stacked memory chip 100A is stacked on the TCI-IO chip 300A using the adhesive layer 400. At this time, the multiple inductors 71 of the stacked memory chip 100A are arranged parallel to and facing the multiple inductors 71 of the TCI-IO chip 300A. That is, each of the multiple inductors 71 of the stacked memory chip 100A overlaps with the inductors 71 of the TCI-IO chip 300A that are arranged parallel to and facing each other. As a result, for example, one inductor 71 of the stacked memory chip 100A and one inductor 71 of the TCI-IO chip 300A that face each other are magnetically coupled, and one inductor 71 of the stacked memory chip 100A and one inductor 71 of the TCI-IO chip 300A can communicate one-to-one and contactlessly.

[0097] Furthermore, in the semiconductor module 10A, the multiple inductors 71 of the stacked memory chip 100A are not overlapped, but the TCI-IO chip 300A is positioned offset from the position of the reference inductor 71 and includes inductors 71HSH, 71VSH, and 71DSH that are positioned overlapping each other.

[0098] Therefore, even if the stacked memory chips 100A are stacked misaligned with respect to the TCI-IO chips 300A, the inductors 71 of the stacked memory chips 100A can select an inductor at an optimal position that enables optimal communication from among inductors that are arranged at offsets in the first direction D1, the second direction D2, and the diagonal direction with respect to the position of the reference inductor 71 on the TCI-IO chip 300A side, and can perform inductor communication with the selected inductor. In other words, the TCI-IO chip 300A includes multiple inductors that are arranged at offset positions and overlapping each other, and therefore includes inductors that are capable of inductor communication depending on the misalignment with the stacked memory chips 100A, and can suppress misalignment of the stacked memory chips 100A with respect to the TCI-IO chips 300A. Therefore, the semiconductor module 10A can suppress signal loss in the inductor communication and suppress degradation of the quality of the inductor communication.

[0099] Third Embodiment A semiconductor module 10B according to a third embodiment will be described with reference to FIGS. 15 to 18. FIG. 15 is a plan view showing a plurality of inductors 71 included in a stacked memory chip 100B included in the semiconductor module 10B. FIG. 16 is an enlarged plan view of a portion of the plurality of inductors 71 shown in FIG. 15. FIG. 17 is a plan view showing a plurality of inductor groups 371C included in a TCI-IO chip 300B included in the semiconductor module 10B. FIG. 18 is an enlarged plan view of a portion of the plurality of inductor groups 371C shown in FIG. 17. Configurations that are the same as or similar to those in FIGS. 1 to 14 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 14 may be omitted.

[0100] 11, the stacked memory chip 100B shown in Fig. 15 is a plan view of the inductor 71 as seen from the first surface 146 side, and for convenience of explanation, the multiple inductors 71 appear to be the same as the first surface 146, but the multiple inductors 71 are actually separated from the first surface 146 like the inductors 71 shown in Fig. 11. Also, the stacked memory chip 100B shown in Fig. 15 omits the multiple TCI-IOs 312 in the stacked memory chip 100, as with the stacked memory chip 100A shown in Fig. 11. 17 is a plan view of a plurality of inductor groups 371C viewed from the first surface 302 side, similar to the TCI-IO chip 300 shown in Fig. 4, and for convenience of explanation, the plurality of inductor groups 371C appear to be the same as the first surface 302, but the plurality of inductor groups 371C are actually separated from the first surface 302 like the inductor group 371 shown in Fig. 2. Although not shown in the figure, similar to the TCI-IO chip 300, the plurality of TCI-IOs 312 are electrically connected to the plurality of inductor groups 371C.

[0101] The semiconductor module 10B differs from the semiconductor module 10 in the following configurations (1) to (3): (1) The inductor group 171 including multiple inductors 71 in the stacked memory chip 100 of the semiconductor module 10 is replaced with the inductor 71 in the stacked memory chip 100B. In other words, the inductor group 171 including multiple inductors 71 is replaced with a single inductor 71. (2) The inductor group 371 including multiple inductors 71 in the TCI-IO chip 300 of the semiconductor module 10 is replaced with an inductor group 371C including multiple inductors 71 in the TCI-IO chip 300B. For example, the inductor group 371C includes multiple inductors 71 that are arranged at positions shifted in one direction (e.g., the first direction D1) and that overlap each other. (3) The multiple inductors 71 of the stacked memory chip 100B and the multiple inductor groups 371C of the TCI-IO chip 300B are arranged at a distance PH2 in the first direction D1 and at a distance PV2 in the second direction D2.

[0102] The configurations of the semiconductor module 10B other than those shown in (1) to (3) are the same as those of the semiconductor module 10. Therefore, here, configurations that are the same as or similar to those of the semiconductor module 10 will be described as necessary, and descriptions of configurations that are the same as or similar to those of the semiconductor module 10 may be omitted.

[0103] The semiconductor module 10B includes a stacked memory chip 100B, a TCI-IO chip 300B, a logic chip 200, and an adhesive layer 400. The semiconductor module 10B may include a bump layer 500 and a substrate 600, similar to the semiconductor module 10. The logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 are similar to the logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 included in the semiconductor module 10. A detailed description of the logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 will be omitted here.

[0104] 15 and 16 , the multiple inductors 71 included in the stacked memory chip 100B are arranged in a matrix along the first direction D1 and the second direction D2. As described above, the multiple inductors 71 are arranged at a distance PH2 in the first direction D1 and at a distance PV2 in the second direction D2. The multiple inductors 71 included in the stacked memory chip 100B have a configuration similar to the multiple inductors 71 in the stacked memory chip 100 of the semiconductor module 10, and therefore a detailed description of the configuration of the inductors 71 will be omitted here.

[0105] 17, the multiple inductor groups 371C included in the TCI-IO chip 300B are arranged in a matrix along the first direction D1 and the second direction D2. As described above, the multiple inductor groups 371C are arranged at a distance PH2 in the first direction D1 and at a distance PV2 in the second direction D2.

[0106] As shown in FIG. 18 , the inductor groups 371C include multiple inductors 71. For example, one inductor group 371C includes inductors 71L, 71M, 71C, 71N, 71O, 71P, 71Q, and 71R. That is, the semiconductor module 10B includes a configuration in which the multiple inductors 71 are arranged in seven sections along the first direction D1. The direction in which the multiple inductors 71 are arranged in a shifted manner may be the second direction D2. Furthermore, the number of sections along the first direction D1 or the second direction D2 may be other than seven. Increasing the number of sections increases the rate at which alignment can be achieved with respect to misalignment between the stacked memory chip 100B and the TCI-IO chip 300B. Note that each of the inductors 71L, 71M, 71C, 71N, 71O, 71P, 71Q, and 71R has a configuration similar to the inductor 71 included in the stacked memory chip 100B shown in FIG. 6 . Therefore, a detailed description of the configuration of the inductor 71 will be omitted here.

[0107] In the inductors 71L, 71M, 71C, 71N, 71O, 71P, 71Q, and 71R, the distance between adjacent inductors along the first direction D1 is a distance PX1, and the distance between adjacent inductors along the second direction D2 is a distance PY1. To accommodate misalignment between the stacked memory chip 100B and the TCI-IO chip 300B, adjacent inductors are spaced apart by a distance PX1 along the first direction D1. Furthermore, to prevent adjacent inductors from shorting out, adjacent inductors are spaced apart by a distance PY1 along the second direction D2. Therefore, the inductors 71L, 71M, 71C, 71N, 71O, 71P, 71Q, and 71R can be arranged overlapping each other without shorting out each other.

[0108] For example, in the inductor 71, the length L1 is 72 μm, the length L2 is 56 μm, the distance PX1 is 1.6 μm, the distance PY1 is 8 μm, the distance PH2 is 83.2 μm, and the distance PV2 is 112 μm.

[0109] Therefore, even if the stacked memory chip 100B is stacked misaligned with respect to the TCI-IO chip 300B, the inductor 71 of the stacked memory chip 100B can select an inductor at an optimal position that enables optimal communication from among the seven inductors that are arranged and shifted along the first direction D1 on the TCI-IO chip 300B side, and can perform inductor communication with the selected inductor. In other words, the TCI-IO chip 300B includes multiple inductors that are arranged and shifted along the first direction D1 and are overlapped, and therefore includes inductors that are capable of inductor communication depending on the misalignment with the stacked memory chip 100B, and can suppress misalignment of the stacked memory chip 100B with respect to the TCI-IO chip 300B. Therefore, the semiconductor module 10B can suppress signal loss in the inductor communication, similar to the semiconductor module 10, and can suppress deterioration in the quality of the inductor communication.

[0110] Fourth Embodiment A semiconductor module 10C according to a fourth embodiment will be described with reference to Fig. 19. Fig. 19 is a plan view showing a plurality of inductors 71 and a plurality of inductors 71HSH included in a TCI-IO chip 300C included in the semiconductor module 10C. Configurations that are the same as or similar to those in Figs. 1 to 18 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 18 may be omitted.

[0111] 12 and 13, the TCI-IO chip 300C shown in Fig. 19 is a plan view of the multiple inductors 71 and the like as seen from the first surface 302 side, and for convenience of explanation, the multiple inductors 71 and the like appear to be the same as the first surface 302, but the multiple inductors 71 are actually separated from the first surface 302 like the inductor group 371 shown in Fig. 12 and 13. Furthermore, although not shown in the drawings, the multiple TCI-IO chips 312 are electrically connected to the multiple inductors 71 and the multiple inductors 71HSH.

[0112] The semiconductor module 10C differs from the semiconductor module 10A in the following configuration (1): (1) The TCI-IO chip 300C includes a plurality of inductors 71 that serve as reference inductors for arranging the inductors at shifted positions, and a plurality of inductors 71 that are arranged at positions shifted in one direction (for example, the first direction D1) from the plurality of reference inductors 71 and that overlap with the plurality of reference inductors 71.

[0113] The configuration of the semiconductor module 10C other than the configuration indicated by (1) is the same as that of the semiconductor module 10A. Therefore, here, configurations that are the same as or similar to those of the semiconductor module 10A will be described as necessary, and descriptions of configurations that are the same as or similar to those of the semiconductor module 10A may be omitted.

[0114] The semiconductor module 10C includes a stacked memory chip 100A, a TCI-IO chip 300C, a logic chip 200, and an adhesive layer 400. Similar to the semiconductor module 10A, the semiconductor module 10C may include a bump layer 500 and a substrate 600. The logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 are similar to the logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 included in the semiconductor module 10. Detailed descriptions of the logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 will be omitted here.

[0115] 19, the TCI-IO chip 300C includes a plurality of inductors 71 that serve as references for arranging inductors with offset positions. Similar to the plurality of inductors 71 of the TCI-IO chip 300A, the plurality of inductors 71 of the TCI-IO chip 300C are arranged in a matrix along the first direction D1 and the second direction D2. For example, the plurality of inductors 71 are arranged at a distance PH in the first direction D1 and at a distance PV in the second direction D2.

[0116] 19, the TCI-IO chip 300C includes a plurality of inductors 71 that are arranged at positions offset in one direction from a plurality of reference inductors 71 and that overlap with the plurality of reference inductors 71. For example, the one direction is the first direction D1. For example, the one direction may be the second direction D2 or a diagonal direction. The direction in which the plurality of reference inductors 71 are offset can be selected as appropriate depending on the specifications, applications, etc. of the semiconductor module 10C.

[0117] For example, the TCI-IO chip 300C includes a plurality of inductors 71HSH. Similar to the plurality of inductors 71HSH of the stacked memory chip 100A, the plurality of inductors 71HSH of the TCI-IO chip 300C are arranged in a matrix along the first direction D1 and the second direction D2. For example, the plurality of inductors 71 are arranged at a distance PH in the first direction D1 and at a distance PV in the second direction D2. Also, similar to the plurality of inductors 71HSH of the stacked memory chip 100A, for example, each of the plurality of inductors 71HSH of the TCI-IO chip 300C is arranged at a position offset by a length (L1 / 2) of half the coil diameter L1 along the first direction D1, with respect to the position of the corresponding inductor 71. In other words, for inductors arranged offset along the first direction D1 with respect to the position of the inductor 71, the value n in L1 / n is 2.

[0118] Furthermore, similar to the semiconductor module 10, in order to prevent adjacent inductors in the same direction from shorting out, adjacent inductors in the same direction are arranged with a shift in a direction different from the same direction to an extent that will prevent shorting. For example, in order to prevent adjacent inductors in the first direction D1 from shorting out, adjacent inductors in the second direction D2 are arranged with a slight shift in the direction D2.

[0119] Therefore, even if the stacked memory chips 100A in the semiconductor module 10C are stacked misaligned with respect to the TCI-IO chips 300C, the inductors 71 of the stacked memory chips 100A can select an inductor that is optimally positioned to enable optimal communication from among the inductors that are positioned misaligned in one direction with respect to the reference inductor 71 on the TCI-IO chip 300C side, and can communicate with the selected inductor. In other words, the TCI-IO chip 300C includes an inductor that is capable of inductor communication depending on the misalignment with the stacked memory chips 100A, and can suppress misalignment of the stacked memory chips 100A with respect to the TCI-IO chips 300C. Therefore, the semiconductor module 10C can suppress signal loss in the inductor communication and suppress degradation in the quality of the inductor communication.

[0120] Furthermore, the semiconductor module 10C includes a configuration in which the inductors 71 are arranged with their positions shifted so that the direction of the inductors is limited to one direction. As a result, the overlapping of the inductors is limited to one direction. This allows for a reduction in the amount of wiring used, such as the length and number of wiring connecting to the inductor 71.

[0121] Fifth Embodiment A semiconductor module 10D according to a fifth embodiment will be described with reference to Fig. 20. Fig. 20 is a plan view showing a plurality of inductors 71 and a plurality of inductors 71VSH included in a stacked memory chip 100D included in the semiconductor module 10D. Configurations that are the same as or similar to those in Figs. 1 to 19 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 18 may be omitted.

[0122] 11, the stacked memory chip 100D shown in Fig. 20 is a plan view of the multiple inductors 71 and the like as seen from the first surface 146 side, and for convenience of explanation, the multiple inductors 71 and the like appear to be the same as the first surface 146, but the multiple inductors 71 and the like are actually separated from the first surface 146 like the multiple inductors 71 shown in Fig. 11. Furthermore, although not shown in the figure, the multiple TCI-IOs 112 are electrically connected to the multiple inductors 71 and the multiple inductors 71VSH.

[0123] The semiconductor module 10D differs from the semiconductor module 10C in the following configuration (1): (1) The stacked memory chip 100D includes a plurality of inductors 71 serving as reference inductors for arranging the inductors at shifted positions, and a plurality of inductors 71VSH that are arranged at positions shifted in the second direction D2 from the plurality of reference inductors 71 and overlap with each other.

[0124] The configuration of the semiconductor module 10D other than the configuration indicated by (1) is the same as that of the semiconductor module 10C. Therefore, here, the configuration that is the same as or similar to that of the semiconductor module 10C will be described as necessary, and the description of the configuration that is the same as or similar to that of the semiconductor module 10C may be omitted.

[0125] The semiconductor module 10D includes a stacked memory chip 100D, a TCI-IO chip 300C, a logic chip 200, and an adhesive layer 400. Similar to the semiconductor module 10C, the semiconductor module 10D may include a bump layer 500 and a substrate 600. The logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 are similar to the logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 included in the semiconductor module 10. Detailed descriptions of the logic chip 200, adhesive layer 400, bump layer 500, and substrate 600 will be omitted here.

[0126] 20 , the stacked memory chip 100D includes a plurality of inductors 71 that serve as references for arranging the inductors in a staggered manner. Similar to the plurality of inductors 71 in the stacked memory chip 100A, the plurality of inductors 71 in the stacked memory chip 100D are arranged in a matrix along the first direction D1 and the second direction D2. For example, the plurality of inductors 71 are arranged at a distance PH in the first direction D1 and at a distance PV in the second direction D2.

[0127] As described above, as shown in FIG. 20, the stacked memory chip 100D includes a plurality of inductors 71VSH that are arranged at positions shifted in the second direction D2 from and overlap with the plurality of reference inductors 71.

[0128] For example, the multiple inductors 71VSH of the stacked memory chip 100D are arranged in a matrix along the first direction D1 and the second direction D2, similar to the multiple inductors 71VSH of the TCI-IO chip 300A. For example, the multiple inductors 71VSH of the stacked memory chip 100D are arranged at a distance PH in the first direction D1 and a distance PV in the second direction D2. Also, for example, similar to the multiple inductors 71VSH of the TCI-IO chip 300A, each of the multiple inductors 71VSH of the stacked memory chip 100D is arranged at a position where the corresponding inductor 71 is shifted along the second direction D2 by a length (L2 / 2) that is half the coil diameter L2, based on the position of the inductor 71. In other words, for inductors that are shifted along the second direction D2 based on the position of the inductor 71, the value n in L2 / n is 2.

[0129] 19, the TCI-IO chip 300C includes a plurality of inductors 71HSH. The plurality of inductors 71HSH are arranged at positions shifted by a length (L1 / 2) that is ½ of the coil diameter L1 along the first direction D1 from the positions of the plurality of inductors 71 of the TCI-IO chip 300C as a reference.

[0130] Furthermore, in order to prevent adjacent inductors in the same direction from shorting out, similarly to the semiconductor module 10, adjacent inductors in the same direction are arranged with a shift in a direction different from the same direction to an extent that will not cause a short circuit. For example, to prevent a short circuit, adjacent inductors in the first direction D1 are arranged with a slight shift in the second direction D2, and adjacent inductors in the second direction D2 are arranged with a slight shift in the first direction D1.

[0131] Therefore, the stacked memory chip 100D and the TCI-IO chip 300C include inductors that are arranged to be shifted in different directions from each other with respect to the position of the reference inductor 71. For example, as described above, the different directions are the first direction D1 and the second direction D2, and a line along the first direction D1 is rotated 90 degrees from a line along the second direction D2. In other words, the semiconductor module 10D includes a configuration in which the inductors arranged on different chips are arranged to be shifted in directions that are rotated 90 degrees from each other with respect to the position of the reference inductor 71.

[0132] Therefore, even if the stacked memory chips 100D in the semiconductor module 10D are stacked with a shift in the first direction D1 relative to the TCI-IO chips 300C, the inductors 71 of the stacked memory chips 100D can select an inductor that is optimally positioned to enable optimal communication from among the inductors that are shifted in the first direction D1 from the position of the reference inductor 71 on the TCI-IO chip 300C side, and can perform inductor communication with the selected inductor. Also, even if the stacked memory chips 100D in the semiconductor module 10D are stacked with a shift in the second direction D2 relative to the TCI-IO chips 300C, the inductors 71 of the TCI-IO chip 300C can select an inductor that is optimally positioned to enable optimal communication from among the inductors that are shifted in the second direction D2 from the position of the reference inductor 71 on the stacked memory chips 100A side, and can perform inductor communication with the selected inductor. That is, the semiconductor module 10D has a stacked memory chip 100D and a TCI-IO chip 300C that can suppress misalignment in different directions, and can suppress misalignment in different directions. Therefore, the semiconductor module 10D can suppress signal loss in the inductor communication and suppress deterioration in the quality of the inductor communication.

[0133] Furthermore, the semiconductor module 10D includes a configuration in which the direction of the inductors 71, which are arranged by shifting the positions of the inductors, is limited to one direction in each of the stacked memory chips 100D and the TCI-IO chips 300C. As a result, the overlapping of the inductors is limited to one direction in each of the stacked memory chips 100D and the TCI-IO chips 300C. Therefore, for example, in each of the stacked memory chips 100D and the TCI-IO chips 300C, it is possible to reduce the amount of wiring used, such as the length and number of wiring connecting to the inductors 71.

[0134] Sixth Embodiment A semiconductor module 10E according to a sixth embodiment will be described with reference to Fig. 21. Fig. 21 is an enlarged plan view of a portion of a plurality of inductors 71 included in the semiconductor module 10E. Configurations that are the same as or similar to those in Figs. 1 to 20 will be described as necessary, and descriptions of configurations that are the same as or similar to those in Figs. 1 to 20 may be omitted.

[0135] The multiple inductors 71 included in the semiconductor module 10E can be appropriately applied to the multiple inductors 71 of the stacked memory chips and the multiple inductors 71 of the TCI-IO chips included in the semiconductor modules 10, 10A, 10B, 10C, or 10D, as long as there is no mutual contradiction. Note that the configuration of each of the multiple inductors 71 included in the semiconductor module 10E is the same as the configuration of the inductor 71 included in the semiconductor module 10 described with reference to FIG.

[0136] 21 , the multiple inductors 71 are arranged in a matrix along the first direction D1 and the second direction D2. For example, the lengths L1 and L2 of the inductors 71 are 65 μm, the distance between the second wirings 31 and 32 is 50 μm, and the distance PH between the inductors 71 arranged in the first direction D1 and the distance PV between the inductors 71 arranged in the second direction D2 are 110 μm.

[0137] For example, in order to suppress misalignment in both the first direction D1 and the second direction D2 when stacked memory chips are stacked with a misalignment relative to the TCI-IO chip, the semiconductor module 10E includes a first configuration divided into two parts in both the first direction D1 and the second direction D2. For example, the first configuration includes two inductors arranged with a 30 μm offset from the reference inductor 71 along the first direction D1, and two inductors arranged with a 30 μm offset from the reference inductor 71 along the second direction D2. In other words, the first configuration includes four inductors arranged with a 30 μm offset from the reference inductor 71. In this case, the value n of L1 / n and L2 / n is 2.

[0138] Furthermore, for example, in order to suppress misalignment in both the first direction D1 and the second direction D2 when stacked memory chips are stacked with a misalignment relative to the TCI-IO chip, the semiconductor module 10E may include a second configuration divided into three parts in both the first direction D1 and the second direction D2. For example, the second configuration includes three inductors arranged with the inductor 71 as a reference, shifted by 20 μm along the first direction D1, and three inductors arranged with the inductor 71 as a reference, shifted by 20 μm along the second direction D2. In other words, the second configuration includes nine inductors arranged with the inductor 71 as a reference. In this case, the value n of L1 / n and L2 / n is 3.

[0139] Furthermore, for example, in order to suppress misalignment in both the first direction D1 and the second direction D2 when stacked memory chips are stacked with a misalignment relative to the TCI-IO chip, the semiconductor module 10E may include a third configuration divided into four parts in both the first direction D1 and the second direction D2. For example, the third configuration includes four inductors arranged with the inductor 71 as a reference, shifted by 15 μm along the first direction D1, and four inductors arranged with the inductor 71 as a reference, shifted by 15 μm along the second direction D2. In other words, the third configuration includes 16 inductors arranged with the inductor 71 as a reference. In this case, the value n of L1 / n and L2 / n is 4.

[0140] As described above, the multiple inductors 71 included in the semiconductor module 10E provide a high degree of design freedom to accommodate misalignment that may occur when stacked memory chips are stacked misaligned relative to the TCI-IO chips. Note that the first, second, and third configurations of the semiconductor module 10E are merely examples, and the number of divisions in the semiconductor module 10E is not limited to the first, second, and third configurations. The number of divisions in the semiconductor module 10E can be selected as appropriate depending on the specifications, applications, etc. of the semiconductor module 10E.

[0141] Seventh Embodiment An example of an inductor communication method for a semiconductor module 10 according to a seventh embodiment will be described with reference to FIGS. 7, 22, and 23. FIGS. 22 and 23 are flowcharts showing an example of an inductor communication method for a semiconductor module 10. Configurations that are the same as or similar to those in FIGS. 1 to 21 will be described as necessary, and descriptions of configurations that are the same as or similar to those in FIGS. 1 to 21 may be omitted. The inductor communication method for a semiconductor module 10 according to the seventh embodiment can be applied as appropriate to the semiconductor modules according to each embodiment as long as there is no mutual contradiction.

[0142] 7-1. Configuration of the Logic Module 211 First, the configuration of the logic module 211 of the semiconductor module 10 will be described with reference to the functional blocks shown in Fig. 7. For example, the logic module 211 included in the semiconductor module 10 includes a determination circuit 221, a path / failure map generation circuit 222, and a table 223.

[0143] For example, the determination circuit 221 has a function capable of determining pass or fail based on strength data of inductor communication. The determination circuit 221 can set a threshold value capable of determining pass or fail based on the strength data of inductor communication. For example, the threshold value may be data based on the strength of communication (i.e., communication strength data), may be data of induced current of the inductor 71 included in the inductor group 171 of the stacked memory chip 100 or the inductor 71 included in the inductor group 371 of the TCI-IO chip 300, or may be data of voltage based on the induced current of the inductor 71 of the stacked memory chip 100 or the inductor 71 of the TCI-IO chip 300. The inductor 71 included in the inductor group 171 of the stacked memory chip 100 may be referred to as a first inductor, and the inductor 71 included in the inductor group 171 of the TCI-IO chip 300 may be referred to as a second inductor.

[0144] For example, the determination circuit 221 determines that inductor communication has succeeded (passed) based on the set thresholds when the following first and second conditions are met. Alternatively, the inductor with the shortest response time between transmitting the first signal and receiving the third signal and the shortest response time between transmitting the second signal and receiving the fourth signal may be determined to be a pass. Note that data 0 may be a voltage or current smaller than data 1, and data 0 may be a voltage or voltage larger than data 1. First condition: A first signal changing from data 0 to data 1 is transmitted from the second inductor to the first inductor, and the second inductor receives a third signal changing from data 0 to data 1 from the first inductor. Second condition: A second signal changing from data 1 to data 0 is transmitted from the second inductor to the first inductor, and the second inductor receives a fourth signal changing from data 1 to data 0 from the first inductor.

[0145] Furthermore, for example, the determination circuit 221 determines that inductor communication has failed based on the set thresholds when the following third and fourth conditions are met. Third condition: When a first signal that changes from data 0 to data 1 is transmitted from the second inductor to the first inductor, and the second inductor receives a fifth signal with data 0 that remains unchanged or a sixth signal with data 1 that remains unchanged from the first inductor. Fourth condition: When a second signal that changes from data 0 to data 1 is transmitted from the second inductor to the first inductor, and the second inductor receives a fifth signal with data 0 that remains unchanged or a sixth signal with data 1 that remains unchanged from the first inductor.

[0146] For example, the path / failure map generating circuit 222 has a function of generating a path / failure map of matched (aligned) first inductors and second inductors based on the determination result of the inductor communication by the determination circuit.

[0147] For example, the table 223 stores (memorizes) the path / failure map generated by the path / failure map generation circuit 222. For example, the table 223 is a storage circuit, and stores a first inductor and a second inductor that are linked together, and stores a pass or a fail in the linked first inductor and second inductor.

[0148] The configuration of the semiconductor module 10 other than the configuration shown in the logic module 211 is the same as that of the semiconductor module 10 described in the first embodiment.

[0149] 22, an example of an inductor communication method of the semiconductor module 10 will be described. The example of the inductor communication method of the semiconductor module 10 shows inductor communication between the inductor group 171 (the inductor 71 included in the inductor group 171) and the inductor group 371 (the inductor 71 included in the inductor group 371).

[0150] 22, when inductor communication of the semiconductor module 10 is started, the logic chip 200 executes a first instruction to select the inductor group 171 (the inductor 71 included in the inductor group 171) and the inductor group 371 (the inductor 71 included in the inductor group 371) (step 11 (S11) in FIG. 22). The first instruction may be an instruction to select all the inductors included in the TCI-IO chip 300 and the stacked memory chip 100, or may be an instruction to select some of the inductors included in the TCI-IO chip 300 and the stacked memory chip 100.

[0151] Next, after the first command, the logic chip 200 executes a second command to perform inductor communication between the selected inductor group 171 (the inductor 71 included in the inductor group 171) and the inductor group 371 (the inductor 71 included in the inductor group 371) (step 13 (S13) in FIG. 22 ). For example, the second command includes a command to transmit to the inductor group 371 (the inductor 71 included in the inductor group 371) a first signal that changes from data 0 to data 1 and a second signal that changes from data 1 to data 0, and to instruct the inductor group 171 (the inductor 71 included in the inductor group 171) to return a response.

[0152] For example, the logic module 211 of the logic chip 200 sends the first instruction and the second instruction to the TCI-IO chip 300 and the stacked memory chip 100 to execute the first instruction and the second instruction.

[0153] For example, if the inductors selected in S11 are all the inductors included in the TCI-IO chip 300 and the stacked memory chip 100, inductor communication is performed for all combinations of the multiple inductors 71 included in the inductor group 371 and the multiple inductors 71 included in the inductor group 171 that face each other, among the combinations of the multiple inductor groups 371 and the multiple inductors 71 included in the inductor group 171.

[0154] Next, the logic chip 200 executes a third instruction executed in S13 to acquire the result of the inductor communication between the selected inductor group 171 (the inductor 71 included in the inductor group 171) and the inductor group 371 (the inductor 71 included in the inductor group 371) (step 15 (S15) in FIG. 22 ). For example, the result of the inductor communication is a third signal from the inductor group 171 (the inductor 71 included in the inductor group 171) that changes from data 0 to data 1, a fourth signal that changes from data 1 to data 0, a fifth signal that includes data 0 with no data change, or a sixth signal that includes data 1 with no data change. For example, the first signal to the sixth signal may be data based on the strength of communication (i.e., communication strength data), may be data on the induced current of the inductor 71 included in the inductor group 171 of the stacked memory chip 100 or the inductor 71 included in the inductor group 371 of the TCI-IO chip 300, or may be data on the voltage based on the induced current of the inductor 71 (e.g., the first inductor) of the stacked memory chip 100 or the inductor 71 (e.g., the second inductor) of the TCI-IO chip 300.

[0155] For example, the logic module 211 of the logic chip 200 transmits a third command to the TCI-IO chip 300 and the stacked memory chip 100 to execute the third command. Furthermore, the logic module 211 of the logic chip 200 acquires data on the induced current of the inductor 71 included in the inductor group 171 of the stacked memory chip 100 or the inductor 71 included in the inductor group 371 of the TCI-IO chip 300 from the TCI-IO chip 300 and the stacked memory chip 100.

[0156] Next, the determination circuit 221 of the logic module 211 of the logic chip 200 executes a fourth command to determine pass or fail using data based on the communication strength acquired in S15 (step 17 (S17) in FIG. 22).

[0157] For example, in S17, the logic module 211 executes a fourth instruction for determining pass or fail, and the determination circuit 221 determines pass or fail based on the data based on the communication strength acquired in S15. For example, if the logic module 211 transmits the first signal and receives the third signal, and if the logic module 211 transmits the second signal and receives the fourth signal, the determination circuit 221 determines pass. If the logic module 211 transmits the first signal and receives the fifth or sixth signal, and if the logic module 211 transmits the second signal and receives the fifth or sixth signal, the determination circuit 221 determines fail. As a result, by executing S17, the semiconductor module 10 can align the inductors, determine a combination of inductors that is well-aligned, and select a combination of inductors that is well-aligned. For example, good alignment may indicate that the induced current is at a maximum, or that the voltage based on the induced current is at a maximum.

[0158] Next, for example, the path / failure map generation circuit 222 of the logic module 211 of the logic chip 200 generates a path / failure map using the inductor combinations and the determination results based on the inductor combinations in S17 (step 19 (S19) in FIG. 22 ). Furthermore, based on the generated path / failure map, the logic module 211 stores the inductors 71 of the associated inductor group 171 and the inductors 71 of the associated inductor group 371 in the table 223, and stores passes or fails in the inductors 71 of the associated inductor group 171 and the inductors 71 of the inductor group 371.

[0159] In this way, the semiconductor module 10 generates a pass / fail map, and can perform inductor communication using a combination of aligned inductor groups (combination of inductors) based on the pass / fail map.

[0160] The sequence in which the semiconductor module 10 determines and selects a combination of inductors that are aligned through steps S11 to S17 may be called a training sequence. For example, by repeatedly executing the training sequence, the semiconductor module 10 may adjust the characteristics of the inductors that have become misaligned over time as the semiconductor module 10 is used.

[0161] Furthermore, for example, when inductor communication is performed by S11 and S12 for all combinations of the plurality of inductors 71 included in the inductor group 371 and the plurality of inductors 71 included in the inductor group 171 that face each other, among the combinations of the plurality of inductor groups 371 and the plurality of inductor groups 171, the combination of inductors for which a response is first confirmed in S13 is determined to be an aligned (passed) inductor in S15. In other words, the combination of inductors with a fast response speed is determined to be an aligned inductor combination.

[0162] Therefore, the inductor communication method of the semiconductor module 10 may include repeating S11 to S17 multiple times and executing S19. In this case, the logic chip 200 executes S11 to S17 once to determine a combination of inductors with a fast response speed, and executes S11 to S17 a second time after the first execution of S11 to S17. Furthermore, in the second execution of S11 to S17, the logic chip 200 controls the TCI-IO chip 300 and the stacked memory chip 100 to execute first to third instructions for inductor communication using a combination of inductor group 171 and inductor group 371 located around the combination of inductors with a fast response speed. Here, for example, the periphery of the combination of inductors with a fast response speed refers to the combination of inductor group 171 and inductor group 371 located above, below, left, and right of the combination of inductors with a fast response speed.

[0163] As a result, the inductor communication method of the semiconductor module 10 can generate a pass / fail map without performing inductor communication for all combinations of inductor groups. Also, the inductor communication method of the semiconductor module 10 can quickly search for the combination of inductors with the best alignment.

[0164] 23 , another example of the inductor communication method of the semiconductor module 10. Similar to the example of the inductor communication method of the semiconductor module 10, this example of the inductor communication method of the semiconductor module 10 illustrates inductor communication between the inductor group 171 (the inductor 71 included in the inductor group 171) and the inductor group 371 (the inductor 71 included in the inductor group 371).

[0165] For example, step 21 (S21) is executed as shown in Fig. 23. S21 is the same as S11.

[0166] Next, after the first command, the logic chip 200 executes a fourth command to change the magnitude of power between the selected inductor group 171 (the inductor 71 included in the inductor group 171) and the selected inductor group 371 (the inductor 71 included in the inductor group 371) and perform inductor communication at multiple power magnitudes (step 23 (S23) in FIG. 23 ). For example, the multiple power magnitudes are a first power, a second power greater than the first power, and a third power greater than the second power. The first power, second power, and third power may be powers with constant current and varying voltage, or may be powers with constant voltage and varying current. Note that the multiple power magnitudes are not limited to three, but may be two, four, or more. For example, the fourth command includes a command to transmit a first power signal, a second power signal, and a third power signal to the inductor group 371 (the inductor 71 included in the inductor group 371) and to instruct the inductor group 171 (the inductor 71 included in the inductor group 171) to return a response.

[0167] For example, the logic module 211 of the logic chip 200 transmits the first instruction and the fourth instruction to the TCI-IO chip 300 and the stacked memory chip 100 to execute the first instruction and the fourth instruction.

[0168] For example, if the inductors selected in S21 are all inductors included in the TCI-IO chip 300 and the stacked memory chip 100, inductor communication is performed for all combinations of multiple inductor groups 371 and multiple inductor groups 171, including multiple inductors 71 included in inductor group 371 that face each other and multiple inductors 71 included in inductor group 171.

[0169] Next, the logic chip 200 executes a fifth instruction executed in S23 to acquire the result of the inductor communication between the selected inductor group 171 (the inductor 71 included in the inductor group 171) and the inductor group 371 (the inductor 71 included in the inductor group 371) (step 25 (S25) in FIG. 23 ). For example, the result of the inductor communication is a first reply signal to the signal of the first power from the inductor group 171 (the inductor 71 included in the inductor group 171), a second reply signal to the signal of the second power, and a third reply signal to the signal of the third power. For example, the first reply signal to the third reply signal may be data based on the strength of communication (i.e., communication strength data), may be data on the induced current of the inductor 71 included in the inductor group 171 of the stacked memory chip 100 or the inductor 71 included in the inductor group 371 of the TCI-IO chip 300, or may be data on the voltage based on the induced current of the inductor 71 (for example, the first inductor) of the stacked memory chip 100 or the inductor 71 (for example, the second inductor) of the TCI-IO chip 300.

[0170] For example, the logic module 211 of the logic chip 200 transmits a fifth command to the TCI-IO chip 300 and the stacked memory chip 100 to execute the fifth command. Also, for example, the logic module 211 of the logic chip 200 acquires data on the induced current of the inductor 71 included in the inductor group 171 of the stacked memory chip 100 or the inductor 71 included in the inductor group 371 of the TCI-IO chip 300 from the TCI-IO chip 300 and the stacked memory chip 100.

[0171] Next, the determination circuit 221 of the logic module 211 of the logic chip 200 executes a sixth command to determine pass or fail using data based on the communication strength acquired in S25 (step 27 (S27) in FIG. 23).

[0172] For example, in S27, the logic module 211 executes a fifth command for determining pass or fail, and the determination circuit 221 determines pass or fail based on the data based on the communication strength acquired in S25. For example, if the logic module 211 receives the third reply signal but does not receive the first or second reply signal, the determination circuit 221 determines pass and that the minimum operating power is the third power. For example, if the logic module 211 receives all of the first to third reply signals, the determination circuit 221 determines pass and that the minimum operating power is the first power. For example, if the logic module 211 does not receive all of the first to third reply signals, the determination circuit 221 determines fail. As a result, by executing S27, the semiconductor module 10 can align inductors, determine a combination of inductors that is well-aligned, and calculate the minimum operating power for the combination of inductors that is well-aligned. Furthermore, by executing S27, the semiconductor module 10 can select a combination of inductors that are well aligned.

[0173] Next, for example, the path / failure map generation circuit 222 of the logic module 211 of the logic chip 200 generates a path / failure map using the inductor combinations in S27, the determination results based on the inductor combinations, and the minimum operating power (step 29 (S29) in FIG. 23 ). Furthermore, based on the generated path / failure map, the logic module 211 stores the inductors 71 of the tied inductor group 171 and the inductors 71 of the inductor group 371 in the table 223, and stores pass or fail for the tied inductors 71 of the inductor group 171 and the inductor group 371. Furthermore, if the tied inductors 71 of the inductor group 171 and the inductor group 371 are pass, the logic module 211 stores data on the minimum operating power for the passed inductors 71 of the inductor group 171 and the inductor 71 of the inductor group 371 in the table 223 based on the generated path / failure map.

[0174] In this way, the semiconductor module 10 generates a pass / fail map, and can perform inductor communication with the minimum operating power using a combination of aligned inductors (combination of inductors) based on the pass / fail map.

[0175] The sequence in which the semiconductor module 10 determines and selects a combination of inductors that are aligned according to steps S21 to S27 may be called a training sequence, similar to the sequence in which the semiconductor module 10 determines and selects a combination of inductors that are aligned according to steps S11 to S17. For example, by repeatedly executing the training sequence, the semiconductor module 10 may adjust the characteristics of the inductors that have become deviated over time as the semiconductor module 10 is used.

[0176] <7-4. Modification of the inductor communication method of the semiconductor module 10>

[0177] The inductor communication method of the semiconductor module 10 may support multiple values. For example, transitions of each of the multiple values ​​may be associated with alignment. For example, the combination of inductors (inductor group) with the fastest response speed may be associated with the highest level of quality information, and the quality information may be assigned levels from high (e.g., level 7) to low (e.g., level 0) in order from the combination of inductors (inductor group) with the fastest response speed to the combination of inductors (inductor group) with the slowest response speed.

[0178] The logic module 211 may include a register 224 (see FIG. 7 ). The register 224 is a storage circuit that can set quality information (e.g., level 0, level 1, ..., level 7) corresponding to a combination of inductors (inductor groups) depending on the type of data (image data, character data, etc.) transmitted and received in inductor communication, the frequency (communication speed), power, etc. The table 223 may store linked combinations of inductors (inductor groups) and quality information (register setting values).

[0179] For example, the quality information may be assigned, in the order of level 0, level 1, ..., level 7, to indicate information with high confidentiality, information with a large amount of data (e.g., video data, image data, etc.), data with a high frequency (high communication speed), or data with low power.

[0180] Furthermore, for example, the transition of each of the multiple values ​​may be associated with a group of inductors arranged in the first direction D1 (for example, the horizontal direction). For example, if the multi-value data is eight-value data, eight inductors (groups of inductors) may be provided along the first direction D1, and the eight values ​​may correspond one-to-one to the eight inductors (groups of inductors).

[0181] Furthermore, the inductor communication method of the semiconductor module 10 may include, after the logic chip 200 transmits a signal (e.g., a first signal, a first power signal, etc.) to the stacked memory chips 100, performing a process to confirm that the signal is correctly received by the stacked memory chips 100. For example, the process to confirm that the signal is correctly received is called a verify process or the like in the technical field of memory devices.

[0182] For example, if the semiconductor module 10 simultaneously transmits signals from adjacent inductor groups 371 (inductors 71) included in the TCI-IO chip 300 to adjacent inductor groups 171 (inductors 71) included in the stacked memory chip 100, a collision may occur.

[0183] To avoid such collisions, the semiconductor module 10 may periodically execute a process of checking whether a communication error has occurred. The process of checking whether a communication error has occurred may be a verify process. Furthermore, if the semiconductor module 10 detects a communication error, the semiconductor module 10 may execute a process of retransmitting a signal to the stacked memory chip 100.

[0184] As a result, the semiconductor module 10 can suppress collisions, communication errors, etc. Therefore, the semiconductor module 10 can suppress deterioration in the quality of inductor communication.

[0185] The various configurations of the semiconductor module exemplified as embodiments of the present invention can be combined as appropriate as long as they are not mutually contradictory, and technical matters common to each embodiment are included in each embodiment even if not explicitly stated. Furthermore, semiconductor modules disclosed in this specification and drawings that have been modified by a person skilled in the art to add, delete, or modify components, or to add, omit, or change conditions as appropriate, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0186] Even if there are other effects and advantages different from those brought about by the aspects of the embodiments disclosed in this specification, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they are naturally understood to be brought about by the present invention.

[0187] 10: semiconductor module, 10A: semiconductor module, 10B: semiconductor module, 10C: semiconductor module, 10D: semiconductor module, 10E: semiconductor module, 11: first wiring, 12: first wiring, 13: first wiring, 21: via, 22: via, 23: via, 24: via, 31: second wiring, 32: second wiring, 37: inductor group, 52: bump, 62: electrode, 71: inductor, 71A: inductor, 71B: inductor, 71C: inductor, 71D: inductor, 71DSH: inductor, 71E: inductor, 71F: inductor, 71G: Inductor, 71H: Inductor, 71HSH: Inductor, 71J: Inductor, 71K: Inductor, 71L: Inductor, 71M: Inductor, 71N: Inductor, 71O: Inductor, 71P: Inductor, 71Q: Inductor, 71R: Inductor, 71VSH: Inductor, 100: Stacked memory chip, 100A: Stacked memory chip, 100B: Stacked memory chip, 100D: Stacked memory chip, 102: First surface, 104: Second surface, 110: Chip, 110n: Chip, 111: Memory module, 112: TCI-IO, 113: Parallel-series Conversion circuit, 114: transmitting / receiving circuit, 130: transistor layer, 131: through electrode, 142: fifth surface, 144: sixth surface, 145: third surface, 146: first surface, 147: fourth surface, 148: second surface, 150: wiring layer, 170: inductor layer, 171: inductor group, 171A: inductor group, 171B: inductor group, 173: semiconductor substrate, 174: element isolation region, 175: activation region, 176: transistor, 177: insulating layer, 178: wiring, 179: insulating layer, 180: wiring, 180A: via, 181: insulating layer, 182: insulating layer, 183: wiring, 200: logic Chip, 202: first surface, 204: second surface, 211: logic module, 221: judgment circuit, 222: pass / fail map generation circuit, 223: table, 224: register, 300: TCI-IO chip, 300A: TCI-IO chip, 300B: TCI-IO chip, 300C: TCI-IO chip, 302: first surface, 304: second surface, 311: TCI-IO control module, 312: TCI-IO, 313: parallel-serial conversion circuit, 314: transmitting / receiving circuit, 370: inductor layer, 371: inductor group, 371A: inductor group, 371B: inductor group,371C: inductor group, 400: adhesive layer, 500: bump layer, 600: substrate, 602: first surface, 604: second surface,

Claims

1. A semiconductor module comprising: a first semiconductor chip including a first surface parallel to a first direction and a second direction intersecting the first direction, a second surface opposite to the first surface, and a group of multiple second inductors spaced apart from the first surface and provided on the first surface; and a stacked memory chip including a bottom surface parallel to the first surface, multiple IC chips provided on the first surface such that the bottom surface and the first surface face each other, and multiple first inductors provided on the multiple IC chips spaced apart from the bottom surface; wherein the group of second inductors includes multiple second inductors, and one first inductor of the multiple first inductors communicates contactlessly with one second inductor of the multiple second inductors that is matched to the one first inductor.

2. The semiconductor module according to claim 1, wherein the plurality of second inductors include an inductor positioned at a position shifted in the first direction from the position of a reference inductor among the plurality of second inductors by an inductor diameter of the second inductor / n (n is an integer of 2 or greater).

3. The semiconductor module according to claim 2, wherein the plurality of second inductors include an inductor positioned at a position shifted by an inductor diameter / n of the second inductor in the second direction relative to the position of a reference inductor among the plurality of second inductors.

4. The semiconductor module according to claim 2, wherein the plurality of first inductors include an inductor positioned at a position shifted in the second direction by an inductor diameter / n of the first inductor with respect to the position of a reference inductor among the plurality of first inductors.

5. The semiconductor module according to claim 4, wherein the plurality of first inductors include an inductor positioned at a position shifted in the first direction from the position of a reference inductor among the plurality of first inductors by an inductor diameter / n of the first inductor.

6. The semiconductor module according to claim 3 or 4, wherein said n is 2.

7. The semiconductor module according to claim 5, wherein said n is 3.

8. The semiconductor module according to claim 5, wherein said n is 7.

9. The semiconductor module according to claim 1, wherein the plurality of IC chips are stacked along the first direction.

10. The semiconductor module according to claim 1, wherein the plurality of IC chips are stacked along the second direction.

11. The semiconductor module according to claim 1, wherein the first inductor includes a first wiring, the second inductor includes a wiring different from the first wiring, and the wiring has a line width greater than the line width of the first wiring.

12. The semiconductor module according to claim 1, further comprising a second semiconductor chip electrically connected to the first semiconductor chip on the second surface side, the second semiconductor chip including a configuration for controlling the non-contact communication.

13. The semiconductor module according to claim 12, wherein the second semiconductor chip includes a determination circuit that determines whether the one first inductor is matched with the one second inductor.

14. The semiconductor module described in claim 13, wherein the second semiconductor chip includes: a pass / fail map generation circuit that uses the judgment result determined by the judgment circuit to generate a pass / fail map indicating whether the one first inductor is matched or not matched with the one second inductor; and a table that stores the pass / fail map.

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