Comparator, ad converter, and imaging device

Abstract

The present invention makes it possible to sample and hold a comparator input while suppressing an increase in the exclusive area of a capacitor.　This comparator comprises: an input capacitor connected to a comparator input; and a sample-and-hold circuit which passes a first voltage level and applies the first voltage level to the input capacitor, and which, when the first voltage level is cut off, samples and holds a second voltage level and applies the sample-and-hold voltage level to the input capacitor. A reference voltage generation circuit for applying a reference voltage to the comparator input may be provided. The comparator input may comprise a first comparator input and a second comparator input.

Description

Comparator, AD converter and imaging device

[0001] The present technology relates to a comparator, an AD converter, and an imaging device. More specifically, the present technology relates to a comparator, an AD converter, and an imaging device capable of AZ (Auto Zero) operation.

[0002] For AD conversion, a technique has been proposed in which signal readout and AD conversion are parallelized by providing a sample-and-hold circuit before a comparator. For example, a technique has been disclosed in which a sample-and-hold unit has three capacitors that hold pixel signals, and captures a pixel signal into one capacitor while outputting an image signal captured in another capacitor to an analog-to-digital converter in parallel (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2019-57873

[0004] However, in the above-mentioned conventional technology, the sample-and-hold unit has three capacitors for holding pixel signals, which may increase the area occupied by the capacitors.

[0005] This technology was developed in light of these circumstances, and aims to enable sample-and-hold of comparator input while suppressing an increase in the area occupied by the capacitor.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a comparator including an input capacitor connected to a comparator input, and a sample-and-hold circuit that passes a first voltage level and applies it to the input capacitor, and that samples and holds a second voltage level and applies it to the input capacitor when the first voltage level is cut off. This provides an effect that level adjustment and sample-and-hold of the comparator input are achieved based on a single input capacitor.

[0007] In the first aspect, the input capacitor may further include a reference voltage generating circuit that applies a reference voltage to the comparator input, thereby achieving sample-and-hold of the comparator input and level adjustment of the comparator input for one input capacitance.

[0008] In the first aspect, the reference voltage generating circuit may include a diode-connected transistor, a current source connected in series with the diode-connected transistor, and a switch connected between the diode-connected transistor and the comparator input, thereby providing an effect that a reference voltage is applied to the comparator input when adjusting the level of the comparator input.

[0009] In the first aspect, the comparator may further include an enable transistor connected in series with the diode-connected transistor, thereby controlling the current flowing through the diode-connected transistor based on whether or not a reference voltage is applied to the comparator input.

[0010] In the first aspect, the circuit may further include an external terminal for applying a reference voltage to the comparator input, thereby providing an effect that the reference voltage is applied to the comparator input from the outside when adjusting the level of the comparator input.

[0011] In addition, in the first aspect, the circuit may further comprise a resistor ladder circuit that applies a reference voltage to the comparator input, thereby providing an effect that the reference voltage applied to the comparator input is adjusted.

[0012] In the first aspect, the sample and hold circuit may include a first sample and hold switch, a second sample and hold switch connected in series to the first sample and hold switch, a bypass switch connected in parallel to the series circuit of the first sample and hold switch and the second sample and hold switch, and a sample and hold capacitor connected to a connection point between the first sample and hold switch and the second sample and hold switch, thereby providing an effect that the sample and hold circuit is controlled based on switching control.

[0013] In the first aspect, the comparator input may include a first comparator input and a second comparator input, thereby achieving a comparison operation of the comparator inputs by the comparator.

[0014] In addition, in the first aspect, the input amplifier may include a reference signal generator that generates a reference signal to be input to the first comparator input, a capacitor connectable to the reference signal generator, a first switch connected between the reference signal generator and the capacitor, and a second switch connected between the first switch and the second comparator input. This provides the effect of realizing level adjustment and sample-and-hold of the comparator input based on a single input capacitor while omitting AZ operation for the first comparator input.

[0015] In the first aspect, the input capacitance may include a first input capacitance connected to the first comparator input and a second input capacitance connected to the second comparator input, thereby enabling AZ operation for the first comparator input and the second comparator input, and achieving level adjustment and sample-and-hold of the second comparator input based on the second input capacitance.

[0016] In the first aspect, the comparator may further include a first transistor having a gate connected to the first comparator input, a second transistor having a gate connected to the second comparator input, a third transistor connected in series with the first transistor, a fourth transistor connected in series with the second transistor and having a gate connected to a gate of the third transistor, and a current source connected to the first transistor and the second transistor, thereby providing an effect of configuring a comparator based on a differential input.

[0017] In the first aspect, the power supply may further include a first AZ (Auto Zero) switch connected between the gate and drain of the first transistor, and a second AZ switch connected between the gate and drain of the second transistor, thereby achieving AZ operations for the first comparator input and the second comparator input based on switching control.

[0018] A second aspect of the present invention is an AD converter including a comparator and a counter that performs counting based on a comparison result of the comparator, the comparator including an input capacitor connected to the comparator input, and a sample-and-hold circuit that passes a first voltage level and applies it to the input capacitor, and that samples and holds a second voltage level and applies it to the input capacitor when the first voltage level is cut off. This provides the effect of realizing level adjustment and sample-and-hold of the comparator input during AD conversion based on a single input capacitor.

[0019] In the second aspect, the present invention may further include a reference voltage generating circuit that applies a reference voltage to the comparator input, thereby achieving, for one input capacitance, sample-and-hold of the comparator input during AD conversion and level adjustment of the comparator input.

[0020] According to a third aspect, the pixel array unit may include a pixel array section in which pixels are arranged in a matrix in row and column directions, and a column ADC section that performs A / D (Analog to Digital) conversion on pixel signals output from the pixels for each column, the column ADC section including a comparator that compares the pixel signals with a reference signal for each column, and a counter that performs counting based on a comparison result of the comparator, the comparator including an input capacitor connected to the comparator input, and a sample-and-hold circuit that passes a first voltage level and applies it to the input capacitor, and that samples and holds a second voltage level and applies it to the input capacitor when the first voltage level is cut off. This provides the effect of achieving level adjustment and sample-and-hold of the comparator input when comparing the pixel signals with the reference signal based on a single input capacitor.

[0021] In addition, in the third aspect, the pixel circuit may further include a reference voltage generation circuit that applies a reference voltage to the comparator input, thereby achieving, for one input capacitance, sample-and-hold of the comparator input when comparing the pixel signal with the reference signal, and level adjustment of the comparator input.

[0022] In a third aspect, the comparator input may include a first comparator input and a second comparator input, the input capacitance may include a first input capacitance connected to the first comparator input and a second input capacitance connected to the second comparator input, the sample and hold circuit may include a first sample and hold switch, a second sample and hold switch connected in series with the first sample and hold switch, a bypass switch connected in parallel to the series circuit of the first sample and hold switch and the second sample and hold switch, and a sample and hold capacitance connected to a connection point of the first sample and hold switch and the second sample and hold switch, and the reference voltage generation circuit may include a diode-connected transistor, a current source connected in series with the diode-connected transistor, and a switch connected between the diode-connected transistor and the comparator input. This provides the effect of achieving level adjustment and sample and hold of the comparator input using a single input capacitance based on switching control.

[0023] In addition, in the third aspect, the pixel may further include a first AZ switch connected to the first input capacitor, a second AZ switch connected to the second input capacitor, and a control circuit that performs P-phase readout from the pixel and AZ operation in parallel, then performs P-phase AD conversion and D-phase readout from the pixel in parallel, and then performs D-phase AD conversion. This provides the effect of realizing AZ operation for the first comparator input and the second comparator input based on switching control, and simultaneously realizing D-phase sampling and P-phase AD conversion.

[0024] Furthermore, in the third aspect, the control circuit may turn on the bypass switch, the switch, the first AZ switch, and the second AZ switch and turn off the first sample and hold switch and the second sample and hold switch when performing the P-phase readout and the AZ operation, turn on the first sample and hold switch and the switch and turn off the bypass switch, the second sample and hold switch, the first AZ switch, and the second AZ switch when performing the P-phase AD conversion and the D-phase readout, and turn on the second sample and hold switch and turn off the bypass switch, the first sample and hold switch, the switch, the first AZ switch, and the second AZ switch when performing the D-phase AD conversion. This brings about an effect that, after the P-phase readout and the AZ operation are performed in parallel based on switching control, the P-phase AD conversion and the D-phase readout are performed in parallel, and then the D-phase AD conversion is performed.

[0025] 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment. FIG. 2 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment. FIG. 3 is a diagram showing a circuit configuration example of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 4 is a block diagram showing a configuration example of an AD conversion unit according to the first embodiment. FIG. 5 is a diagram showing a circuit configuration example of a comparator according to the first embodiment. FIG. 6 is a timing chart showing an operation example of a comparator according to the first embodiment. FIG. 7 is a block diagram showing an example of P-phase readout and AZ operation of a comparator according to the first embodiment. FIG. 8 is a block diagram showing an example of P-phase AD conversion and D-phase readout of a comparator according to the first embodiment. FIG. 9 is a block diagram showing an example of D-phase AD conversion of a comparator according to the first embodiment. FIG. 10 is a block diagram showing a configuration example of an AD conversion unit according to a second embodiment. FIG. 11 is a block diagram showing an input example of a reference voltage according to the second embodiment. FIG. 12 is a block diagram showing a configuration example of an AD conversion unit according to a third embodiment. FIG. 13 is a timing chart showing an operation example of a comparator according to the third embodiment. FIG. 14 is a block diagram showing a configuration example of an AD conversion unit according to a fourth embodiment. FIG. 15 is a timing chart showing an operation example of a comparator according to the fourth embodiment. FIG. 16 is a block diagram showing a configuration example of an AD conversion unit according to a fifth embodiment. 13 is a timing chart showing an example of an operation of a comparator according to a fifth embodiment. FIG. 14 is a timing chart showing an example of an operation of a comparator according to a sixth embodiment. FIG. 15 is a perspective view showing an example of a stack of a solid-state imaging device according to a seventh embodiment. FIG. 16 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 17 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0026] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which the P-phase level of a pixel signal is sampled and held in an input capacitance, and the D-phase level of the pixel signal is sampled and held in a sample and hold capacitance) 2. Second embodiment (an example in which a reference voltage is applied to an inverting input of a comparator based on an external input of a column ADC unit) 3. Third embodiment (an example in which a reference voltage generation circuit that applies a reference voltage to an inverting input of a comparator can be disabled) 4. Fourth embodiment (an example in which a sample and hold capacitance is provided in a reference voltage generation circuit that applies a reference voltage to an inverting input of a comparator) 5. Fifth embodiment (an example in which a configuration in which the P-phase level of a pixel signal is sampled and held in an input capacitance, and the D-phase level of the pixel signal is sampled and held in a sample and hold capacitance is applied to SAZ (Single Auto Zero)) 6. 6. Sixth embodiment (an example in which a configuration in which a D-phase level of a pixel signal is sampled and held in an input capacitor and a P-phase level of a pixel signal is sampled and held in a sample-and-hold capacitor is applied to DDS (Double Data Sampling)) 7. Seventh embodiment (an example in which pixel array units are stacked) 8. Example of application to a moving body

[0027] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0028] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0029] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0030] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. Single-slope AD conversion can be used to digitize the electrical signal. In this case, the solid-state imaging device 102 may support CDS (Correlated Double Sampling) readout or DDS (Dynamic Differential Sampling) readout. Each pixel may include a single photodiode or multiple photodiodes with different sensitivities. The solid-state imaging device 102 is, for example, a complementary metal oxide semiconductor (CMOS) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may also be a lateral overflow integration capacitor (LOFIC) image sensor.

[0031] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0032] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0033] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0034] The display unit 106 displays captured images and various information that supports the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0035] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0036] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0037] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0038] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0039] The pixel array unit 111 includes a plurality of pixels PX. The pixels PX are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel PX can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel PX is connected to a horizontal drive line HSL for each row and to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PX for each row when reading out a signal from each pixel PX. The vertical signal line VSL transmits the pixel signals read out from the pixels PX to the column signal processing unit 114 for each column.

[0040] Each pixel PX may be a single pixel, a four-pixel shared pixel, or an eight-pixel shared pixel. The pixel PX may also include an image plane phase difference pixel. Each pixel PX may support rolling shutter readout or global shutter readout. The pixels PX may also form a Bayer array or a quad-Bayer array. The light received by each pixel PX may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0041] The vertical scanning circuit 112 scans the pixels PX to be read in the column direction. The vertical scanning circuit 112 may be configured to include a vertical register. Here, when reading out signals from each pixel PX, the vertical scanning circuit 112 can drive each pixel PX row by row via a horizontal drive line HSL.

[0042] The column readout circuit 113 can form a source follower with each pixel PX when reading out a signal from the pixel PX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL for each column based on the charge held in each pixel PX.

[0043] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel PX. For example, the column signal processing unit 114 can perform CDS processing based on the signals transmitted in the column direction from each pixel PX. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel PX, and output an imaging signal Gout. The imaging signal Gout may include not only imaging data but also phase difference data. The column signal processing unit 114 includes a column ADC unit 114A.

[0044] The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel PX and the reference signal REF. This AD conversion may be single-slope AD conversion. In CDS processing, a P-phase level (also referred to as a reset level) and a D-phase level (also referred to as a signal level) are read from each pixel PX. Then, during AD conversion of the pixel signal, the P-phase level can be subtracted from the D-phase level. Here, the column ADC unit 114A samples and holds the P-phase level and the D-phase level for each column, thereby parallelizing the D-phase readout and the P-phase AD conversion and increasing the frame rate. At this time, the column ADC unit 114A can reduce the area occupied by the capacitance by using an AZ capacitor to sample and hold one of the P-phase level and the D-phase level.

[0045] The horizontal scanning circuit 115 scans the pixels PX to be read in the row direction. The horizontal scanning circuit 115 may be configured to include a horizontal register.

[0046] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame. The control circuit 116 can also control the sample-and-hold timing and AD conversion timing of the P-phase level and the D-phase level.

[0047] FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0048] 1, a pixel PX includes a photodiode PD, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 can be MOS transistors.

[0049] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode PD is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to a power supply voltage VDD via a reset transistor 123. The power supply voltage VDD is connected to a vertical signal line VSL via a series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0050] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, reset signal RST, and selection signal SEL can be transmitted to each pixel PX via the horizontal drive line HSL in FIG.

[0051] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode PD is transferred to the floating diffusion FD. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes depending on the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is applied to the vertical signal line VSL via the selection transistor 125 and transmitted via the vertical signal line VSL. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0052] Here, in reading out the P-phase level, the reset transistor 123 is turned on to reset the floating diffusion FD, and then the source potential of the amplification transistor 124 corresponding to the potential of the floating diffusion FD is transmitted via the vertical signal line VSL. In reading out the D-phase level, the transfer transistor 122 is turned on to transfer the charge accumulated in the photodiode PD to the floating diffusion FD, and then the source potential of the amplification transistor 124 corresponding to the potential of the floating diffusion FD is transmitted via the vertical signal line VSL.

[0053] 4 is a block diagram showing an example of the configuration of an AD conversion unit according to the first embodiment, which shows an example of the configuration of an AD conversion unit for one column.

[0054] In the figure, pixels PX are connected to each vertical signal line VSL. At this time, the amplification transistor 124 of each pixel PX is connected to the vertical signal line VSL via the selection transistor 125.

[0055] The column readout circuit 113 includes a current source LM. A current source LM is provided for each column. Each current source LM is connected to a vertical signal line VSL. During signal readout, each current source LM can form a source follower with each pixel PX via the vertical signal line VSL. Each current source LM may be a MOS transistor.

[0056] The column ADC unit 114A samples the P-phase level and the D-phase level and holds them for each column, thereby parallelizing the D-phase readout and the P-phase AD conversion, thereby enabling a faster frame rate. In this case, the column ADC unit 114A uses the input capacitance C2 to sample and hold the P-phase level, eliminating the need for a dedicated sample-and-hold capacitance for the P-phase level sample and hold, while enabling the P-phase readout and the AZ operation to be parallelized. The column ADC unit 114A includes a comparator CP, a counter CN, a sample-and-hold circuit SPC, and a reference voltage generation circuit VSC for each column. The reference voltage generation circuit VSC may be shared by multiple columns.

[0057] The sample and hold circuit SPC passes a first voltage level on the vertical signal line VSL and applies it to the input capacitor C2, and samples and holds a second voltage level when the first voltage level is cut off and applies it to the input capacitor C2. The first voltage level may be a P-phase level read out from the pixel PX. The second voltage level may be a D-phase level read out from the pixel PX. The sample and hold circuit SPC includes a sample and hold capacitor C0, sample and hold switches SW1 and SW2, and a bypass switch PW.

[0058] The sample and hold switches SW1 and SW2 are connected in series to each other. A bypass switch PW is connected in parallel to the series circuit of the sample and hold switches SW1 and SW2. A sample and hold capacitor C0 is connected to the connection point of the sample and hold switches SW1 and SW2. The input side of the sample and hold switch SW1 is connected to the vertical signal line VSL, and the output side of the sample and hold switch SW2 is connected to the input capacitor C2 via a buffer BF.

[0059] The reference voltage generating circuit VSC applies a reference voltage to the inverting input of the comparator CP. The reference voltage can adjust the inverting input of the comparator CP to the operating point of the comparator CP. The reference voltage generating circuit VSC includes a diode-connected transistor DT, a current source GA, and a switch KW.

[0060] The diode-connected transistor DT is connected in series with the current source GA. The output of the diode-connected transistor DT is connected to the inverting input of the comparator CP via a switch KW. The output of the diode-connected transistor DT can be taken from the gate of the diode-connected transistor DT. The diode-connected transistor DT may be a MOS transistor.

[0061] The comparator CP compares the pixel signal transmitted via the vertical signal line VSL with a reference signal REF. The reference signal REF can be generated based on DA conversion of digital data. The reference signal REF can be shared by multiple columns. In this case, the column ADC unit 114A may include a reference signal generation unit REC that generates the reference signal REF. The reference signal generation unit REC may include a DA converter.

[0062] An input capacitor C1 is connected to the non-inverting input of the comparator CP, and an input capacitor C2 is connected to the inverting input of the comparator CP. A reference signal REF is applied to the input capacitor C1, and the output of a buffer BF is applied to the input capacitor C2. An AZ switch AW1 is connected between the non-inverting input and non-inverting output of the comparator CP, and an AZ switch AW2 is connected between the inverting input and inverting output of the comparator CP.

[0063] The counter CN performs a counting operation for each column based on the period until the level of the pixel signal read from the pixel PX matches the level of the ramp wave of the reference signal REF, and generates a digital value DA of the pixel signal read from the pixel PX for each column. The digital value DA may be CDS data.

[0064] FIG. 5 is a diagram illustrating an example of a circuit configuration of a comparator according to the first embodiment.

[0065] In the figure, a comparator CP balances comparator inputs Vin1 and Vin2 based on auto-zero operation, and then outputs a voltage VC corresponding to the difference between the comparator inputs Vin1 and Vin2. The comparator CP includes PMOS transistors 231 and 232, NMOS transistors 233 and 234, a current source 235, and AZ switches AW1 and AW2. The characteristics of the diode-connected transistor DT can be set to be equivalent to those of the PMOS transistor 232.

[0066] The PMOS transistor 231 and the NMOS transistor 233 are connected in series to each other. The PMOS transistor 232 and the NMOS transistor 234 are connected in series to each other. The sources of the PMOS transistors 231 and 232 are connected to the power supply voltage VDD, and the gates of the PMOS transistors 231 and 232 are connected to the drain of the PMOS transistor 231. In this case, the PMOS transistors 231 and 232 can form a current mirror.

[0067] A reference signal REF is input via an input capacitor C1 to the gate of the NMOS transistor 233. A vertical signal line VSL is connected to the gate of the NMOS transistor 234 for each column via an input capacitor C2.

[0068] An AZ switch AW1 is connected between the gate and drain of the NMOS transistor 233, and an AZ switch AW2 is connected between the gate and drain of the NMOS transistor 234. The sources of the NMOS transistors 233 and 234 are connected to the ground potential via a current source 235.

[0069] Here, during the auto-zero period, when the AZ switches AW1 and AW2 are turned on, a current flows through each of the PMOS transistors 231 and 232 based on the current mirror operation of the PMOS transistors 231 and 232. Then, charge is accumulated in each of the input capacitors C1 and C2 so that the non-inverting input and the inverting input of the comparator CP are balanced.

[0070] Fig. 6 is a timing chart showing an example of the operation of the comparator according to the first embodiment, Fig. 7 is a block diagram showing an example of P-phase readout and AZ operation of the comparator according to the first embodiment, Fig. 8 is a block diagram showing an example of P-phase AD conversion and D-phase readout of the comparator according to the first embodiment, and Fig. 9 is a block diagram showing an example of D-phase AD conversion of the comparator according to the first embodiment. Fig. 7 shows the signal flow at time T1 in Fig. 6, Fig. 8 shows the signal flow at time T2 in Fig. 6, and Fig. 9 shows the signal flow at time T3 in Fig. 6.

[0071] 6, a P-phase readout period PRD, an auto-zero period AZ, a P-phase AD conversion period PAD, a D-phase readout period DRD, and a D-phase AD conversion period DAD are provided within 1H (horizontal period). The P-phase readout period PRD and the auto-zero period AZ are parallelized. The P-phase AD conversion period PAD and the D-phase readout period DRD are parallelized. The P-phase readout period PRD includes a P-phase settling period. The D-phase readout period DRD includes a D-phase settling period.

[0072] The reference signal REF is provided with ramp waves RNP and RND, which are applied to the comparator input Vin1. The ramp wave RNP is compared with the P-phase level of the pixel signal. The ramp wave RND is compared with the D-phase level of the pixel signal.

[0073] During the P-phase readout period PRD and the auto-zero period AZ, as shown in FIGS. 6 and 7 , the switch KW is turned on, and the reference voltage generated by the diode-connected transistor DT is applied to the inverting input of the comparator CP (R2). The bypass switch PW and the AZ switches AW1 and AW2 are turned on, and the P-phase level of the pixel signal transmitted via the vertical signal line VSL is applied to the input capacitor C2 (R1), activating the AZ operation of the comparator CP. At this time, while balancing the comparator inputs Vin1 and Vin2, charge is accumulated in the input capacitors C1 and C2 so that the inverting input of the comparator CP coincides with the operating point of the comparator CP, and the P-phase level of the pixel signal is sampled and held by the input capacitor C2.

[0074] During the P-phase AD conversion period PAD and the D-phase readout period DRD, as shown in FIGS. 6 and 8 , the switch KW is turned on, and the reference voltage generated by the diode-connected transistor DT is applied to the inverting input of the comparator CP (R2). The comparator CP then compares a potential corresponding to the P-phase level sampled and held by the input capacitor C2 with the ramp wave RNP, and outputs the timing at which the level of the ramp wave RNP matches the P-phase level sampled and held by the input capacitor C2 as the comparison result. At this time, the P-phase level read out from the pixel PX is AD-converted for each column based on the counting operation until the level of the ramp wave RNP matches the P-phase level sampled and held by the input capacitor C2. Furthermore, the sample-and-hold switch SW1 is turned on, and the D-phase level of the pixel signal transmitted via the vertical signal line VSL is applied to the sample-and-hold capacitor C0 and sampled and held by the sample-and-hold capacitor C0 (R3).

[0075] 6 and 9, during the D-phase AD conversion period DAD, the sample-and-hold switch SW2 is turned on, and the D-phase level of the pixel signal sampled and held in the sample-and-hold capacitor C0 is applied to the comparator input Vin2 via the input capacitor C2 (R4). Then, the comparator CP compares a potential corresponding to the D-phase level sampled and held in the sample-and-hold capacitor C0 with the ramp wave RND, and outputs the timing when the level of the ramp wave RND matches the D-phase level sampled and held in the sample-and-hold capacitor C0 as the comparison result. At this time, the D-phase level read out from the pixel PX is AD-converted for each column based on the count operation until the level of the ramp wave RND matches the D-phase level sampled and held in the sample-and-hold capacitor C0.

[0076] Here, the control circuit 116 can control the on / off of the bypass switch PW, the sample-and-hold switches SW1 and SW2, the switch KW, and the AZ switches AW1 and AW2, and can also control the output timing of the reference signal REF.

[0077] As described above, in the first embodiment, the P-phase level of the pixel signal is sampled and held in the input capacitor C2, and the D-phase level of the pixel signal is sampled and held in the sample and hold capacitor C0. This eliminates the need for a dedicated sample and hold capacitor for the P-phase level of the pixel signal, and makes it possible to parallelize the P-phase readout period PRD and the auto-zero period AZ, as well as the P-phase AD conversion period PAD and the D-phase readout period DRD. This makes it possible to increase the frame rate while suppressing an increase in the area occupied by the capacitors of the column ADC unit 114A.

[0078] 2. Second Embodiment In the first embodiment described above, a reference voltage generation circuit VSC is provided to apply a reference voltage to the inverting input of the comparator CP. In this second embodiment, the reference voltage is applied to the inverting input of the comparator CP based on an external input to the column ADC unit 114A.

[0079] FIG. 10 is a block diagram illustrating an example of the configuration of an AD conversion unit according to the second embodiment.

[0080] In the figure, this solid-state imaging device includes a column ADC unit 114A' instead of the column ADC unit 114A of the first embodiment. Other configurations of this solid-state imaging device are the same as those of the solid-state imaging device of the first embodiment.

[0081] The column ADC unit 114A' includes a switch KW instead of the reference voltage generation circuit VSC of the first embodiment. At this time, an external input VEX is applied to the inverting input of the comparator CP via the switch KW. Other configurations of the column ADC unit 114A' are the same as those of the column ADC unit 114A of the first embodiment.

[0082] A reference voltage can be applied to the external input VEX, and the switch KW can be turned on at the timing when the reference voltage is applied to the inverting input of the comparator CP.

[0083] FIG. 11 is a block diagram showing an example of input of a reference voltage according to the second embodiment.

[0084] In the figure, the external input VEX may be applied via a pad electrode PE or via a ladder resistor RDA. In this case, a switch EW1 may be connected between the external input VEX and the pad electrode PE, and a switch EW2 may be connected between the external input VEX and the ladder resistor RDA. Each of the switches EW1 and EW2 can be turned on at the timing when a reference voltage is applied to the inverting input of the comparator CP. The reference voltage applied to the inverting input of the comparator CP can be adjusted by adjusting the voltage applied to the pad electrode PE or the ladder resistor RDA.

[0085] As described above, in the second embodiment, the reference voltage is applied to the inverting input of the comparator CP based on the external input of the column ADC unit 114 A. This makes it possible to apply the reference voltage to the inverting input of the comparator CP without requiring the reference voltage generation circuit VSC, and also makes it possible to optimize the reference voltage according to the characteristics of the comparator CP.

[0086] 3. Third Embodiment In the first embodiment described above, a reference voltage generation circuit VSC is provided to apply a reference voltage to the inverting input of the comparator CP. In this third embodiment, the reference voltage generation circuit that applies a reference voltage to the inverting input of the comparator CP can be disabled.

[0087] FIG. 12 is a block diagram illustrating an example of the configuration of an AD conversion unit according to the third embodiment.

[0088] In the figure, this reference voltage generation circuit is the same as that of the first embodiment described above, except that an enable transistor ET is added to the reference voltage generation circuit VSC. Other configurations of this reference voltage generation circuit are the same as those of the reference voltage generation circuit VSC of the first embodiment described above.

[0089] The enable transistor ET is connected between the diode-connected transistor DT and the current source GA. The enable transistor ET may be a MOS transistor. An enable signal EN is applied to the gate of the enable transistor ET.

[0090] FIG. 13 is a timing chart showing an example of the operation of the comparator according to the third embodiment.

[0091] In the figure, the enable transistor ET is turned on when the switch KW is turned on. At this time, during the period when the reference voltage is not applied to the inverting input of the comparator CP, the current flowing through the diode-connected transistor DT is cut off.

[0092] In this way, in the third embodiment described above, the reference voltage generation circuit that applies the reference voltage to the inverting input of the comparator CP can be disabled, which makes it possible to cut off the current flowing through the diode-connected transistor DT during the period when the reference voltage is not applied to the inverting input of the comparator CP, thereby achieving low power consumption.

[0093] 4. Fourth Embodiment In the first embodiment described above, a reference voltage generation circuit VSC is provided to apply a reference voltage to the inverting input of the comparator CP. In this fourth embodiment, a sample-and-hold capacitor is provided in the reference voltage generation circuit that applies a reference voltage to the inverting input of the comparator CP.

[0094] FIG. 14 is a block diagram illustrating an example of the configuration of an AD conversion unit according to the fourth embodiment.

[0095] In the figure, this reference voltage generation circuit is similar to that of the third embodiment except that switches W11 and W12 and a sample-and-hold capacitor C3 are added to the reference voltage generation circuit of the third embodiment. Other configurations of this reference voltage generation circuit are the same as those of the reference voltage generation circuit of the third embodiment.

[0096] The switches W11 and W12 are connected in series to each other. The series circuit of the switches W11 and W12 is connected to the gate of the diode-connected transistor DT. The switches W11 and W12 may be MOS transistors. A sample-and-hold capacitor C3 is connected to the connection point of the switches W11 and W12. The switches W11 and W12 and the sample-and-hold capacitor C3 may be shared by multiple columns.

[0097] FIG. 15 is a timing chart showing an example of the operation of the comparator according to the fourth embodiment.

[0098] In the figure, switch W11 and enable transistor ET are turned on when AZ switches AW1 and AW2 are turned on. At this time, the reference voltage generated by diode-connected transistor DT is applied to sample-and-hold capacitor C3 and sampled and held. Switch W12 is turned on when switch KW is turned on. At this time, the reference voltage sampled and held by sample-and-hold capacitor C3 is applied to the inverting input of comparator CP. Furthermore, while AZ switches AW1 and AW2 are off, the current flowing through diode-connected transistor DT is cut off.

[0099] In this way, in the fourth embodiment described above, the sample and hold capacitor C3 is provided in the reference voltage generation circuit that applies the reference voltage to the inverting input of the comparator CP, which makes it possible to cut off the current flowing through the diode-connected transistor DT while the AZ switches AW1 and AW2 are turned off, thereby achieving low power consumption.

[0100] 5. Fifth Embodiment In the first embodiment described above, the P-phase level of the pixel signal is sampled and held in the input capacitor C2, and the D-phase level of the pixel signal is sampled and held in the sample and hold capacitor C0. In this fifth embodiment, a configuration in which the P-phase level of the pixel signal is sampled and held in the input capacitor C2, and the D-phase level of the pixel signal is sampled and held in the sample and hold capacitor C0 is applied to the SAZ.

[0101] FIG. 16 is a block diagram illustrating an example of the configuration of an AD conversion unit according to the fifth embodiment.

[0102] In the figure, this solid-state imaging device includes a column ADC unit 514A instead of the column ADC unit 114A of the first embodiment. Other configurations of this solid-state imaging device are the same as those of the solid-state imaging device of the first embodiment.

[0103] The column ADC unit 514A includes a comparator CP' and a reference voltage generation circuit VRC instead of the comparator CP and the reference voltage generation circuit VSC of the first embodiment described above. Other configurations of the column ADC unit 514A are similar to the configuration of the column ADC unit 114A of the first embodiment described above.

[0104] The comparator CP' does not have the input capacitance C1 and the AZ switch AW1 of the first embodiment. In this case, the comparator CP' can perform SAZ based on the input capacitance C2 and the AZ switch AW2.

[0105] The reference voltage generating circuit VRC applies a reference voltage to the inverting input of the comparator CP'. The reference voltage generating circuit VRC includes switches W51 and W52 and a capacitor C5.

[0106] The switches W51 and W52 are connected in series. A reference signal REF is input to the input side of the switch W51, and the output side of the switch W52 is connected to the inverting input of the comparator CP'. The switches W51 and W52 may be MOS transistors. A capacitor C5 is connected to the connection point of the switches W51 and W52. The switches W51 and W52 and the capacitor C5 may be shared by multiple columns.

[0107] FIG. 17 is a timing chart showing an example of the operation of the comparator according to the fifth embodiment.

[0108] In the figure, 1H includes a P-phase read period PRD, an auto-zero period AZ, a P-phase AD conversion period PAD, a D-phase read period DRD, and a D-phase AD conversion period DAD. The P-phase read period PRD and the auto-zero period AZ are parallelized. The P-phase AD conversion period PAD and the D-phase read period DRD are parallelized.

[0109] During the P-phase readout period PRD and the auto-zero period AZ, the switches SW51 and SW52 are turned on, and the reference signal REF is applied to the capacitor C5 for sample-and-holding, and also applied to the inverting input of the comparator CP. The bypass switch PW and the AZ switch AW2 are turned on, and the P-phase level of the pixel signal transmitted via the vertical signal line VSL is applied to the input capacitor C2, activating the AZ operation of the comparator CP. At this time, charge is accumulated in the input capacitor C2 so that the inverting input of the comparator CP coincides with the operating point of the comparator CP, and the P-phase level of the pixel signal is sample-and-hold in the input capacitor C2.

[0110] During the P-phase AD conversion period PAD and the D-phase readout period DRD, the switch SW52 is turned on, and the reference signal REF sampled and held by the capacitor C5 is applied to the inverting input of the comparator CP. The comparator CP then compares a potential corresponding to the P-phase level sampled and held by the input capacitor C2 with the ramp wave RNP, and outputs the timing at which the level of the ramp wave RNP matches the P-phase level sampled and held by the input capacitor C2 as the comparison result. At this time, the P-phase level read out from the pixel PX is AD-converted for each column based on the counting operation until the level of the ramp wave RNP matches the P-phase level sampled and held by the input capacitor C2. Furthermore, the sample-and-hold switch SW1 is turned on, and the D-phase level of the pixel signal transmitted via the vertical signal line VSL is applied to the sample-and-hold capacitor C0 and sampled and held by the sample-and-hold capacitor C0.

[0111] During the D-phase AD conversion period DAD, the sample-and-hold switch SW2 is turned on, and the D-phase level of the pixel signal sampled and held in the sample-and-hold capacitor C0 is applied to the comparator input Vin2 via the input capacitor C2. Then, the comparator CP compares a potential corresponding to the D-phase level sampled and held in the sample-and-hold capacitor C0 with the ramp wave RND, and outputs the timing when the level of the ramp wave RND matches the D-phase level sampled and held in the sample-and-hold capacitor C0 as the comparison result. At this time, the D-phase level read out from the pixel PX is AD-converted for each column based on the count operation until the level of the ramp wave RND matches the D-phase level sampled and held in the sample-and-hold capacitor C0.

[0112] As described above, in the fifth embodiment, a configuration is applied to the SAZ in which the P-phase level of the pixel signal is sampled and held in the input capacitor C2 and the D-phase level of the pixel signal is sampled and held in the sample and hold capacitor C0. This eliminates the need for a sample and hold capacitor dedicated to the P-phase level of the pixel signal, as well as the input capacitor C1 on one side of the comparator CP' and the AZ switch AW1. It is therefore possible to parallelize the P-phase readout period PRD and the auto-zero period AZ, and also to parallelize the P-phase AD conversion period PAD and the D-phase readout period DRD. This makes it possible to increase the frame rate while suppressing an increase in the area occupied by the capacitors of the column ADC unit 514A.

[0113] 6. Sixth Embodiment In the first embodiment described above, a configuration in which the P-phase level of a pixel signal is sampled and held in the input capacitor C2 and the D-phase level of the pixel signal is sampled and held in the sample and hold capacitor C0 is applied to a CDS. In this sixth embodiment, a configuration in which the D-phase level of a pixel signal is sampled and held in the input capacitor and the P-phase level of the pixel signal is sampled and held in the sample and hold capacitor is applied to a DDS.

[0114] 18 is a timing chart showing an example of the operation of the comparator according to the sixth embodiment. In this sixth embodiment, the column ADC unit 114A according to the first embodiment may be used, or the column ADC unit 114A′ according to the second embodiment may be used.

[0115] In the figure, 1H includes a P-phase read period PRD, an auto-zero period AZ, a P-phase AD conversion period PAD, a D-phase read period DRD, and a D-phase AD conversion period DAD. The D-phase read period DRD and the auto-zero period AZ are parallelized. The D-phase AD conversion period DAD and the P-phase read period PRD are parallelized.

[0116] During the D-phase readout period DRD and the auto-zero period AZ, the switch KW is turned on, and a reference voltage provided by the external input VEX is applied to the inverting input of the comparator CP. The bypass switch PW and the AZ switches AW1 and AW2 are turned on, and the D-phase level of the pixel signal transmitted via the vertical signal line VSL is applied to the input capacitor C2, activating the AZ operation of the comparator CP. At this time, while balancing the comparator inputs Vin1 and Vin2, charge is accumulated in the input capacitors C1 and C2 so that the inverting input of the comparator CP coincides with the operating point of the comparator CP, and the D-phase level of the pixel signal is sampled and held by the input capacitor C2.

[0117] During the D-phase AD conversion period DAD and the P-phase readout period PRD, the switch KW is turned on, and a reference voltage provided by the external input VEX is applied to the inverting input of the comparator CP. The comparator CP then compares a potential corresponding to the D-phase level sampled and held by the input capacitor C2 with the ramp wave RND, and outputs the timing at which the level of the ramp wave RND matches the D-phase level sampled and held by the input capacitor C2 as the comparison result. At this time, the D-phase level read out from the pixel PX is AD-converted for each column based on the counting operation until the level of the ramp wave RND matches the D-phase level sampled and held by the input capacitor C2. Furthermore, the sample-and-hold switch SW1 is turned on, and the P-phase level of the pixel signal transmitted via the vertical signal line VSL is applied to the sample-and-hold capacitor C0 and sampled and held by the sample-and-hold capacitor C0.

[0118] During the P-phase AD conversion period PAD, the sample-and-hold switch SW2 is turned on, and the P-phase level of the pixel signal sampled and held in the sample-and-hold capacitor C0 is applied to the comparator input Vin2 via the input capacitor C2. The comparator CP then compares a potential corresponding to the P-phase level sampled and held in the sample-and-hold capacitor C0 with the ramp wave RNP, and outputs the timing at which the level of the ramp wave RNP matches the P-phase level sampled and held in the sample-and-hold capacitor C0 as the comparison result. At this time, the P-phase level read out from the pixel PX is AD-converted for each column based on the counting operation until the level of the ramp wave RNP matches the P-phase level sampled and held in the sample-and-hold capacitor C0.

[0119] As described above, in the sixth embodiment, a configuration is applied to a DDS in which the D-phase level of a pixel signal is sampled and held in an input capacitor, and the P-phase level of the pixel signal is sampled and held in a sample and hold capacitor. This makes it possible to increase the frame rate in a DDS while suppressing an increase in the area occupied by the capacitor of the column ADC unit. 7. Seventh Embodiment In the first embodiment, the P-phase level of a pixel signal is sampled and held in an input capacitor C2, and the D-phase level of the pixel signal is sampled and held in a sample and hold capacitor C0. In this seventh embodiment, semiconductor chips each having a pixel array unit in which pixels are arranged in a matrix are stacked.

[0120] FIG. 19 is a perspective view showing an example of a stack of pixel array units according to the seventh embodiment.

[0121] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0122] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0123] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction. The column ADC 926 can be formed with any of the comparators according to the first to sixth embodiments described above.

[0124] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0125] As described above, in the fourth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0126] 8. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0127] FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0128] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 20, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0129] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0130] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0131] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0132] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0133] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0134] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0135] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0136] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0137] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 20, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0138] FIG. 21 is a diagram showing an example of the installation position of the imaging unit 12031.

[0139] In FIG. 21, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0140] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0141] 21 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0142] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0143] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0144] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0145] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0146] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, each comparator in the above-described embodiment can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to increase the frame rate while suppressing an increase in the area occupied by the capacity of the imaging unit 12031.

[0147] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0148] The present technology may also be configured as follows: (1) A comparator comprising: an input capacitance connected to a comparator input; and a sample-and-hold circuit that passes a first voltage level and applies it to the input capacitance, and that samples and holds a second voltage level when the first voltage level is cut off, and applies it to the input capacitance. (2) The comparator according to (1), further comprising: a reference voltage generation circuit that applies a reference voltage to the comparator input. (3) The comparator according to (2), wherein the reference voltage generation circuit comprises: a diode-connected transistor; a current source connected in series with the diode-connected transistor; and a switch connected between the diode-connected transistor and the comparator input. (4) The comparator according to (3), further comprising: an enable transistor connected in series with the diode-connected transistor. (5) The comparator according to any one of (1) to (4), further comprising: an external terminal that applies a reference voltage to the comparator input. (6) The comparator according to any one of (1) to (5), further comprising a resistor ladder circuit that applies a reference voltage to the comparator input. (7) The comparator according to any one of (1) to (6), wherein the sample and hold circuit comprises: a first sample and hold switch; a second sample and hold switch connected in series to the first sample and hold switch; a bypass switch connected in parallel to the series circuit of the first sample and hold switch and the second sample and hold switch; and a sample and hold capacitor connected to a connection point between the first sample and hold switch and the second sample and hold switch. (8) The comparator according to any one of (1) to (7), wherein the comparator input comprises: a first comparator input and a second comparator input. (9) The comparator according to (8), comprising: a reference signal generator that generates a reference signal to be input to the first comparator input; a capacitor connectable to the reference signal generator; a first switch connected between the reference signal generator and the capacitor; and a second switch connected between the first switch and the second comparator input.(10) The comparator according to (8) or (9), wherein the input capacitance comprises: a first input capacitance connected to the first comparator input; and a second input capacitance connected to the second comparator input. (11) The comparator according to (10), comprising: a first transistor having a gate connected to the first comparator input, a second transistor having a gate connected to the second comparator input, a third transistor connected in series with the first transistor, a fourth transistor connected in series with the second transistor and having a gate connected to the gate of the third transistor, and a current source connected to the first transistor and the second transistor. (12) The comparator according to (11), further comprising: a first AZ (Auto Zero) switch connected between the gate and drain of the first transistor, and a second AZ switch connected between the gate and drain of the second transistor. (13) An AD converter comprising: a comparator; and a counter that performs counting based on a comparison result of the comparator, wherein the comparator comprises: an input capacitance connected to a comparator input; and a sample-and-hold circuit that passes a first voltage level and applies it to the input capacitance, and samples and holds a second voltage level and applies it to the input capacitance when the first voltage level is cut off. (14) The AD converter according to (13), further comprising: a reference voltage generation circuit that applies a reference voltage to the comparator input. (15) An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in row and column directions; and a column ADC section that performs AD (Analog to Digital) conversion for each column of pixel signals output from the pixels, wherein the column ADC section comprises: a comparator that compares the pixel signals with a reference signal for each column; and a counter that performs counting based on the comparison result of the comparator, wherein the comparator comprises: an input capacitor connected to a comparator input; and a sample-and-hold circuit that passes a first voltage level and applies it to the input capacitor, and samples and holds a second voltage level when the first voltage level is cut off, and applies it to the input capacitor.(16) The imaging device according to (15), further comprising: a reference voltage generation circuit that applies a reference voltage to the comparator input. (17) The imaging device according to (16), wherein the comparator input comprises: a first comparator input and a second comparator input, the input capacitance comprises: a first input capacitance connected to the first comparator input and a second input capacitance connected to the second comparator input, the sample and hold circuit comprises: a first sample and hold switch, a second sample and hold switch connected in series with the first sample and hold switch, a bypass switch connected in parallel to the series circuit of the first sample and hold switch and the second sample and hold switch, and a sample and hold capacitance connected to a connection point of the first sample and hold switch and the second sample and hold switch, and the reference voltage generation circuit comprises: a diode-connected transistor, a current source connected in series with the diode-connected transistor, and a switch connected between the diode-connected transistor and the comparator input. (18) The imaging device described in (17) further includes: a first AZ switch connected to the first input capacitance; a second AZ switch connected to the second input capacitance; and a control circuit that performs P-phase readout from the pixel and AZ operation in parallel, then performs P-phase AD conversion and D-phase readout from the pixel in parallel, and then performs D-phase AD conversion. (19) The imaging device described in (18), wherein the control circuit turns on the bypass switch, the switch, the first AZ switch, and the second AZ switch and turns off the first sample and hold switch and the second sample and hold switch when performing the P-phase readout and AZ operation; turns on the first sample and hold switch and the switch and turns off the bypass switch, the second sample and hold switch, the first AZ switch, and the second AZ switch when performing the P-phase AD conversion and the D-phase readout; and turns on the second sample and hold switch and turns off the bypass switch, the first sample and hold switch, the switch, the first AZ switch, and the second AZ switch when performing the D-phase AD conversion.

[0149] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 114A Column ADC unit 115 Horizontal scanning circuit 116 Control circuit PX Pixel HSL Horizontal drive line VSL Vertical signal line PD Photodiode FD Floating diffusion 122 Transfer transistor 123 Reset transistor 124 Amplifying transistor 125 Selection transistor LM, GA Current source SPC Sample and hold circuit C0 Sample and hold capacitance SW1, SW2 Sample and hold switch PW Bypass switch VSC Reference voltage generation circuit DT Diode-connected transistor KW Switch C1, C2 Input capacitance CP Comparator AW1, AW2 AZ switch CN Counter

Claims

1. A comparator comprising: an input capacitor connected to a comparator input; and a sample-and-hold circuit that passes a first voltage level to apply to said input capacitor, and that samples and holds a second voltage level to apply to said input capacitor when said first voltage level is cut off.

2. The comparator according to claim 1, further comprising a reference voltage generating circuit for applying a reference voltage to the comparator input.

3. The comparator according to claim 2, wherein the reference voltage generating circuit comprises: a diode-connected transistor; a current source connected in series with the diode-connected transistor; and a switch connected between the diode-connected transistor and the comparator input.

4. The comparator of claim 3, further comprising: an enable transistor connected in series with said diode-connected transistor.

5. The comparator according to claim 1, further comprising an external terminal for applying a reference voltage to the comparator input.

6. The comparator of claim 1, further comprising a resistor ladder circuit for applying a reference voltage to the comparator input.

7. The comparator according to claim 1, wherein the sample and hold circuit comprises: a first sample and hold switch; a second sample and hold switch connected in series to the first sample and hold switch; a bypass switch connected in parallel to the series circuit of the first sample and hold switch and the second sample and hold switch; and a sample and hold capacitor connected to the connection point between the first sample and hold switch and the second sample and hold switch.

8. The comparator of claim 1, wherein the comparator input comprises: a first comparator input; and a second comparator input.

9. A comparator as described in claim 8, comprising: a reference signal generating unit that generates a reference signal to be input to the first comparator input; a capacitance connectable to the reference signal generating unit; a first switch connected between the reference signal generating unit and the capacitance; and a second switch connected between the first switch and the second comparator input.

10. A comparator as claimed in claim 8, wherein the input capacitance comprises: a first input capacitance connected to the first comparator input; and a second input capacitance connected to the second comparator input.

11. The comparator according to claim 10, comprising: a first transistor having a gate connected to the first comparator input; a second transistor having a gate connected to the second comparator input; a third transistor connected in series with the first transistor; a fourth transistor connected in series with the second transistor and having a gate connected to the gate of the third transistor; and a current source connected to the first transistor and the second transistor.

12. The comparator according to claim 11, further comprising: a first AZ (Auto Zero) switch connected between the gate and drain of the first transistor; and a second AZ switch connected between the gate and drain of the second transistor.

13. An AD converter comprising: a comparator; and a counter that performs counting based on a comparison result of the comparator, wherein the comparator comprises: an input capacitor connected to a comparator input; and a sample-and-hold circuit that passes a first voltage level and applies it to the input capacitor, and that samples and holds a second voltage level and applies it to the input capacitor when the first voltage level is cut off.

14. The AD converter according to claim 13, further comprising a reference voltage generating circuit for applying a reference voltage to the comparator input.

15. An imaging device comprising: a pixel array section in which pixels are arranged in a matrix in the row and column directions; and a column ADC section that performs AD (Analog to Digital) conversion for each column of pixel signals output from the pixels, wherein the column ADC section comprises a comparator that compares the pixel signals with a reference signal for each column; and a counter that performs counting based on the comparison result of the comparator, wherein the comparator comprises: an input capacitor connected to the comparator input; and a sample and hold circuit that passes a first voltage level and applies it to the input capacitor, and samples and holds a second voltage level when the first voltage level is cut off, and applies it to the input capacitor.

16. The imaging device according to claim 15, further comprising a reference voltage generating circuit for applying a reference voltage to the comparator input.

17. The imaging device according to claim 16, wherein the comparator input comprises a first comparator input and a second comparator input; the input capacitance comprises a first input capacitance connected to the first comparator input and a second input capacitance connected to the second comparator input; the sample and hold circuit comprises a first sample and hold switch, a second sample and hold switch connected in series with the first sample and hold switch, a bypass switch connected in parallel to the series circuit of the first sample and hold switch and the second sample and hold switch, and a sample and hold capacitance connected to the connection point of the first sample and hold switch and the second sample and hold switch; and the reference voltage generation circuit comprises a diode-connected transistor, a current source connected in series with the diode-connected transistor, and a switch connected between the diode-connected transistor and the comparator input.

18. The imaging device of claim 17, further comprising: a first AZ switch connected to the first input capacitance; a second AZ switch connected to the second input capacitance; and a control circuit that performs P-phase readout from the pixel and AZ operation in parallel, then performs P-phase AD conversion and D-phase readout from the pixel in parallel, and then performs D-phase AD conversion.

19. The imaging device of claim 18, wherein the control circuit turns on the bypass switch, the switch, the first AZ switch, and the second AZ switch and turns off the first sample and hold switch and the second sample and hold switch when performing the P-phase readout and AZ operation; turns on the first sample and hold switch and the switch and turns off the bypass switch, the second sample and hold switch, the first AZ switch, and the second AZ switch when performing the P-phase AD conversion and the D-phase readout; and turns on the second sample and hold switch and turns off the bypass switch, the first sample and hold switch, the switch, the first AZ switch, and the second AZ switch when performing the D-phase AD conversion.

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