Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device includes a chip having a first main surface and a second main surface on the opposite side of the first main surface, and, within the chip, a semiconductor region provided in a surface layer part of the first main surface, and a device structure formed in a surface layer part of the semiconductor region. The semiconductor region includes a stacked structure formed by a first layer positioned on the second main surface side and made from a first semiconductor material being a wide bandgap semiconductor material, and a second layer positioned on the first main surface side and having an absorption coefficient higher than that of the first layer.

Description

Semiconductor device and method for manufacturing the same Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-113662 filed with the Japan Patent Office on July 16, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0003] Patent Document 1 discloses a semiconductor device including a SiC semiconductor layer, in which a trench is formed in a main surface of the SiC semiconductor layer.

[0004] International Publication No. 2020 / 031971

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device including: a chip having a first main surface and a second main surface opposite the first main surface; a semiconductor region disposed within the chip in a surface layer portion of the first main surface; and a device structure formed in the surface layer portion of the semiconductor region. The semiconductor region may include a stacked structure including a first layer on the second main surface side, the first layer being made of a first semiconductor material that is a wide bandgap semiconductor material, and a second layer on the first main surface side, the second layer having a higher absorption coefficient than the first layer.

[0006] One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including: a first step of preparing a wafer having a wafer main surface and made of a wide bandgap semiconductor material; a stacked structure formation step of forming, on a surface layer portion of the wafer main surface, a stacked structure in which a first layer made of a first semiconductor material that is a wide bandgap semiconductor material and a second layer having a higher absorption coefficient than the first layer are stacked on the first layer; and an exposure step of exposing a resist formed on the second layer through a photomask to form a resist mask on the second layer.

[0007] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a chip. FIG. 4 is a perspective view showing an example layout of a chip. FIG. 5 is an enlarged plan view showing a main portion of the first main surface shown in FIG. 3 . FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is an enlarged view of a portion surrounded by dashed-dotted line VIII in FIG. 6 . FIG. 9 is an enlarged view of a portion surrounded by dashed-dotted line IX in FIG. 7 . FIG. 10 is a schematic diagram showing a wafer used in manufacturing the semiconductor device. FIG. 11A is a cross-sectional view showing a method for manufacturing the semiconductor device. FIG. 11B is a cross-sectional view showing a process subsequent to FIG. 11A . FIG. 11C is a cross-sectional view showing a process subsequent to FIG. 11B . FIG. 11D is a cross-sectional view showing a process subsequent to FIG. 11C . FIG. 11E is a cross-sectional view showing a process subsequent to FIG. 11D . 11F is a cross-sectional view showing a step after FIG. 11E. FIG. 11G is a cross-sectional view showing a step after FIG. 11F. FIG. 11H is a cross-sectional view showing a step after FIG. 11G. FIG. 11I is a cross-sectional view showing a step after FIG. 11H. FIG. 11J is a cross-sectional view showing a step after FIG. 11I. FIG. 11K is a cross-sectional view showing a step after FIG. 11J. FIG. 11L is a cross-sectional view showing a step after FIG. 11K. FIG. 11M is a cross-sectional view showing a step after FIG. 11L. FIG. 11N is a cross-sectional view showing a step after FIG. 11M. FIG. 11O is a cross-sectional view showing a step after FIG. 11N. FIG. 11P is a cross-sectional view showing a step after FIG. 11O. FIG. 12 is a cross-sectional view showing a main part of a semiconductor device according to a second embodiment of the present disclosure, corresponding to FIG. 8. FIG. 13 is a cross-sectional view showing a main part of the semiconductor device, corresponding to FIG. 9. FIG. 14A is a cross-sectional view showing a method for manufacturing the semiconductor device. FIG. 14B is a cross-sectional view showing a step after FIG. 14A. Fig. 14C is a cross-sectional view showing a step after Fig. 14B. Fig. 14D is a cross-sectional view showing a step after Fig. 14C. Fig. 14E is a cross-sectional view showing a step after Fig. 14D. Fig. 14F is a cross-sectional view showing a step after Fig. 14E. Fig. 14G is a cross-sectional view showing a step after Fig. 14F. Fig. 14H is a cross-sectional view showing a step after Fig. 14G. Fig. 14I is a cross-sectional view showing a step after Fig. 14H.14J is a cross-sectional view showing a step after FIG. 14I. FIG. 14K is a cross-sectional view showing a step after FIG. 14J. FIG. 14L is a cross-sectional view showing a step after FIG. 14K. FIG. 15 is a cross-sectional view showing a main part of a semiconductor device according to a first modification of the first embodiment, and corresponds to FIG. 8. FIG. 16 is a cross-sectional view showing a main part of the semiconductor device, and corresponds to FIG. 9. FIG. 17A is a cross-sectional view showing a part of a method for manufacturing the semiconductor device, and corresponds to FIG. 11G. FIG. 17B is a cross-sectional view showing a part of a method for manufacturing the semiconductor device, and corresponds to FIG. 11I. FIG. 18 is a cross-sectional view showing a main part of a semiconductor device according to a second modification of the first embodiment, and corresponds to FIG. 8. FIG. 19 is a cross-sectional view showing a main part of the semiconductor device, and corresponds to FIG. 9. FIG. 20A is a cross-sectional view showing a part of a method for manufacturing the semiconductor device, and corresponds to FIG. 11G. FIG. 20B is a cross-sectional view showing a part of a method for manufacturing the semiconductor device, and corresponds to FIG. 11I.

[0008] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] Fig. 1 is a plan view showing a semiconductor device 1A according to a first embodiment of the present disclosure. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of a chip 2. Fig. 4 is a perspective view showing an example layout of the chip 2.

[0013] 1 to 4, a semiconductor device 1A is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a trench gate vertical structure.

[0014] Semiconductor device 1A includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1A is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0015] Wide bandgap semiconductors are semiconductors with a bandgap that exceeds that of Si (silicon). ２ O ３ Examples of wide bandgap semiconductors include gallium oxide (Gallium Oxide). In this embodiment, the chip 2 is a "SiC chip" that includes a SiC single crystal. In other words, the semiconductor device 1A is a "SiC semiconductor device."

[0016] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2.

[0017] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0018] The semiconductor device 1A includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "base region (layer)," a "semiconductor region (layer)," a "drain region (layer)," or the like.

[0019] The first semiconductor region 6 extends in a layered form along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an n-type (first conductivity type) semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal), and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 (substrate) has a predetermined off direction and off angle.

[0020] The first semiconductor region 6 may have a thickness T1 ( FIG. 4 ) of 10 μm to 500 μm inclusive. The thickness T1 of the first semiconductor region 6 may have a value belonging to at least one of the ranges of 10 μm to 50 μm inclusive, 50 μm to 100 μm inclusive, 100 μm to 150 μm inclusive, 150 μm to 200 μm inclusive, 200 μm to 300 μm inclusive, 300 μm to 400 μm inclusive, and 400 μm to 500 μm inclusive.

[0021] The first semiconductor region 6 (SiC substrate) includes a hexagonal SiC single crystal. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, the hexagonal SiC single crystal includes a 4H-SiC single crystal. The hexagonal SiC single crystal may also include other polytypes.

[0022] The second main surface 4 is preferably formed by the c-plane of the SiC single crystal. In this case, the second main surface 4 is preferably formed by the carbon face ((000-1) face) of the SiC single crystal.

[0023] The semiconductor device 1A includes an n-type second semiconductor region (semiconductor region) 7 formed in a surface layer portion of the first main surface 3. The second semiconductor region (semiconductor region, drift region) 7 may also be referred to as a "semiconductor region (layer)," "drift region (layer)," or the like. The second semiconductor region 7 has an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6. The second semiconductor region 7 is formed in a region closer to the first main surface 3 than the first semiconductor region 6 in a cross-sectional view, and is electrically connected to the first semiconductor region 6.

[0024] The second semiconductor region 7 extends in a layered form along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer. The second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal). The second semiconductor region 7 forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0025] 2 and 4, the second semiconductor region 7 preferably has a thickness T2 (FIG. 4) that is less than the thickness T1 of the first semiconductor region 6. The thickness T2 of the second semiconductor region 7 may be greater than the thickness T1 (FIG. 4) of the first semiconductor region 6.

[0026] The thickness T2 of the second semiconductor region 7 may be 5 μm or more and 15 μm or less. The thickness T2 of the second semiconductor region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0027] 2 and 4 , the second semiconductor region 7 includes a stacked structure of a first layer 7 a on the second main surface 4 side and a second layer 7 b on the first main surface 3 side. The stacked structure may be a two-layer structure. The first layer 7 a and the second layer 7 b have different crystal structures. An interface 7 c between the first layer 7 a and the second layer 7 b is a flat surface parallel to the first main surface 3.

[0028] The first layer 7a extends in a layered form along the first main surface 3 at a position away from the first main surface 3 on the second main surface 4 side. The first layer 7a is formed over the entire surface portion of the second semiconductor region 7 on the second main surface 4 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The first layer 7a forms a boundary layer between the second semiconductor region 7 and the first semiconductor region 6.

[0029] The first layer 7a has a first thickness T11 (FIG. 4). The first thickness T11 may be 5 μm or more and 15 μm or less. The first thickness T11 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0030] The first layer 7a is made of a hexagonal SiC single crystal (first semiconductor material). The hexagonal SiC single crystal has a plurality of polytypes, including 2H—SiC single crystal, 4H—SiC single crystal, and 6H—SiC single crystal. In this embodiment, the hexagonal SiC single crystal includes a 4H—SiC single crystal. The hexagonal SiC single crystal may also include other polytypes. The first layer 7a may also be referred to as a "first region," a "hexagonal layer," a "hexagonal region," a "4H—SiC layer," a "4H—SiC region," or the like.

[0031] Hexagonal SiC single crystals have relatively large bandgaps. The bandgap (energy bandgap) of 2H—SiC is 3.33 (eV), the bandgap of 4H—SiC is 3.26 (eV), and the bandgap of 6H—SiC is 3.02 (eV).

[0032] The upper surface (boundary surface 7c (FIG. 2)) of the first layer 7a is preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 may be formed by the silicon surface ((0001) plane) of the SiC single crystal.

[0033] 2 and 4, the second layer 7b extends in a layered manner along the first main surface 3. The upper surface of the second layer 7b is the first main surface 3. The second layer 7b may be formed over the entire surface portion on the first main surface 3 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The first main surface 3 may be formed by the (111) plane of the SiC single crystal.

[0034] The second layer 7b has a second thickness T12 (FIG. 4). The second thickness T12 is less than the first thickness T11 (T12<T11). The second thickness T12 is preferably 0.5 μm or more and 12 μm or less. The second thickness T12 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, and 10 μm or more and 12 μm or less.

[0035] The ratio (T12 / T11) of the second thickness T12 to the first thickness T11 may be 0.05 or more and 0.8 or less. The ratio (T12 / T11) may have a value belonging to at least one of the ranges of 0.05 or more and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, and 0.7 or more and 0.8 or less.

[0036] The second thickness T12 of the second layer 7b may be the same as the first thickness T11 of the first layer 7a, or may be greater than the first thickness T11.

[0037] The second layer 7b is made of a cubic SiC single crystal (second semiconductor material). The cubic SiC single crystal includes a 3C (cubic)-SiC single crystal. The second layer 7b may be referred to as a "second region," a "cubic crystal layer," a "cubic crystal region," a "3C-SiC layer," a "3C-SiC region," or the like.

[0038] The band gap (energy band gap) of cubic SiC single crystal (3C-SiC) is 2.23 (eV), which means that cubic SiC single crystal (3C-SiC) has a narrower band gap than hexagonal SiC single crystal (2H-SiC, 4H-SiC, 6H-SiC, etc.).

[0039] The first layer 7a and the second layer 7b have different absorption coefficients (light absorption coefficients) for the laser light used in the exposure process (FIGS. 11G, 11I, etc.). The first layer 7a is a low-absorption layer with a relatively low absorption coefficient for laser light. Because the hexagonal SiC single crystal constituting the first layer 7a has a relatively large band gap, the first layer 7a has a relatively low absorption coefficient for laser light.

[0040] The second layer 7b is a high-absorption layer having a relatively high absorption coefficient for laser light. The cubic SiC single crystal constituting the second layer 7b has a relatively small band gap, so the second layer 7b has a relatively high absorption coefficient for laser light.

[0041] The laser light includes a short wavelength laser. The short wavelength laser may include an ultraviolet (UV) laser having a wavelength of 150 nm or more and 400 nm or less. The ultraviolet laser includes an ArF excimer laser, a KrF excimer laser, a XeCl excimer laser, a XeF excimer laser, and an F ２ The laser may include at least one of the excimer lasers.

[0042] The ArF excimer laser has a wavelength of 188 nm or more and 198 nm or less (more specifically, 193 nm), and the KrF excimer laser has a wavelength of 243 nm or more and 253 nm or less (more specifically, 248 nm).

[0043] The XeCl excimer laser has a wavelength of 303 nm or more and 313 nm or less (more specifically, 308 nm), and the XeF excimer laser has a wavelength of 346 nm or more and 356 nm or less (more specifically, 351 nm).

[0044] F ２ Excimer lasers have a wavelength of 152 nm to 162 nm (more specifically, 157 nm), and extreme ultraviolet (EUV) light has a wavelength of 13 nm to 14 nm (more specifically, 13.5 nm).

[0045] The short wavelength laser may also include an extreme ultraviolet (EUV) laser having a wavelength of 13 nm or more and 14 nm or less.

[0046] 1 to 4, semiconductor device 1A includes an active region 8 defined in chip 2. Active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. Active region 8 is defined in an inner portion of chip 2 and spaced apart from the periphery of first main surface 3 (first to fourth side surfaces 5A to 5D).

[0047] The active region 8 is set to a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The ratio (area ratio) of the planar area of ​​the active region 8 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. The area ratio may have a value belonging to at least one of the ranges of 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 0.95 or less.

[0048] The semiconductor device 1A includes a peripheral region 9 set outside the active region 8 in the chip 2. The peripheral region 9 is a region that does not include a device structure (transistor structure Tr). The peripheral region 9 is set on the periphery of the chip 2. That is, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8 in plan view. The peripheral region 9 extends in a strip shape along the active region 8 in plan view and is set in the shape of a polygonal ring (a square ring in this embodiment) that surrounds the active region 8.

[0049] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures (trench structures) 15 formed in the active region 8. The gate structures 15 may also be referred to as "trench structures," "trench gate structures," or the like.

[0050] The plurality of gate structures 15 are formed in an inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. The plurality of gate structures 15 are arranged at intervals in the first direction X in a plan view, and each extend in a band shape in the second direction Y. The plurality of gate structures 15 are arranged in a stripe shape extending in the second direction Y in a plan view.

[0051] The plurality of gate structures 15 are formed in the second layer 7b of the second semiconductor region 7. The gate structures 15 are not formed in the first layer 7a. The gate structures 15 are formed away from the first layer 7a toward the first main surface 3.

[0052] The semiconductor device 1A includes a p-type outer well region 40 formed in the peripheral region 9. A source potential is applied to the outer well region 40. The outer well region 40 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7 (for example, a base region 71 described later).

[0053] The outer well region 40 includes a first outer well region 42 and a plurality of second outer well regions 43. The first outer well region 42 and the plurality of second outer well regions 43 may be referred to as a "termination region" and a "field region," respectively. The first outer well region 42 and the plurality of second outer well regions 43 may also be collectively referred to as an "outer well region." The first outer well region 42 may also be referred to as a "termination well region," a "JTE region (Junction Termination Extension region)," or the like. The second outer well region 43 may also be referred to as a "guard region," a "field limit region," or the like.

[0054] 3 and 4 , the first outer well region 42 is a quadrangular ring-shaped region defined by a thick solid line and a thick dashed line. The first outer well region 42 has a portion extending in a first direction X and a portion extending in a second direction Y. In this embodiment, the first outer well region 42 is formed in a polygonal ring shape (a quadrangular ring in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds a plurality of gate structures 15.

[0055] The first outer well region 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). In this embodiment, the first outer well region 42 is formed in the peripheral region 9 and surrounds the active region 8. A source potential is applied to the first outer well region 42.

[0056] When a reverse bias voltage is applied, the first outer well region 42 spreads a depletion layer into the second semiconductor region 7. The depletion layer originating in the first outer well region 42 spreads in the horizontal and thickness directions, and relieves the electric field in the vicinity of the boundary between the active region 8 and the peripheral region 9.

[0057] 2, the first outer well region 42 straddles the first layer 7a and the second layer 7b of the second semiconductor region 7. The first outer well region 42 includes a lower region 42a formed in the first layer 7a and an upper region 42b formed in the second layer 7b. The first outer well region 42 is formed over the entire depth of the second layer 7b. The upper region 42b may be formed in the second layer 7b and not in the first layer 7a. In other words, the lower region 42a may be omitted.

[0058] 3 and 4 , each of the multiple second outer well regions 43 has a portion extending in the first direction X and a portion extending in the second direction Y. In this embodiment, each second outer well region 43 is formed in a polygonal ring shape (a square ring in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the first outer well region 42.

[0059] Each of the plurality of second outer well regions 43 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape). In this embodiment, the plurality of second outer well regions 43 are arranged in the outer periphery region 9 at intervals outward from the first outer well region 42.

[0060] The number of second outer well regions 43 is arbitrary. The number of second outer well regions 43 may be 1 or more and 15 or less. The number of second outer well regions 43 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15. The number of second outer well regions 43 is typically 1 or more and 10 or less. In this embodiment, the semiconductor device 1A includes, as an example, four second outer well regions 43.

[0061] The second outer well region 43 is formed in an electrically floating state. A source potential may be applied to the second outer well region 43.

[0062] The second outer well regions 43 expand the depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating in the second outer well regions 43 expands in the horizontal and thickness directions and merges with the depletion layer originating in the first outer well region 42. The second outer well regions 43 expand the depletion layer originating in the first outer well region 42 toward the periphery of the first main surface 3, thereby alleviating the electric field in the periphery (peripheral region 9) of the first main surface 3.

[0063] 2 , the second outer well region 43 straddles the first layer 7a and the second layer 7b of the second semiconductor region 7. The second outer well region 43 includes a lower region 43a formed in the first layer 7a and an upper region 43b formed in the second layer 7b. The upper region 43b is formed over the entire depth of the second layer 7b. The second outer well region 43 may be formed in the second layer 7b and not in the first layer 7a. In other words, the lower region 43a may be omitted.

[0064] 2, semiconductor device 1A includes an insulating interlayer film 47 formed on first main surface 3. Interlayer film 47 may be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. Interlayer film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Interlayer film 47 preferably includes a silicon oxide film.

[0065] 1 and 2 , semiconductor device 1A includes a source electrode 51 disposed on first main surface 3. Source electrode 51 is a terminal electrode to which a source potential is applied from the outside. Source electrode 51 may also be referred to as a "source pad electrode," a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like. Source electrode 51 is disposed on a portion of interlayer film 47 that covers active region 8.

[0066] In this embodiment, the source electrode 51 has a first pad portion 51 a, a second pad portion 51 b, and a third pad portion 51 c. The first pad portion 51 a has a relatively large planar area and constitutes the main body of the source electrode 51. In this embodiment, the first pad portion 51 a has a polygonal shape (a quadrangle in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the first main surface 3.

[0067] The second pad portion 51b has a planar area smaller than that of the first pad portion 51a, and extends in a strip shape (rectangular) from one end of the first pad portion 51a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C. The third pad portion 51c has a planar area smaller than that of the first pad portion 51a, and extends in a strip shape (rectangular) from the other end of the first pad portion 51a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 51b in the second direction Y.

[0068] The plane area of ​​the third pad portion 51c may be approximately equal to the plane area of ​​the second pad portion 51b. The plane area of ​​the third pad portion 51c may be larger than the plane area of ​​the second pad portion 51b, or may be smaller than the plane area of ​​the second pad portion 51b. Either or both of the second pad portion 51b and the third pad portion 51c may be used as a terminal portion for monitoring current.

[0069] The source electrode 51 does not necessarily have to have both the second pad portion 51 b and the third pad portion 51 c at the same time. The source electrode 51 may have only one of the second pad portion 51 b and the third pad portion 51 c. The source electrode 51 may be composed of only the first pad portion 51 a, and may not have both the second pad portion 51 b and the third pad portion 51 c.

[0070] 1 and 2, semiconductor device 1A includes a source wiring 56 arranged around source electrode 51 on interlayer film 47. The same potential (source potential) as the potential (source potential) applied to source electrode 51 is applied to source wiring 56. Source wiring 56 may also be referred to as a "termination electrode (wiring)," "wiring," "first wiring," "finger electrode," "source finger," or the like.

[0071] The source wiring 56 has a wiring width less than the electrode width of the source electrode 51, and is selectively routed on the interlayer film 47. In this embodiment, the source wiring 56 is drawn from the source electrode 51 (first pad portion 51 a) to the fourth side surface 5D. The source wiring 56 is drawn from the active region 8 to the peripheral region 9.

[0072] The source wiring 56 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 8). In this embodiment, the source wiring 56 has a polygonal ring shape (a square ring shape in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (the active region 8). The source wiring 56 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The source wiring 56 may be either ended or endless.

[0073] 1 and 2 , semiconductor device 1A includes a gate electrode 57 disposed on first main surface 3. Gate electrode 57 is a terminal electrode to which a gate potential is applied from the outside. Gate electrode 57 may also be referred to as a "second pad electrode," a "second main surface electrode," a "second terminal electrode," or the like.

[0074] The gate electrode 57 is disposed on a portion of the interlayer film 47 that covers the active region 8, with a gap between it and the source electrode 51. In this embodiment, the gate electrode 57 is disposed in a region on the third side surface 5C side of the first pad portion 51a, and faces the first pad portion 51a in the first direction X. The gate electrode 57 is interposed in a region between the second pad portion 51b and the third pad portion 51c, and faces both the second pad portion 51b and the third pad portion 51c in the second direction Y.

[0075] The gate electrode 57 has a polygonal shape (a quadrilateral shape in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 57 has a planar area smaller than the planar area of ​​the source electrode 51. The gate electrode 57 has a planar area smaller than the planar area of ​​the first pad portion 51a. The gate electrode 57 may also have a planar area smaller than the planar area of ​​the second pad portion 51b (third pad portion 51c).

[0076] 1 and 2 , semiconductor device 1A includes gate wiring 58 extending from gate electrode 57 onto first main surface 3. Gate wiring 58 may also be referred to as "wiring," "second wiring," "finger electrode," "gate finger," etc. Gate wiring 58 transmits the gate potential applied to gate electrode 57 to other regions.

[0077] The gate wiring 58 is drawn out from the gate electrode 57 onto the portion of the interlayer film 47 that covers the active region 8, and is routed to the region between the source electrode 51 and the source wiring 56, with a gap between each of the source electrode 51 and the source wiring 56.

[0078] The gate wiring 58 has a portion extending in a strip shape in the first direction X in a plan view and a portion extending in a strip shape in the second direction Y, and intersects (specifically, orthogonally) with ends (both ends in this embodiment) of the plurality of gate structures 15. In this embodiment, the gate wiring 58 is formed in a strip shape with ends having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 51.

[0079] 2 , semiconductor device 1A includes a drain electrode 59 covering second main surface 4. Drain electrode 59 is a terminal electrode to which a drain potential is applied from the outside. Drain electrode 59 may also be referred to as a “third pad electrode,” a “third main surface electrode,” a “third terminal electrode,” or the like.

[0080] The drain electrode 59 is electrically connected to the first semiconductor region 6. The drain electrode 59 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain electrode 59 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0081] A breakdown voltage that can be applied between source electrode 51 and drain electrode 59 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, 2500 V or more and 2750 V or less, and 2750 V or more and 3000 V or less.

[0082] Fig. 5 is an enlarged plan view showing a main portion of the first main surface 3 shown in Fig. 3. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 5. Fig. 8 is an enlarged view of a portion surrounded by dashed-dotted line VIII in Fig. 6. Fig. 9 is an enlarged view of a portion surrounded by dashed-dotted line IX in Fig. 7. The configuration of the transistor structure Tr formed in the active region 8 (the inner portion of the first main surface 3) of the semiconductor device 1A will be described with reference to Figs. 5 to 9.

[0083] 6 to 9 , semiconductor device 1A includes a p-type body region 10 formed in a surface layer portion of first main surface 3 in active region 8. Body region 10 is formed in second layer 7b of second semiconductor region 7. That is, body region 10 is made of cubic 3C (cubic)-SiC single crystal (SiC single crystal).

[0084] The body region 10 may be referred to as an "impurity region," a "channel region," or the like. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential. The body region 10 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7 (for example, a base region 71 described later). The body region 10 has a p-type impurity concentration of, for example, 1×10 １７ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0085] The body region 10 is formed in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. In this embodiment, the body region 10 is formed over the entire active region 8. The body region 10 is formed in a surface layer portion of the second semiconductor region 7 and extends in a layered form along the first main surface 3. The body region 10 does not have to be formed in the peripheral region 9.

[0086] The body region 10 is formed at a distance from the bottom of the second semiconductor region 7 (first semiconductor region 6) toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The body region 10 is formed at a distance from a depth position of the middle part of the second semiconductor region 7 toward the first main surface 3.

[0087] The body region 10 is formed in a region on the first main surface 3 side of the second semiconductor region 7 in a cross-sectional view, and is electrically connected to the second semiconductor region 7. The body region 10 forms a pn junction (body diode) with the second semiconductor region 7. The body region 10 spreads a depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer originating in the body region 10 spreads in the horizontal direction and thickness direction within the second semiconductor region 7.

[0088] 6 to 9 , semiconductor device 1A includes an n-type source region 11 formed in a surface layer portion of first main surface 3 in active region 8. A source potential is applied to source region 11. Source region 11 has a higher n-type impurity concentration than a medium concentration region 72 and a high concentration region 73 (described later) of second semiconductor region 7. The n-type impurity concentration of source region 11 is higher than the p-type impurity concentration of body region 10.

[0089] The source region 11 is formed in an inner portion of the first main surface 3 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer peripheral region 9. The source region 11 may be formed inwardly at a distance from the periphery of the body region 10. The source region 11 is formed in a surface layer portion of the body region 10, and extends in a layered form along the first main surface 3.

[0090] The source region 11 is formed in the second layer 7b of the second semiconductor region 7. That is, the source region 11 is made of cubic 3C (cubic)-SiC single crystal (SiC single crystal).

[0091] The source region 11 is formed at a distance from the bottom of the body region 10 toward the first main surface 3, and faces the second semiconductor region 7 across a part of the body region 10. The source region 11 is formed in a region on the first main surface 3 side of the body region 10 in a cross-sectional view, and is electrically connected to the body region 10.

[0092] The plurality of gate structures 15 are formed in an inner portion of the first main surface 3 at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and are not formed in the outer peripheral region 9. The plurality of gate structures 15 are arranged at intervals in the first direction X in a plan view, and each extend in a band shape in the second direction Y. The plurality of gate structures 15 are arranged in a stripe shape extending in the second direction Y in a plan view.

[0093] The extension direction of the multiple gate structures 15 coincides with the off-direction of the SiC single crystal. With respect to the second direction Y, both ends of the multiple gate structures 15 may be located in a region between the peripheral edge of the body region 10 and the peripheral edge of the source region 11. The multiple gate structures 15 may be arranged at intervals in the second direction Y in a plan view, and each extend in a strip shape in the first direction X.

[0094] The plurality of gate structures 15 penetrates the body region 10 and the source region 11 to reach the second semiconductor region 7. The plurality of gate structures 15 are formed at intervals from the depth position of the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0095] The plurality of gate structures 15 may be formed at intervals from a depth position of an intermediate portion of the second semiconductor region 7 toward the first main surface 3, or may be located on the bottom side of the second semiconductor region 7 with respect to the depth position of the intermediate portion of the second semiconductor region 7. The plurality of gate structures 15 are formed substantially perpendicular to the first main surface 3. The plurality of gate structures 15 may be formed in a shape that tapers toward the bottom of the second semiconductor region 7.

[0096] The inclination angle (absolute value) of the sidewall (long side) of the gate structure 15 relative to the vertical line may be 85° or more and 95° or less. The inclination angle may have a value belonging to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The inclination angle is preferably 87° or more and 93° or less.

[0097] The gate structure 15 may have a width of 0.1 μm to 2 μm, and may have a width in at least one of the ranges of 0.1 μm to 0.25 μm, 0.25 μm to 0.5 μm, 0.5 μm to 0.75 μm, 0.75 μm to 1 μm, 1 μm to 1.25 μm, 1.25 μm to 1.5 μm, 1.5 μm to 1.75 μm, and 1.75 μm to 2 μm.

[0098] The gate structure 15 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate structure 15 is measured from the first main surface 3. The depth of the gate structure 15 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the gate structure 15 is preferably 0.5 μm or more and 1.5 μm or less.

[0099] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value belonging to at least one of the ranges of 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. The aspect ratio is preferably 1.5 to 2.5.

[0100] 6 to 9, one gate structure 15 will be described. The gate structure 15 includes a trench 16, an insulating film 17, and a buried electrode 18. The trench 16 is formed in the first main surface 3 and defines the wall surfaces (side walls and bottom wall) of the gate structure 15. The trench 16 may be referred to as an "element trench," a "gate trench," etc. The insulating film 17 may be referred to as a "trench insulating film," an "element insulating film," a "gate insulating film," etc. The buried electrode 18 may be referred to as a "buried electrode," a "gate electrode," etc.

[0101] 8 and 9 , trench 16 is formed in first main surface 3 so as to extend from first main surface 3 toward second semiconductor region 7. Trench 16 defines the inner surface of gate structure 15. Trench 16 has a pair of side surfaces 19 and a bottom surface 20. Bottom surface 20 of trench 16 preferably has a portion that extends flat along first main surface 3. Side surface 19 of trench 16 is entirely disposed in second layer 7b. Bottom surface 20 of trench 16 is disposed in second layer 7b.

[0102] The trench 16 has a trench depth DT in the vertical direction Z. The trench depth DT may be 0.1 μm or more and 5 μm or less. The trench depth DT may have a value belonging to any one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less. The trench depth DT is preferably 0.1 μm or more and 1.5 μm or less. In this embodiment, the trench depth DT is smaller than the second thickness T12 ( FIG. 4 ) (DT<T12).

[0103] The trench depth DT is preferably equal to or greater than half of the second thickness T12 (FIG. 4). The trench depth DT is preferably equal to or greater than half of the second thickness T12.

[0104] The ratio of the trench depth DT to the second thickness T12 (DT / T12) may be 0.5 to 0.95 inclusive. The thickness ratio may have a value belonging to any one of the ranges of 0.5 to 0.6 inclusive, 0.6 to 0.7 inclusive, 0.7 to 0.8 inclusive, 0.8 to 0.85 inclusive, 0.85 to 0.9 inclusive, and 0.9 to 0.95 inclusive.

[0105] The trench depth DT of the trench 16 is greater than the first distance L1 between the boundary surface 7c and the bottom surface 20 of the trench 16. In other words, the first distance L1 is shorter than the trench depth DT (L1<DT).

[0106] The ratio (L1 / T12) of the first distance L1 to the second thickness T12 may be 0.05 or more and 1 or less. The thickness ratio may have a value belonging to any one of the ranges of 0.05 or more and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or more, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 1 or less.

[0107] It is particularly preferable that the flat portion of the bottom surface 20 of the trench 16 extends substantially parallel to the first main surface 3. In other words, it is preferable that the bottom surface 20 of the trench 16 has a flat portion extending in the off-direction. Of course, the bottom surface 20 of the trench 16 may be curved in an arc shape toward the second main surface 4.

[0108] Between adjacent trenches 16, a mesa portion 21 is formed, which is formed by a part of the second semiconductor region 7. The mesa portion 21 may be referred to as an "element mesa portion."

[0109] The mesa portion 21 has one top surface 22 and two side surfaces 19. The top surface 22 is a part of the first main surface 3. The side surfaces 19 of the mesa portion 21 are defined by the side surfaces 19 of the trench 16. An internal region of the mesa portion 21 surrounded by the one top surface 22 and the two side surfaces 19 is disposed in the second layer 7b. In other words, the entire mesa portion 21 is disposed in the second layer 7b.

[0110] 5, the gate structures 15 (trenches 16) and mesa portions 21 are strip-shaped extending along the second direction Y and are arranged alternately in the first direction X. The trenches 16 and mesa portions 21 are arranged in a stripe pattern as a whole.

[0111] 8 and 9, insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that insulating film 17 include a silicon oxide film made of an oxide of chip 2.

[0112] The insulating film 17 covers the wall surface of the trench 16. The insulating film 17 includes a first film portion and a second film portion. The first film portion covers the side wall of the trench 16 in a film-like manner. The second film portion covers the bottom wall of the trench 16 in a film-like manner and is continuous with the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.

[0113] The insulating film 17 may have a thickness of 10 nm to 150 nm, and may have a thickness in at least one range of 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, and 125 nm to 150 nm.

[0114] The buried electrode 18 is buried in the trench 16 with the insulating film 17 sandwiched therebetween. The buried electrode 18 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. The buried electrode 18 faces the second semiconductor region 7, the body region 10, and the source region 11 with the insulating film 17 sandwiched therebetween.

[0115] The buried electrode 18 is buried up to the middle of the trench 16 in the depth direction. The buried electrode 18 has an upper surface 30 located closer to the second main surface 4 than the first main surface 3. A low step is formed on the second main surface 4 side between the upper surface 30 of the buried electrode 18 and the first main surface 3, and this step forms a recess 31 in the upper part of the trench 16 that is partitioned by the upper surface 30 of the buried electrode 18 and the side surface 19 of the trench 16.

[0116] The recess 31 is a space sandwiched between both side surfaces 19 of the trench 16 and an upper surface 30 of the buried electrode 18. The recess 31 is formed in a continuous strip shape in the depth direction (second direction Y) of the trench 16. The insulating film 17 is selectively formed in a region sandwiched between the inner surface of the trench 16 and the buried electrode 18, and the side surface 19 of the recess 31 (part of the side surface 19 of the trench 16) is exposed from the insulating film 17.

[0117] The gate structure 15 includes channel regions 26 ( FIG. 8 ) formed in the body region 10 between the source regions 11 and the intermediate concentration regions 72 described below. The inversion and non-inversion of the channel regions 26 are controlled by the gate structure 15. A plurality of channel regions 26 are provided. The plurality of channel regions 26 form current paths connecting the source regions 11 and the intermediate concentration regions 72 along side surfaces 19 of the plurality of gate structures 15 in the body region 10.

[0118] 6 to 9, the plurality of gate structures 15 includes a plurality of first gate structures 15A and a plurality of second gate structures 15B. The plurality of first gate structures 15A and the plurality of second gate structures 15B are alternately arranged in the first direction X.

[0119] The semiconductor device 1A includes a plurality of electric field relaxation layers 25 formed in regions below the plurality of gate structures 15 in the chip 2 (second semiconductor region 7) of the active region 8. The plurality of electric field relaxation layers 25 are formed at intervals from one another in the first direction X (horizontal direction). The electric field relaxation layers 25 are p-type regions. The electric field relaxation layers 25 may also be referred to as "gate well regions," "first well regions," etc.

[0120] A source potential is applied to one of the electric field relaxation layers 25. The electric field relaxation layer 25 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7 (for example, a base region 71 described later). The p-type impurity concentration of the electric field relaxation layer 25 may be higher than the p-type impurity concentration of the body region 10 or may be lower than the p-type impurity concentration of the body region 10.

[0121] The p-type impurity concentration of one field relaxation layer 25 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the electric field buffer layer 25 may have the following peak value: The p-type impurity concentration of the electric field buffer layer 25 is preferably adjusted by at least one trivalent element. The trivalent element of the electric field buffer layer 25 may be at least one of boron, aluminum, gallium, and indium.

[0122] The multiple electric field relaxation layers 25 are each formed in the thickness range between the bottom of the second semiconductor region 7 and the bottom walls of the multiple gate structures 15, and overlap the multiple gate structures 15 in a one-to-one correspondence in the thickness direction.

[0123] The plurality of electric field relaxation layers 25 each extend in a strip shape in the second direction Y in a plan view following the extension direction of the corresponding gate structure 15. That is, the plurality of electric field relaxation layers 25 are arranged in a stripe shape extending in the second direction Y in a plan view. In other words, the plurality of electric field relaxation layers 25 are formed in a region below the corresponding gate structure 15 along the bottom surface 20 of the corresponding trench 16 ( FIGS. 8 and 9 ).

[0124] The extension direction of the multiple electric field relaxation layers 25 coincides with the off-direction of the SiC single crystal. The multiple electric field relaxation layers 25 may extend in the first direction X according to the extension direction of the multiple gate structures 15. In this case, the multiple electric field relaxation layers 25 intersect (specifically, are perpendicular to) the off-direction.

[0125] The plurality of electric field relaxation layers 25 are formed at intervals from the bottom of the second semiconductor region 7 toward the bottom wall sides of the plurality of gate structures 15, and face the first semiconductor region 6 across a part of the second semiconductor region 7. Each of the plurality of electric field relaxation layers 25 has an upper end located on the bottom wall side of the corresponding gate structure 15, and a bottom located on the bottom side of the second semiconductor region 7 (the side facing the second main surface 4).

[0126] The upper end of each electric field relaxation layer 25 is formed at a distance from the bottom of the body region 10 toward the bottom wall of the corresponding gate structure 15. The upper end of each electric field relaxation layer 25 may be in contact with the bottom of the corresponding gate structure 15.

[0127] The upper end of each electric field relaxation layer 25 may have a portion that is along the side wall of the corresponding gate structure 15. The upper end of each electric field relaxation layer 25 may be formed at a distance from the bottom wall of the corresponding gate structure 15 toward the bottom of the second semiconductor region 7.

[0128] Each of the electric field relaxation layers 25 has a bulge 25 a and a bottom 25 b. The bulge 25 a extends horizontally in an arc shape from a region directly below the corresponding gate structure 15 to both sides of the corresponding gate structure 15. Each of the electric field relaxation layers 25 is formed in a tapered shape from the bulge 25 a to the bottom. The bottoms 25 b extend from the bulge 25 a in a direction along the first main surface 3.

[0129] Each bottom 25b may be located on the bottom wall side of the multiple gate structures 15 relative to the intermediate portion of the second semiconductor region 7, or may be located on the bottom side of the second semiconductor region 7 (the side facing the second main surface 4) relative to the intermediate portion of the second semiconductor region 7.

[0130] One electric field relaxation layer 25 may have a width greater than or less than the width of the gate structure 15. The width of the electric field relaxation layer 25 may be 0.1 μm or more and 2 μm or less. The width of the electric field relaxation layer 25 may have a value belonging to at least one of the ranges of 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less.

[0131] 8 and 9 , one electric field relaxation layer 25 may have a relaxation depth DR that is less than the depth (trench depth DT) of the gate structure 15, or may have a relaxation depth DR that is greater than the depth of the gate structure 15. The relaxation depth DR is the depth of the electric field relaxation layer 25 when the bottom wall of the gate structure 15 is used as the reference.

[0132] The relaxation depth DR may be greater than 0 μm and less than or equal to 5 μm. The relaxation depth DR may have a value belonging to at least one of the following ranges: greater than 0 μm and less than or equal to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0133] One electric field relaxation layer 25 may have an aspect ratio greater than 0 and equal to or less than 2. The aspect ratio of the electric field relaxation layer 25 is the ratio of the depth of the electric field relaxation layer 25 to the width of the electric field relaxation layer 25.

[0134] The aspect ratio may have a value belonging to at least one of the ranges of greater than 0 and less than or equal to 0.25, 0.25 or more and less than or equal to 0.5, 0.5 or more and less than or equal to 0.75, 0.75 or more and less than or equal to 1, 1 or more and less than or equal to 1.25, 1.25 or more and less than or equal to 1.5, 1.5 or more and less than or equal to 1.75, and 1.75 or more and less than or equal to 2.

[0135] One electric field relaxation layer 25 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the electric field relaxation layer 25 spreads a depletion layer into the second semiconductor region 7. The depletion layer originating from the electric field relaxation layer 25 spreads in the horizontal direction and the thickness direction, and relaxes the electric field with respect to the active region 8 (gate structure 15).

[0136] 8 and 9 , one electric field relaxation layer 25 straddles the first layer 7a and the second layer 7b. That is, the electric field relaxation layer 25 straddles the boundary surface 7c in the vertical direction Z. The bulging portion 25a may straddle the first layer 7a and the second layer 7b. Although not shown, the bulging portion 25a may be disposed only in the first layer 7a, or the bulging portion 25a may be disposed only in the second layer 7b.

[0137] A second distance L2 between the interface 7c and the bottom 25b of the electric field buffer layer 25 is longer than a first distance L1 between the interface 7c and the bottom surface 20 of the trench 16. In other words, the first distance L1 is shorter than the second distance L2 (L1<L2).

[0138] 5, 7, and 9, the semiconductor device 1A includes a plurality of contact regions 27 formed in the chip 2 (second semiconductor region 7) in the active region 8. The contact regions 27 may also be referred to as "gate contacts," etc. A source potential is applied to the contact regions 27.

[0139] The contact region 27 has a p-type impurity concentration higher than the n-type impurity concentration of a base region 71 (described later). The contact region 27 may have a p-type impurity concentration higher than the n-type impurity concentration of a medium concentration region 72 (described later). The p-type impurity concentration of the contact region 27 is higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the contact region 27 is higher than the p-type impurity concentration of the field buffer layer 25.

[0140] The p-type impurity concentration of the contact region 27 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration of the contact region 27 may have the following peak value: The p-type impurity concentration of the contact region 27 is preferably adjusted by at least one trivalent element. The trivalent element of the contact region 27 may be at least one of boron, aluminum, gallium, and indium.

[0141] The contact regions 27 are formed at intervals in regions along the gate structures 15. The contact regions 27 are formed in a one-to-many correspondence with the gate structures 15. The contact regions 27 are formed at intervals in the second direction Y following the extension direction of the corresponding gate structures 15.

[0142] 5 , with respect to one and the other gate structures 15, the plurality of contact regions 27 along one gate structure 15 face the plurality of contact regions 27 along the other gate structure 15 in the first direction X in a plan view. In other words, the plurality of contact regions 27 are generally arranged in a matrix at intervals in the first direction X and the second direction Y in a plan view.

[0143] In plan view, one of the plurality of contact regions 27 may face a region between the other of the plurality of contact regions 27 in the first direction X. In other words, the plurality of contact regions 27 may be generally arranged in a staggered pattern with intervals in the first direction X and the second direction Y in plan view.

[0144] In this embodiment, the contact regions 27 extend in a strip shape along the gate structures 15 in a plan view. The lengths of the contact regions 27 in the second direction Y may be equal to or different from one another. The lengths of the contact regions 27 in the second direction Y are adjusted according to the area of ​​the channel to be formed.

[0145] The channel area is the total area of ​​the portions of the source region 11 exposed from the plurality of contact regions 27. That is, the channel area increases or decreases depending on the ratio of the total planar area of ​​the plurality of contact regions 27. It is preferable that the total planar area of ​​the plurality of contact regions 27 is less than the channel area.

[0146] That is, in the region between a pair of adjacent gate structures 15, the total planar area of ​​the plurality of contact regions 27 is preferably less than the planar area of ​​the source region 11. With such a configuration, an increase in the resistance value (on-resistance) due to a short channel is suppressed.

[0147] The length of the contact region 27 may be greater than or less than the width of the gate structure 15. The length of the contact region 27 may be greater than or less than the pitch of the gate structures 15. The length of the contact region 27 may be greater than or less than the pitch of two adjacent gate structures 15.

[0148] The interval between the multiple contact regions 27 may be greater than the width of the gate structures 15 or may be smaller than the width of the gate structures 15. The interval between the contact regions 27 may be greater than the pitch between the gate structures 15 or may be smaller than the pitch between the gate structures 15. The interval between the contact regions 27 may be greater than the pitch between two adjacent gate structures 15 or may be smaller than the pitch between two adjacent gate structures 15.

[0149] 7 and 9, the plurality of contact regions 27 are interposed in regions between the bottom walls of the plurality of gate structures 15 and the bottoms 25b of the plurality of electric field relaxation layers 25. The plurality of contact regions 27 are connected to the bottom walls of the corresponding gate structures 15 and the corresponding electric field relaxation layers 25.

[0150] The plurality of contact regions 27 increase the p-type impurity concentration at the upper end of the corresponding electric field reduction layer 25. The contact regions 27 have a first portion 27a extending along the sidewall of the gate structure 15 and a second portion 27b extending along the bottom wall of the gate structure 15. The second portion 27b extends from the region directly below the gate structure 15 to both sides of the gate structure 15.

[0151] The first portion 27a of the contact region 27 is electrically connected to the body region 10 in the surface layer portion of the first main surface 3, and electrically connects the corresponding electric field relaxation layer 25 to the body region 10. This prevents the electric field relaxation layer 25 from being electrically floating, and improves the electrical response characteristics of the electric field relaxation layer 25.

[0152] The contact region 27 has an upper end exposed from the first main surface 3. In this embodiment, the upper end of the contact region 27 is exposed from the sidewall of the trench 16 at the opening end of the trench 16. The upper end of the contact region 27 may extend horizontally in the surface layer portion of the body region 10.

[0153] The plurality of contact regions 27 are formed in the second layer 7b of the second semiconductor region 7. The contact regions 27 are not formed in the first layer 7a. The contact regions 27 are formed away from the first layer 7a toward the first main surface 3.

[0154] 6 and 8, the semiconductor device 1A includes a plurality of p-type high concentration regions 28 disposed in the bottom portions of the plurality of second gate structures 15B. The plurality of high concentration regions 28 are formed in a one-to-many correspondence with the corresponding second gate structures 15B. The plurality of high concentration regions 28 are disposed at intervals in the second direction Y. On the other hand, no high concentration regions 28 are formed in the bottom portions of the trenches 16 of the plurality of first gate structures 15A.

[0155] The multiple high-concentration regions 28 face the multiple second portions 27b (contact regions 27) in the second direction Y. One high-concentration region 28 is sandwiched between two second portions 27b in the second direction Y. The two high-concentration regions 28 sandwich one second portion 27b in the second direction Y. One high-concentration region 28 contacts two second portions 27b adjacent to each other in the second direction Y.

[0156] 8 , one of the high-concentration regions 28 will be described. The high-concentration region 28 is sandwiched between the bottom (bottom surface 20 in this embodiment) of the trench 16 of the first gate structure 15A and the electric field relaxation layer 25. The high-concentration region 28 contacts the bottom surface 20 of the trench 16.

[0157] The high-concentration region 28 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7 (for example, the base region 71 described below). The high-concentration region 28 may have a p-type impurity concentration higher than the n-type impurity concentration of the medium-concentration region 72 described below. The p-type impurity concentration of the high-concentration region 28 is higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the high-concentration region 28 is higher than the p-type impurity concentration of the field relaxation layer 25. The p-type impurity concentration of the high-concentration region 28 may be equal to the p-type impurity concentration of the contact region 27.

[0158] The p-type impurity concentration of the high concentration region 28 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３The p-type impurity concentration of the high-concentration region 28 may have the following peak value: The p-type impurity concentration of the high-concentration region 28 is preferably adjusted by at least one trivalent element. The trivalent element of the high-concentration region 28 may be at least one of boron, aluminum, gallium, and indium.

[0159] The plurality of high concentration regions 28 are formed in the second layer 7b of the second semiconductor region 7. The high concentration regions 28 are not formed in the first layer 7a. The high concentration regions 28 are formed away from the first layer 7a toward the first main surface 3.

[0160] 6 to 9, the second semiconductor region 7 of the semiconductor device 1A includes a stacked structure of a base region 71 and a medium concentration region 72.

[0161] The base region 71 is formed closer to the second main surface 4 than the electric field reduction layer 25 and away from the body region 10. The base region 71 extends in a layered form along the first main surface 3 at a position away from the body region 10 and the trench 16 toward the second main surface 4. The base region 71 is formed over the entire surface layer portion of the second semiconductor region 7 on the second main surface 4 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The base region 71 forms a boundary layer between the second semiconductor region 7 and the first semiconductor region 6.

[0162] The thickness of the base region 71 may be, for example, not less than 0.5 μm and not more than 15 μm, and is preferably not less than 1 μm and not more than 10 μm.

[0163] The n-type impurity concentration of the base region 71 is preferably lower than the n-type impurity concentration of the first semiconductor region 6. The base region 71 has a dopant concentration of 1×10 １６ cm －３ 1x10 or more １７ cm －３ The n-type impurity concentration of the base region 71 may have a peak value of the following: The n-type impurity concentration of the base region 71 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the base region 71 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0164] The base region 71 is formed closer to the second main surface 4 than the electric field reduction layer 25 and away from the body region 10. The base region 71 extends in a layered form along the first main surface 3 at a position away from the body region 10 and the trench 16 toward the second main surface 4. The base region 71 is formed over the entire surface layer portion of the second semiconductor region 7 on the second main surface 4 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The base region 71 forms a boundary surface between the second semiconductor region 7 and the first semiconductor region 6. In this embodiment, the base region 71 is formed in the first layer 7a.

[0165] The medium concentration region 72 is formed between the base region 71 and the body region 10, on the side of the trench 16 and the electric field relaxation layer 25. The medium concentration region 72 is in contact with the body region 10 and the electric field relaxation layer 25, and extends in a layered form along the first main surface 3. The medium concentration region 72 is formed in the entire surface layer portion of the second semiconductor region 7 on the first main surface 3 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The medium concentration region 72 forms a boundary surface between the second semiconductor region 7 and the body region 10.

[0166] The thickness of the intermediate concentration region 72 may be 0.1 μm or more and 0.5 μm or less, and is preferably 0.15 μm or more and 0.4 μm or less.

[0167] The n-type impurity concentration of the intermediate concentration region 72 is higher than the n-type impurity concentration of the base region 71. The intermediate concentration region 72 has an n-type impurity concentration of 1×10 １７ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the intermediate concentration region 72 may have a peak value of the following: The n-type impurity concentration of the intermediate concentration region 72 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the intermediate concentration region 72 may have a concentration gradient that gradually increases and / or gradually decreases in the thickness direction (crystal growth direction) of the chip 2.

[0168] In this embodiment, the n-type impurity concentration of the medium concentration region 72 is adjusted by nitrogen. The medium concentration region 72 may have an n-type impurity concentration adjusted by at least one pentavalent element. For example, the n-type impurity concentration of the medium concentration region 72 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0169] The medium-concentration region 72 spans the first layer 7a and the second layer 7b. The medium-concentration region 72 includes a first medium-concentration region 72a formed in the first layer 7a and a second medium-concentration region 72b formed in the second layer 7b. The first medium-concentration region 72a has a layer shape along the first main surface 3. The second medium-concentration region 72b has a layer shape extending along the first main surface 3.

[0170] 6 to 9, the semiconductor device 1A includes a main surface insulating film 45 that selectively covers the first main surface 3. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 45 preferably includes the same type of insulating material as the insulating film 17. In this embodiment, the main surface insulating film 45 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 45 includes a silicon oxide film made of an oxide of the chip 2.

[0171] The main surface insulating film 45 is connected to the insulating films 17 of the plurality of gate structures 15 in the active region 8 , and exposes the buried electrodes 18 of the plurality of gate structures 15 .

[0172] The main surface insulating film 45 covers the second semiconductor region 7, the first outer well region 42 ( FIG. 2 ), and the second outer well region 43 ( FIG. 2 ) in the peripheral region 9. In this embodiment, the main surface insulating film 45 is continuous with the first to fourth side surfaces 5A to 5D in the peripheral portion of the first main surface 3. The main surface insulating film 45 may be formed at a distance inward from the peripheral portion of the first main surface 3, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0173] The semiconductor device 1A includes an insulating interlayer film 47 that selectively covers the first main surface 3 with the main surface insulating film 45 sandwiched therebetween. The interlayer film 47 may also be referred to as an "insulating film," an "interlayer insulating film," an "intermediate insulating film," or the like. The interlayer film 47 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 47 preferably includes a silicon oxide film.

[0174] The interlayer film 47 covers the plurality of gate structures 15 (buried electrodes 18) on the active region 8 side. The interlayer film 47 covers the second semiconductor region 7, the first outer well region 42, and the second outer well region 43 on the peripheral region 9 side, with the main surface insulating film 45 sandwiched therebetween.

[0175] In this embodiment, the interlayer film 47 is continuous with the first to fourth side surfaces 5A to 5D at the peripheral portion of the first main surface 3. The interlayer film 47 may be formed at a distance inward from the peripheral portion of the first main surface 3, exposing the peripheral portion of the first main surface 3 (the second semiconductor region 7).

[0176] The interlayer film 47 may have a thickness of 0.5 μm or more and 3 μm or less. The thickness of the interlayer film 47 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0177] The semiconductor device 1A includes a plurality of gate openings (not shown) formed in the interlayer film 47 in the active region 8. The plurality of gate openings are formed in a one-to-many correspondence with a corresponding one of the gate structures 15. In this embodiment, the plurality of gate openings penetrate the interlayer film 47 and expose one end or the other end of each of the plurality of gate structures 15 (buried electrodes 18).

[0178] The plurality of gate openings may each have an opening end curved in an arc shape. The plurality of gate openings may be formed in a quadrangular shape, a rectangular shape (strip shape) extending in the first direction X, a rectangular shape (strip shape) extending in the second direction Y, a circular shape, or the like in a plan view. The plurality of gate openings may each have an opening end curved in an arc shape.

[0179] The semiconductor device 1A includes a plurality of source openings 49 formed in an interlayer film 47 in the active region 8. The plurality of source openings 49 are formed in portions of the interlayer film 47 that cover the active region 8. In this embodiment, the plurality of source openings 49 are formed in regions between adjacent gate structures 15, respectively, and expose the plurality of source regions 11 and the plurality of contact regions 27, respectively.

[0180] The plurality of source openings 49 penetrate the main surface insulating film 45 and the interlayer film 47, and expose the corresponding plurality of source regions 11 and the corresponding plurality of contact regions 27. Each of the plurality of source openings 49 may have an opening end that is curved in an arc shape.

[0181] The source openings 49 may be formed in a one-to-many correspondence with the regions between adjacent gate structures 15. In this case, the source openings 49 may be formed at intervals along the regions between the corresponding gate structures 15. In this case, the source openings 49 may be formed in a quadrangular, rectangular (strip-like), circular, or other shape in plan view.

[0182] The semiconductor device 1A includes at least one outer opening 50 ( FIG. 2 ) (one in this embodiment) formed in the interlayer film 47 in the peripheral region 9. The outer opening 50 penetrates the main surface insulating film 45 and the interlayer film 47. In this embodiment, the outer opening 50 is formed in a polygonal ring shape (specifically, a square ring shape) surrounding the inner portion (active region 8) of the first main surface 3 in plan view.

[0183] 6 to 9 , as described above, semiconductor device 1A includes source electrode 51 disposed on first main surface 3. Source electrode 51 extends from above interlayer film 47 into the plurality of source openings 49, and is electrically connected to the plurality of source regions 11 and the plurality of contact regions 27 within the plurality of source openings 49.

[0184] 8 and 9 , in this embodiment, the source electrode 51 has a layered structure including a lower electrode film 52 and a main electrode film 53, which are layered in this order from the chip 2 side. In this embodiment, the lower electrode film 52 has a layered structure including a first electrode film 52a and a second electrode film 52b. In this embodiment, the first electrode film includes a Ti film, and the second electrode film includes a TiN film. The lower electrode film 52 does not necessarily have to have a layered structure, and may have a single-layer structure consisting of either the first electrode film (Ti film) or the second electrode film (TiN film).

[0185] The first electrode film 52a has a thickness less than the thickness of the interlayer film 47. The thickness of the first electrode film 52a may be 10 nm or more and 100 nm or less. The thickness of the first electrode film 52a may have a value belonging to at least one of the ranges of 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.

[0186] The second electrode film 52b has a thickness less than that of the interlayer film 47. The thickness of the second electrode film 52b is preferably greater than that of the first electrode film 52a. The thickness of the second electrode film 52b may be 50 nm or more and 200 nm or less. The thickness of the second electrode film 52b may have a value belonging to at least one of the ranges of 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.

[0187] The lower electrode film 52 collectively covers the region of the interlayer film 47 where the multiple source openings 49 are formed, and extends into the multiple source openings 49 from above the interlayer film 47. The lower electrode film 52 has a portion that covers the insulating main surface of the interlayer film 47 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 49 in a film-like manner, and a portion that covers the first main surface 3 in the multiple source openings 49. The lower electrode film 52 is mechanically and electrically connected to the multiple source regions 11 and the multiple contact regions 27 in the source openings 49.

[0188] The main electrode film 53 contains a different conductive material from that of the lower electrode film 52. The main electrode film 53 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film. The main electrode film 53 has a thickness greater than the thickness (total thickness) of the lower electrode film 52. The thickness of the main electrode film 53 is preferably greater than the thickness of the interlayer film 47.

[0189] The thickness of the main electrode film 53 may be 0.5 μm or more and 5 μm or less. The thickness of the main electrode film 53 may have a value belonging to at least one of the ranges of 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0190] The main electrode film 53 directly covers the lower electrode film 52. The main electrode film 53 collectively covers the region of the interlayer film 47 where the plurality of source openings 49 are formed, and backfills the plurality of source openings 49.

[0191] The main electrode film 53 has a portion that covers the insulating main surface of the interlayer film 47 with the lower electrode film 52 sandwiched therebetween, a portion that covers the wall surfaces of the plurality of source openings 49 with the lower electrode film 52 sandwiched therebetween, and a portion that covers the first main surface 3 with the lower electrode film 52 sandwiched therebetween. The main electrode film 53 is electrically connected to the plurality of source regions 11 and the plurality of contact regions 27 via the lower electrode film 52 within the plurality of source openings 49.

[0192] 1 and 2, the source wiring 56 is drawn from the active region 8 to the peripheral region 9, enters the outer opening 50 (FIG. 2) from above the interlayer film 47, and is electrically connected to the first outer well region 42.

[0193] The source wiring 56 has an inner edge portion on the inner side (active region 8 side) of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the source wiring 56 is located within the active region 8 and faces one or more (multiple in this embodiment) gate structures 15 with the interlayer film 47 interposed therebetween.

[0194] Although a cross-sectional structure is omitted, the source wiring 56 has a laminated structure including a lower electrode film 52 and a main electrode film 53 laminated in this order from the chip 2 side, similar to the source electrode 51 .

[0195] Although the cross-sectional structure is omitted, the aforementioned gate electrode 57 (FIG. 1) and gate wiring 58 (FIG. 1) also have a laminated structure including a lower electrode film 52 and a main electrode film 53 laminated in this order from the chip 2 side, similar to the source electrode 51 and source wiring 56.

[0196] 10 is a schematic diagram showing a wafer 150 used in manufacturing the semiconductor device 1A. Referring to FIG. 10, the wafer 150 is a base material of the chip 2 and includes a SiC single crystal. The wafer 150 is formed in a flat disk shape. Of course, the wafer 150 may also be formed in a flat rectangular parallelepiped shape. The wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0197] The second wafer main surface 152 corresponds to the second main surface 4 of the chip 2. The first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of a 4H—SiC single crystal. The first wafer main surface 151 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 152 is formed by the carbon surface of the SiC single crystal. The wafer 150 (the first wafer main surface 151 and the second wafer main surface 152) has a predetermined off-direction and off-angle. The first wafer main surface 151 and the second wafer main surface 152 may be formed by the c-plane of a 2H—SiC single crystal or the c-plane of a 6H—SiC single crystal.

[0198] The wafer 150 has a mark 154 on the wafer side surface 153 that indicates the crystal orientation of the SiC single crystal. The mark 154 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 151 in a plan view.

[0199] The mark 154 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 154 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0200] The wafer 150 includes a first semiconductor region 6 in a region (surface layer portion) on the first wafer main surface 151 side. The first semiconductor region 6 has a layer shape extending along the first wafer main surface 151. In this embodiment, the first semiconductor region 6 is made of the wafer main body (specifically, a SiC wafer).

[0201] The wafer 150 includes a second semiconductor region 7 in a region (surface layer) on the second wafer main surface 152 side. The second semiconductor region 7 has a layered shape extending along the second main surface 4 and is electrically connected to the first semiconductor region 6. In this embodiment, the second semiconductor region 7 is made of an epitaxial layer (specifically, a SiC epitaxial layer). That is, in this embodiment, the wafer 150 is made of an epitaxial wafer (a so-called epi-wafer) having a layered structure including a wafer main body and an epitaxial layer. In this embodiment, the second semiconductor region 7 includes a first layer 7a made of a hexagonal SiC single crystal. In this embodiment, the hexagonal SiC single crystal includes a 4H—SiC single crystal. The hexagonal SiC single crystal may include a 2H—SiC single crystal or a 6H—SiC single crystal.

[0202] For example, a plurality of device regions 155 and a plurality of cutting lines 156 are set on the wafer 150 by alignment marks or the like. Each device region 155 corresponds to a semiconductor device 1A. Each of the plurality of device regions 155 is set to have a quadrangular shape in a plan view.

[0203] In this embodiment, the multiple device regions 155 are set in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 155 are set at intervals inward from the periphery of the first wafer main surface 151 in a plan view. The multiple cutting lines 156 are set in a grid pattern extending along the first direction X and the second direction Y to partition the multiple device regions 155.

[0204] 11A to 11P are cross-sectional views showing a manufacturing method of the semiconductor device 1A. Each of the cross-sections shows a portion of the active region 8 in one device region 155. In each of the left figures of the drawings in FIG. 11A to 11P, the cross-section corresponds to the cross-section in FIG. 8, and the right figures correspond to the cross-section in FIG. 9.

[0205] Referring to FIG. 11A , first, the aforementioned wafer 150 is prepared. A first layer 7a is formed on a first wafer main surface 151 of the wafer 150 as part of the second semiconductor region 7. The first layer 7a is made of a SiC epitaxial layer having a 4H—SiC crystal structure. Next, referring to FIG. 11B , a second layer 7b is formed on the first wafer main surface 151, stacked on the first layer 7a. The second layer 7b is made of a SiC epitaxial layer having a 3H—SiC crystal structure. The step of forming the second layer 7b on the first layer 7a involves epitaxially growing SiC from the first wafer main surface 151.

[0206] This forms the second semiconductor region 7 having a stacked structure of the first layer 7a and the second layer 7b (stacked structure forming step). The top surface of the second layer 7b becomes the first main surface 3. The first main surface 3 may be formed by the (111) plane of the SiC single crystal. The first wafer main surface 151 becomes the interface 7c between the first layer 7a and the second layer 7b.

[0207] The formation of the second layer 7b (the formation of the SiC epitaxial layer of 3C-SiC) may be performed simultaneously with the formation of the first layer 7a (the formation of the SiC epitaxial layer of 4H-SiC).

[0208] Next, referring to FIG. 11C , a medium-concentration base region 161 is formed in the surface layer portion of the first main surface 3 in the wafer 150 (second semiconductor region 7 ( FIG. 11B )). The medium-concentration base region 161 is the base of the medium-concentration region 72. In the process of forming the medium-concentration base region 161, n-type impurities are introduced into the second semiconductor region 7 by ion implantation. The implantation of the n-type impurities forms the medium-concentration base region 161, which extends in a layered manner in the horizontal direction along the first main surface 3.

[0209] The ion implantation method may be either or both of a channeling ion implantation method and a random ion implantation method. In the channeling ion implantation process, n-type impurities are introduced into the second semiconductor region 7 ( FIG. 11B ) along an axial channel of the second semiconductor region 7. The axial channel is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the second semiconductor region 7, and is surrounded by atomic rows that constitute a crystal axis that extends in the stacking direction (crystal growth direction).

[0210] In the channeling ion implantation process, the n-type impurity is implanted deep into the second semiconductor region 7 while repeatedly undergoing small-angle scattering due to the channeling effect. That is, in the case of the channeling implantation method, the probability of the n-type impurity colliding with the atomic rows of the SiC single crystal is reduced. Therefore, the channeling ion implantation process is effective when introducing the impurity (n-type impurity) into a relatively deep region.

[0211] On the other hand, in the random ion implantation process, n-type impurities are introduced into the second semiconductor region 7 in random directions. The random direction is a direction other than the axial channel of the second semiconductor region 7 (i.e., a direction intersecting the axial channel). For example, the random direction is the vertical direction Z. In the random ion implantation process, the probability of collision of n-type impurities with atomic rows of the SiC single crystal is high, so an impurity region (n-type impurity region) is formed in a relatively shallow region. Therefore, the random ion implantation process is effective when introducing impurities (n-type impurities) into a relatively shallow region.

[0212] The medium-concentration base region 161 may be formed in the second semiconductor region 7 ( FIG. 11B ) at a distance from the first main surface 3 toward the bottom of the second semiconductor region 7. Of course, the medium-concentration base region 161 may be exposed from the first main surface 3. Considering the offset of p-type impurities and n-type impurities in later processes, it is preferable that the medium-concentration base region 161 be formed at a distance from the first main surface 3.

[0213] The base medium-concentration region 161 is formed to straddle the first layer 7 a and the second layer 7 b from top to bottom. By forming the base medium-concentration region 161, which is the base of the medium-concentration region 72, the second semiconductor region 7, excluding the surface layer portion, is divided into the base region 71 and the medium-concentration region 72.

[0214] The base medium-concentration region 161 formed in the first layer 7a becomes the first medium-concentration region 72a. The base medium-concentration region 161 formed in the second layer 7b becomes the second medium-concentration region 72b. The first medium-concentration region 72a and the second medium-concentration region 72b are included in the medium-concentration region 72.

[0215] Next, referring to FIG. 11D , a base body region 162 is formed in the surface layer portion of the first main surface 3 in the wafer 150 (second semiconductor region 7 ( FIG. 11B )). The base body region 162 is the base of the body region 10. In the process of forming the base body region 162, p-type impurities are introduced into the second semiconductor region 7 by ion implantation.

[0216] The ion implantation method may be either one or both of channeling ion implantation and random ion implantation. Since the p-type impurity is introduced into a region shallower than the medium concentration base region 161, the ion implantation method is preferably random ion implantation. This forms the base body region 162 extending in layers horizontally along the first main surface 3.

[0217] 11E, a base source region 163 is formed in a surface layer portion of the first main surface 3. In this step, a first mask 164 having a predetermined layout is first placed on the first main surface 3. The first mask 164 may be an inorganic mask (e.g., a silicon oxide film) or an organic mask (resist mask). The first mask 164 exposes regions where a plurality of source regions 11 (FIGS. 8 and 9) are to be formed, and covers the other regions.

[0218] Next, n-type impurities are introduced into the second semiconductor region 7 ( FIG. 11B ) by ion implantation via the first mask 164. As a result, a base source region 163 is formed in the surface layer of the first main surface 3 within the wafer 150 (base body region 162). The base source region 163 is the base of the multiple source regions 11. In the process of forming the base source region 163, n-type impurities are introduced into the base body region 162 by ion implantation. The first mask 164 is removed after this process.

[0219] The ion implantation method may be either or both of channeling ion implantation and random ion implantation. Since the n-type impurity is introduced into a region shallower than the base body region 162, the ion implantation method is preferably random ion implantation. This forms the base source region 163 extending horizontally in a layered manner along the first main surface 3.

[0220] The order of the steps of forming the base medium concentration region 161, the body region 10, and the base source region 163 is arbitrary and may be interchanged as appropriate.

[0221] 11F, a plurality of mesas 21 and a plurality of trenches 16 are formed on the first main surface 3 (trench formation process). In this process, a second mask 165 having a predetermined layout is first formed on the first main surface 3. The second mask 165 may be an inorganic mask (e.g., a silicon oxide film) or an organic mask (resist mask). The second mask 165 exposes regions where the plurality of trenches 16 are to be formed and covers other regions.

[0222] Next, unnecessary portions of the wafer 150 are removed by etching through the second mask 165. The etching may be wet etching or dry etching, or both. As a result, a plurality of mesas 21 and a plurality of trenches 16 are formed. Furthermore, the base body region 162 and the base source region 163 are separated by the plurality of trenches 16, and the body region 10 and the source region 11 are formed.

[0223] In this step, the plurality of trenches 16 are formed substantially perpendicular to the first main surface 3. That is, the side surfaces 19 of the plurality of trenches 16 have an inclination angle of 87° or more and 93° or less. The side surfaces 19 of the plurality of trenches 16 are also formed flat along the horizontal direction. The trenches 16 having flat bottom surfaces 20 improve the accuracy of introducing impurities through the bottom surfaces 20. The second mask 165 is removed after this step.

[0224] 11G and 11H, a plurality of electric field relaxation layers 25 (FIG. 11H) are formed in regions along the bottom surfaces 20 of the plurality of trenches 16. In this step, ion implantation is performed using a first resist mask (resist mask) 166 (FIG. 11H) having a predetermined pattern. The first resist mask 166 has, for example, first openings 167 (FIG. 11H) that expose regions where the electric field relaxation layers 25 are to be formed. The formation of the first openings 167 will now be described.

[0225] 11G , when forming first opening 167, first resist (resist) 168 is formed on first main surface 3. First resist 168 is formed by coating using a spin coater, a spray coater, or the like. First resist 168 is, for example, a positive resist.

[0226] Thereafter, the first resist 168 is selectively exposed by photolithography through a first photomask (photomask) 169 (exposure step). The first resist 168 is then developed to form a first opening 167 shown in FIG. 11H. If the first resist 168 is a positive resist, the exposed portion of the first resist 168 is removed. This forms a first resist mask 166 having the first opening 167.

[0227] The first resist 168 may be exposed by a short-wavelength laser irradiation method using a first photomask 169. The short-wavelength laser may include an ultraviolet (UV) laser having a wavelength of 150 nm or more and 400 nm or less. The ultraviolet laser may be an ArF excimer laser, a KrF excimer laser, a XeCl excimer laser, a XeF excimer laser, or an F ２ The short wavelength laser may include at least one of an excimer laser and an extreme ultraviolet (EUV) laser having a wavelength of 13 nm or more and 14 nm or less.

[0228] By using the short wavelength laser irradiation method with the first photomask 169, the adhesion of the first resist mask 166 to the first main surface 3 can be appropriately adjusted.

[0229] After the first resist mask 166 is formed, p-type impurities are then introduced into the trenches 16 by ion implantation through the first resist mask 166. The ion implantation may be either or both of channeling ion implantation and random ion implantation.

[0230] The ion implantation is preferably a random ion implantation, and the p-type impurity is introduced into the wafer 150 at an implantation angle that is approximately perpendicular to the first main surface 3. The ion implantation is preferably a perpendicular ion implantation, not an oblique ion implantation. This process prevents the introduction of the p-type impurity into the wafer 150 through the two side surfaces 19 of the trench 16.

[0231] In the random ion implantation step, p-type impurities may be implanted in a single step at a target depth position in the medium concentration region 72 (first medium concentration region 72 a and second medium concentration region 72 b). The p-type impurities may be implanted in multiple steps at different target depth positions in the medium concentration region 72 with different implantation energies. In either the single-step implantation step or the multistep implantation step, the p-type impurities may include a step of implanting the p-type impurities multiple times at the same target depth position in the medium concentration region 72.

[0232] The number of injection stages (number of target depth positions) of p-type impurities in the multistage injection process is adjusted appropriately depending on the thickness of the electric field relaxation layer 25. The number of injection stages may be 2, 3, 4, 5, 6, 7, 8, 9, or 10. The number of injection stages is preferably 2 or more and 5 or less. In the case of the multistage injection process, p-type impurities are injected into different target depth positions so that the injection sites of the p-type impurities overlap.

[0233] In the multistage implantation process, the dose (impurity concentration) of the p-type impurity with respect to the medium concentration region 72 may be adjusted to increase as the implantation location becomes deeper. Also, in the medium concentration region 72, the implantation energy of the p-type impurity with respect to the medium concentration region 72 may be adjusted to increase as the implantation location becomes deeper.

[0234] As a result, a plurality of electric field relaxation layers 25 having a plurality of bulging portions 25a that gradually increase and decrease in thickness in a stepwise manner are formed in regions along the bottom surfaces 20 of the plurality of trenches 16. The plurality of electric field relaxation layers 25 are all formed at the same depth position.

[0235] The plurality of electric field relaxation layers 25 are formed so as to vertically straddle the second intermediate concentration region 72 b and the first intermediate concentration region 72 a. Because the second intermediate concentration region 72 b and the first intermediate concentration region 72 a are included in the second layer 7 b and the first layer 7 a, respectively, the plurality of electric field relaxation layers 25 are all formed so as to vertically straddle the second layer 7 b and the first layer 7 a. In other words, the plurality of electric field relaxation layers 25 straddle the boundary surface 7 c in the vertical direction Z.

[0236] Furthermore, the second intermediate concentration region 72b is divided into a plurality of regions by the plurality of electric field buffer layers 25, thereby forming a plurality of second intermediate concentration regions 72b. The first resist mask 166 is then removed.

[0237] 11I and 11J, a plurality of high-concentration regions 28 (FIG. 11J) are formed in a predetermined number of electric field relaxation layers 25 in regions along the bottom surfaces 20 of the plurality of trenches 16. In this step, ion implantation is performed using a second resist mask (resist mask) 171 (FIG. 11J) having a predetermined pattern. The second resist mask 171 has, for example, second openings 172 (FIG. 11J) that expose regions where the high-concentration regions 28 are to be formed. The formation of the second openings 172 will now be described.

[0238] 11I, when forming the second opening 172, first, a second resist 173 is formed on the first main surface 3. Then, the second resist (resist) 173 is selectively exposed to light by photolithography through a second photomask (photomask) 174 (exposure step). The second resist 173 is formed by coating using a spin coater, a spray coater, or the like. The second resist 173 is, for example, a positive resist.

[0239] 11J is formed by developing the second resist 173. If the second resist 173 is a positive resist, the exposed portion of the second resist 173 is removed. This forms a second resist mask 171 having the second opening 172.

[0240] The second resist 173 may be exposed by a short-wavelength laser irradiation method using the second photomask 174. The short-wavelength laser may include an ultraviolet (UV) laser having a wavelength of 150 nm or more and 400 nm or less. The ultraviolet laser may be an ArF excimer laser, a KrF excimer laser, a XeCl excimer laser, a XeF excimer laser, or an F ２ The short wavelength laser may include at least one of an excimer laser and an extreme ultraviolet (EUV) laser having a wavelength of 13 nm or more and 14 nm or less.

[0241] After the second resist mask 171 is formed, p-type impurities are then introduced into the trenches 16 by ion implantation via the second resist mask 171. The ion implantation may be either or both of channeling ion implantation and random ion implantation.

[0242] The ion implantation is preferably a random ion implantation, and the p-type impurity is introduced into the wafer 150 at an implantation angle that is approximately perpendicular to the first main surface 3. The ion implantation is preferably a perpendicular ion implantation, not an oblique ion implantation. This process suppresses the introduction of the p-type impurity into the second semiconductor region 7 through the two side surfaces 19 of the trench 16.

[0243] As a result, a plurality of high concentration regions 28 are formed in each of the plurality of electric field relaxation layers 25. The second resist mask 171 is then removed.

[0244] 11K, a plurality of contact regions 27 are formed in the wafer 150 (second semiconductor region 7) in regions that are aligned with the plurality of trenches 16. In this step, first, a third mask (not shown) having a predetermined layout (a layout that selectively exposes a portion of the first main surface 3 and a portion of the plurality of trenches 16) is formed on the first main surface 3.

[0245] Next, p-type impurities are introduced into the wafer 150 through the first main surface 3 and the plurality of trenches 16 by ion implantation using a third mask (not shown). The ion implantation may be either or both of channeling ion implantation and random ion implantation. In this embodiment, the ion implantation is random ion implantation. As a result, contact regions 27 are formed in the second semiconductor regions 7. The third mask (not shown) is then removed.

[0246] 11K, a base insulating film 175 is formed on the first main surface 3. The base insulating film 175 serves as a base for the plurality of insulating films 17 and the main surface insulating film 45. The base insulating film 175 is formed in the form of a film along the first main surface 3 and the wall surfaces of the plurality of trenches 16. The base insulating film 175 may be formed by either or both of a CVD method and an oxidation method (for example, a thermal oxidation method).

[0247] 11L, a first base electrode film 176 is formed on the base insulating film 175. The first base electrode film 176 serves as a base for the plurality of buried electrodes 18. The first base electrode film 176 has a portion that covers the first main surface 3 with the base insulating film 175 interposed therebetween, and a portion that is buried in the plurality of trenches 16 with the base insulating film 175 interposed therebetween. The base insulating film 175 may be formed by a CVD method.

[0248] 11M, unnecessary portions of the first base electrode film 176 are removed by etching until the base insulating film 175 is exposed. The etching may be either wet etching or dry etching, or both. This results in the formation of a plurality of buried electrodes 18. Furthermore, a plurality of gate structures 15 (first gate structures 15A and second gate structures 15B) are formed.

[0249] 11N, an interlayer film 47 is formed on the first main surface 3. The interlayer film 47 collectively covers the first main surface 3 and the plurality of gate structures 15. The interlayer film 47 may be formed by a CVD method.

[0250] 11O , a fourth mask 177 having a predetermined layout is formed on the interlayer film 47. The fourth mask 177 may be an organic mask (resist mask). The fourth mask 177 exposes regions where a plurality of source openings 49 and a plurality of gate openings (not shown) are to be formed, and covers the remaining regions. Next, unnecessary portions of the interlayer film 47 are removed by etching via the fourth mask 177. The etching may be either or both of wet etching and dry etching.

[0251] Next, unnecessary portions of the base insulating film 175 are removed by etching via the fourth mask 177. The etching method may be either wet etching or dry etching, or both. The unnecessary portions of the base insulating film 175 may be removed simultaneously with the interlayer film 47. As a result, a plurality of source openings 49 and a plurality of gate openings (not shown) are formed in the interlayer film 47. The base insulating film 175 is also divided into the insulating film 17 and the main surface insulating film 45. The fourth mask 177 is then removed.

[0252] 11P, a second base electrode film 178 is formed on the interlayer film 47. The second base electrode film 178 is a base for the source electrode 51, the gate electrode 57, and the gate wiring 58. The second base electrode film 178 has a layered structure including the lower electrode film 52 and the main electrode film 53. The lower electrode film 52 has a layered structure including the first electrode film 52a and the second electrode film 52b.

[0253] The first electrode film 52a may be formed by either or both of a sputtering method and a vapor deposition method. The first electrode film 52a is formed in a film shape along the first main surface 3, the interlayer film 47, the wall surfaces of the plurality of source openings 49, and the wall surfaces of the plurality of gate openings (not shown). The second electrode film 52b may be formed by either or both of a sputtering method and a vapor deposition method. The second electrode film 52b is stacked on the first electrode film 52a and is formed in a film shape along the first main surface 3, the interlayer film 47, the wall surfaces of the plurality of source openings 49, and the wall surfaces of the plurality of gate openings (not shown).

[0254] The main electrode film 53 is formed on the lower electrode film 52. The main electrode film 53 may be formed by either or both of a sputtering method and a vapor deposition method. The main electrode film 53 is laminated on the lower electrode film 52 and is formed in a film shape along the first main surface 3, the interlayer film 47, the wall surfaces of the plurality of source openings 49, and the wall surfaces of the plurality of gate openings (not shown).

[0255] Next, the second base electrode film 178 is divided into the source electrode 51, the gate electrode 57, and the gate wiring 58. In this process, unnecessary portions of the main electrode film 53 (portions other than the regions where the source electrode 51, the gate electrode 57, and the gate wiring 58 are to be formed) are removed by etching using a mask (not shown) having a predetermined layout. The etching method may be either or both of wet etching and dry etching. The mask (not shown) is removed after the etching process of the main electrode film 53.

[0256] Next, unnecessary portions of the lower electrode film 52 are removed by etching using the main electrode film 53 as a mask. The unnecessary portions of the lower electrode film 52 are removed until the interlayer film 47 is exposed. The step of removing the lower electrode film 52 includes a step of removing the second electrode film 52b by etching and a step of removing the first electrode film 52a by etching. The etching method may be either or both of wet etching and dry etching.

[0257] This forms the source electrode 51, the gate electrode 57 (FIG. 1), and the gate wiring 58 (FIG. 1). Of course, unnecessary portions of the lower electrode film 52 may be removed by etching using a mask (not shown) in the etching step of the main electrode film 53.

[0258] Thereafter, a drain pad electrode 140 (FIG. 2) is formed on the second wafer main surface 152. The drain pad electrode 140 may be formed by sputtering or vapor deposition. Then, the wafer 150 is cut along the cutting lines 156 to cut out a plurality of semiconductor devices 1A. Through the steps including those described above, the semiconductor device 1A is manufactured.

[0259] 11G and 11I, a short wavelength laser (e.g., an ultraviolet (UV) laser) is irradiated. In order to form a device structure (transistor structure Tr) with high precision, it is necessary to irradiate the resists 168 and 173 with the short wavelength laser (e.g., an ultraviolet laser) at desired positions with high precision in the exposure process.

[0260] If the mesa portion 21 is disposed in the first layer 7a, which has a relatively low absorption coefficient for the short-wavelength laser, there is a risk that the short-wavelength laser irradiated toward the first main surface 3 will pass through the mesa portion 21 from the trench 16 and reach the resists 168, 173 in the adjacent trenches 16. In other words, there is a risk that unintended areas of the positive resists 168, 173 will be exposed and removed in the subsequent development process.

[0261] 11I, there is a risk that the second resist 173 in the adjacent trench 16 may be irradiated with a short-wavelength laser, even though the adjacent trench 16 is covered with the second photomask 174. Then, in the development process, there is a risk that part or all of the second resist 173 in the adjacent trench 16 may be removed. Then, there is a risk that the pattern of the second opening 172 in the second resist mask 171 may differ from the intended pattern (collapse may occur). In this case, there is a risk that the subsequent ion implantation cannot be performed with high precision, and as a result, there is a risk that the device structure (transistor structure Tr) cannot be formed with high precision.

[0262] In contrast, with this method, the mesa portion 21 (as a whole) is disposed in the second layer 7b, which has a relatively high absorption coefficient for the short-wavelength laser. Therefore, in the exposure process shown in FIGS. 11G and 11I (particularly FIG. 11I), the short-wavelength laser does not pass through the mesa portion 21 from within the trench 16 (see the dashed line in FIG. 11I). This suppresses or prevents the short-wavelength laser from irradiating the second resist 173 in the adjacent trench 16. This allows the second opening 172 in the second resist mask 171 to be formed with high precision. Therefore, the device structure (transistor structure Tr) can be formed with high precision.

[0263] Furthermore, the first layer 7a included in the second semiconductor region 7 (drift region) is made of 4H—SiC (hexagonal SiC single crystal, first semiconductor material) which has a high dielectric breakdown field strength, thereby achieving a reduction in on-resistance.

[0264] 12 and 13 are cross-sectional views showing a main part of a semiconductor device 1B according to a second embodiment of the present disclosure. Fig. 12 shows a cross section taken at the same position as Fig. 8. Fig. 13 shows a cross section taken at the same position as Fig. 9. In Fig. 12 and 13, the same reference numerals are used to designate components equivalent to those of the semiconductor device 1A according to the first embodiment, and detailed descriptions thereof will be omitted.

[0265] 12 and 13 , semiconductor device 1B has a configuration in which the stacked structure of second semiconductor region 7 in semiconductor device 1A is modified. In semiconductor device 1B, second semiconductor region 7 includes a stacked structure of first layer 7p on the second main surface 4 side and second layer 7q on the first main surface 3 side, instead of the stacked structure of first layer 7a and second layer 7b. That is, the semiconductor region includes a stacked structure of first layer 7p and second layer 7q. In this configuration, first layer 7p and second layer 7q have a common crystal structure. First layer 7p and second layer 7q have different impurity concentrations.

[0266] The first layer 7p extends in a layered form along the first main surface 3 at a position away from the first main surface 3 on the second main surface 4 side. The first layer 7p is formed over the entire surface portion of the second semiconductor region 7 on the second main surface 4 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The first layer 7p is the boundary surface of the second semiconductor region 7 with the first semiconductor region 6. The first layer 7p has the same thickness (first thickness T11 ( FIG. 4 )) as the first layer 7a.

[0267] The second layer 7q has a layer shape extending along the first main surface 3. The upper surface of the second layer 7q is the first main surface 3. The second layer 7q is formed over the entire surface portion on the first main surface 3 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The second layer 7q has the same thickness as the first layer 7a (second thickness T12 (FIG. 4); T12<T11). The second layer 7q is exposed from the first main surface 3.

[0268] The second semiconductor region 7 of the semiconductor device 1B includes a base region 71, a medium concentration region 72, and a high concentration region 73. The base region 71 is included in the first layer 7p, which is a low concentration region. Details of the base region 71 have already been described in the first embodiment, so description thereof will be omitted.

[0269] As described above, the thickness of the medium concentration region 72 may be 0.1 μm or more and 0.5 μm or less. The thickness of the medium concentration region 72 is preferably 0.15 μm or more and 0.4 μm or less. The n-type impurity concentration of the medium concentration region 72 is higher than the n-type impurity concentration of the base region 71. The medium concentration region 72 has an n-type impurity concentration of 1×10 １７ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the medium-concentration region 72 may have a peak value of the following n-type impurity concentration. The n-type impurity concentration of the medium-concentration region 72 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the medium-concentration region 72 may have a concentration gradient that gradually increases and / or gradually decreases in the thickness direction (crystal growth direction) of the chip 2. The medium-concentration region 72 is included in the first layer 7p.

[0270] The n-type impurity concentration of the high concentration region 73 is preferably higher than the n-type impurity concentration of the medium concentration region 72. The high concentration region 73 has a concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration of the high-concentration region 73 may have a peak value of the following n-type impurity concentration. The n-type impurity concentration of the high-concentration region 73 may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the high-concentration region 73 may have a concentration gradient that gradually increases and / or gradually decreases in the thickness direction (crystal growth direction) of the chip 2. The high-concentration region 73 is included in the second layer 7q.

[0271] In this embodiment, the n-type impurity concentrations of the medium concentration region 72 and the high concentration region 73 are adjusted by nitrogen. The medium concentration region 72 and the high concentration region 73 may have n-type impurity concentrations adjusted by at least one pentavalent element. For example, the n-type impurity concentrations of the medium concentration region 72 and the high concentration region 73 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0272] The semiconductor device 1B includes a p-type body region 90 formed in a surface layer portion of the first main surface 3. In the semiconductor device 1B, the body region 90 is used in place of the body region 10 of the semiconductor device 1A. The body region 90 may also be referred to as an "impurity region," a "channel region," or the like. A source potential may be applied to the body region 90. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be a ground potential. The body region 90 has a p-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7 (e.g., the base region 71).

[0273] In this embodiment, the body region 90 has a p-type impurity concentration higher than the n-type impurity concentration of the intermediate concentration region 72. The body region 90 has a p-type impurity concentration of, for example, 1×10 １８ cm －３ 1x10 or more １９ cm －３ The p-type impurity concentration may have the following peak value: The body region 90 is included in the second layer 7q, which is a high-concentration region.

[0274] The plurality of contact regions 27 have a p-type impurity concentration higher than the n-type impurity concentration of the base region 71. The contact region 27 may have a p-type impurity concentration higher than the n-type impurity concentration of a medium concentration region 72 described below. The p-type impurity concentration of the contact region 27 is higher than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the contact region 27 is higher than the p-type impurity concentration of the electric field relaxation layer 25.

[0275] The p-type impurity concentration of one contact region 27 is 1×10 １８ cm －３ 1x10 or more ２１ cm－３ The p-type impurity concentration of the contact region 27 may be as follows: The p-type impurity concentration of the contact region 27 is preferably adjusted by at least one trivalent element. The trivalent element of the contact region 27 may be at least one of boron, aluminum, gallium, and indium. Other details of the contact region 27 have already been described in the first embodiment, and therefore will not be described here. The multiple contact regions 27 are included in the second layer 7q, which is a high-concentration region.

[0276] In this embodiment, the second layer 7q has a relatively high n-type impurity concentration and a relatively high p-type impurity concentration. The n-type impurity concentration in the second layer 7q is higher than the p-type impurity concentration and the n-type impurity concentration in the first layer 7p. The p-type impurity concentration in the second layer 7q is higher than the p-type impurity concentration and the n-type impurity concentration in the first layer 7p. In other words, the second layer 7q has a higher impurity concentration than the first layer 7p. The second layer 7q is a high-absorption layer having a relatively high absorption coefficient for laser light, and therefore has a relatively high absorption coefficient for laser light.

[0277] The first layer 7p and the second layer 7q have different absorption coefficients (light absorption coefficients) for the laser light used in the exposure process (FIGS. 14G, 14I, etc.). The first layer 7p is a low-concentration layer with a relatively low impurity concentration, and therefore has a relatively low absorption coefficient for the laser light. That is, the second layer 7q has a higher absorption coefficient for the laser light than the first layer 7p.

[0278] The laser light includes a short wavelength laser. The short wavelength laser may include an ultraviolet (UV) laser having a wavelength of 150 nm or more and 400 nm or less. The ultraviolet laser includes an ArF excimer laser, a KrF excimer laser, a XeCl excimer laser, a XeF excimer laser, and an F ２ The short wavelength laser may include at least one of an excimer laser and an extreme ultraviolet (EUV) laser having a wavelength of 13 nm or more and 14 nm or less.

[0279] The first layer 7p is made of a hexagonal SiC single crystal (first semiconductor material). The hexagonal SiC single crystal has a plurality of polytypes, including 2H—SiC single crystal, 4H—SiC single crystal, and 6H—SiC single crystal. In this embodiment, the hexagonal SiC single crystal includes a 4H—SiC single crystal. The hexagonal SiC single crystal may also include other polytypes.

[0280] In this embodiment, the second layer 7q has the same crystal structure as the first layer 7p. The second layer 7q is made of a hexagonal SiC single crystal (first semiconductor material). When the first layer 7p contains 4H—SiC single crystal, the second layer 7q also contains 4H—SiC single crystal.

[0281] The electric field relaxation layer 25 straddles the first layer 7p and the second layer 7q. That is, the electric field relaxation layer 25 straddles the boundary surface 7r in the vertical direction Z. As shown in Figures 12 and 13, the bulging portion 25a may straddle the first layer 7p and the second layer 7q. Although not shown, the bulging portion 25a may be disposed only in the first layer 7p, or the bulging portion 25a may be disposed only in the second layer 7q.

[0282] A second distance L2 (FIGS. 12 and 13) between the interface 7r and the bottom 25b of the electric field buffer layer 25 is longer than a first distance L1 (FIGS. 12 and 13) between the interface 7r and the bottom surface 20 of the trench 16. In other words, the first distance L1 is shorter than the second distance L2 (L1<L2).

[0283] The entire side surface 19 of the trench 16 is disposed on the second layer 7b. The bottom surface 20 of the trench 16 is disposed on the second layer 7b.

[0284] 14A to 14L are cross-sectional views showing a manufacturing method of semiconductor device 1B. 14A to 14L show a cross section of a portion of active region 8 in one device region 155. In 14A to 14L, the left drawings correspond to the cross section in FIG. 12, and the right drawings correspond to the cross section in FIG. 13.

[0285] 14A , first, the aforementioned wafer 150 is prepared. Next, referring to FIG. 14B , a base medium concentration region 181 is formed in the wafer 150 (second semiconductor region 7) in a surface layer portion of the first wafer main surface 151. In this embodiment, the first wafer main surface 151 corresponds to the first main surface 3. The base medium concentration region 181 is the base of the medium concentration region 72.

[0286] In the process of forming the base medium concentration region 181, the base medium concentration region 181 is formed in a region away from the first main surface 3 (first wafer main surface 151) toward the second main surface 4. The base medium concentration region 181 extends in a layered manner in the horizontal direction along the first main surface 3. In the process of forming the base medium concentration region 181, n-type impurities are introduced into the second semiconductor region 7 by ion implantation.

[0287] The ion implantation method may be either one or both of a channeling ion implantation method and a random ion implantation method. Details of the channeling ion implantation method and the random ion implantation method have already been described in the first embodiment, so a description thereof will be omitted.

[0288] In the process of forming the base medium concentration region 181, since the base medium concentration region 181 is formed at a distance from the first wafer main surface 151 (first main surface 3) toward the second main surface 4, it is preferable to adopt a channeling ion implantation process.

[0289] 14C , a high-concentration base region 182 is formed in the surface layer portion of the first main surface 3 in the wafer 150 (second semiconductor region 7 ( FIG. 14B )). The high-concentration base region 182 is the base of the high-concentration region 73.

[0290] In the process of forming the high-concentration base region 182, the high-concentration base region 182 is formed in a region directly above the formation position of the medium-concentration base region 181 and away from the first main surface 3 toward the second main surface 4. In the process of forming the high-concentration base region 182, n-type impurities are introduced into the second semiconductor region 7 by ion implantation. In the process of forming the high-concentration base region 182, the high-concentration base region 182 is formed, extending in a layered manner in the horizontal direction along the first main surface 3.

[0291] The ion implantation method is as described above. In the process of forming the medium base concentration region 181, since the medium base concentration region 181 is formed at a distance from the first wafer main surface 151 (first main surface 3) toward the second main surface 4, a channeling ion implantation process is preferably employed as the ion implantation method. The high concentration base region 182 is formed so as to be stacked on the medium base concentration region 181.

[0292] The high-concentration base region 182 may be formed in the second semiconductor region 7 at a distance from the first main surface 3 toward the bottom of the second semiconductor region 7. Of course, the high-concentration base region 182 may be exposed from the first main surface 3. Considering the offset of p-type impurities and n-type impurities in later processes, it is preferable that the high-concentration base region 182 be formed at a distance from the first main surface 3.

[0293] By forming the base medium concentration region 181, which is the base of the medium concentration region 72, and the base high concentration region 182, which is the base of the high concentration region 73, the portion of the second semiconductor region 7 excluding the surface layer portion is partitioned into the base region 71, the medium concentration region 72, and the high concentration region 73. In other words, these steps partition the second semiconductor region 7 into a first layer 7p and a second layer 7q.

[0294] Next, referring to FIG. 14D , a base body region 183 is formed in the surface layer of the high-concentration base region 182 in the wafer 150 (second semiconductor region 7 ( FIG. 14B )). The base body region 183 is the base of the body region 90. The base body region 183 is a region having a higher p-type impurity concentration than the base body region 162 according to the first embodiment.

[0295] In the process of forming the base body region 183, p-type impurities are introduced into the second semiconductor region 7 by ion implantation. The ion implantation may be either or both of channeling ion implantation and random ion implantation. This forms the base body region 183 extending in a layered manner in the horizontal direction along the first main surface 3.

[0296] In the process of forming the base body region 183, in a non-forming region (right diagram in FIG. 14D ) where the source region 11 ( FIG. 12 ) is not formed in a plan view, the base body region 183 is formed to reach the first main surface 3. Therefore, after the process of forming the base body region 183, the base body region 183 is exposed to the first main surface 3.

[0297] On the other hand, in the step of forming the base body region 183, in a non-formation region (left diagram in FIG. 14D ) where the source region 11 is not formed in a plan view, the base body region 183 is formed to a depth that does not reach the first main surface 3. Therefore, in this non-formation region, after the step of forming the base body region 183, the surface of the base body region 183 is at a depth position spaced apart from the first main surface 3.

[0298] Next, referring to FIG. 14E , a base source region 184 is formed in the surface layer portion of the first main surface 3. In this step, first, a first mask 164 having a predetermined layout is placed on the first main surface 3. Next, n-type impurities are introduced into the second semiconductor region 7 ( FIG. 14B ) by ion implantation via the first mask 164. As a result, the base source region 184 is formed in the surface layer portion of the first main surface 3 within the wafer 150. The base source region 184 is the base of the multiple source regions 11. In the step of forming the base source region 184, n-type impurities are introduced into the surface layer portion of the first main surface 3 by ion implantation. The first mask 164 is removed after this step.

[0299] The ion implantation method may be either or both of channeling ion implantation and random ion implantation. Since the n-type impurity is introduced into the surface layer portion of the first main surface 3, the ion implantation method is preferably random ion implantation. This forms the base-source region 184 extending in a layered manner in the horizontal direction along the first main surface 3.

[0300] The order of the steps of forming the base medium concentration region 181, the base high concentration region 182, the base body region 183, and the base source region 184 may be arbitrarily changed and may be suitably reversed.

[0301] As a result, the second semiconductor region 7 is formed, which has a stacked structure of the first layer 7p, which is a low-concentration layer, and the second layer 7q, which is a high-concentration layer (stacked structure forming step). At this time, the interface between the first layer 7p and the second layer 7q is the interface 7r.

[0302] Next, referring to FIG. 14F , a plurality of mesas 21 and a plurality of trenches 16 are formed on the first main surface 3 (trench formation process). In this process, first, a second mask 165 having a predetermined layout is formed on the first main surface 3. Next, unnecessary portions of the wafer 150 are removed by etching through the second mask 165. The etching process may be either wet etching or dry etching, or both. This results in the formation of a plurality of mesas 21 and a plurality of trenches 16. Furthermore, the base body region 183 and the base source region 184 are separated by the plurality of trenches 16, thereby forming the body region 90 and the source region 11. The second mask 165 is removed after this process.

[0303] 14G and 14H, a plurality of electric field relaxation layers 25 (FIG. 14H) are formed in regions along the bottom surfaces 20 of the plurality of trenches 16. In this step, ion implantation is performed using a first resist mask 166 (FIG. 14H) having a predetermined pattern. The first resist mask 166 has, for example, first openings 167 (FIG. 14H) that expose regions where the electric field relaxation layers 25 are to be formed. The formation of the first openings 167 will now be described.

[0304] 14G , when forming first opening 167, first resist 168 is formed on first main surface 3. First resist 168 is formed by coating using a spin coater, a spray coater, or the like. First resist 168 is, for example, a positive resist.

[0305] Thereafter, the first resist 168 is selectively exposed by photolithography through a first photomask 169 (photomask) (exposure step). The first resist 168 is then developed to form the first opening 167 shown in FIG. 14H. If the first resist 168 is a positive resist, the exposed portion of the first resist 168 is removed. This forms the first resist mask 166 having the first opening 167.

[0306] The first resist 168 may be exposed by a short-wavelength laser irradiation method using a first photomask 169. The short-wavelength laser may include an ultraviolet (UV) laser having a wavelength of 150 nm or more and 400 nm or less. The ultraviolet laser may be an ArF excimer laser, a KrF excimer laser, a XeCl excimer laser, a XeF excimer laser, or an F ２ The short wavelength laser may include at least one of an excimer laser and an extreme ultraviolet (EUV) laser having a wavelength of 13 nm or more and 14 nm or less.

[0307] After the first resist mask 166 is formed, p-type impurities are then introduced into the trenches 16 by ion implantation through the first resist mask 166. The ion implantation may be either or both of channeling ion implantation and random ion implantation.

[0308] The ion implantation is preferably a random ion implantation, and the p-type impurity is introduced into the wafer 150 at an implantation angle that is approximately perpendicular to the first main surface 3. The ion implantation is preferably a perpendicular ion implantation, not an oblique ion implantation. This process prevents the introduction of the p-type impurity into the wafer 150 through the two side surfaces 19 of the trench 16.

[0309] The plurality of electric field relaxation layers 25 are formed so as to vertically straddle the high concentration region 73 and the medium concentration region 72. The high concentration region 73 and the medium concentration region 72 are included in the second layer 7q and the first layer 7p, respectively. Therefore, the plurality of electric field relaxation layers 25 are all formed so as to vertically straddle the second layer 7q and the first layer 7p. In other words, the plurality of electric field relaxation layers 25 straddle the boundary surface 7r in the vertical direction Z.

[0310] Furthermore, the high concentration region 73 is divided into a plurality of regions by the plurality of electric field relaxation layers 25, thereby forming a plurality of high concentration regions 73. The first resist mask 166 is then removed.

[0311] 14I and 14J, a plurality of high-concentration regions 28 (FIG. 14J) are formed in a predetermined number of electric field relaxation layers 25 in regions along the bottom surfaces 20 of the plurality of trenches 16. In this step, ion implantation is performed using a second resist mask 171 (FIG. 14J) having a predetermined pattern. The second resist mask 171 has, for example, second openings 172 (FIG. 14J) that expose regions where the high-concentration regions 28 are to be formed. The formation of the second openings 172 will now be described.

[0312] 14I , when forming the second opening 172, first, a second resist 173 is formed on the first main surface 3. Then, the second resist (resist) 173 is selectively exposed to light by photolithography through a second photomask (photomask) 174 (exposure step). The second resist 173 is formed by coating using a spin coater, a spray coater, or the like. The second resist 173 is, for example, a positive resist.

[0313] Thereafter, the second resist 173 is developed to form the second opening 172 shown in Fig. 14J. If the second resist 173 is a positive resist, the exposed portion of the second resist 173 is removed. This forms the second resist mask 171 having the second opening 172.

[0314] The second resist 173 may be exposed by a short wavelength laser irradiation method using the second photomask 174. The ultraviolet laser may be an ArF excimer laser, a KrF excimer laser, a XeCl excimer laser, a XeF excimer laser, or an F ２ The short wavelength laser may include at least one of an excimer laser and an extreme ultraviolet (EUV) laser having a wavelength of 13 nm or more and 14 nm or less.

[0315] By using the short wavelength laser irradiation method with the second photomask 174, the adhesion of the second resist mask 171 to the first main surface 3 can be appropriately adjusted.

[0316] After the second resist mask 171 is formed, p-type impurities are then introduced into the trenches 16 by ion implantation via the second resist mask 171. The ion implantation may be either or both of channeling ion implantation and random ion implantation.

[0317] The ion implantation is preferably a random ion implantation, and the p-type impurity is introduced into the wafer 150 at an implantation angle that is approximately perpendicular to the first main surface 3. The ion implantation is preferably a perpendicular ion implantation, not an oblique ion implantation. This process suppresses the introduction of the p-type impurity into the second semiconductor region 7 through the two side surfaces 19 of the trench 16.

[0318] As a result, a plurality of high concentration regions 28 are formed in each of the plurality of electric field relaxation layers 25. The second resist mask 171 is then removed.

[0319] 14K , a plurality of contact regions 27 are formed in the wafer 150 (second semiconductor region 7) in regions that are aligned with the plurality of trenches 16. In this step, first, a third mask (not shown) having a predetermined layout (a layout that selectively exposes a portion of the first main surface 3 and a portion of the plurality of trenches 16) is formed on the first main surface 3.

[0320] Next, p-type impurities are introduced into wafer 150 through first main surface 3 and the plurality of trenches 16 by ion implantation using a third mask (not shown). The ion implantation may be either or both of channeling ion implantation and random ion implantation. In this embodiment, the ion implantation is random ion implantation.

[0321] The random ion implantation may be a vertical ion implantation. In this case, the p-type impurity is introduced into the wafer 150 at an implantation angle that is approximately perpendicular to the first main surface 3. The random ion implantation may be an oblique ion implantation. In this case, the p-type impurity is introduced into the wafer 150 at an implantation angle that is oblique to the first main surface 3. The implantation angle may be greater than 0° and equal to or less than 10°. As a result, the contact region 27 is formed in the second semiconductor region 7. The third mask (not shown) is then removed.

[0322] 14K, a base insulating film 175 is formed on the first main surface 3. The base insulating film 175 serves as a base for the plurality of insulating films 17 and the main surface insulating film 45. The base insulating film 175 is formed in the form of a film along the first main surface 3 and the wall surfaces of the plurality of trenches 16. The base insulating film 175 may be formed by either or both of a CVD method and an oxidation method (for example, a thermal oxidation method).

[0323] 14L, a first base electrode film is formed on base insulating film 175. The first base electrode film serves as the base of a plurality of buried electrodes 18. Since the subsequent steps are the same as the steps shown in FIGS. 11L to 11P, a description of these steps will be omitted.

[0324] After the drain pad electrode 140 (FIG. 2) is formed on the second wafer main surface 152, the wafer 150 is cut along the cutting lines 156 to cut out a plurality of semiconductor devices 1B. Through the steps including those described above, the semiconductor device 1B is manufactured.

[0325] 14G and 14I, a short wavelength laser (e.g., an ultraviolet (UV) laser) is irradiated. In order to form a device structure (transistor structure Tr) with high precision, it is necessary to irradiate the resists 168 and 173 with the short wavelength laser (e.g., an ultraviolet laser) at desired positions with high precision in the exposure process.

[0326] If the mesa portion 21 is disposed in the first layer 7p, which has a relatively low absorption coefficient for the short-wavelength laser, there is a risk that the short-wavelength laser irradiated toward the first main surface 3 will pass through the mesa portion 21 from the trench 16 and reach the resists 168, 173 in the adjacent trenches 16. In other words, there is a risk that unintended areas of the positive resists 168, 173 will be exposed and removed in the subsequent development step.

[0327] 14I , even though the adjacent trenches 16 are covered with the second photomask 174, there is a risk that the second resist 173 in the adjacent trenches 16 may be irradiated with a short-wavelength laser. Then, in the development process, there is a risk that part or all of the second resist 173 in the adjacent trenches 16 may be removed. Then, there is a risk that the pattern of the second openings 172 in the second resist mask 171 may differ from the intended pattern (the pattern may collapse). In this case, the subsequent ion implantation may not be performed with high precision, and as a result, there is a risk that the device structure (transistor structure Tr) may not be formed with high precision.

[0328] In contrast, with this method, the mesa portion 21 (as a whole) is disposed in the second layer 7q, which has a relatively high absorption coefficient for the short-wavelength laser. Therefore, in the exposure process shown in FIGS. 14G and 14I (particularly FIG. 14I), the short-wavelength laser does not pass through the mesa portion 21 from within the trench 16 (see the dashed line in FIG. 14I). This suppresses or prevents the short-wavelength laser from irradiating the second resist 173 in the adjacent trench 16. This allows the second opening 172 in the second resist mask 171 to be formed with high precision. Therefore, the device structure (transistor structure Tr) can be formed with high precision.

[0329] Furthermore, the first layer 7p and the second layer 7q included in the second semiconductor region 7 (drift region) are made of 4H—SiC (hexagonal SiC single crystal, first semiconductor material) which has a high dielectric breakdown field strength, thereby achieving a reduction in on-resistance.

[0330] 15 and 16 are diagrams showing a main part of a semiconductor device 1A according to a first modified example of the first embodiment. Fig. 15 shows a cross section taken at the same position as Fig. 8. Fig. 16 shows a cross section taken at the same position as Fig. 9. In Fig. 15 and 16, the same reference numerals are used to designate components equivalent to those of the semiconductor device 1A according to the first embodiment, and detailed descriptions thereof will be omitted.

[0331] 15 and 16 , the semiconductor device 1A according to the first modification has a configuration in which the features of the semiconductor device 1B according to the second embodiment are added. In the semiconductor device 1A according to the first modification, the first layer 7a and the second layer 7b have different impurity concentrations. The first layer 7a is made of a hexagonal SiC single crystal (first semiconductor material). The first layer 7a is made of a hexagonal SiC single crystal. The second layer 7b is made of a cubic SiC single crystal.

[0332] In the first modification, the n-type impurity concentration in the second layer 7 b is higher than the p-type impurity concentration and the n-type impurity concentration in the first layer 7 a. The p-type impurity concentration in the second layer 7 b is higher than the p-type impurity concentration and the n-type impurity concentration in the first layer 7 a. In other words, the second layer 7 b has a higher impurity concentration than the first layer 7 a.

[0333] Specifically, in the semiconductor device 1A according to the first modification, the second intermediate concentration region 72b has a higher n-type impurity concentration than the first intermediate concentration region 72a. １８ cm －３ 1x10 or more ２１ cm －３The n-type impurity concentration of the second intermediate concentration region 72b may have a peak value of the n-type impurity concentration below 1 / 2. The n-type impurity concentration of the second intermediate concentration region 72b may be approximately constant in the thickness direction. Of course, the n-type impurity concentration of the second intermediate concentration region 72b may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2. The second intermediate concentration region 72b may also be referred to as a high concentration region.

[0334] In the semiconductor device 1A according to the first modification, a p-type body region 90 is formed instead of the p-type body region 10. The body region 90 has a p-type impurity concentration higher than the n-type impurity concentration of the first intermediate concentration region 72a. The body region 90 has a p-type impurity concentration of, for example, 1×10 １８ cm －３ 1x10 or more １９ cm －３ The p-type impurity concentration may have the following peak value:

[0335] 17A and 17B are cross-sectional views showing a part of the manufacturing method of semiconductor device 1A according to the first modification. Figures 17A and 17B show the steps corresponding to Figures 11G and 11I, respectively. The exposure step of the manufacturing method of semiconductor device 1A according to the first modification will now be described.

[0336] 17A , when forming the first resist mask 166, first, a first resist (resist) 168 is formed on the first main surface 3. The first resist 168 is, for example, a positive resist. Thereafter, the first resist 168 is selectively exposed to light by photolithography via a first photomask (photomask) 169 (exposure step).

[0337] The first resist 168 is exposed by a short-wavelength laser irradiation method using a first photomask 169. The short-wavelength laser may include an ultraviolet (UV) laser having a wavelength of 150 nm or more and 400 nm or less, or an extreme ultraviolet (EUV) laser having a wavelength of 13 nm or more and 14 nm or less.

[0338] 17B , when forming the second resist mask 171, first, a second resist 173 is formed on the first main surface 3. The second resist 173 is, for example, a positive resist. Thereafter, the second resist 173 is selectively exposed to light by photolithography via a second photomask 174 (exposure step).

[0339] The second resist 173 is exposed by a short-wavelength laser irradiation method using a second photomask 174. The short-wavelength laser may include an ultraviolet (UV) laser having a wavelength of 150 nm or more and 400 nm or less, or an extreme ultraviolet (EUV) laser having a wavelength of 13 nm or more and 14 nm or less.

[0340] In the first modification, the entire mesa portion 21 is disposed in the second layer 7b, which has a relatively high absorption coefficient for short-wavelength laser light. Therefore, in the exposure process shown in FIGS. 17A and 17B (particularly FIG. 17B ), the short-wavelength laser light does not pass through the mesa portion 21 from within the trench 16 (see the dashed line in FIG. 17B ). Therefore, as shown in FIG. 17B , irradiation of the short-wavelength laser light onto the second resist 173 in the adjacent trench 16 can be suppressed or prevented. This allows the second opening 172 in the second resist mask 171 to be formed with high precision. Therefore, the device structure (transistor structure Tr) can be formed with high precision.

[0341] 18 and 19 are diagrams showing a main part of a semiconductor device 1A according to a second modification of the first embodiment. Fig. 18 shows a cross section taken at the same position as Fig. 8. Fig. 19 shows a cross section taken at the same position as Fig. 9. In Fig. 18 and 19, the same reference numerals are used to designate components equivalent to those of the semiconductor device 1A according to the first embodiment, and detailed descriptions thereof will be omitted.

[0342] The semiconductor device 1A according to the second modification is different from the first embodiment in that the second layer 7b is formed only on the surface layer of each mesa portion 21, rather than on the entire mesa portion 21.

[0343] The mesa portion 21 has one top surface 22, two side surfaces 19, and a mesa interior 24. The top surface 22 is a part of the first main surface 3. The side surfaces 19 of the mesa portion 21 are defined by the side surfaces 19 of the trench 16. The mesa interior 24 is a portion of the mesa portion 21 that is covered (surrounded) by the one top surface 22 and the two side surfaces 19. The upper edge of the mesa interior 24 is formed at a position spaced inward from the top surface 22. The side edges of the mesa interior 24 are formed at positions spaced inward from the side surfaces 19.

[0344] The mesa interior 24 is formed in the first layer 7a, which is a low ultraviolet absorption layer. In this embodiment, the first layer 7a is made of 4H—SiC and is a low ultraviolet absorption layer. In this embodiment, the second semiconductor region 7 and the electric field relaxation layer 25 are also formed in the first layer 7a.

[0345] On the other hand, the surface portion of the mesa portion 21, including the side surface 19 and the top surface 22 of the mesa portion 21, is disposed on the second layer 7b. In this embodiment, the second layer 7b is made of 3C-SiC, and is a highly ultraviolet absorbing layer.

[0346] The n-type source region 11 extends across the first layer 7a and the second layer 7b. The n-type source region 11 may be disposed only in the second layer 7b.

[0347] The n-type contact region 27 extends across the first layer 7a and the second layer 7b. The p-type body region 10 also extends across the first layer 7a and the second layer 7b.

[0348] 20A and 20B are cross-sectional views showing a part of a manufacturing method of the semiconductor device 1A according to the second modification, which respectively show steps corresponding to FIGS.

[0349] 20A , when forming the first resist mask 166, first, a first resist (resist) 168 is formed on the first main surface 3. The first resist 168 is, for example, a positive resist. Thereafter, the first resist 168 is selectively exposed to light by photolithography via a first photomask (photomask) 169 (exposure step).

[0350] The first resist 168 is exposed by a short-wavelength laser irradiation method using a first photomask 169. The short-wavelength laser may include an ultraviolet (UV) laser having a wavelength of 150 nm or more and 400 nm or less, or an extreme ultraviolet (EUV) laser having a wavelength of 13 nm or more and 14 nm or less.

[0351] 20B , when forming the second resist mask 171, first, a second resist 173 is formed on the first main surface 3. The second resist 173 is, for example, a positive resist. Thereafter, the second resist 173 is selectively exposed to light by photolithography via a second photomask 174 (exposure step).

[0352] The second resist 173 is exposed by a short-wavelength laser irradiation method using a second photomask 174. The short-wavelength laser may include an ultraviolet (UV) laser having a wavelength of 150 nm or more and 400 nm or less, or an extreme ultraviolet (EUV) laser having a wavelength of 13 nm or more and 14 nm or less.

[0353] In the second modification, the surface layer of the mesa portion 21 (top surface 22 and two side surfaces 19) is disposed on the second layer 7b, which has a relatively high absorption coefficient for short-wavelength laser light. Therefore, in the exposure process shown in FIGS. 20A and 20B (particularly FIG. 20B), the short-wavelength laser light does not pass through the mesa portion 21 from within the trench 16 (see the dashed line in FIG. 20B). Therefore, as shown in FIG. 20B, irradiation of the short-wavelength laser light onto the second resist 173 in the adjacent trench 16 can be suppressed or prevented. This allows the second opening 172 in the second resist mask 171 to be formed with high accuracy. Therefore, the device structure (transistor structure Tr) can be formed with high accuracy.

[0354] 18 and 19, bottom surfaces 20 of the plurality of trenches 16 are disposed in the first layer 7a. In a second modified example, bottom surfaces 20 of the plurality of trenches 16 may be disposed in the second layer 7b instead of the first layer 7a.

[0355] 18 to 20B may be applied to the second embodiment. That is, instead of the entire mesa portion 21, only the surface portion of each mesa portion 21 (two side surfaces 19 and the top surface 22) may be disposed on the second layer 7q, and the mesa interior 24 of each mesa portion 21 may be disposed on the first layer 7p. The bottom surfaces 20 of the trenches 16 may be disposed on the first layer 7p or on the second layer 7b.

[0356] The above-described embodiment (including variations) can be implemented in further other embodiments.

[0357] Wide bandgap semiconductors are semiconductors that have a bandgap larger than that of silicon. Wide bandgap semiconductor single crystals include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga ２ O ３ ) are examples.

[0358] In the above-described embodiment (including the modified example), both the first layer 7 a and the second layer 7 b are made of wide bandgap semiconductors, where the first semiconductor material constituting the first layer 7 a has a higher bandgap than the second semiconductor material constituting the second layer 7 b.

[0359] The second semiconductor material constituting the second layer 7b may include a single crystal other than a wide bandgap semiconductor. The second layer 7b may include a single crystal of silicon (Si, bandgap: 1.12 eV). That is, the second semiconductor material may be silicon.

[0360] The second semiconductor material constituting the second layer 7b may be a narrow bandgap semiconductor material, such as mercury cadmium telluride (Hg1-xCdxTe, bandgap: 1.5 eV), mercury zinc telluride (Hg1-xZnxTe, bandgap: -0.15 eV to 2.25 eV), lead selenide (PbSe, bandgap: 0.27 eV), lead(II) sulfide (PbS, bandgap: 0.37 eV), lead telluride (PbTe, bandgap: 0.32 eV), indium arsenide (InAs, bandgap: 0.354 eV), indium antimonide (InSb, bandgap: 0.17 eV), gallium antimonide (GaSb, bandgap: 0.67 eV), cadmium arsenide (Cd ３ As ２ , band gap: 0.5 eV or more and 0.6 eV or less), bismuth telluride (Bi ２ Te ３ , band gap: 0.21 eV), tin telluride (SnTe, band gap: 0.18 eV), tin selenide (SnSe, band gap: 0.18 eV), silver selenide (Ag ２ Se, band gap: 0.07 eV), magnesium silicide (Mg ２ Si, band gap: 0.73 eV).

[0361] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0362] In the above-described embodiments, the n-type first semiconductor region 6 has been described. However, a p-type first semiconductor region 6 may also be employed. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, in the above description, the "source" of the MISFET structure is replaced with the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced with the "collector" of the IGBT structure. The p-type first semiconductor region 6 may be a p-type region containing a trivalent element introduced into a surface layer portion of the second main surface 4 of the chip 2 by ion implantation.

[0363] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0364] [Supplementary Note 1-1] A semiconductor device (1A, 1B) comprising: a chip (2) having a first main surface (3) and a second main surface (4) opposite to the first main surface (3); a semiconductor region (7) disposed in a surface layer portion of the first main surface (3) within the chip (2); and a device structure (Tr) formed in the surface layer portion of the semiconductor region (7), wherein the semiconductor region (7) comprises a stacked structure of a first layer (7a, 7p) on the second main surface (4) side, the first layer (7a, 7p) being made of a first semiconductor material that is a wide band gap semiconductor material, and a second layer (7b, 7q) on the first main surface (3) side, the second layer (7b, 7q) having a higher absorption coefficient than the first layer (7a, 7p).

[0365] According to this configuration, in the stacked structure of the first layer (7a, 7p) and the second layer (7b, 7q), the second layer (7b, 7q) on the first main surface (3) side has a higher absorption coefficient than the first layer (7a, 7p) on the second main surface (4) side. Therefore, in the exposure process, it is possible to suppress or prevent the exposure light from passing through the surface layer portion of the first main surface (3) and irradiating the resist (168, 173) in other regions. This suppresses or prevents the opening pattern of the resist (168, 173) from collapsing. Therefore, it is possible to form the device structure (Tr) with high precision.

[0366] [Appendix 1-2] The semiconductor device (1A, 1B) according to appendix 1-1, wherein the second layer (7b, 7q) has a higher ultraviolet absorption coefficient than the first layer (7a, 7p).

[0367] According to this configuration, in the exposure step, ultraviolet (UV) light for exposure can be suppressed or prevented from passing through the surface layer of the first main surface (3) and irradiating the resist (168, 173) in other regions, thereby more effectively improving the dimensional accuracy of the device structure (Tr).

[0368] [Supplementary Note 1-3] The semiconductor device (1A) according to Supplementary Note 1-1 or Supplementary Note 1-2, wherein the second layer (7b) is made of a second semiconductor material having a band gap narrower than that of the first semiconductor material.

[0369] According to this configuration, the second semiconductor material contained in the second layer (7b) has a narrower band gap than the first semiconductor material contained in the first layer (7a), and therefore, a configuration in which the second layer (7b) absorbs exposure light more easily than the first layer (7a) can be realized relatively easily.

[0370] [Supplementary Note 1-4] The semiconductor device (1A) according to Supplementary Note 1-3, wherein the first semiconductor material includes a hexagonal SiC single crystal, and the second semiconductor material includes a cubic SiC single crystal.

[0371] According to this configuration, the cubic SiC single crystal has a narrower band gap than the hexagonal SiC single crystal, and therefore, it is possible to relatively easily realize a configuration in which the second layer (7b) absorbs the exposure light more easily than the first layer (7a).

[0372] [Appendix 1-5] The semiconductor device (1A) according to Appendix 1-4, wherein the hexagonal SiC single crystal includes at least one of a 2H—SiC single crystal, a 4H—SiC single crystal, and a 6H—SiC single crystal, and the cubic SiC single crystal includes a 3C—SiC single crystal.

[0373] [Appendix 1-6] The semiconductor device (1A, 1B) according to any one of Appendices 1-3 to 1-5, wherein the second layer (7b, 7q) has a higher impurity concentration than the first layer (7a, 7p).

[0374] According to this configuration, the second layers (7b, 7q) have a higher impurity concentration than the first layers (7a, 7p). Therefore, the second layers (7b, 7q) absorb light more easily than the first layers (7a, 7p). Therefore, a configuration in which the second layers (7b, 7q) absorb exposure light more easily than the first layers (7a, 7p) can be realized relatively easily.

[0375] [Supplementary Note 1-7] The semiconductor device (1A, 1B) according to any one of Supplementary Note 1-1 to Supplementary Note 1-6, further comprising: a trench structure (15) having trenches (16) extending from the first main surface (3) toward the inside of the semiconductor region (7) and having a bottom surface, the trench structures (15) being arranged in a stripe pattern; and a plurality of mesa portions (21) sandwiched and partitioned by a plurality of adjacent trenches (16), the plurality of mesa portions (21) each having a top surface (22) and a side surface (19) disposed in the second layer (7b, 7q).

[0376] According to this configuration, the top surface (22) and side surface (19) of the mesa portion are disposed on the second layer (7b, 7q). Therefore, in the exposure process, the light for exposure does not pass from the trench (16) to the mesa portion (21). This suppresses or prevents the light from irradiating the resist (168, 173) in the adjacent trench (16). Therefore, the device structure (Tr) can be formed with high precision.

[0377] [Supplementary Note 1-8] The semiconductor device (1A, 1B) according to Supplementary Note 1-7, wherein the entirety of each of the mesa portions (21) is disposed on the second layer (7b, 7q).

[0378] [Appendix 1-9] The semiconductor device (1A) according to Appendix 1-7, wherein each of the mesa portions (21) is covered by the top surface (22) and the side surface (19), and further includes a mesa interior (24) disposed in the first layer (7a, 7p).

[0379] [Supplementary Note 1-10] The semiconductor device (1A, 1B) according to any one of Supplementary Note 1-7 to Supplementary Note 1-9, wherein the bottom surface (20) of the trench (16) is disposed in the second layer (7b, 7q).

[0380] [Appendix 1-11] The semiconductor device (1A, 1B) according to any one of Appendices 1-7 to 1-10, wherein the semiconductor region (7) includes a drift region (7) of a first conductivity type, and further includes an electric field relaxation layer (25) of a second conductivity type formed in a region below the trench structure (15) within the drift region (72) along the bottom surface (20) of the trench, and the electric field relaxation layer (25) spans the first layer (7a, 7p) and the second layer (7b, 7q).

[0381] [Appendix 1-12] The semiconductor device (1A, 1B) according to Appendix 1-11, wherein a first distance (L1) between an interface (7c, 7r) between the first layer (7a, 7p) and the second layer (7b, 7q) and the bottom surface (20) of the trench (16) is shorter than a second distance (L2) between the interface (7c) and a bottom (25b) of the electric field relaxation layer (25).

[0382] [Appendix 1-13] The semiconductor device (1A, 1B) according to any one of Appendices 1-7 to 1-12, wherein a first distance (L1) between an interface (7c, 7r) between the first layer (7a, 7p) and the second layer (7b, 7q) and the bottom surface (20) of the trench (16) is shorter than a trench depth (DT) of the trench (16).

[0383] [Supplementary Note 1-14] The semiconductor device (1A, 1B) according to any one of Supplementary Note 1-7 to Supplementary Note 1-13, wherein the semiconductor region (7) includes a drift region (7) of a first conductivity type, and the device structure (Tr) includes: a body region (10) of a second conductivity type formed in a surface layer portion of the drift region (7); a source region (11) of the first conductivity type formed in a surface layer portion of the body region (10); and a plurality of trench gate structures (11) each having a plurality of gate trenches (16) arranged in a stripe pattern and penetrating the source region (11) and the body region (10), gate insulating films (17) formed on the inner surfaces of the plurality of gate trenches (16), and gate electrodes (18) embedded in the plurality of gate trenches (16) via the gate insulating films (17), and wherein the plurality of trench gate structures (11) are formed as a plurality of the trench structures (15).

[0384] [Appendix 1-15] The semiconductor device (1A, 1B) according to any one of Appendices 1-1 to 1-14, wherein the second thickness (T12) of the second layer (7b, 7q) is smaller than the first thickness (T11) of the first layer (7a, 7p).

[0385] [Appendix 1-16] A method for manufacturing a semiconductor device (1A, 1B), comprising: a step of preparing a wafer (150) made of a wide bandgap semiconductor material; a stacked structure forming step of forming, on a surface layer portion of a main surface (3) of the wafer (150), a stacked structure in which a first layer (7a, 7p) made of a first semiconductor material that is a wide bandgap semiconductor material and a second layer (7b, 7q) having a higher absorption coefficient than the first layer (7a, 7p) are stacked on the first layer (7a, 7p); and an exposure step of exposing resists (168, 173) formed on the second layers (7b, 7q) via photomasks (169, 174) to form resist masks (166, 171) on the second layers (7b, 7q).

[0386] According to this method, a laminated structure is formed on the surface of the main surface (3) of the wafer (150) including a first layer (7a, 7p) made of a wide bandgap semiconductor material and a second layer (7b, 7q) having a higher absorption coefficient than the first layer (7a, 7p).Then, an exposure process is performed on the first layer (7a, 7p).

[0387] The upper second layer (7b, 7q) has a higher absorption coefficient than the first layer (7a, 7p). Therefore, in the exposure step, it is possible to suppress or prevent the exposure light from passing through the surface layer of the first main surface (3) and irradiating the resist (168, 173) in other regions. This suppresses or prevents the opening pattern of the resist (168, 173) from collapsing.

[0388] [Appendix 1-17] The method for manufacturing a semiconductor device (1A) according to Appendix 1-16, further comprising, after the stacked structure forming step and prior to the exposure step, a trench forming step of forming a plurality of trenches (16) in a stripe pattern, in which a plurality of mesa portions (21) are formed by being sandwiched between a plurality of adjacent trenches (16) so that top surfaces (22) and side surfaces (19) are located on the second layer (7b, 7q).

[0389] According to this method, the top surface (22) and side surface (19) of the mesa portion (21) are disposed on the second layer (7b, 7q). Therefore, during the exposure process, light does not pass through the mesa portion (21) from the trench (16). This suppresses or prevents light from being irradiated onto the resist (168, 173) in the adjacent trench (16). This suppresses or prevents the opening pattern of the resist (168, 173) from collapsing.

[0390] [Appendix 1-18] A method for manufacturing a semiconductor device (1A) according to appendix 1-16 or appendix 1-17, wherein the stacked structure forming step includes a step of forming the second layer (7b) made of a second semiconductor material having a band gap narrower than that of the first semiconductor material on the first layer (7a).

[0391] According to this method, the second semiconductor material contained in the second layer (7b) has a narrower band gap than the first semiconductor material contained in the first layer (7a), and therefore, it is relatively easy to realize a configuration in which the second layer (7b) absorbs exposure light more easily than the first layer (7a).

[0392] [Appendix 1-19] A method for manufacturing a semiconductor device (1A) according to Appendix 1-18, wherein the stacked structure forming step includes a step of forming the second layer (7b) containing a 3C-SiC single crystal on the first layer (7a) containing at least one of a 2H-SiC single crystal, a 4H-SiC single crystal, and a 6H-SiC single crystal.

[0393] [Appendix 1-20] A method for manufacturing a semiconductor device (1A, 1B) according to any one of Appendices 1-16 to 1-19, wherein the second layer (7b, 7q) has a higher concentration of impurities of the first conductivity type than the first layer (7a, 7p).

[0394] According to this method, the second layers (7b, 7q) have a higher impurity concentration than the first layers (7a, 7p). Therefore, the second layers (7b, 7q) absorb light more easily than the first layers (7a, 7p). Therefore, a configuration in which the second layers (7b, 7q) absorb exposure light more easily than the first layers (7a, 7p) can be realized relatively easily.

[0395] 1A: Semiconductor device 1B: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: First semiconductor region 7: Second semiconductor region 7a: First layer 7b: Second layer 7c: Boundary surface 7p: First layer 7q: Second layer 7r: Boundary surface 8: Active region 9: Peripheral region 10: Body region 11: Source region 15: Gate structure 15A: First gate structure 15B: Second gate structure 16: Trench 17: Insulating film 18: Buried electrode 19: Side surface 20: Bottom surface 21: Mesa portion 22: Top surface 24: Inside mesa 25: Electric field relaxation layer 25a: Bulging portion 25b: Bottom portion 26: Channel region 27: Contact region 27a: First portion 27b: Second portion 28: High concentration region 30: Upper surface 31: Recess 38: First electrode film 39: Second electrode film 40: Outer well region 42: First outer well region 42a: Lower region 42b: Upper region 43: Second outer well region 43a: Lower region 43b: Upper region 45: Main surface insulating film 47: Interlayer film 49: Source opening 50: Outer opening 51: Source electrode 51a: First pad portion 51b: Second pad portion 51c: Third pad portion 52: Lower electrode film 52a: First electrode film 52b: Second electrode film 53: Main electrode film 56: Source wiring 57: Gate electrode 58: Gate wiring 59: Drain electrode 71: Base region 72: Medium concentration region 72a: First medium concentration region 72b: Second medium concentration region 73: High concentration region 90: Body region 140: Drain pad electrode 150: Wafer 151: First wafer main surface 152: Second wafer main surface 153: Wafer side surface 154: Mark 155: Device region 156: Planned cutting line 161: Base medium concentration region 162: Base body region 163: Base source region164: First mask 165: Second mask 166: First resist mask 167: First opening 168: First resist 169: First photomask 171: Second resist mask 172: Second opening 173: Second resist 174: Second photomask 175: Base insulating film 176: First base electrode film 177: Fourth mask 178: Second base electrode film 181: Medium base concentration region 182: High base concentration region 183: Base body region 184: Base source region DR: Relaxation depth DT: Trench depth L1: First distance L2: Second distance T1: Thickness T2: Thickness T11: First thickness T12: Second thickness Tr: Transistor structure X: First direction Y: Second direction Z: Vertical direction

Claims

1. A semiconductor device comprising: a chip having a first main surface and a second main surface opposite the first main surface; a semiconductor region within the chip arranged in a surface layer portion of the first main surface; and a device structure formed in the surface layer portion of the semiconductor region, wherein the semiconductor region has a stacked structure consisting of a first layer on the second main surface side, the first layer being made of a first semiconductor material that is a wide bandgap semiconductor material, and a second layer on the first main surface side, the second layer having a higher absorption coefficient than the first layer.

2. The semiconductor device according to claim 1, wherein said second layer has a higher ultraviolet absorption coefficient than said first layer.

3. The semiconductor device according to claim 1 or 2, wherein the second layer is made of a second semiconductor material having a bandgap narrower than that of the first semiconductor material.

4. The semiconductor device according to claim 3, wherein the first semiconductor material includes a hexagonal SiC single crystal, and the second semiconductor material includes a cubic SiC single crystal.

5. The semiconductor device according to claim 4, wherein the hexagonal SiC single crystal includes at least one of a 2H-SiC single crystal, a 4H-SiC single crystal, and a 6H-SiC single crystal, and the cubic SiC single crystal includes a 3C-SiC single crystal.

6. The semiconductor device according to any one of claims 3 to 5, wherein the second layer has a higher impurity concentration than the first layer.

7. A semiconductor device according to any one of claims 1 to 6, further comprising: a plurality of trench structures arranged in a stripe pattern, each trench having a bottom surface and extending from said first main surface into said semiconductor region; and a plurality of mesa portions separated by a plurality of adjacent trenches, each mesa portion having a top surface and a side surface disposed on said second layer.

8. The semiconductor device according to claim 7, wherein each of said mesas is entirely disposed on said second layer.

9. The semiconductor device according to claim 7, wherein each of said mesa portions further includes a mesa interior portion covered by said top surface and said side surface and disposed on said first layer.

10. The semiconductor device according to any one of claims 7 to 9, wherein the bottom surface of the trench is disposed in the second layer.

11. The semiconductor device according to any one of claims 7 to 10, wherein the semiconductor region includes a drift region of a first conductivity type, and further includes an electric field relaxation layer of a second conductivity type formed in the drift region below the trench structure along the bottom surface of the trench, and the electric field relaxation layer straddles the first layer and the second layer.

12. The semiconductor device of claim 11, wherein a first distance between the interface between the first layer and the second layer and the bottom surface of the trench is shorter than a second distance between the interface and the bottom of the electric field relaxation layer.

13. A semiconductor device according to any one of claims 7 to 12, wherein a first distance between an interface between the first layer and the second layer and the bottom surface of the trench is shorter than a depth of the trench.

14. The semiconductor device according to any one of claims 7 to 13, wherein the semiconductor region includes a drift region of a first conductivity type, and the device structure includes: a body region of a second conductivity type formed in a surface layer portion of the drift region; a source region of the first conductivity type formed in a surface layer portion of the body region; and a plurality of trench gate structures that penetrate the source region and the body region and are arranged in a stripe pattern, gate insulating films formed on the inner surfaces of the plurality of gate trenches, and gate electrodes embedded in the plurality of gate trenches via the gate insulating films, and the plurality of trench gate structures are formed as a plurality of the trench structures.

15. The semiconductor device according to any one of claims 1 to 14, wherein the second thickness of the second layer is smaller than the first thickness of the first layer.

16. A method for manufacturing a semiconductor device, comprising: a step of preparing a wafer made of a wide bandgap semiconductor material; a layered structure forming step of forming a layered structure on the surface layer of a main surface of the wafer, the layered structure including a first layer made of a first semiconductor material that is a wide bandgap semiconductor material and a second layer having a higher absorption coefficient than the first layer stacked on the first layer; and an exposure step of exposing a resist formed on the second layer through a photomask to form a resist mask on the second layer.

17. A method for manufacturing a semiconductor device according to claim 16, further comprising, after the stacked structure forming step and prior to the exposure step, a trench forming step of forming a plurality of trenches in a stripe pattern, in which a plurality of mesa portions separated by a plurality of adjacent trenches are formed so that their top surfaces and side surfaces are located on the second layer.

18. The method for manufacturing a semiconductor device according to claim 16 or 17, wherein the step of forming a stacked structure includes the step of forming, on the first layer, the second layer made of a second semiconductor material having a band gap narrower than that of the first semiconductor material.

19. The method for manufacturing a semiconductor device according to claim 18, wherein the step of forming a stacked structure includes a step of forming the second layer containing 3C-SiC single crystal on the first layer containing at least one of 2H-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal.

20. A method for manufacturing a semiconductor device according to any one of claims 16 to 19, wherein the second layer has a higher impurity concentration than the first layer.

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