Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises: a device structure which includes a plurality of conductive structures that are formed in an active region of an SiC chip; an insulating film which covers the conductive structures; and a main surface electrode which covers the conductive structures with the insulating film being interposed therebetween. The insulating film has a layered structure of a first insulating film and a second insulating film, and a first film thickness ratio of a first lateral film thickness, which is the film thickness of a portion that covers a first side wall of the conductive structure in the first insulating film, to a first upper film thickness, which is the film thickness of a portion that covers a first upper wall of the conductive structure in the first insulating film is different from a second film thickness ratio of a second lateral film thickness, which is the film thickness of a portion that covers the first side wall in the second insulating film, to a second upper film thickness, which is the film thickness of a portion that covers the first upper wall in the second insulating film.

Description

Semiconductor device and method for manufacturing the same Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-114034 filed with the Japan Patent Office on July 17, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0003] Patent Document 1 discloses a semiconductor device including a SiC semiconductor layer having a first main surface, a plurality of trench gate structures formed on the first main surface, and an interlayer insulating film formed on the first main surface so as to cover the plurality of trench gate structures. Each trench gate structure includes a gate electrode made of polysilicon. The interlayer insulating film covering the gate electrode is formed by a CVD method.

[0004] Japanese Patent Application Laid-Open No. 2023-091047

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device including a SiC chip having a first main surface on which an active region is formed and a second main surface opposite the first main surface, a device structure including a plurality of conductive structures made of polysilicon formed in the active region, an insulating film formed on the first main surface to cover the conductive structures, and a main surface electrode covering the conductive structures via the insulating film. The insulating film may have a stacked structure of a first insulating film on the first main surface side and a second insulating film on the main surface electrode side. A first thickness ratio of a first lateral thickness, which is the thickness of a portion of the first insulating film covering a first sidewall of the conductive structure to a first upper thickness, which is the thickness of a portion of the first insulating film covering a first upper wall of the conductive structure, is different from a second thickness ratio of a second lateral thickness, which is the thickness of a portion of the second insulating film covering the first sidewall, to a second upper thickness, which is the thickness of a portion of the second insulating film covering the first upper wall.

[0006] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method including the steps of: preparing a SiC wafer having a wafer main surface; forming a device structure on the wafer main surface, the device structure including a plurality of conductive structures made of polysilicon; forming an insulating film on the wafer main surface to cover the plurality of conductive structures; and forming a main surface electrode to cover the insulating film. The insulating film forming step may include a plasma step of forming the insulating film using a plasma CVD method.

[0007] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure, and is a plan view showing the layout of a principal surface electrode film. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing the layout of a first principal surface. FIG. 4 is an enlarged view of a portion surrounded by dashed line IV in FIG. 3. FIG. 5A is a cross-sectional view taken along line VA-VA in FIG. 4. FIG. 5B is a cross-sectional view taken along line VB-VB in FIG. 4. FIG. 6 is a schematic diagram showing a wafer used in manufacturing the semiconductor device. FIG. 7A is a cross-sectional view showing a method for manufacturing the semiconductor device. FIG. 7B is a cross-sectional view showing a step subsequent to FIG. 7A. FIG. 7C is a cross-sectional view showing a step subsequent to FIG. 7B. FIG. 7D is a cross-sectional view showing a step subsequent to FIG. 7C. FIG. 7E is a cross-sectional view showing a step subsequent to FIG. 7D. FIG. 7F is a cross-sectional view showing a step subsequent to FIG. 7E. FIG. 7G is a cross-sectional view showing a step subsequent to FIG. 7F. FIG. 7H is a cross-sectional view showing a step subsequent to FIG. 7G. FIG. 7I is a cross-sectional view showing a step subsequent to FIG. 7H. 7J is a cross-sectional view showing a step subsequent to FIG. 7I. FIG. 8 is a flow chart showing the flow of an insulating film formation step according to the first embodiment. FIG. 9 is a schematic cross-sectional view showing a vertical cross section of a low-pressure CVD apparatus used in a low-pressure CVD method. FIG. 10 is a schematic cross-sectional view showing a vertical cross section of a plasma CVD apparatus used in a plasma CVD method. FIG. 11 is a timing chart for explaining an example of on / off switching of dual frequencies in a plasma CVD method. FIG. 12 is a timing chart for explaining another example of on / off switching of dual frequencies in a plasma CVD method. FIG. 13 is a diagram showing a first aspect of the composition of an interlayer insulating film. FIG. 14 is a diagram showing a second aspect of the composition of an interlayer insulating film. FIG. 15 is a diagram showing a third aspect of the composition of an interlayer insulating film. FIG. 16 is a diagram showing a fourth aspect of the composition of an interlayer insulating film. FIG. 17 is a cross-sectional view showing a second aspect of a device structure. FIG. 18 is a cross-sectional view showing a third aspect of a device structure. FIG. 19A is a cross-sectional view showing a main portion of a semiconductor device according to a second embodiment of the present disclosure. Fig. 19B is a cross-sectional view showing a main part of the semiconductor device according to the second embodiment of the present disclosure, Fig. 20A is a cross-sectional view showing a method for manufacturing the semiconductor device according to the second embodiment of the present disclosure, and Fig. 20B is a cross-sectional view showing a step subsequent to Fig. 20A.Fig. 20C is a cross-sectional view showing a step subsequent to Fig. 20B. Fig. 21 is a flow chart showing the flow of an insulating film formation step according to the second embodiment. Fig. 22 is a diagram showing a fifth aspect of the composition of an interlayer insulating film. Fig. 23 is a diagram showing a sixth aspect of the composition of an interlayer insulating film. Fig. 24 is a diagram showing a seventh aspect of the composition of an interlayer insulating film.

[0008] DETAILED DESCRIPTION Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0009] The accompanying drawings are all schematic diagrams and are not strictly illustrated, and the scale, ratio, angle, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated explanations have been omitted or simplified. For structures whose explanations have been omitted or simplified, the explanation given before the omission or simplification applies.

[0010] When the term "substantially" is used in this specification, this term includes a numerical value (form) that is substantially equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0011] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." Of course, "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." "n-type" is a conductivity type resulting from a pentavalent element, and "p-type" is a conductivity type resulting from a trivalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] FIG. 1 is a plan view of a semiconductor device 1 according to an embodiment of the present disclosure, showing the layout of a principal surface electrode film 19. A surface insulating film 34 (FIG. 2) is not shown in FIG. 1. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1. FIG. 3 is a plan view showing the layout of a first principal surface 3. FIG. 4 is an enlarged view of a portion surrounded by dashed dotted line IV in FIG. 3. FIG. 5A is a cross-sectional view taken along line VA-VA in FIG. 4. FIG. 5B is a cross-sectional view taken along line VB-VB in FIG. 4.

[0013] The semiconductor device 1 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. The transistor structure Tr has a planar gate vertical structure (planar structure).

[0014] 1 to 3, semiconductor device 1 includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, chip 2 includes a single crystal of a wide bandgap semiconductor. In other words, semiconductor device 1 is a "wide bandgap semiconductor device." Chip 2 may also be referred to as a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0015] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. In other words, the semiconductor device 1 is a "SiC semiconductor device."

[0016] Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0017] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side (FIG. 2), and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.

[0018] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, the first main surface 3 is preferably formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is preferably formed by the carbon surface ((000-1) surface) of the SiC single crystal. The first main surface 3 and the second main surface 4 may have an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be greater than 0° and not more than 10°. The off-angle is preferably not more than 5°.

[0019] The first side surface 5A and the second side surface 5B extend in a second direction Y that intersects with the first direction X along the first main surface 3, and face the first direction X. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the first direction X and face the second direction Y along the first main surface 3.

[0020] In this embodiment, the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal, and the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal.

[0021] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0022] The first to fourth side surfaces 5A to 5D may have lengths of 0.5 mm or more and 20 mm or less in plan view. The lengths of the first to fourth side surfaces 5A to 5D may have a value that belongs to any one of the ranges of 0.5 mm or more and 1 mm or less, 1.5 mm or more and 2 mm or less, 2 mm or more and 5 mm or less, 5 mm or more and 10 mm or less, 10 mm or more and 15 mm or less, and 15 mm or more and 20 mm or less. The lengths of the first to fourth side surfaces 5A to 5D may be 5 mm or more.

[0023] 2, 5A, and 5B, semiconductor device 1 (chip 2) includes an n-type first semiconductor layer 6 formed in a surface layer portion of second main surface 4. A drain potential is applied to first semiconductor layer 6 as a first potential (high potential). First semiconductor layer 6 may also be referred to as a "semiconductor region (layer)," a "base region (layer)," a "drain region (layer)," or the like.

[0024] The first semiconductor layer 6 extends in a layered form along the second main surface 4, and forms the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 is made of a SiC substrate (substrate) including a SiC single crystal (semiconductor single crystal), and has the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of a substrate made of a SiC single crystal (i.e., a SiC substrate).

[0025] The first semiconductor layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value: The first semiconductor layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction.

[0026] The first semiconductor layer 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value belonging to at least one of the ranges of 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or more, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0027] 2 , 5A and 5B , the semiconductor device 1 includes a drain pad electrode 7 covering the second main surface 4. The drain pad electrode 7 is mechanically and electrically connected to the first semiconductor layer 6. The drain pad electrode 7 forms ohmic contact with the first semiconductor layer 6.

[0028] The drain pad electrode 7 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 7 may also cover part of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0029] 2, 5A, and 5B, semiconductor device 1 (chip 2) includes an n-type second semiconductor layer 8 formed in a surface layer portion of first main surface 3. Second semiconductor layer 8 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. Second semiconductor layer 8 extends in a layered form along first main surface 3, and forms first main surface 3 and first to fourth side surfaces 5A to 5D.

[0030] In this embodiment, the second semiconductor layer 8 is an n-type semiconductor layer. The second semiconductor layer 8 may be an epitaxial layer (i.e., a SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal). The second semiconductor layer 8 is an epitaxial layer (SiC epitaxial layer) grown from the first semiconductor layer 6.

[0031] The second semiconductor layer 8 has a lower end and an upper end. The lower end of the second semiconductor layer 8 is the starting point of crystal growth, and the upper end of the second semiconductor layer 8 is the ending point of crystal growth. The lower end of the second semiconductor layer 8 is also the bottom of the second semiconductor layer 8. Since the second semiconductor layer 8 is grown continuously from the first semiconductor layer 6, the lower end of the second semiconductor layer 8 coincides with the upper end of the first semiconductor layer 6.

[0032] The second semiconductor layer 8 includes an n-type drift region 9 as an example of a first impurity region. In this embodiment, the drift region 9 is formed by a portion (n-type portion) of the second semiconductor layer 8. The second semiconductor layer 8 preferably has a substantially constant n-type impurity concentration in the thickness direction. The second semiconductor layer 8 may have a lower n-type impurity concentration than the first semiconductor layer 6.

[0033] The second semiconductor layer 8 has a thickness less than that of the first semiconductor layer 6. The thickness of the second semiconductor layer 8 may be 5 μm or more and 15 μm or less. The thickness of the second semiconductor layer 8 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0034] 1 to 4, a semiconductor device 1 includes an active region 10 and a peripheral region 11 defined on a first main surface 3 of a chip 2. The active region 10 and the peripheral region 11 are formed on the first main surface 3 of the chip 2. As shown in FIG.

[0035] The active region 10 includes a device structure (i.e., a transistor structure Tr) and is a region (element region) where an output current (drain current) is generated. The active region 10 is set in an inner portion of the chip 2 at a distance from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) in a plan view. The active region 10 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 10 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0036] 2 to 4 and 5A, the semiconductor device 1 includes a plurality of p-type body regions 12 formed in a surface layer portion of the second semiconductor layer 8 in the active region 10. The body regions 12 are an example of second impurity regions. A source potential is applied to the plurality of body regions 12 as a low potential (second potential) different from a high potential (first potential). The plurality of body regions 12 are arranged at intervals in the second direction Y (m-axis direction) and are each formed in a strip shape extending in the first direction X (a-axis direction). In other words, the plurality of body regions 12 are arranged in stripes extending in the first direction X (a-axis direction).

[0037] Each body region 12 provides a unit cell UC (FIG. 5A) of a planar gate transistor. Each unit cell UC (FIG. 5A) includes at least a body region 12 and a source region 46 (described later), and may be the smallest unit that functions as a MIS transistor. In this configuration, the multiple unit cells UC (FIG. 5A) are arranged in stripes extending in the a-axis direction (first direction X).

[0038] Each of the plurality of body regions 12 has a size of, for example, 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration may have the following peak value:

[0039] 2 and 5A , the plurality of body regions 12 are formed at intervals from the bottom of the second semiconductor layer 8 toward the first main surface 3, and face the first semiconductor layer 6 across a part of the second semiconductor layer 8. The plurality of body regions 12 are preferably formed at intervals from the middle of the second semiconductor layer 8 toward the first main surface 3.

[0040] 5A , the semiconductor device 1 includes one or more n-type source regions 46 formed in the surface layer portions of the body regions 12 in the active region 10. The source regions 46 are an example of a third impurity region. In this embodiment, a plurality of (two in this embodiment) source regions 46 are formed at intervals in the surface layer portion of each body region 12. Each of the plurality of source regions 46 has an n-type impurity concentration higher than the n-type impurity concentration of the drift region 9. Each of the plurality of source regions 46 has an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0041] The multiple source regions 46 may each extend in a strip shape along the extension direction of the corresponding body region 12 (i.e., the first direction X). Of course, the multiple source regions 46 may be formed at intervals along the extension direction of the corresponding body region 12. The multiple source regions 46 are formed at intervals from the bottom of the corresponding body region 12 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding body region 12. The multiple source regions 46 define a channel region 47 along the first main surface 3 at the periphery of the body region 12.

[0042] 5A , the semiconductor device 1 includes one or more p-type body contact regions 48 formed in the surface layer portions of the body regions 12 in the active region 10. The body contact regions 48 may also be referred to as "back gate regions." In this embodiment, one body contact region 48 is formed in a region between the adjacent source regions 46 in the surface layer portion of each body region 12.

[0043] Each of the body contact regions 48 has a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 12. Each of the body contact regions 48 has a p-type impurity concentration (peak value) of 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0044] Each body contact region 48 may extend in a strip shape along the extension direction of the corresponding body region 12. Of course, each body contact region 48 may be formed at intervals along the extension direction of the corresponding body region 12. Each body contact region 48 is formed at an interval from the bottom of the corresponding body region 12 toward the first main surface 3, and is formed at an interval from the peripheral edge of the corresponding body region 12 inward.

[0045] 1 to 4, peripheral region 11 is a region that does not include a device structure (transistor structure Tr). Peripheral region 11 is provided in a region between the periphery of chip 2 and active region 10 in a plan view. Peripheral region 11 extends in a band shape along active region 10 in a plan view, and is set in a polygonal ring shape (a square ring shape in this embodiment) that surrounds active region 10.

[0046] 2 and 4 , the semiconductor device 1 includes a plurality of planar electrode-type gate structures 14 arranged on the first main surface 3 in the active region 10. In this embodiment, the plurality of gate structures 14 are arranged at intervals in the second direction Y (m-axis direction) and are each formed in a strip shape extending in the first direction X (a-axis direction). That is, the plurality of gate structures 14 are arranged in stripes extending in the first direction X (a-axis direction). The extending direction of the plurality of gate structures 14 coincides with the off-direction of the SiC single crystal.

[0047] Hereinafter, one gate structure 14 has a stacked structure including a gate insulating film 15 and a gate electrode (conductive structure) 16. The gate structure 14 does not have insulating sidewall structures (spacers) on the sides of the gate electrode 16. The gate insulating film 15 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the gate insulating film 15 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the gate insulating film 15 includes a silicon oxide film made of an oxide of the chip 2. The gate insulating film 15 is formed on the first main surface 3 so as to cover the entire active region 10.

[0048] 2, 4, and 5A, in this embodiment, the gate electrodes 16 are arranged at intervals in the second direction Y (m-axis direction) and are each formed in a strip shape extending in the first direction X (a-axis direction). That is, the gate electrodes 16 are arranged in stripes extending in the first direction X (a-axis direction). The extending direction of the gate electrodes 16 coincides with the off-direction of the SiC single crystal.

[0049] 5A , the plurality of gate electrodes 16 are arranged at intervals on the first main surface 3 so as to overlap with at least one channel region 47 in the stacking direction (vertical direction Z). The plurality of gate electrodes 16 control the inversion and non-inversion of the channel (current path) in the body region 12 in response to a gate potential.

[0050] Each gate electrode 16 has one first upper wall 16a and two first side walls 16b. In this embodiment, the first upper wall 16a may extend substantially parallel to the gate insulating film 15 (first main surface 3). The first upper wall 16a extends in the vertical direction Z on the gate insulating film 15, and the first side walls 16b extend in the vertical direction Z on the gate insulating film 15. In other words, the gate electrode 16 is formed in a quadrangular shape (a flattened rectangular shape) in a cross-sectional view.

[0051] The gate electrode 16 is made of conductive polysilicon. The gate electrode 16 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0052] 2, the semiconductor device 1 includes an interlayer insulating film 18 as an example of an insulating film. The interlayer insulating film 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the interlayer insulating film 18 is preferably a silicon oxide film. The interlayer insulating film 18 may also be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. The interlayer insulating film 18 may also be referred to as a PMD (Pre Metal Dielectric) film.

[0053] 5A , a plurality of source contact openings 52 are formed in the interlayer insulating film 18, each opening directly above a corresponding one of the body regions 12. The source contact openings 52 are formed in a region between a pair of gate electrodes 16 facing each other in the second direction Y. The source contact openings 52 penetrate the interlayer insulating film 18 and the gate insulating film 15. The source contact openings 52 are arranged at intervals in the direction in which the pair of gate electrodes 16 face each other, i.e., in the second direction Y.

[0054] The plurality of source contact openings 52 penetrate both a first insulating film 50 (described later) and a second insulating film 51 (described later) of the interlayer insulating film 18, and have wall surfaces defined by both the first insulating film 50 and the second insulating film 51. The plurality of source contact openings 52 expose the corresponding plurality of source regions 46 and body contact regions 48, respectively.

[0055] In this embodiment, the source contact openings 52 are formed in strips extending along the first direction X, one for each unit cell UC ( FIG. 4 ). Each unit cell UC may have a plurality of source contact openings 52. For example, a plurality of strip-shaped source contact openings 52 may be formed along the first direction X for each unit cell UC, or a row of relatively short strip-shaped source contact openings 52 may be arranged along the first direction X for each unit cell UC.

[0056] 1 and 2, the semiconductor device 1 includes a main surface electrode film 19 disposed on an interlayer insulating film 18. In Fig. 1, the main surface electrode film 19 is indicated by a hatched area. The main surface electrode film 19 includes a source electrode film 20 and a gate electrode film 21.

[0057] 5A and 5B , in this embodiment, the main surface electrode film 19 (source electrode film 20 and gate electrode film 21) has a laminated structure including a lower electrode film 60 and a main electrode film 61 laminated in this order from the chip 2 side. The lower electrode film 60 may include, for example, either Ti or TiN. The lower electrode film 60 may include, for example, both Ti and TiN. The lower electrode film 60 may also be a laminated film in which a Ti film and a TiN film are laminated.

[0058] The main electrode film 61 contains a different conductive material from that of the lower electrode film 60. The main electrode film 61 may contain at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The main electrode film 61 has a thickness greater than the thickness (total thickness) of the lower electrode film 60. The thickness of the main electrode film 61 is preferably greater than the thickness of the interlayer insulating film 18.

[0059] 1 , the source electrode film 20 is a film that is physically and electrically separated from the gate electrode film 21. The source electrode film 20 is disposed on the interlayer insulating film 18 at a distance from the gate electrode film 21. The source electrode film 20 is an electrode to which a source potential is applied from the outside. The source electrode film 20 may also be referred to as a "source pad electrode," a "source metal," a "first pad electrode," or the like.

[0060] The source electrode film 20 is made of a metal material containing Al (aluminum). The source electrode film 20 includes an Al-based metal film. The source electrode film 20 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0061] The source electrode film 20 includes a source pad electrode 22 as an example of a main surface electrode and a source wiring 23, which are arranged on the active region 10 in a plan view.

[0062] The source pad electrode 22 has a recess in a plan view. The source pad electrode 22 is a terminal electrode to which a source potential is applied from the outside. The source pad electrode 22 may be referred to as a "first pad electrode," a "first main surface electrode," a "first terminal electrode," or the like.

[0063] In this embodiment, the source pad electrode 22 has a first pad portion 22 a, a second pad portion 22 b, and a third pad portion 22 c. The first pad portion 22 a has a relatively large planar area and forms the main body of the source pad electrode 22. In this embodiment, the first pad portion 22 a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the fourth side surface 5D than the center of the active region 10.

[0064] The second pad portion 22b has a planar area smaller than that of the first pad portion 22a, and is extended in a strip shape (rectangular shape) from one side end of the first pad portion 22a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C side.

[0065] The third pad portion 22c has a planar area smaller than that of the first pad portion 22a, and is extended in a strip shape (square shape) from the other side end of the first pad portion 22a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 22b in the second direction Y.

[0066] 5A , the source pad electrode 22 covers the plurality of gate electrodes 16 with the interlayer insulating film 18 sandwiched therebetween. The source pad electrode 22 is electrically connected to the plurality of body regions 12 and the like via the plurality of source contact openings 52. Specifically, a lower electrode film 60 of the source pad electrode 22 is formed so as to extend along the wall surfaces of the plurality of source contact openings 52 and the first main surface 3. A portion of the main electrode film 61 of the source pad electrode 22 extends into the plurality of source contact openings 52 and is in contact with the source region 46 and the body contact region 48.

[0067] 1 , the source wiring 23 has a wiring width less than the electrode width of the source pad electrode 22, and is selectively routed on the interlayer insulating film 18. In this embodiment, the source wiring 23 is led out from the source pad electrode 22 to the third side surface 5C side. The source wiring 23 is led out from the active region 10 to the peripheral region 11.

[0068] The source wiring 23 extends in a strip shape along the periphery of the first main surface 3 (the periphery of the active region 10). In this embodiment, the source wiring 23 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part of the first main surface 3 (the active region 10). The source wiring 23 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape). The source wiring 23 may be either ended or endless.

[0069] The source wiring 23 is supplied with the same potential (source potential) as the potential (source potential) supplied to the source pad electrode 22. The source wiring 23 may also be referred to as a "termination electrode (wiring)," a "finger electrode," a "source finger," or the like.

[0070] The gate electrode film 21 is an electrode to which a gate potential is applied from the outside. The gate electrode film 21 may also be called a "second principal surface electrode," a "gate pad," a "gate metal," a "second pad electrode," or the like.

[0071] The gate electrode film 21 is made of a metal material containing Al (aluminum). The gate electrode film 21 includes an Al-based metal film. The gate electrode film 21 may include at least one of a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0072] The gate electrode film 21 includes a gate pad electrode 24 and a gate wiring 25. In this embodiment, the gate pad electrode 24 is disposed on the peripheral region 11. Specifically, the gate pad electrode 24 is disposed in a region close to the center of one side of the first main surface 3 (the third side surface 5C in this embodiment) in a plan view. The gate pad electrode 24 is disposed in a recess formed in the source electrode film 20. The gate pad electrode 24 may be disposed in a region along the center of any of the first to fourth side surfaces 5A to 5D in a plan view. The gate pad electrode 24 may be disposed at any corner of the chip 2 on the first main surface 3 in a plan view. The gate pad electrode 24 may be disposed in the center of the first main surface 3 in a plan view. The gate pad electrode 24 may be disposed on the active region 10. In this embodiment, the gate pad electrode 24 is formed in a quadrangular shape in a plan view.

[0073] In this embodiment, the gate pad electrode 24 is formed in a quadrangular shape in a plan view. The gate pad electrode 24 may also be referred to as a "second pad electrode," a "gate pad," a "gate metal," a "second pad electrode," or the like.

[0074] The gate wiring 25 is routed from the gate pad electrode 24 around the periphery of the active region 10, surrounding the active region 10. The gate wiring 25 transmits the gate potential applied to the gate pad electrode 24 to the plurality of gate electrodes 16 (FIGS. 2 and 4).

[0075] The gate wiring 25 extends in a strip shape outward from the outer edge of the gate pad electrode 24. The gate wiring 25 includes a plurality of finger wirings 28, 29 extending in strip shapes in different directions from the outer edge of the gate pad electrode 24. The plurality of finger wirings 28, 29 are arranged in a non-parallel positional relationship with each other. The plurality of finger wirings 28, 29 may include a first finger wiring 28 and a second finger wiring 29.

[0076] The first finger wiring 28 and the second finger wiring 29 extend from the gate pad electrode 24 in opposite directions along the periphery of the chip 2, and as a whole surround the source pad electrode 22. The first finger wiring 28 and the second finger wiring 29 are an example of gate periphery wiring.

[0077] In this embodiment, first finger wiring 28 extends from gate pad electrode 24 in the first direction X along third side surface 5C, first side surface 5A, and fourth side surface 5D in this order, and has tip portion 28a in the center of fourth side surface 5D in the first direction X. Second finger wiring 29 extends from gate pad electrode 24 in the first direction X along third side surface 5C, second side surface 5B, and fourth side surface 5D in this order, and has tip portion 29a in the center of fourth side surface 5D in the first direction X. Tip portions 28a and 29a face each other with a space between them in the first direction X.

[0078] The first finger wiring 28 and the second finger wiring 29 are each formed in a substantially U-shape in a plan view, and have corners at positions corresponding to the corners of the chip 2. The first finger wiring 28 may be referred to as, for example, a "first peripheral wiring," a "first peripheral electrode," a "first peripheral finger wiring," a "first peripheral finger electrode," or the like. The second finger wiring 29 may be referred to as, for example, a "second peripheral wiring," a "second peripheral electrode," a "second peripheral finger wiring," a "second peripheral finger electrode," or the like. The first finger wiring 28 and the second finger wiring 29 may be collectively referred to as a "peripheral wiring," a "peripheral electrode," a "peripheral finger wiring," a "peripheral finger electrode," or the like that surround the active region 10.

[0079] 2 , a breakdown voltage that can be applied between the source electrode film 20 and the drain pad electrode 7 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value belonging to at least one of the ranges of 500 V or more and 750 V or less, 750 V or more and 1000 V or less, 1000 V or more and 1250 V or less, 1250 V or more and 1500 V or less, 1500 V or more and 1750 V or less, 1750 V or more and 2000 V or less, 2000 V or more and 2250 V or less, 2250 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0080] 2 , the semiconductor device 1 includes a surface insulating film 34 that selectively covers the main surface electrode film 19 and the interlayer insulating film 18 on the first main surface 3. The surface insulating film 34 includes a gate pad opening 36 that exposes a portion of the gate pad electrode 24 as a gate pad 35. The surface insulating film 34 covers the periphery of the gate pad electrode 24 and the entire area of ​​the gate wiring 25. The gate pad opening 36 is formed in a quadrangular shape in a plan view.

[0081] The surface insulating film 34 may have a layered structure including an inorganic insulating film and an organic insulating film stacked in this order from the chip 2 side, for example. The surface insulating film 34 may include at least one of an inorganic insulating film and an organic insulating film, and does not necessarily have to include both an inorganic insulating film and an organic insulating film at the same time. The inorganic insulating film may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The inorganic insulating film preferably includes an insulating material different from that of the interlayer insulating film 18. The organic insulating film is preferably made of a polyimide film, a polyamide film, or a polybenzoxazole film. In this embodiment, the organic insulating film includes a polybenzoxazole film.

[0082] The surface insulating film 34 includes a source pad opening 38 that exposes a part of the source electrode film 20 as a source pad 37. The surface insulating film 34 covers the peripheral edge of the source pad electrode 22.

[0083] The source pad opening 38 is formed in a polygonal shape in plan view along the periphery of the source pad electrode 22. The plane area of ​​the source pad opening 38 is preferably larger than the plane area of ​​the gate pad opening 36.

[0084] 2 , 4 , and 5B , semiconductor device 1 includes p-type outer body region 13 formed in peripheral region 11 in a surface layer portion of first main surface 3. Outer body region 13 preferably has a p-type impurity concentration substantially equal to the p-type impurity concentration of body region 12. Of course, the p-type impurity concentration of outer body region 13 may be lower than the p-type impurity concentration of body region 12 or higher than the p-type impurity concentration of body region 12.

[0085] 4 , outer body region 13 is formed at a distance from the periphery of first main surface 3 (first to fourth side surfaces 5A to 5D) toward active region 10 and extends in a strip shape along active region 10. Outer body region 13 has a portion extending in a strip shape in first direction X and a portion extending in a strip shape in second direction Y in plan view, thereby partitioning active region 10 from multiple directions. In this embodiment, outer body region 13 is partitioned in a polygonal ring shape (a square ring shape in this embodiment) that surrounds active region 10 in plan view and has four sides parallel to the periphery of first main surface 3.

[0086] Outer body region 13 has an inner edge portion on the active region 10 side and an outer edge portion on the peripheral side of first main surface 3. The inner edge portion of outer body region 13 is connected to the plurality of body regions 12 at a portion extending in first direction X. As a result, outer body region 13 is fixed to the same potential as the plurality of body regions 12.

[0087] 2 and 5B , outer body region 13 is formed at a distance from the bottom of second semiconductor layer 8 toward first main surface 3, and faces first semiconductor layer 6 across a part of second semiconductor layer 8. Outer body region 13 is preferably formed at a distance from the middle of second semiconductor layer 8 toward first main surface 3. Outer body region 13 preferably has a thickness (depth) substantially equal to the thickness (depth) of body region 12. Outer body region 13 is exposed from first main surface 3.

[0088] 2 to 4 , semiconductor device 1 includes a p-type termination region 39 formed on first main surface 3 in peripheral region 11. Termination region 39 may also be referred to as a "well region," "termination well region," or the like. Termination region 39 may have a p-type impurity concentration approximately equal to the p-type impurity concentration of outer body region 13. The p-type impurity concentration of termination region 39 may be higher than the p-type impurity concentration of outer body region 13, or may be lower than the p-type impurity concentration of outer body region 13.

[0089] The termination region 39 is formed in a region between the periphery of the first main surface 3 and the outer body region 13, with a space inward from the periphery of the first main surface 3. The termination region 39 extends in a band shape along the outer body region 13 in a plan view. The termination region 39 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view, and defines the active region 10 from multiple directions.

[0090] In this embodiment, the termination region 39 surrounds the outer body region 13 in plan view and is defined as a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The termination region 39 has an inner edge on the active region 10 side and an outer edge on the periphery of the first main surface 3. The inner edge of the termination region 39 is connected to the outer edge of the outer body region 13. This fixes the termination region 39 to the same potential as the outer body region 13 and electrically connects it to the multiple body regions 12 via the outer body region 13. The termination region 39 may have an edge that connects the portion extending in the first direction X and the portion extending in the second direction Y in plan view in an arc shape (preferably a quadrant arc shape) ( FIG. 4 ).

[0091] 2 , termination region 39 is formed at a distance from the bottom of second semiconductor layer 8 toward first main surface 3, and faces first semiconductor layer 6 across a part of second semiconductor layer 8. Termination region 39 is preferably formed at a distance from the middle of second semiconductor layer 8 toward first main surface 3. Termination region 39 may have a thickness (depth) substantially equal to the thickness (depth) of outer body region 13.

[0092] The termination region 39 (inner edge portion) has an overlap region 40 that overlaps the outer edge portion of the outer body region 13. The overlap region 40 is a high-concentration region that includes the outer edge portion of the outer body region 13 and the inner edge portion of the termination region 39. In other words, the overlap region 40 includes both the p-type impurity of the outer body region 13 and the p-type impurity of the termination region 39. The overlap region 40 has a p-type impurity concentration that is higher than both the p-type impurity concentration of the outer body region 13 and the p-type impurity concentration of the termination region 39.

[0093] 4 , semiconductor device 1 includes at least one (a plurality of, in this embodiment) outer opening 53 formed in interlayer insulating film 18 in peripheral region 11. The plurality of outer openings 53 are formed in a portion of interlayer insulating film 18 that covers termination region 39. The plurality of outer openings 53 penetrate interlayer insulating film 18 to expose termination region 39. In this embodiment, the plurality of outer openings 53 are formed in a portion of interlayer insulating film 18 that covers overlap region 40 to expose overlap region 40.

[0094] 2 to 4 , semiconductor device 1 includes at least one (preferably two to 20) p-type field region 41 formed in the surface layer portion of first main surface 3 in peripheral region 11. The number of field regions 41 is typically three to eight. In this embodiment, semiconductor device 1 includes three field regions 41. The field regions 41 are formed in an electrically floating state and relieve the electric field within chip 2 at the periphery of first main surface 3. Field region 41 may have a p-type impurity concentration approximately equal to the p-type impurity concentration of body region 12 (termination region 39). The p-type impurity concentration of field region 41 may be higher or lower than the p-type impurity concentration of body region 12 (termination region 39).

[0095] The field regions 41 are formed in strip shapes extending along the active region 10 (termination region 39) in plan view. Each of the field regions 41 has a strip-like portion extending in the first direction X and a strip-like portion extending in the second direction Y. In this embodiment, the field regions 41 are formed in polygonal ring shapes (quadrilateral ring shapes in this embodiment) surrounding the active region 10 (termination region 39) in plan view. The field regions 41 may have edge portions that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) ( FIG. 4 ).

[0096] 2 , the plurality of field regions 41 are formed at intervals from the bottom of the second semiconductor layer 8 toward the first main surface 3, and face the first semiconductor layer 6 across a part of the second semiconductor layer 8. The plurality of field regions 41 are preferably formed at intervals from the middle of the second semiconductor layer 8 toward the first main surface 3.

[0097] 2 and 5B, the semiconductor device 1 includes a peripheral insulating film 42 that covers the first main surface 3 in the peripheral region 11. The peripheral insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the peripheral insulating film 42 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 42 includes a silicon oxide film made of an oxide of the chip 2. The peripheral insulating film 42 is preferably made of the same type of insulating material as the insulating material of the gate insulating film 15. The peripheral insulating film 42 preferably has a thickness approximately equal to that of the gate insulating film 15.

[0098] The peripheral insulating film 42 covers the first main surface 3 in the peripheral region 11 in a film-like manner. The peripheral insulating film 42 collectively covers the outer body region 13, the termination region 39, and the plurality of field regions 41. The peripheral insulating film 42 is connected to the plurality of gate insulating films 15 on the active region 10 side. Specifically, the peripheral insulating film 42 is formed integrally with the plurality of gate insulating films 15, and together with the plurality of gate insulating films 15, forms a single insulating film.

[0099] 4 and 5B , semiconductor device 1 includes underlying wiring 55 arranged on first main surface 3 in peripheral region 11. Underlying wiring 55 is arranged on peripheral insulating film 42 in peripheral region 11. Underlying wiring 55 is an underlying film for gate electrode film 21, and is laid out immediately below gate electrode film 21. Underlying wiring 55 has a portion formed immediately below gate wiring 25.

[0100] The underlying wiring 55 is made of the same material as the gate electrode 16 and is formed integrally with the gate electrode 16. The underlying wiring 55 is an endless or terminated line. The underlying wiring 55 is made of conductive polysilicon. The underlying wiring 55 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both.

[0101] 4 , specifically, the underlying wiring 55 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view, thereby dividing the active region 10 from multiple directions. The underlying wiring 55 has multiple portions connected in a T-shape to the multiple gate electrodes 16. As a result, the underlying wiring 55 is fixed to the same potential as the multiple gate electrodes 16.

[0102] In this embodiment, the underlying interconnect 55 surrounds the active region 10 in a plan view and is defined as a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3. The underlying interconnect 55 may be terminated or endless. In this embodiment, the underlying interconnect 55 extends in a strip shape (a ring shape in this embodiment) along the outer body region 13 in a plan view and faces the outer body region 13 across the outer insulating film 42 over the entire area in the stacking direction. The underlying interconnect 55 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view ( FIG. 4 ).

[0103] The underlying interconnect 55 is formed to be narrower than the outer body region 13 in a plan view, and is disposed on the outer body region 13 at a distance from the inner and outer edges of the outer body region 13. That is, in this embodiment, the plurality of gate electrodes 16 are extended onto the outer body region 13, and the underlying interconnect 55 is connected to the plurality of gate electrodes 16 above the outer body region 13.

[0104] 5B , the width of the underlying interconnect 55 is preferably larger than the width of the gate electrode 16. The width of the underlying interconnect 55 is the width in a direction perpendicular to the extending direction. Of course, the width of the underlying interconnect 55 may be equal to or smaller than the width of the gate electrode 16. The width of the underlying interconnect 55 may be larger than the width of the outer body region 13. The thickness of the underlying interconnect 55 may be approximately equal to the thickness of the gate electrode 16.

[0105] The underlying wiring 55 has one second upper wall 55a and two second side walls 55b. In this embodiment, the second upper wall 55a may extend substantially parallel to the peripheral insulating film 42 (first main surface 3). The second upper wall 55a extends in the vertical direction Z on the peripheral insulating film 42, and the second side walls 55b extend in the vertical direction Z on the peripheral insulating film 42. In other words, the underlying wiring 55 is formed in a quadrangular shape (a flat rectangular shape) in cross section.

[0106] 4 and 5B , a plurality of gate contact openings 54 are formed in the interlayer insulating film 18 directly above the underlying wiring 55. The plurality of gate contact openings 54 penetrate the interlayer insulating film 18. The gate wiring 25 is electrically connected to the underlying wiring 55 via the plurality of gate contact openings 54. A portion of the main electrode film 61 of the underlying wiring 55 extends into the plurality of gate contact openings 54 and is in contact with the underlying wiring 55.

[0107] 2 , 5A and 5B , interlayer insulating film 18 is disposed on first main surface 3 so as to cover both active region 10 and peripheral region 11. Interlayer insulating film 18 covers almost the entire area of ​​active region 10. Interlayer insulating film 18 covers almost the entire area of ​​peripheral region 11. Interlayer insulating film 18 may be formed, for example, over almost the entire first main surface 3.

[0108] 5A and 5B , in this embodiment, the interlayer insulating film 18 has a laminated structure of a first insulating film 50 on the first main surface 3 side and a second insulating film 51 on the main surface electrode film 19 side. The first insulating film 50 may be formed, for example, over almost the entire first main surface 3.

[0109] The first insulating film 50 may also be referred to as a "lower insulating film," a "first intermediate insulating film," a "lower intermediate insulating film," a "first interlayer film," a "lower interlayer film," or the like. The first insulating film 50 is arranged so as to cover both the active region 10 and the peripheral region 11. The first insulating film 50 covers almost the entire active region 10. The first insulating film 50 covers almost the entire peripheral region 11. The first insulating film 50 may be formed, for example, over almost the entire first main surface 3.

[0110] The first insulating film 50 includes a silicon oxide film. The first insulating film 50 is a film formed by low-pressure CVD. The first insulating film 50 is a TEOS film (tetraethyl orthosilicate film) containing TEOS (tetraethyl orthosilicate) as a raw material. Impurities such as phosphorus and boron are not added to the first insulating film 50. The first insulating film 50 has a single-layer structure or a multilayer structure.

[0111] 5A and 5B , the first insulating film 50 includes a plurality of first upper portions 50 a and a plurality of first side portions 50 b. The plurality of first upper portions 50 a cover the first upper wall 16 a of the gate electrode 16 and the second upper wall 55 a of the underlying wiring 55. The plurality of first side portions 50 b cover the first side wall 16 b of the gate electrode 16 and the second side wall 55 b of the underlying wiring 55.

[0112] Each first upper portion 50a has a first upper film thickness T11. The first upper film thickness T11 is, for example, not less than 1000 Å and not more than 2000 Å. The first upper film thickness T11 may have a value belonging to at least one of the ranges of not less than 1000 Å and not more than 1250 Å, not more than 1250 Å, not more than 1500 Å, not more than 1500 Å, not more than 1750 Å, and not more than 1750 Å and not more than 2000 Å.

[0113] Each first side portion 50b has a first lateral thickness T12. The first lateral thickness T12 is, for example, not less than 500 Å and not more than 1500 Å. The first lateral thickness T12 may have a value belonging to at least one of the ranges of not less than 500 Å and not more than 750 Å, not more than 750 Å and not more than 1000 Å, not more than 1000 Å and not more than 1250 Å, and not more than 1250 Å and not more than 1500 Å. The first lateral thickness T12 is preferably, for example, not less than 500 Å and not more than 1000 Å.

[0114] The first film thickness ratio (T12 / T11), which is the ratio of the first lateral film thickness T12 to the first upper film thickness T11, is 0.3 or more and less than 1.0. The first film thickness ratio (T12 / T11) is preferably, for example, 0.3 or more and 0.7 or less. The first film thickness ratio (T12 / T11) may have a value belonging to at least one of the ranges of 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, and 0.6 or more and 0.7 or less. It is particularly preferable that the first film thickness ratio (T12 / T11) be 0.4 or more and 0.6 or less.

[0115] The second insulating film 51 may be referred to as an "upper insulating film," a "second intermediate insulating film," an "upper intermediate insulating film," a "second interlayer film," an "upper interlayer film," or the like. The second insulating film 51 is arranged so as to cover both the active region 10 and the peripheral region 11. The second insulating film 51 covers almost the entire active region 10. The second insulating film 51 covers almost the entire peripheral region 11. The second insulating film 51 may be formed, for example, over almost the entire first main surface 3.

[0116] The second insulating film 51 includes a silicon oxide film. The second insulating film 51 is a P-CVD film formed by a plasma CVD method. The second insulating film 51 is a TEOS (tetraethyl orthosilicate) film containing TEOS (tetraethyl orthosilicate) as a raw material. In this embodiment, the second insulating film 51 preferably includes at least one of a silicon oxide film containing phosphorus (PSG (phosphorus silicate glass) film) and a silicon oxide film containing phosphorus and boron (BPSG (boron phosphorus silicate glass) film). In other words, the second insulating film 51 is doped with impurities such as phosphorus and boron. The second insulating film 51 has a single-layer structure or a multilayer structure.

[0117] 5A and 5B , the second insulating film 51 includes a plurality of second upper portions 51 a and a plurality of second side portions 51 b. The plurality of second upper portions 51 a sandwich the first upper portion 50 a and cover the first upper wall 16 a of the gate electrode 16. The plurality of second upper portions 51 a sandwich the first upper portion 50 a and cover the second upper wall 55 a of the underlying wiring 55.

[0118] The second side portions 51b sandwich the first side portion 50b and cover the first sidewall 16b of the gate electrode 16. The second side portions 51b sandwich the first side portion 50b and cover the second sidewall 55b of the underlying wiring 55.

[0119] Each second upper portion 51a has a second upper film thickness T21. The second upper film thickness T21 is, for example, not less than 4000 Å and not more than 9000 Å. The second upper film thickness T21 may have a value belonging to at least one of the ranges of not less than 4000 Å and not more than 5000 Å, not more than 5000 Å and not more than 6000 Å, not more than 6000 Å and not more than 7000 Å, not more than 7000 Å and not more than 8000 Å. The second upper film thickness T21 is preferably, for example, not less than 5000 Å and not more than 7000 Å.

[0120] The second upper film thickness T21 is greater than the first upper film thickness T11. A third film thickness ratio (T21 / T11) of the second upper film thickness T21 to the first upper film thickness T11 is, for example, 2.0 or more and 9.0 or less. The third film thickness ratio (T21 / T11) may have a value belonging to at least one of the ranges of 2.0 or more and 3.5 or less, 3.5 or more and 5.0 or less, 5.0 or more and 7.0 or less, and 7.0 or more and 9.0 or less.

[0121] Each second side portion 51b has a second lateral thickness T22. The second lateral thickness T22 is, for example, 4000 Å or more and 9000 Å or less. The second lateral thickness T22 may have a value belonging to at least one of the ranges of 4000 Å or more and 5000 Å or less, 5000 Å or more and 6000 Å or less, 6000 Å or more and 7000 Å or less, 7000 Å or more and 8000 Å or more and 9000 Å or less. The second lateral thickness T22 is preferably, for example, 5000 Å or more and 7000 Å or less.

[0122] The second film thickness ratio (T22 / T21), which is the ratio of the second lateral film thickness T22 to the second upper film thickness T21, is, for example, 0.9 or more and 1.1 or less. The second film thickness ratio (T22 / T21) is preferably 0.95 or more and 1.05 or less.

[0123] The second film thickness ratio (T22 / T21) is different from the first film thickness ratio (T12 / T11). The second film thickness ratio (T22 / T21) is greater than the first film thickness ratio (T12 / T11). In other words, the first film thickness ratio (T12 / T11) is smaller than the second film thickness ratio (T22 / T21).

[0124] The ratio ((T22 / T21) / (T12 / T11)) of the second film thickness ratio (T22 / T21) to the first film thickness ratio (T12 / T11) is 1.5 or more and 3.0 or less. The ratio ((T1 / W1) / (T2 / W2)) may have a value belonging to at least one of the ranges of 1.5 or more and 2.0 or less, 2.0 or more and 2.5 or less, and 2.5 or more and 3.0 or less.

[0125] 6 is a schematic diagram showing a SiC wafer 150 used in manufacturing the semiconductor device 1. Referring to FIG. 6, the SiC wafer 150 is a base material of the chip 2 and includes a SiC single crystal. The SiC wafer 150 is formed in a flat disk shape. Of course, the SiC wafer 150 may also be formed in a flat rectangular parallelepiped shape. The SiC wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.

[0126] The first wafer main surface 151 corresponds to the first main surface 3 of the chip 2 (see, for example, FIG. 5A ), and the second wafer main surface 152 corresponds to the second main surface 4 of the chip 2 (see, for example, FIG. 5A ). The first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of the SiC single crystal. The first wafer main surface 151 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 152 is formed by the carbon surface of the SiC single crystal. The SiC wafer 150 (the first wafer main surface 151 and the second wafer main surface 152) has the off-direction and off-angle described above.

[0127] The SiC wafer 150 has a mark 154 on the wafer side surface 153 that indicates the crystal orientation of the SiC single crystal. The mark 154 may include either or both of an orientation flat and an orientation notch. The orientation flat is a cutout that is linearly cut out in a plan view. The orientation notch is a cutout that is concave (e.g., tapered) toward the center of the first wafer main surface 151 in a plan view.

[0128] The mark 154 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The mark 154 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0129] The SiC wafer 150 includes a second semiconductor layer 8 (see FIG. 7A , etc., which will be described next) in a region (surface layer portion) on the first wafer main surface 151 side. The second semiconductor layer 8 is formed in a layer shape extending along the first wafer main surface 151. In this embodiment, the second semiconductor layer 8 is made of an epitaxial layer (specifically, a SiC epitaxial layer). An n-type drift region 9 is formed in the second semiconductor layer 8.

[0130] The SiC wafer 150 includes a first semiconductor layer 6 (see FIG. 7A , etc., which will be described next) in a region (surface layer portion) on the second wafer main surface 152 side. The first semiconductor layer 6 is formed in a layer shape extending along the second main surface 4 and is electrically connected to the first semiconductor layer 6. In this embodiment, the first semiconductor layer 6 is made of the wafer main body (specifically, the SiC wafer). That is, in this embodiment, the SiC wafer 150 is made of an epitaxial wafer (a so-called epiwafer) having a layered structure including the wafer main body and an epitaxial layer.

[0131] For example, a plurality of device regions 155 and a plurality of cutting lines 156 are set on the SiC wafer 150 by alignment marks or the like. Each device region 155 corresponds to a semiconductor device 1. Each of the plurality of device regions 155 is set to have a quadrangular shape in a plan view.

[0132] In this embodiment, the multiple device regions 155 are set in a matrix along the first direction X and the second direction Y in a plan view. The multiple device regions 155 are set at intervals inward from the periphery of the first wafer main surface 151 in a plan view. The multiple cutting lines 156 are set in a grid pattern extending along the first direction X and the second direction Y to partition the multiple device regions 155.

[0133] 7A to 7J are cross-sectional views illustrating a method for manufacturing the semiconductor device 1. FIGS. 7A to 7J illustrate a portion of the active region 10 of one device region 155 (FIG. 6). FIGS. 7A to 7J correspond to the cross section (part of the active region 10) of FIG. 5A. FIG. 8 is a flow diagram illustrating the procedure for forming an insulating film according to the first embodiment. FIG. 9 is a schematic cross-sectional view illustrating a vertical section of a low-pressure CVD apparatus 100 used in the low-pressure CVD method. FIG. 10 is a schematic cross-sectional view illustrating a vertical section of a plasma CVD apparatus 120 used in the plasma CVD method. FIG. 11 is a timing chart illustrating an example of on / off switching of dual frequencies in the plasma CVD method. FIG. 12 is a timing chart illustrating another example of on / off switching of dual frequencies in the plasma CVD method.

[0134] Referring to FIG. 7A , first, the aforementioned SiC wafer 150 is prepared. Next, referring to FIG. 7B , a base mask 160 is formed on the first wafer main surface 151. The base mask 160 is preferably an inorganic mask (i.e., a hard mask). The base mask 160 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the base mask 160 is made of a silicon oxide film (insulating film) and may be formed by a chemical vapor deposition (CVD) method. Next, the base mask 160 is patterned to form a base opening 161. The base opening 161 selectively exposes a region of the first wafer main surface 151 where the body region 12 is to be formed.

[0135] Next, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation via the base mask 160. As a result, a plurality of body regions 12 are formed.

[0136] 7C , sidewalls 162 are selectively formed on the first wafer main surface 151 to cover the base mask 160 and the body region 12. The sidewalls 162 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the sidewalls 162 may be made of a silicon oxide film. The sidewalls 162 may be formed by a CVD method.

[0137] Next, a first mask 163 is formed on the first wafer main surface 151. The first mask 163 may be formed using an organic material. The organic material may include a positive or negative photosensitive resin film (i.e., a resist film). Of course, the first mask 163 may be formed using an inorganic material (for example, a silicon oxide film, a silicon nitride film, a polysilicon film, etc.). Next, the first mask 163 is patterned to form a first opening 164. The first opening 164 selectively exposes a region of the first wafer main surface 151 where the source region 46 is to be formed.

[0138] Next, n-type impurities are selectively introduced into the surface layer of the body region 12 by ion implantation via the first mask 163, thereby forming the source region 46. After the source region 46 is formed, the first mask 163 is removed. The source region 46 defines a channel region 47.

[0139] 7D , a second mask 165 is formed on the first wafer main surface 151. The second mask 165 may be formed using an organic material. The organic material may include a positive or negative photosensitive resin film (i.e., a resist film). Of course, the second mask 165 may be formed using an inorganic material (e.g., a silicon oxide film, a silicon nitride film, a polysilicon film, etc.). Next, the second mask 165 is patterned to form a second opening 166. The second opening 166 selectively exposes a region of the first wafer main surface 151 where the body contact region 48 is to be formed.

[0140] Next, n-type impurities are selectively introduced into the surface layer of the body region 12 by ion implantation via the second mask 165, thereby forming the body contact region 48. After the body contact region 48 is formed, the second mask 165, the base mask 160, and the sidewall 162 are removed.

[0141] 7E, a base insulating film 167 is formed to cover the first wafer main surface 151. The base insulating film 167 is the base of the gate insulating film 15 (FIG. 5A) and the peripheral insulating film 42 (FIG. 5B). The base insulating film 167 may be formed by a CVD method or an oxidation treatment method (for example, a thermal oxidation treatment method).

[0142] Next, referring to FIG. 7F , a base electrode 168 is formed on the base insulating film 167. The base electrode 168 is the base of the gate electrode 16 and the underlying wiring 55 ( FIG. 5B ). The base electrode 168 is made of conductive polysilicon. The base electrode 168 may be formed by a CVD method. Next, the base electrode 168 is patterned. As a result, the gate electrode 16 is formed in the active region 10, and the underlying wiring 55 ( FIG. 5B ) is formed in the peripheral region 11.

[0143] Next, referring to FIG. 7G, a first insulating film 50 is formed on the first wafer main surface 151. As a result, the first insulating film 50 is formed so as to contact the gate electrode 16 and the underlying wiring 55 (FIG. 5B). The first insulating film 50 is formed by a low-pressure CVD method. The first insulating film 50 includes a plurality of first upper portions 50a and a plurality of first side portions 50b. Each of the first upper portions 50a has a first upper film thickness T11. Each of the first side portions 50b has a first lateral film thickness T12.

[0144] 7H , a second insulating film 51 is formed on the first insulating film 50. The second insulating film 51 is formed by plasma CVD. The second insulating film 51 includes a plurality of second upper portions 51 a and a plurality of second side portions 51 b. Each second upper portion 51 a has a second upper film thickness T21. Each second side portion 51 b has a second lateral film thickness T22. By forming the second insulating film 51, an interlayer insulating film 18 including a stacked structure of the first insulating film 50 and the second insulating film 51 is formed (insulating film forming step).

[0145] 8, in the formation of interlayer insulating film 18 (insulating film forming step), first, first insulating film 50 is formed by low-pressure CVD (step S1 in FIG. 8). Formation of first insulating film 50 by low-pressure CVD is performed using low-pressure CVD apparatus 100 shown in FIG. 9. In this low-pressure CVD, TEOS (tetraethyl orthosilicate) is used as a raw material, and phosphorus or boron is not added to the raw material (LP TEOS).

[0146] 9 , the low-pressure CVD apparatus 100 is a batch-type apparatus for processing a plurality of SiC wafers 150 at once. The low-pressure CVD apparatus 100 includes a box-shaped chamber 101 having an internal space, a holding unit 102 for holding the plurality of SiC wafers 150 in a horizontal position within the internal space of the chamber 101, a source supply unit for supplying a source material (e.g., a source gas) into the chamber 101, a decompression unit for decompressing the internal space of the chamber 101, and a heater 103 for heating the plurality of SiC wafers 150 from outside the chamber 101. The chamber 101 includes a cylindrical inner tube 104 and an outer tube 105 surrounding the upper and sides of the inner tube 104. The inner tube 104 and the outer tube 105 may be made of quartz. The holding unit 102 includes a vertical holder 107 that holds a plurality of SiC wafers 150 stacked vertically, and a support table 106 that supports the vertical holder 107 from below. The raw material supply unit includes a supply pipe 108 that introduces raw material from a raw material supply source into the internal space of the chamber 101. The decompression unit includes a decompression pipe 109 and a vacuum pump 110 that is connected to the internal space of the chamber 101 via the decompression pipe 109.

[0147] The SiC wafer 150 with the gate electrode 16 formed in the active region 10 (as shown in FIG. 7F ) is carried into the internal space of the chamber 101. The internal space of the chamber 101 is depressurized by the depressurization unit and kept at a predetermined low pressure, and the internal space of the chamber 101 is kept at a predetermined high temperature by heating by the heater 103. In this state, raw materials are supplied from the raw material supply unit to the internal space of the chamber 101, whereby a silicon oxide film (SiO ２ As a result, as shown in FIG. 7G, a first insulating film 50 is formed on the first wafer main surface 151 of the SiC wafer 150. When a predetermined film formation time has elapsed since the start of film formation, a silicon oxide film (SiO ２ After that, the SiC wafer 150 is unloaded from the chamber 101.

[0148] The low-pressure CVD apparatus 100 is equipped with a cleaning unit. The cleaning unit includes a clean gas supply pipe 111 for supplying clean gas from a clean gas supply source into the chamber 101, a clean gas exhaust pipe 112 for exhausting the clean gas from the chamber 101, and an opening / closing valve 113 for opening and closing the clean gas exhaust pipe 112. The low-pressure CVD apparatus 100 is equipped with a cleaning function. After the SiC wafer 150 is unloaded from the chamber 101, the low-pressure CVD apparatus 100 uses the cleaning unit to clean the inside of the chamber 101.

[0149] 8, after the formation of the first insulating film 50, a second insulating film 51 is then formed by a plasma CVD (P-CVD) method (step S2 in FIG. 8). The formation of the second insulating film 51 by the plasma CVD method is carried out using a plasma CVD apparatus 120 shown in FIG. 10. In this plasma CVD method, TEOS (tetraethyl orthosilicate) is used as a raw material. In this plasma CVD method, at least one of phosphorus and boron is added to the raw material (P-CVD (PSG and / or BPSG)).

[0150] Referring to FIG. 10 , the plasma CVD apparatus 120 is a single-wafer processing apparatus that processes SiC wafers 150 one by one. The plasma CVD apparatus 120 includes a box-shaped chamber 121 having an internal space, a lower electrode 122 accommodated in the internal space of the chamber 121, an upper electrode 123 facing upward relative to the lower electrode 122 in the internal space of the chamber 121, a raw material supply unit for supplying raw materials into the chamber 121, and a decompression unit for decompressing the internal space of the chamber 121. The lower electrode 122 includes a stage 127 that supports the SiC wafer 150 from below and a rod 126 extending downward from the stage 127. A portion of the rod 126 is exposed to the external space of the chamber 121 and is grounded. A number of discharge ports 130 are formed on the lower surface of the upper electrode 123. The raw material supply unit supplies raw materials from a raw material supply source to the internal space of the chamber 121 via supply pipes 131 and the discharge ports 130. A high frequency (first frequency, e.g., 13.6 MHz) power supply 128 and a low frequency (first frequency, e.g., 400 kHz) power supply 129 are connected to the upper electrode 123. The decompression unit includes a decompression pipe 132 and a vacuum pump 133 connected to the internal space of the chamber 121 via the decompression pipe 132.

[0151] An SiC wafer 150 with a first insulating film 50 formed on a first wafer main surface 151 (the state shown in FIG. 7G ) is loaded into the internal space of the chamber 121. With the internal space of the chamber 121 decompressed by the decompression unit and maintained at a predetermined low pressure, a high frequency (first frequency, e.g., 13.6 MHz) is applied between the electrodes by the high frequency power supply 128. Also, with the internal space of the chamber 121 maintained at the above-mentioned low pressure, a low frequency (second frequency, e.g., 400 kHz) is applied between the electrodes by the high frequency power supply 128. This generates plasma in the chamber 121, and the raw material is converted into plasma. In this configuration, two frequencies, a high frequency and a low frequency, are applied between the electrodes.

[0152] 11, discharges using two frequencies may be performed in a superimposed manner. Specifically, application of a high frequency wave from a high frequency power supply (HF) 128 and application of a low frequency wave from a low frequency power supply (HF) 129 may be performed in parallel (simultaneously).

[0153] 12, discharges using two frequencies may be performed alternately. Specifically, application of a high frequency wave from a high frequency power supply (HF) 128 and application of a low frequency wave from a low frequency power supply (HF) 129 may be performed alternately.

[0154] As a result, a silicon oxide film (SiO ２ As a result, as shown in FIG. 7H, a second insulating film 51 is formed on the first insulating film 50. When a predetermined film formation time has elapsed since the start of film formation, a silicon oxide film (SiO ２ After that, the SiC wafer 150 is unloaded from the chamber 121.

[0155] The plasma CVD apparatus 120 is equipped with a cleaning unit, which includes a clean gas supply pipe 134 for supplying clean gas from a clean gas supply source into the chamber 121, a clean gas exhaust pipe 135 for exhausting the clean gas from the inside of the chamber 101, and an opening / closing valve 136 for opening and closing the clean gas exhaust pipe 112.

[0156] The plasma CVD apparatus 120 has a cleaning function. After the SiC wafer 150 is unloaded from the chamber 121, the plasma CVD apparatus 120 cleans the inside of the chamber 121 using a cleaning unit.

[0157] After the second insulating film 51 is formed, a reflow process (heat treatment process) is performed on the second insulating film 51 containing at least one of PSG and BPSG. This allows the corners of the second insulating film 51 to be rounded (smoothed). As a result, the adhesion of the main-surface electrode film 19 and the surface insulating film 34 to the interlayer insulating film 18 (second insulating film 51) can be improved.

[0158] 7I, a third mask having a predetermined layout is placed on interlayer insulating film 18. The third mask exposes regions where a plurality of source contact openings 52 are to be formed and covers other regions. Next, unnecessary portions of interlayer insulating film 18 and unnecessary portions of base insulating film 167 are removed by etching using the third mask.

[0159] In this step, unnecessary portions of the interlayer insulating film 18 and unnecessary portions of the base insulating film 167 are removed in this order. The etching method may be wet etching and / or dry etching. The etching method is preferably anisotropic dry etching (e.g., RIE (Reactive Ion Etching)).

[0160] By removing the unnecessary portions of the interlayer insulating film 18, a plurality of source contact openings 52 and a plurality of gate contact openings 54 (FIG. 5B) are formed in the interlayer insulating film 18. By removing the unnecessary portions from the base insulating film 167, the gate insulating film 15 and the peripheral insulating film 42 (FIG. 5B) are formed. The third mask is then removed.

[0161] 7J, the lower electrode film 60 is formed on the interlayer insulating film 18. The lower electrode film 60 may be formed by sputtering or vapor deposition.

[0162] Next, a main electrode film 61 is formed on the lower electrode film 60. The main electrode film 61 is formed by sputtering. This results in the formation of a source pad electrode 22 (source electrode film 20). The source pad electrode 22 (source electrode film 20) is electrically connected to the plurality of body regions 12 via the source contact openings 52.

[0163] Thereafter, a surface insulating film 34 ( FIG. 2 ) is selectively formed on the surface of the source pad electrode 22 (source electrode film 20). Thereafter, a drain pad electrode 7 ( FIG. 5A , etc.) is formed on the second wafer main surface 152. The drain pad electrode 7 may be formed by sputtering or vapor deposition. Then, the SiC wafer 150 is cut along the cutting lines 156, and a plurality of semiconductor devices 1 are cut out. The semiconductor device 1 is manufactured through the processes including those described above.

[0164] The interlayer insulating film 18 (silicon oxide film) covering the gate electrode 16 made of polysilicon and the underlying wiring 55 is sometimes called a PMD film.

[0165] Conventionally, these PMD films have generally been formed by atmospheric pressure CVD (a type of thermal CVD) using an atmospheric pressure CVD apparatus. This is because the gate electrode 16 and underlying wiring 55 are made of polysilicon. If a PMD film were to be formed by radio frequency plasma CVD, it was thought that the gate electrode 16 and underlying wiring 55, both made of polysilicon, might be damaged by radio frequency plasma, and therefore, the PMD film has not been formed by radio frequency plasma CVD.

[0166] However, silicon oxide films formed by atmospheric pressure CVD have the problem of being relatively rough (not dense) and also have the problem of poor conformability to the shape of the substrate on which they are formed.

[0167] In contrast, in the semiconductor device 1 according to the first embodiment, the interlayer insulating film (PMD film) 18 has a laminated structure of a first insulating film 50 and a second insulating film 51. The upper second insulating film 51 is a P-CVD film formed by plasma CVD.

[0168] That is, when the formation of the second insulating film 51 by the plasma CVD method begins, the wall surfaces 16a and 16b of the gate electrode 16 and the wall surfaces 55a and 55b of the underlying wiring 55 are already covered with the first insulating film 50. Therefore, the plasma generated during the plasma CVD method is not directly supplied to the gate electrode 16 and the underlying wiring 55. This allows the interlayer insulating film 18 including the P-CVD film to be formed while avoiding damage to the gate electrode 16 and the underlying wiring 55. Furthermore, the P-CVD film is a dense film and has high conformability to the shape of the substrate. This allows the formation of a high-quality interlayer insulating film 18 (PMD film) that covers the conductive structure while avoiding damage caused by high-frequency plasma.

[0169] However, atmospheric pressure CVD also has the problem that particles are easily generated when forming silicon oxide films using atmospheric pressure CVD equipment. The generation of particles can be suppressed if workers clean the chamber after each film formation in the atmospheric pressure CVD equipment. However, this places a heavy burden on workers for maintenance.

[0170] In contrast, in the first embodiment, the low-pressure CVD apparatus 100 is used to form the first insulating film 50 that contacts (directly covers) the gate electrode 16 and the underlying wiring 55, and then the plasma CVD apparatus 120 is used to form the second insulating film 51. In other words, in the first embodiment, an atmospheric pressure CVD apparatus is not used to form the interlayer insulating film 18 (PMD film). In the low-pressure CVD apparatus 100 and the plasma CVD apparatus 120, the chambers 101 and 121 are depressurized during film formation, so there is little residual raw material in the chambers 101 and 121, and there is little particle generation to begin with. In addition, the low-pressure CVD apparatus 100 and the plasma CVD apparatus 120 have cleaning functions. This reduces the maintenance burden on workers.

[0171] Furthermore, in the first embodiment, the silicon oxide film is formed using two frequencies, a high frequency (first frequency) and a low frequency (second frequency), in the plasma CVD method. In this case, the influence on the substrate on which the film is formed can be reduced compared to when only high frequency is used. Therefore, the interlayer insulating film 18 (PMD film) having a P-CVD film can be formed while further preventing damage to the gate electrode 16 and the underlying wiring 55.

[0172] The second insulating film 51 is a film (TEOS film) formed using TEOS as a raw material. Using TEOS as a raw material facilitates film control. Therefore, the interlayer insulating film 18 (PMD film) can be formed as a precise film.

[0173] 13 to 16, variations in the composition of the interlayer insulating film 18 will be described. 13 to 16 are diagrams showing first to fourth aspects of the composition of the interlayer insulating film 18, respectively. The interlayer insulating film 18 included in the semiconductor device 1 includes a first insulating film 50 and a second insulating film 51.

[0174] 13, the first insulating film 50 is a film (LP-TEOS film) formed by low-pressure CVD using TEOS as a raw material. The second insulating film 51 is a film (P-TEOS film) formed by plasma CVD using TEOS as a raw material, and contains at least one of PSG and BPSG (including PSG and / or BPSG).

[0175] 14, the first insulating film 50 is a film (LP-TEOS film) formed by low-pressure CVD using TEOS as a raw material. The second insulating film 51 is a film (P-TEOS film) formed by plasma CVD using TEOS as a raw material. The second insulating film 51 is not doped with phosphorus or boron. In other words, the second insulating film 51 does not contain PSG or BPSG.

[0176] Referring to FIG. 15, the first insulating film 50 is a film formed by low pressure CVD (LP-SiO ２ The first insulating film 50 is made of silane (SiH ４The second insulating film 51 is a film (P-TEOS film) formed by plasma CVD using TEOS as a raw material, and contains at least one of PSG and BPSG (including PSG and / or BPSG).

[0177] Referring to FIG. 16, the first insulating film 50 is a film formed by low pressure CVD (LP-SiO ２ The first insulating film 50 is formed using silane as a raw material instead of TEOS. The second insulating film 51 is a film (P-SiO ２ The second insulating film 51 is formed using silane as a raw material instead of TEOS. The second insulating film 51 includes at least one of PSG and BPSG (including PSG and / or BPSG).

[0178] 17 is a cross-sectional view showing a second embodiment of the device structure. Referring to FIG. 17 , in the transistor structure Tr of the semiconductor device 1 of this embodiment, the first sidewalls 16b of each gate electrode 16 are inclined obliquely with respect to the first top wall 16a. That is, each gate electrode 16 is formed in a tapered shape (preferably an isosceles trapezoid) in cross-sectional view. Specifically, the two first sidewalls 16b form an obtuse angle with the first top wall 16a. The angle θ formed between the first top wall 16a and the first sidewalls 16b is greater than 90° and not greater than 135°. Preferably, the angle θ is greater than 90° and not greater than 120°.

[0179] The first insulating film 50 has a plurality of first side portions 50b formed along the plurality of first sidewalls 16b. Each first side portion 50b has a third lateral thickness T32. The third lateral thickness T32 is, for example, not less than 750 Å and not more than 2000 Å. The third lateral thickness T32 is preferably, for example, not less than 750 Å and not more than 1500 Å.

[0180] The thickness ratio (T32 / T11), which is the ratio of the third lateral thickness T32 to the first upper thickness T11, is 0.5 or more and less than 1.0. The thickness ratio (T32 / T11) is preferably, for example, 0.5 or more and 0.8 or less. The thickness ratio (T32 / T11) is particularly preferably 0.6 or more and 0.7 or less.

[0181] The semiconductor device 1 according to the second embodiment of the device structure (the semiconductor device 1 according to the embodiment shown in FIG. 17) can also achieve the same effects as the semiconductor device 1 according to the aforementioned embodiments (the embodiments of FIGS. 1 to 16).

[0182] 18 is a cross-sectional view showing a third embodiment of the device structure, in which a transistor structure Tr of a semiconductor device 1 of this embodiment has a trench gate type vertical structure (trench structure).

[0183] The semiconductor device 1 includes a plurality of trenches 76 formed in the first major surface 3. Between adjacent trenches 76, mesa portions 77 are formed by portions of the second semiconductor layer 8. The mesa portions 77 are strip-shaped extending along the first direction X and arranged alternately in the second direction Y. The plurality of trenches 76 and the plurality of mesa portions 77 are arranged in a stripe pattern as a whole. Each mesa portion 77 provides a unit cell UC of a trench-gate transistor. Each mesa portion 77 includes at least a body region 12 and a source region 46, and may be the minimum unit functioning as a MIS transistor. The body region 12 and the source region 46 are formed in order in the mesa portion 77 from the bottom of the trench 76 toward the first major surface 3.

[0184] The semiconductor device 1 includes a trench insulating film 78 that covers the inner surface of the trench 76. The trench insulating film 78 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 78 has a single-layer structure made of a silicon oxide film. The trench insulating film 78 may also include a silicon oxide film made of an oxide of the chip 2.

[0185] The semiconductor device 1 includes a gate electrode 79, which is an example of a conductive structure, buried in the trench 76 via a trench insulating film (gate insulating film) 78. The gate electrode 79 faces the body region 12 (channel region 47) across the trench insulating film 78. The gate electrode 79 may include p-type or n-type conductive polysilicon.

[0186] The semiconductor device 1 according to the third embodiment of the device structure (the semiconductor device 1 according to the embodiment shown in FIG. 18) can also achieve the same effects as the semiconductor device 1 according to the above-described embodiments (the embodiments shown in FIGS. 1 to 16).

[0187] Fig. 19A is a diagram showing a semiconductor device 201 according to a second embodiment of the present disclosure, showing a cross section taken at the same position as Fig. 5A. Fig. 19B is a diagram showing a semiconductor device 201 according to the second embodiment of the present disclosure, showing a cross section taken at the same position as Fig. 5B. In the following description, configurations common to the first embodiment will be denoted by the same reference numerals, and description thereof will be omitted.

[0188] 19A and 19B , the semiconductor device 201 includes an interlayer insulating film 218 as an example of an insulating film, instead of the interlayer insulating film 18. The interlayer insulating film 218 may be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. The interlayer insulating film 218 may also be referred to as a PMD (Pre-Metal Dielectric) film. The interlayer insulating film 218 includes a second insulating film 51. The second insulating film 51 is a P-CVD film formed by a plasma CVD method. The interlayer insulating film 218 does not include a film formed by a low-pressure CVD method. Of course, the interlayer insulating film 218 does not include a film formed by an atmospheric pressure CVD method (or a sub-atmospheric pressure CVD method).

[0189] The interlayer insulating film 218 covers the gate electrodes 16 and the underlying interconnections 55. The second insulating film 51 is in contact with the first upper wall 16a and the first side wall 16b of the gate electrode 16. The second insulating film 51 is in contact with the second upper wall 55a and the second side wall 55b of the underlying interconnections 55.

[0190] The second insulating film 51 includes a plurality of second upper portions 51 a and a plurality of second side portions 51 b. The plurality of second upper portions 51 a contact the first upper wall 16 a of the gate electrode 16. The plurality of second upper portions 51 a contact the second upper wall 55 a of the underlying wiring 55.

[0191] The second side portions 51b are in contact with the first sidewall 16b of the gate electrode 16. The second side portions 51b are in contact with the second sidewall 55b of the underlying wiring 55.

[0192] The second film thickness ratio (T22 / T21), which is the ratio of the second lateral film thickness T22 to the second upper film thickness T21, is, for example, 0.9 or more and 1.1 or less. The second film thickness ratio (T22 / T21) is preferably 0.95 or more and 1.05 or less.

[0193] 20A to 20C are cross-sectional views showing a method for manufacturing a semiconductor device 201. Each of the cross-sections shows a portion of an active region 10 in one device region 155 (FIG. 6). FIG. 21 is a flow chart showing the flow of an insulating film formation process according to the second embodiment.

[0194] 7B to 7F are sequentially performed on the SiC wafer 150. In the step shown in FIG. 7F, a gate electrode 16 and an underlying wiring 55 (FIG. 5B) are formed on the first wafer main surface 151 of the SiC wafer 150.

[0195] 20A, a second insulating film 51 is formed on the first wafer main surface 151. As a result, the second insulating film 51 is formed so as to contact the gate electrode 16 and the underlying wiring 55 (FIG. 5B). The second insulating film 51 is formed by a plasma CVD method. The second insulating film 51 includes a plurality of second upper portions 51a and a plurality of second side portions 51b. Each second upper portion 51a has a second upper film thickness T21. Each second side portion 51b has a second lateral film thickness T22.

[0196] 21, in this embodiment, the interlayer insulating film 218 is formed by forming the second insulating film 51 by plasma CVD (step S11 in FIG. 21). That is, the insulating film formation process is realized only by forming the second insulating film 51 by plasma CVD. The formation of the second insulating film 51 by plasma CVD is performed using the plasma CVD apparatus 120 shown in FIG. 10. In this plasma CVD method, TEOS (tetraethyl orthosilicate) is used as a raw material. In this plasma CVD method, at least one of phosphorus and boron is added to the raw material (P-CVD (PSG and / or BPSG)). Details of the plasma CVD method have already been explained, so they will not be described here.

[0197] After the second insulating film 51 is formed, a reflow process (heat treatment process) is performed on the second insulating film 51 containing at least one of PSG and BPSG. This allows the corners of the second insulating film 51 to be rounded (smoothed). As a result, the adhesion of the main surface electrode film 19 and the surface insulating film 34 to the interlayer insulating film 218 (second insulating film 51) can be improved.

[0198] 20B , a third mask having a predetermined layout is placed on interlayer insulating film 218. The third mask exposes regions where source contact openings 52 are to be formed and covers other regions. Next, unnecessary portions of interlayer insulating film 218 and unnecessary portions of base insulating film 167 are removed by etching using the third mask.

[0199] In this step, unnecessary portions of the interlayer insulating film 218 and unnecessary portions of the base insulating film 167 are removed in this order. The etching method may be wet etching and / or dry etching. The etching method is preferably anisotropic dry etching (e.g., RIE (Reactive Ion Etching)).

[0200] By removing unnecessary portions of the interlayer insulating film 218, a plurality of source contact openings 52 are formed in the interlayer insulating film 218. By removing unnecessary portions from the base insulating film 167, the gate insulating film 15 and the peripheral insulating film 42 are formed. The third mask is then removed. Next, referring to FIG. 20C , a lower electrode film 60 is formed on the interlayer insulating film 218. The lower electrode film 60 may be formed by sputtering or vapor deposition.

[0201] Next, a main electrode film 61 is formed on the lower electrode film 60. The main electrode film 61 is formed by sputtering. This results in the formation of a source pad electrode 22 (source electrode film 20). The source pad electrode 22 (source electrode film 20) is electrically connected to the plurality of body regions 12 via the source contact openings 52.

[0202] Thereafter, a surface insulating film 34 ( FIG. 2 ) is selectively formed on the surface of the source pad electrode 22 (source electrode film 20). Thereafter, a drain pad electrode 7 ( FIG. 19A , etc.) is formed on the second wafer main surface 152. The drain pad electrode 7 may be formed by sputtering or vapor deposition. Then, the SiC wafer 150 is cut along the cutting lines 156 to cut out a plurality of semiconductor devices 201. Through the steps including those described above, the semiconductor device 201 is manufactured.

[0203] In the semiconductor device 201 according to the second embodiment, the interlayer insulating film (PMD film) 218 ​​includes a second insulating film 51 made of a P-CVD film formed by a plasma CVD method. When the formation of the second insulating film 51 by the plasma CVD method starts, the wall surfaces 16 a and 16 b of the gate electrode 16 and the wall surfaces 55 a and 55 b of the underlying wiring 55 are exposed.

[0204] However, in the plasma CVD method according to the second embodiment, the silicon oxide film is formed using two frequencies, a high frequency (first frequency) and a low frequency (second frequency). In this case, the influence on the substrate can be reduced compared to when only high frequency is used. Therefore, the interlayer insulating film 218 (PMD film) having a P-CVD film can be formed while avoiding damage to the gate electrode 16 and the underlying wiring 55.

[0205] In addition, the same effects as those described in the first embodiment (the embodiment shown in FIGS. 1 to 16) are achieved.

[0206] 22 to 24, variations in the composition of the interlayer insulating film 218 will be described. 22 to 24 are diagrams showing fifth to seventh aspects of the composition of the interlayer insulating film 218, respectively. The interlayer insulating film 218 included in the semiconductor device 201 includes a second insulating film 51.

[0207] Referring to FIG. 22, the second insulating film 51 (interlayer insulating film 218) is a film (P-TEOS film) formed by plasma CVD using TEOS as a raw material, and contains at least one of PSG and BPSG (including PSG and / or BPSG).

[0208] 23, second insulating film 51 (interlayer insulating film 218) is a film (P-TEOS film) formed by plasma CVD using TEOS as a raw material. Second insulating film 51 is not doped with phosphorus or boron. That is, second insulating film 51 does not contain PSG or BPSG.

[0209] Referring to FIG. 24, the second insulating film 51 (interlayer insulating film 218) is a film (P—SiO ２ The second insulating film 51 is formed using silane as a raw material instead of TEOS. The second insulating film 51 includes at least one of PSG and BPSG (including PSG and / or BPSG).

[0210] Although the embodiments of the present disclosure have been described above, the present disclosure can be embodied in other forms.

[0211] For example, in the above-described embodiment, the configuration in which the plurality of unit cells UC are arranged in a stripe pattern has been described as an example, but in the transistor structure Tr, the plurality of unit cells UC are not limited to being arranged in a stripe pattern.

[0212] For example, a plurality of unit cells UC may be arranged in a matrix (rows and columns). In this case, the gate electrodes 16 may be arranged in a lattice pattern. That is, the plurality of unit cells UC may be partitioned into a matrix by the lattice-shaped gate electrodes 16.

[0213] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0214] [Supplementary Note 1-1] The present invention includes a SiC chip (2) having a first main surface (3) on which an active region (10) is formed and a second main surface (4) opposite to the first main surface (3); a device structure (Tr) formed in the active region (10) and including a plurality of conductive structures (16, 79) made of polysilicon; an insulating film (18) formed on the first main surface (3) so as to cover the conductive structures (16, 79); and a main surface electrode (22) covering the conductive structures (16, 79) via the insulating film (18), wherein the insulating film (18) has a stacked structure of a first insulating film (50) on the first main surface (3) side and a second insulating film (51) on the main surface electrode (22) side, a first thickness ratio (T12 / T11) of a first lateral thickness (T12), which is the thickness of a portion of the first insulating film (50) covering a first side wall (16b) of the conductive structure (16), to a first upper thickness (T11), which is the thickness of a portion of the first insulating film (50) covering a first upper wall (16a) of the conductive structure (16, 79), is different from a second thickness ratio (T22 / T21) of a second lateral thickness (T22), which is the thickness of a portion of the second insulating film (51) covering the first side wall (16b), to a second upper thickness (T21), which is the thickness of a portion of the second insulating film (51) covering the first upper wall (16a).

[0215] [Supplementary Note 1-2] The semiconductor device (1) according to Supplementary Note 1-1, wherein the first film thickness ratio (T12 / T11) is smaller than the second film thickness ratio (T22 / T21).

[0216] [Appendix 1-3] The semiconductor device (1) according to appendix 1-1 or appendix 1-2, wherein the first film thickness ratio (T12 / T11) is equal to or greater than 0.3 and less than 1.0.

[0217] [Appendix 1-4] The semiconductor device (1) according to any one of Appendices 1-1 to 1-3, wherein the second upper film thickness (T12) is greater than the first upper film thickness (T11).

[0218] [Appendix 1-5] The semiconductor device (1) according to any one of appendix 1-1 to appendix 1-4, wherein a third film thickness ratio (T21 / T11) of the second upper film thickness (T21) to the first upper film thickness (T11) is 2.0 or more and 9.0 or less.

[0219] [Appendix 1-6] The semiconductor device (1) according to any one of appendices 1-1 to 1-5, wherein the first upper film thickness (T11) of the first insulating film (50) is 1000 Å or more and 2000 Å or less.

[0220] [Supplementary Note 1-7] The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-6, wherein the plurality of conductive structures (16) are formed in a stripe pattern.

[0221] [Appendix 1-8] The semiconductor device (1) according to any one of Appendices 1-1 to 1-7, wherein the second insulating film (51) contains at least one of phosphosilicate glass and borophosphosilicate glass.

[0222] [Appendix 1-9] The semiconductor device (1) according to appendix 1-8, wherein the first insulating film (50) does not contain phosphosilicate glass or borophosphosilicate glass.

[0223] [Supplementary Note 1-10] The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-9, including a planar structure including a first impurity region (9) of a first conductivity type formed in a surface layer portion of the first main surface (3), wherein the device structure (Tr) further includes a second impurity region (12) of a second conductivity type formed in a surface layer portion of the first impurity region (9) and a third impurity region (46) of the first conductivity type formed in an inner region of the second impurity region (12), and wherein the conductive structure includes a gate electrode (16) facing the second impurity region (12) via a gate insulating film (15).

[0224] [Supplementary Note 1-11] The semiconductor device (1) according to any one of Supplementary Note 1-1 to Supplementary Note 1-9, including a trench structure including a first impurity region (9) of a first conductivity type formed in a surface layer portion of the first main surface (3), wherein the device structure (Tr) further includes a trench (76) defining a mesa portion (77), and a second impurity region (12) of a second conductivity type and a third impurity region (46) of the first conductivity type formed in the mesa portion (77) in this order in a direction from a bottom of the trench (76) toward the first main surface (3), and wherein the conductive structure includes a gate electrode (79) buried in the trench (76) via a gate insulating film (78).

[0225] [Appendix 1-12] A method for manufacturing a semiconductor device (1, 201), comprising: a step of preparing a SiC wafer (150) having a wafer main surface (151); a step of forming a device structure (Tr) on the wafer main surface (151) including a plurality of conductive structures (16) made of polysilicon; an insulating film forming step of forming an insulating film (18, 218) on the wafer main surface (151) to cover the plurality of conductive structures (Tr); and a step of forming a main surface electrode (22) to cover the insulating film (18, 218), wherein the insulating film forming step includes a plasma step of forming the insulating film (18, 218) using a plasma CVD method.

[0226] [Appendix 1-13] A method for manufacturing a semiconductor device (1, 201) according to appendix 1-12, wherein the plasma process includes a process for forming a silicon oxide film using a plasma CVD method.

[0227] [Appendix 1-14] A method for manufacturing a semiconductor device (1, 201) according to appendix 1-12 or appendix 1-13, wherein the plasma process includes a step of forming the insulating film (18, 218) made of a silicon oxide film by a plasma CVD method using TEOS as a raw material.

[0228] [Appendix 1-15] A method for manufacturing a semiconductor device (1, 201) according to any one of Appendices 1-12 to 1-14, wherein the plasma process uses the plasma CVD method using a first frequency and a second frequency lower than the first frequency.

[0229] [Appendix 1-16] A method for manufacturing a semiconductor device (1, 201) according to any one of Appendices 1-12 to 1-15, wherein the insulating film forming step further includes a first insulating film forming step of forming, using a low-pressure CVD method, a first insulating film (50) that contacts and covers the plurality of conductive structures (16), and the plasma step includes a second insulating film forming step of forming, using the plasma CVD method, a second insulating film (51) that is stacked on the first insulating film (50) and covers the plurality of conductive structures (16).

[0230] [Appendix 1-17] A method for manufacturing a semiconductor device (1, 201) according to appendix 1-16, wherein the first insulating film formation step includes a step of forming the first insulating film (50) made of a silicon oxide film by a low-pressure CVD method using TEOS as a raw material.

[0231] REFERENCE SIGNS LIST 1...Semiconductor device, 2...Chip, 3...First main surface, 4...Second main surface, 5A...First side surface, 5B...Second side surface, 5C...Third side surface, 5D...Fourth side surface, 6...First semiconductor layer, 7...Drain pad electrode, 8...Second semiconductor layer, 9...Drift region (first impurity region), 10...Active region, 11...Peripheral region, 12...Body region (second impurity region), 13...Outer body region, 14...Gate structure, 15...Gate insulating film, 16...Gate electrode (conductive structure), 16a...First upper wall, 16b...First side wall, 18...Interlayer insulating film (insulating film), 19...Main surface electrode film, 20...Source electrode film, 21...Gate electrode film 22...source pad electrode (main surface electrode), 22a...first pad portion, 22b...second pad portion, 22c...third pad portion, 23...source wiring, 24...gate pad electrode, 25...gate wiring, 28...first finger wiring, 28a...tip portion, 29...second finger wiring, 29a...tip portion, 34...surface insulating film, 35...gate pad, 36...gate pad opening, 37...source pad, 38...source pad opening, 39...termination region, 40...overlap region, 41...field region, 42...peripheral insulating film, 46...source region (third impurity region), 47...channel region, 48...bo De-contact region, 50...first insulating film, 50a...first upper portion, 50b...first side portion, 51...second insulating film, 51a...second upper portion, 51b...second side portion, 52...source contact opening, 53...outer contact opening, 54...gate contact opening, 55...underlying wiring, 55a...second upper wall, 55b...second side wall, 60...lower electrode film, 61...main electrode film, 76...trench, 77...mesa portion, 78...trench insulating film (gate insulating film), 79...gate electrode, 100...low-pressure CVD apparatus, 101...chamber, 102...holding unit, 103...heater, 104...inner tube, 105...outer tube

[0023] 106: Support stand, 107: Vertical holder, 108: Supply pipe, 109: Pressure reduction pipe, 110: Vacuum pump, 111: Clean gas supply pipe, 112: Clean gas exhaust pipe, 113: Opening / closing valve, 120: Plasma CVD apparatus, 121: Chamber, 122: Lower electrode, 123: Upper electrode, 126: Rod portion, 127: Stage portion, 128: High frequency power supply, 129: Low frequency power supply, 130: Discharge port, 131: Supply pipe, 132: Pressure reduction pipe, 133: Vacuum pump, 134: Clean gas supply pipe, 135: Clean gas exhaust pipe, 136: Opening / closing valve, 150: SiC wafer151...first wafer main surface, 152...second wafer main surface, 153...wafer side surface, 154...mark, 155...device region, 156...planned cutting line, 160...base mask, 161...base opening, 162...sidewall, 163...first mask, 164...first opening, 165...second mask, 166...second opening, 167...base insulating film, 168...base electrode, 201...semiconductor device, 218...interlayer insulating film (insulating film), Tr...transistor structure (device structure), UC...unit cell,

Claims

1. A semiconductor device comprising: a SiC chip having a first main surface on which an active region is formed and a second main surface opposite the first main surface; a device structure including a plurality of conductive structures made of polysilicon formed in the active region; an insulating film formed on the first main surface so as to cover the conductive structures; and a main surface electrode covering the conductive structures via the insulating film, wherein the insulating film has a stacked structure of a first insulating film on the first main surface side and a second insulating film on the main surface electrode side, and wherein a first film thickness ratio of a first lateral film thickness, which is the film thickness of a portion of the first insulating film covering a first side wall of the conductive structure, to a first upper film thickness, which is the film thickness of a portion of the first insulating film covering a first upper wall of the conductive structure, is different from a second film thickness ratio of a second lateral film thickness, which is the film thickness of a portion of the second insulating film covering the first side wall, to a second upper film thickness, which is the film thickness of a portion of the second insulating film covering the first upper wall.

2. The semiconductor device according to claim 1, wherein said first film thickness ratio is smaller than said second film thickness ratio.

3. The semiconductor device according to claim 1 or 2, wherein the first film thickness ratio is equal to or greater than 0.3 and less than 1.

0.

4. The semiconductor device according to any one of claims 1 to 3, wherein the second upper film thickness is greater than the first upper film thickness.

5. The semiconductor device according to any one of claims 1 to 4, wherein a third film thickness ratio of said second upper film thickness to said first upper film thickness is not less than 2.0 and not more than 9.

0.

6. The semiconductor device according to any one of claims 1 to 5, wherein the first upper film thickness is 1000 Å or more and 2000 Å or less.

7. The semiconductor device according to any one of claims 1 to 6, wherein the plurality of conductive structures are formed in a stripe pattern.

8. The semiconductor device according to any one of claims 1 to 7, wherein the second insulating film contains at least one of phosphosilicate glass and borophosphosilicate glass.

9. The semiconductor device according to claim 8, wherein said first insulating film does not contain phosphosilicate glass or borophosphosilicate glass.

10. A semiconductor device according to any one of claims 1 to 9, comprising a planar structure including a first impurity region of a first conductivity type formed in a surface layer portion of said first main surface, said device structure further including a second impurity region of a second conductivity type formed in a surface layer portion of said first impurity region, and a third impurity region of the first conductivity type formed in an inner region of said second impurity region, and said conductive structure including a gate electrode facing said second impurity region via a gate insulating film.

11. A semiconductor device according to any one of claims 1 to 9, comprising a trench structure including a first impurity region of a first conductivity type formed in a surface layer portion of said first main surface, said device structure further including a trench defining a mesa portion, and a second impurity region of a second conductivity type and a third impurity region of the first conductivity type formed in said mesa portion in that order in a direction from the bottom of said trench toward said first main surface, and said conductive structure including a gate electrode buried in said trench via a gate insulating film.

12. A method for manufacturing a semiconductor device, comprising: a step of preparing a SiC wafer having a wafer main surface; a step of forming a device structure including a plurality of conductive structures made of polysilicon on the wafer main surface; an insulating film forming step of forming an insulating film on the wafer main surface to cover the plurality of conductive structures; and a step of forming a main surface electrode to cover the insulating film, wherein the insulating film forming step includes a plasma step of forming the insulating film using a plasma CVD method.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the plasma process includes a step of forming a silicon oxide film using a plasma CVD method.

14. The method for manufacturing a semiconductor device according to claim 12 or 13, wherein the plasma process includes a step of forming the insulating film made of a silicon oxide film by plasma CVD using TEOS as a raw material.

15. The method for manufacturing a semiconductor device according to any one of claims 12 to 14, wherein the plasma process employs the plasma CVD method using a first frequency and a second frequency lower than the first frequency.

16. A method for manufacturing a semiconductor device according to any one of claims 12 to 15, wherein the insulating film forming step further includes a first insulating film forming step of forming, using a low-pressure CVD method, a first insulating film that contacts and covers the plurality of conductive structures, and the plasma step includes a second insulating film forming step of using the plasma CVD method to form a second insulating film that is stacked on the first insulating film and covers the plurality of conductive structures.

17. The method for manufacturing a semiconductor device according to claim 16, wherein the first insulating film forming step includes a step of forming the insulating film made of a silicon oxide film by low pressure CVD using TEOS as a raw material.

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