Smart IC substrate, smart IC module, and IC card comprising same

Abstract

A smart IC substrate according to an embodiment comprises: a base comprising one surface and the other surface opposite to the one surface; and a conductive pattern part disposed on the one surface of the base, wherein the base comprises a plurality of holes, each penetrating at least a portion of the base in the thickness direction thereof, and the plurality of holes include a plurality of bonding holes and dummy holes spaced apart from the plurality of bonding holes.

Description

Smart IC substrate, smart IC module and IC card including the same

[0001] The embodiments relate to a smart IC substrate, a smart IC module, and an IC card including the same.

[0002] An IC card is a plastic card with an integrated circuit chip capable of storing and processing information. An IC card contains an IC chip that stores the necessary information and transmits this information to a reader in the form of an electrical signal. These IC cards are manufactured by inserting a smart IC module into the card body.

[0003] Smart IC modules are classified as single-type or dual-type depending on the arrangement of the metal layers. Single-type modules have electrode patterns on only one side of the substrate. Dual-type modules have electrode patterns on both sides of the substrate.

[0004] Additionally, smart IC modules are categorized into contact, contactless, hybrid, and combi cards, depending on how the card is used. Contact cards transmit and receive information through physical contact. Contactless cards transmit and receive information without physical contact. Furthermore, hybrid and combi cards incorporate both contact and contactless functions.

[0005] Contact-type smart IC modules transmit and receive information through physical contact. Contactless smart IC modules use wireless communication capabilities (e.g., Near Field Communication (NFC)) to transmit and receive information without physical contact. Combi-type smart IC modules and hybrid smart IC modules incorporate both physical contact and contactless wireless communication capabilities.

[0006] Smart IC cards in these smart IC card modules are widely used in various fields such as credit cards, SIM cards, security cards, and ID cards. The smart IC substrate applied to these smart IC cards includes a substrate and an electrode pattern arranged on the substrate. The electrode pattern includes a bonding surface and a contact surface. The bonding surface of the electrode pattern refers to one surface of the electrode pattern. For example, the bonding surface of the electrode pattern refers to the surface of the electrode pattern that is connected to the IC chip. In addition, the contact surface of the electrode pattern refers to the other surface of the electrode pattern that is exposed to the outside of the smart IC card. For example, the contact surface of the electrode pattern refers to the surface that makes contact with an external device (e.g., a card reader).

[0007] At this time, the substrate applied to the smart IC substrate has a relatively large thickness. For example, the thickness of the substrate applied to the smart IC substrate is 80 to 150 μm. Accordingly, the elasticity of the smart IC substrate may be reduced due to the relatively large thickness of the substrate, which may result in a decrease in mechanical reliability.

[0008] For example, a smart IC substrate is attached to the body of a smart IC card. The smart IC card is provided to be bendable. However, the low elasticity of the smart IC substrate can reduce the flexibility of the smart IC card, making it unusable in various environments.

[0009] In addition, smart IC cards are bent depending on the usage environment, and the stress generated by the bending is transmitted to the smart IC substrate. At this time, the smart IC substrate has relatively low elasticity, and therefore, the stress generated by the bending may be concentrated on the smart IC substrate. In addition, if the stress is concentrated on the smart IC substrate, the metal pattern may be separated from the substrate, which may cause a problem of reduced electrical reliability and / or physical reliability. In addition, if the stress is concentrated on the smart IC substrate, the connecting member that electrically connects the terminal of the chip and the metal pattern may be separated from the terminal or the metal pattern. In this case, an operational reliability problem may occur, in which the chip attached to the smart IC substrate does not operate normally.

[0010] Therefore, a new structure of a smart IC substrate capable of efficiently dispersing stress acting on the smart IC substrate is required.

[0011] Embodiments provide a smart IC substrate, a smart IC module, and an IC card including the same, wherein physical reliability and / or electrical reliability are disclosed.

[0012] In addition, the embodiment provides a smart IC substrate with improved elasticity, a smart IC module, and an IC card including the same.

[0013] In addition, the embodiment provides a smart IC substrate, a smart IC module, and an IC card including the same, which can efficiently distribute stress applied depending on the usage environment.

[0014] In addition, the embodiment provides a smart IC substrate, a smart IC module, and an IC card including the same, which can improve molding characteristics by controlling the flowability of a molding member.

[0015] In addition, the embodiment provides a smart IC substrate, a smart IC module, and an IC card including the same with improved adhesion to a molding member.

[0016] In addition, the embodiment provides a smart IC substrate, a smart IC module, and an IC card including the same, which can improve the thickness uniformity of a molding member.

[0017] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0018] A smart IC substrate according to an embodiment comprises a substrate including one side and an opposite side; and a conductive pattern portion disposed on the one side of the substrate; wherein the substrate includes a plurality of holes penetrating at least a portion of the substrate along a thickness direction of the substrate, and the plurality of holes include a plurality of bonding holes and dummy holes spaced apart from the plurality of bonding holes.

[0019] In addition, the surface of the above-mentioned substrate defines a chip attachment area to which a chip is attached, the plurality of bonding holes are arranged in a peripheral area of ​​the chip attachment area and spaced apart from each other along a peripheral direction of the chip attachment area, and the dummy holes are arranged on the inside of the peripheral area.

[0020] Additionally, the horizontal distance from the dummy hole to the central axis of the chip attachment area in the horizontal direction is smaller than the horizontal distance from each of the plurality of bonding holes to the central axis.

[0021] In addition, the conductive pattern portion includes a metal layer disposed on the one surface of the substrate; an upper cover layer disposed on the metal layer; a first lower cover layer disposed under the metal layer exposed through the bonding hole; and a second lower cover layer disposed under the metal layer exposed through the dummy hole.

[0022] Additionally, the plurality of bonding holes entirely penetrate the substrate along the thickness direction, and the dummy holes partially penetrate the substrate along the thickness direction.

[0023] Additionally, at least one of the planar shape of the dummy hole, the width of the dummy hole in the first horizontal direction, and the width of the dummy hole in the second horizontal direction perpendicular to the first horizontal direction is different from at least one of the planar shape of the bonding hole, the width of the bonding hole in the first horizontal direction, and the width of the bonding hole in the second horizontal direction.

[0024] Additionally, the conductive pattern portion includes a plurality of pads spaced apart from each other on the one surface of the substrate, and each of the plurality of bonding holes overlaps each of the plurality of pads along the thickness direction.

[0025] Additionally, the plurality of pads include a first pad overlapping the chip attachment area along the thickness direction, and the first pad includes an outer portion overlapping one of the plurality of bonding holes along the thickness direction, and an inner portion overlapping the dummy hole along the thickness direction.

[0026] In addition, the conductive pattern portion further includes a dummy pattern overlapping the chip attachment area along the thickness direction, wherein the dummy pattern overlaps the dummy hole along the thickness direction and does not overlap the bonding hole along the thickness direction.

[0027] Additionally, at least one of the plurality of pads includes a dummy pad, and the bonding hole overlapping the dummy pad along the thickness direction is an auxiliary dummy hole.

[0028] Additionally, the dummy hole includes a first dummy hole extending along a first horizontal direction, and a second dummy hole spaced apart from the first dummy hole with the chip attachment area therebetween and extending along the first horizontal direction.

[0029] Additionally, at least one of the first dummy hole and the second dummy hole is provided discontinuously along the first horizontal direction.

[0030] Additionally, at least one of the length of the first dummy hole in the first horizontal direction and the width of the first dummy hole in the second horizontal direction perpendicular to the first horizontal direction is different from at least one of the length of the second dummy hole in the first horizontal direction and the width of the second dummy hole in the second horizontal direction.

[0031] In addition, the dummy hole further includes at least one of a third dummy hole provided between the first dummy hole and the second dummy hole and extending in the second horizontal direction, and a fourth dummy hole spaced apart from the third dummy hole with the chip attachment area therebetween and extending along the second horizontal direction.

[0032] Additionally, at least one of the first dummy hole and the second dummy hole is connected to at least one of the third dummy hole and the fourth dummy hole.

[0033] A smart IC substrate according to an embodiment includes a substrate; a first conductive pattern portion disposed on an upper surface of the substrate; and a second conductive pattern portion disposed on a lower surface of the substrate; wherein the substrate includes a plurality of through holes overlapping the first conductive pattern portion along a vertical direction, and the second conductive pattern portion includes a pad portion disposed on the lower surface of the substrate, and an extension portion extending from the pad portion along a circumferential direction of an area in which the plurality of through holes are disposed and surrounding the area.

[0034] Additionally, the second conductive pattern portion further includes a partition wall portion extending from the extension portion toward the region and disposed between adjacent through holes among the plurality of through holes.

[0035] In addition, the second conductive pattern portion further includes a bonding portion provided at an end of the partition wall portion, and the width of the bonding portion is larger than the width of the partition wall portion and the width of the extension portion.

[0036] Additionally, the width of the partition wall portion has a range of 100 ㎛ to 200 ㎛.

[0037] Additionally, the width of the bonding portion has a range of 300 µm to 650 µm.

[0038] In addition, the second conductive pattern portion includes a first portion and a second portion that are spaced apart from each other on the lower surface of the substrate and each have the pad portion, the extension portion, the partition wall portion, and the bonding portion, and the extension portion of the first portion of the second conductive pattern portion is provided to surround a part of the area, and the extension portion of the second portion of the second conductive pattern portion is provided to surround a remaining part of the area.

[0039] In addition, one end of the extension of the first part and one end of the extension of the second part are spaced apart by a first separation distance, and the other end of the extension of the first part and the other end of the extension of the second part are spaced apart by a second separation distance, and the first separation distance and the second separation distance are smaller than the width of each of the plurality of through holes.

[0040] Additionally, the first spacing distance and the second spacing distance have a range of 50 μm to 200 μm.

[0041] Additionally, the pad portion includes a plurality of joining holes penetrating the upper and lower surfaces of the pad portion.

[0042] In addition, the pad portion includes a central region and an outer region, and the opening ratio in the outer region by the plurality of coupling holes is greater than the opening ratio in the central region by the plurality of coupling holes.

[0043] In addition, the smart IC substrate includes a first adhesive layer disposed between the substrate and the first conductive pattern portion, and a second adhesive layer disposed between the substrate and the second conductive pattern portion, wherein the thickness of the first adhesive layer and the thickness of the second adhesive layer are different.

[0044] Additionally, the smart IC substrate further includes a first cover layer disposed on the first conductive pattern portion; and a second cover layer disposed within the plurality of through holes and disposed under the first conductive pattern portion.

[0045] An embodiment may provide a smart IC substrate with dummy holes, thereby improving electrical reliability and / or mechanical reliability of the smart IC substrate.

[0046] That is, the smart IC substrate of the embodiment includes a substrate and a conductive pattern portion arranged on the substrate. In addition, the substrate includes a plurality of holes. In this case, the plurality of holes include a plurality of bonding holes and dummy holes spaced apart from the plurality of bonding holes. In this case, the bonding holes are provided for performing a bonding process, and are particularly holes for electrically connecting a chip attached to the smart IC substrate and the conductive pattern portion. In addition, the dummy holes may perform a different function from the bonding holes.

[0047] In other words, the dummy holes can function to provide flexibility to the smart IC substrate. For example, the dummy holes can function to distribute stress applied to the smart IC substrate when the smart IC substrate is bent or twisted, thereby maintaining adhesion between the smart IC substrate and the main body of the smart IC card.

[0048] Additionally, the dummy holes can control the flowability of the molding material applied while the chip is attached to the smart IC substrate. For example, the dummy holes can control the flowability of the molding material to prevent the molding material from flowing excessively beyond the outer region of the bonding hole. For example, the dummy holes can control the volume of the molding material while ensuring that the molding material is applied at the correct location.

[0049] Furthermore, the embodiment can form dummy holes during the process of forming bonding holes. Therefore, the embodiment can improve the mechanical and / or electrical reliability of a smart IC substrate without additional processes or material changes, and furthermore, can facilitate upper limit management of the molding member by utilizing the dummy holes.

[0050] The smart IC substrate of the embodiment includes a first conductive pattern portion arranged on an upper surface of a substrate, and a second conductive pattern portion arranged on a lower surface of the substrate. At this time, the substrate includes a plurality of through holes that overlap with the first conductive pattern portion in a vertical direction. In addition, the second conductive pattern portion includes a pad portion arranged on the lower surface of the substrate, and an extension portion that extends from the pad portion in a circumferential direction of an area in which a plurality of through holes are arranged and surrounds the area.

[0051] At this time, the area where the through hole is arranged may refer to a molding area where the molding member is to be arranged. For example, the inner area of ​​the extension surrounded by the extension of the second conductive pattern portion may refer to a molding area where the molding member is to be arranged.

[0052] The extension of the second conductive pattern portion can prevent the molding member from flowing out to an area other than the designated area described above during the molding process of the chip that is performed later. For example, the extension of the second conductive pattern portion can function as a dam that prevents the molding member of the chip from flowing out of the designated area while ensuring that the molding member is placed only in the designated area. Through this, the embodiment can ensure that the chip and the connecting member (to be described later) connecting the chip and the pads are stably molded through the molding member, thereby improving the operating characteristics of the chip. Therefore, the embodiment can prevent external moisture or foreign substances from penetrating into the molding area of ​​the chip, thereby further improving the operating reliability.

[0053] Furthermore, the embodiment can improve the processability in the process of forming a molding member by using an extension of the second conductive pattern portion, thereby improving the product yield.

[0054] In addition, the embodiment can use the extension of the second conductive pattern portion to make the molding member formed in the inner region of the extension portion have a constant thickness, thereby further improving product reliability.

[0055] Additionally, the second conductive pattern portion may further include a partition wall portion extending from the extension portion toward an area where the through holes are arranged. The partition wall portion may extend from the extension portion toward an area between the through holes.

[0056] The bulkhead portion can further improve the processability in the process of forming the molding member, and further improve the processability in the process of wire bonding the chip and the second conductive pattern portion.

[0057] For example, the partition wall can demarcate the area between multiple through holes. Thus, the embodiment can utilize the partition wall to ensure stable protection of the wires connected to the inside of each through hole. For example, the partition wall can demarcate each area where the through holes are arranged, thereby ensuring stable molding in each demarcated area.

[0058] Additionally, the second conductive pattern portion may further include a bonding portion arranged at an end of the barrier rib portion. The bonding portion may have a constant diameter. The bonding portion may function as a bonding pad for electrically connecting the terminal of the chip and the second conductive pattern portion.

[0059] In this case, the embodiment can utilize a partition wall portion to provide a bonding portion adjacent to the through hole, thereby improving the processability in the wire bonding process of the chip and the second conductive pattern portion, and thereby enabling more stable molding of the wire connected to the bonding portion using the extension portion. Accordingly, the embodiment can further improve product reliability and further enable more stable operation of the smart IC substrate.

[0060] In addition, the pad portion may include a plurality of bonding holes. The plurality of bonding holes may allow a bonding member (e.g., solder) to be stably positioned during a process of bonding the pad portion of the second conductive pattern portion and the antenna pattern. For example, the bonding holes may be regions for forming a hot melting agent during solder bonding or bonding using ACF, thereby preventing the hot melting agent and the bonding agent from adhering to each other and interfering with each other. Accordingly, the bonding holes may be concentratedly positioned at the edge of the pad portion to prevent the bonding agent from being lifted from the outside.

[0061] FIG. 1 is a plan view of one side of a smart IC substrate according to the first embodiment.

[0062] Figure 2 is a plan view of the other surface of the smart IC substrate according to the first embodiment.

[0063] FIG. 3 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the first embodiment.

[0064] Figure 4 is a cross-sectional view taken along the BB' direction of Figure 2.

[0065] FIG. 5 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the second embodiment.

[0066] FIG. 6 is a cross-sectional view taken along the BB' direction of FIG. 2 according to the second embodiment.

[0067] Fig. 7 is a cross-sectional view taken along the BB' direction of Fig. 2 according to the third embodiment.

[0068] Figure 8 is a plan view of the other surface of the smart IC substrate according to the fourth embodiment.

[0069] Figure 9 is a plan view of the other surface of the smart IC substrate according to the fifth embodiment.

[0070] FIG. 10 is a plan view of the other surface of a smart IC substrate according to a sixth embodiment.

[0071] Fig. 11 is a plan view showing a dummy hole according to the first modified example.

[0072] Fig. 12 is a plan view showing a dummy hole according to a second modified example.

[0073] Fig. 13 is a plan view showing a dummy hole according to a third modified example.

[0074] Fig. 14 is a plan view showing a dummy hole according to the fourth modified example.

[0075] Fig. 15 is a plan view of the other surface of the smart IC substrate according to the seventh embodiment.

[0076] Fig. 16 is a cross-sectional view taken along the AA' direction of Fig. 15.

[0077] Figure 17 is a plan view of one side of a smart IC substrate according to the eighth embodiment.

[0078] Fig. 18 is a plan view of the other surface of the smart IC substrate according to the eighth embodiment.

[0079] Fig. 19 is a cross-sectional view taken along the AA' direction of Fig. 18 according to the eighth embodiment.

[0080] Fig. 20 is a cross-sectional view taken along the AA' direction of Fig. 18 according to the ninth embodiment.

[0081] Fig. 21 is a cross-sectional view taken along the AA' direction of Fig. 18 according to the 10th embodiment.

[0082] Fig. 22 is a cross-sectional view taken along the AA' direction of Fig. 18 according to the 11th embodiment.

[0083] Fig. 23 is a cross-sectional view taken along the AA' direction of Fig. 18 according to the 12th embodiment.

[0084] Fig. 24 is a cross-sectional view taken along the AA' direction of Fig. 18 according to the 13th embodiment.

[0085] FIG. 25 is a plan view of the other surface of a smart IC substrate according to another embodiment.

[0086] FIG. 26 is a plan view of the other surface of a smart IC substrate according to another embodiment.

[0087] Figure 27 is a plan view showing a smart IC module according to one embodiment.

[0088] Fig. 28 is a cross-sectional view showing a smart IC module according to an embodiment.

[0089] Fig. 29 is a perspective view showing a smart IC card according to an embodiment.

[0090] Figure 30 is a cross-sectional view schematically showing the smart IC card of Figure 29.

[0091] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the described embodiments, but may be implemented in various different forms. Within the scope of the technical concept of the present invention, one or more of the components of the embodiments may be selectively combined or substituted for use.

[0092] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0093] Additionally, the terminology used in the embodiments of the present invention is for the purpose of describing the embodiments and is not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C.

[0094] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and are not intended to limit the nature, order, or sequence of the components.

[0095] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0096] Additionally, when it is described as being formed or disposed "above or below" each component, above or below includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or disposed between the two components.

[0097] Additionally, when expressed as “upper or lower,” it can include the meaning of not only the upward direction but also the downward direction based on one component.

[0098]

[0099] Hereinafter, a smart IC substrate, a smart IC module, and a smart IC card including the same according to an embodiment will be described with reference to the drawings.

[0100] FIG. 1 is a plan view of one side of a smart IC substrate according to a first embodiment, FIG. 2 is a plan view of the other side of the smart IC substrate according to the first embodiment, FIG. 3 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the first embodiment, FIG. 4 is a cross-sectional view taken along the BB' direction of FIG. 2, FIG. 5 is a cross-sectional view taken along the AA' direction of FIG. 2 according to the second embodiment, FIG. 6 is a cross-sectional view taken along the BB' direction of FIG. 2 according to the second embodiment, FIG. 7 is a cross-sectional view taken along the BB' direction of FIG. 2 according to the third embodiment, FIG. 8 is a plan view of the other side of a smart IC substrate according to a fourth embodiment, FIG. 9 is a plan view of the other side of a smart IC substrate according to a fifth embodiment, and FIG. 10 is a plan view of the other side of a smart IC substrate according to a sixth embodiment.

[0101]

[0102] Referring to FIGS. 1 to 4, the smart IC substrate (100) includes a substrate (110) and a conductive pattern portion (120).

[0103] At this time, the smart IC substrate (100) in the first embodiment may be a single type in which the conductive pattern portion (120) is arranged only on one side of the substrate (110).

[0104] The substrate (110) includes one side (110S1) and a second side (110S2) opposite to the first side (110S1). In addition, the conductive pattern portion (120) is arranged on the first side (110S1) of the substrate (110).

[0105] Here, being placed on one side (110S1) is not only understood as a configuration in which the conductive pattern portion (120) is in direct contact with one side (110S1) of the substrate (110), but can also be understood as another configuration between the one side (110S1) of the substrate (110) and the conductive pattern portion (120).

[0106] One side (110S1) of the substrate (110) and the other side (110S2) of the substrate (110) mean opposite sides. The one side (110S1) of the substrate (110) may be defined as a contact surface. For example, the one side (110S1) of the substrate (110) may mean a surface that can recognize information of a smart IC module through direct or indirect contact. In addition, the other side (110S2) of the substrate (110) may be defined as a bonding surface. For example, the other side (110S2) of the substrate (110) may mean a surface for bonding with a mounted chip when a chip (to be described later) is mounted.

[0107] The substrate (110) comprises a resin material. The substrate (110) may have a certain strength. The substrate (110) may include a reinforcing member. For example, the substrate (110) may be provided as a prepreg having a reinforcing member such as glass fiber. Specifically, the substrate (110) may be provided by dispersing glass fiber and silicon-based filler (Si filler) within an epoxy resin.

[0108] The substrate (110) may be rigid or flexible. For example, the substrate (110) may include glass or plastic. For example, the substrate (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. Alternatively, the substrate (110) may include polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or sapphire.

[0109] The substrate (110) may include an optically isotropic film. For example, the substrate (110) may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), or an optically isotropic polymethyl methacrylate (PMMA).

[0110] Alternatively, the substrate (110) may be bent while having a partially curved surface. That is, the substrate (110) may be bent while having a partially flat surface and a partially curved surface. In detail, the ends of the substrate (110) may be bent while having a curved surface. Alternatively, the substrate (110) may be bent while having a random curvature.

[0111] The substrate (110) may have a thickness within a set range. For example, the thickness of the substrate (110) may be 80 μm to 150 μm, 90 μm to 140 μm, or 100 μm to 120 μm. If the thickness of the substrate (110) is less than 80 μm, the support capacity and / or rigidity of the substrate (110) may be reduced, which may make it difficult to stably place the conductive pattern portion (120). If the thickness of the substrate (110) exceeds 150 μm, the thickness of the smart IC substrate may increase, and thereby the thickness of the smart IC card including the smart IC substrate (100) may increase, making it difficult to make it thin.

[0112] The substrate (110) has insulating properties. For example, the substrate (110) may be provided to support the conductive pattern portion (120) and provide insulation between the plurality of electrode patterns constituting the conductive pattern portion (120). For example, the substrate (110) may prevent short circuits between the plurality of electrode patterns.

[0113] The substrate (110) may have a hole (TH). The hole (TH) may penetrate the substrate (110). For example, the hole (TH) may penetrate one surface (110S1) of the substrate (110) and the other surface (110S2) of the other surface (110S2) of the substrate (110) along a third direction (3D). Here, the third direction (3D) may refer to a direction from the one surface (110S1) of the substrate (110) toward the other surface (110S2) of the substrate (110), and may be referred to as a vertical direction or a thickness direction. However, the embodiment is not limited thereto. As will be described in other embodiments below, a plurality of holes (TH) are provided, and at least one of the plurality of holes (TH) may be provided as a recess penetrating a portion of the substrate (110) from the other surface (110S2) of the substrate (110) toward one surface (110S1) of the substrate (110).

[0114] The substrate (110) may have a plurality of holes (TH) spaced apart from each other. Here, having a plurality of holes (TH) may mean that a plurality of holes are provided that are not connected or communicate with each other.

[0115] Holes (TH) can be divided into multiple groups. For example, holes (TH) can be divided into multiple groups based on their function. Alternatively, holes (TH) can be divided into multiple groups based on their location. Alternatively, holes (TH) can be divided into multiple groups based on their planar shape.

[0116] For example, the hole (TH) provided in the substrate (110) may include a bonding hole (BH) and a dummy hole (DH).

[0117] In one embodiment, the bonding hole (BH) and the dummy hole (DH) can be distinguished according to their function.

[0118] A bonding hole (BH) may refer to a hole in which a connecting member (e.g., a wire) for electrically connecting to a chip (to be described later) mounted on a smart IC substrate (100) is placed. For example, the bonding hole (BH) may provide a bonding space for electrically connecting a terminal of the chip and a conductive pattern portion (120) on the smart IC substrate (100) using a connecting member. Preferably, the bonding hole (BH) may refer to a space in which a connecting member for electrically connecting the chip and the conductive pattern portion (120) is placed. Accordingly, a connecting member connected to a terminal of the chip may be inserted into the bonding hole (BH).

[0119] In contrast, a dummy hole (DH) may refer to a hole having a different function from that of a bonding hole (BH). For example, a dummy hole (DH) may refer to a hole in which a connecting member is not placed. Preferably, the dummy hole (DH) may function to alleviate or disperse stress applied to the smart IC substrate (100). For example, the dummy hole (DH) may function to provide elasticity to the smart IC substrate (100). For example, the dummy hole (DH) may function to disperse stress applied to the smart IC substrate (100) in an environment in which the smart IC substrate (100) is bent or twisted, thereby maintaining adhesion between the smart IC substrate (100) and the main body of the smart IC card. In addition, the dummy hole (DH) may function to control the flowability of a molding member applied while a chip is attached to the smart IC substrate (100). For example, the dummy hole (DH) can control the flowability of the molding member to prevent the molding member from flowing excessively beyond the outer region of the bonding hole (BH). For example, the dummy hole (DH) can function to control the volume of the molding member while ensuring that the molding member is applied at an accurate location.

[0120] In another embodiment, the bonding hole (BH) and the dummy hole (DH) can be distinguished according to their placement positions.

[0121] For example, the substrate (110) may include a chip attachment area (CAR) to which a chip is attached. The bonding hole (BH) may be positioned relatively far from the chip attachment area (CAR). In addition, the dummy hole (DH) may be positioned closer to the chip attachment area (CAR) than the bonding hole (BH). For example, one side (110S1) or the other side (110S2) of the substrate (110) includes a central axis (CA) in a horizontal direction. In this case, the horizontal distance from the central axis (CA) to the dummy hole (DH) may be smaller than the horizontal distance from the central axis (CA) to the bonding hole (BH). In addition, the bonding hole (BH) may be positioned around the outer region of the chip attachment area (CAR) at a predetermined distance from the chip attachment area (CAR). In addition, the dummy hole (DH) may be positioned inside the outer region of the chip attachment area (CAR) where the bonding hole (BH) is positioned. Here, the central axis (CA) may mean the central axis in the horizontal direction of the chip attachment area (CAR).

[0122] In another embodiment, the bonding hole (BH) and the dummy hole (DH) can be distinguished according to their planar shapes.

[0123] The bonding hole (BH) may have a planar shape to ensure that the connecting member can be stably inserted and that the bonding process of the connecting member can proceed smoothly. Accordingly, the planar shape of the bonding hole (BH) may be determined in consideration of the bonding reliability of the connecting member. For example, the planar shape of the bonding hole (BH) may have a circular shape, but is not limited thereto, and may be modified into any other shape that allows for smooth and stable bonding of the connecting member.

[0124] In contrast, the dummy hole (DH) may have a planar shape capable of efficiently dispersing the stress acting on the smart IC substrate (100). For example, the planar shape of the dummy hole (DH) may be determined in consideration of the direction of the stress acting on the smart IC substrate (100). For example, the smart IC substrate (100) may have a shape in which the width in the first direction (1D) is greater than the width in the second direction (2D). In this case, the stress in the first direction (1D) may be greater on the smart IC substrate (100). Therefore, the dummy hole (DH) may have a planar shape in which the width in the first direction (1D) is greater than the width in the second direction (2D).

[0125] At this time, the bonding hole (BH) may include a plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) spaced apart from each other in the horizontal direction. At this time, although the drawing illustrates that the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) are provided in six numbers, this is not limited thereto. For example, the number of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) provided in the substrate (110) may increase or decrease depending on the type of chip mounted on the smart IC substrate (100). For example, the number of terminals of a chip mounted on a smart IC substrate (100) may be less than 6 or more than 6, and accordingly, the number of a plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) provided in the substrate (110) may be less than 6 or more than 6.

[0126] A plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) may be arranged to be spaced apart from each other along the circumferential direction of the chip attachment area (CAR). For example, the other surface (110S2) of the substrate (110) may define the chip attachment area (CAR). In addition, the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) may be provided at positions spaced apart from the chip attachment area (CAR), respectively, and may be provided to penetrate one surface (110S1) and the other surface (110S2) of the substrate (110) at positions spaced apart from each other along the circumferential direction of the chip attachment area (CAR). For example, the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) may be provided to be spaced apart from each other along the circumferential direction of the chip attachment area (CAR).

[0127] Here, the peripheral region may refer to a region surrounding the outer side of the chip attachment region (CAR). Alternatively, the peripheral region may refer to a region surrounding the chip attachment region (CAR). Alternatively, the peripheral region may refer to a region that contacts or overlaps with the molding member (1300) described later. For example, the peripheral region may refer to an inner side of an end of the molding member (1300) or an area that contacts or overlaps with an end of the molding member (1300).

[0128] A plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) can expose a bonding surface (e.g., a lower surface) of a conductive pattern portion (120) arranged on one surface (110S1) of a substrate (110) to electrically connect the terminal of the chip with the conductive pattern portion (120).

[0129] Each of the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) has a width (W1) of a set range. The width (W1) of each of the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) may refer to a diameter of each of the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6). Alternatively, the width (W1) of each of the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) may be defined as the minimum distance between the inner walls of the holes passing through the central axis in the horizontal direction of each of the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6).

[0130] The width (W1) of each of the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) may be 500 µm to 1000 µm, 600 µm to 900 µm, or 700 µm to 800 µm. If the width (W1) of at least one bonding hole among the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) is less than 500 µm, it may be difficult to secure a wire bonding space, and thus, process characteristics in the wire bonding process may deteriorate. In addition, when the width (W1) of at least one bonding hole among the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) exceeds 1000 μm, the volume of the molding member for filling the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) may increase, thereby increasing the manufacturing cost, or the volume of the molding member may increase excessively, thereby reducing the flowability of the molding member.

[0131] The dummy hole (DH) may be positioned closer to the chip attachment area (CAR) or the central axis (CA) than the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6). At least one dummy hole (DH) may be provided. Preferably, the dummy hole (DH) may include a plurality of dummy holes (DH1, DH2) spaced apart in the horizontal direction. For example, the dummy hole (DH) may be provided in an inner region of a peripheral region of the chip attachment area (CAR) in which the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) are arranged. Therefore, the dummy hole (DH) may be provided closer to the chip attachment area (CAR) than the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6).

[0132] The dummy hole (DH) may include a first dummy hole (DH1) arranged on the first side of the central axis (CA). For example, in a plan view, the first dummy hole (DH1) may be provided on the left side of the central axis (CA) of the other surface (110S2) of the substrate (110).

[0133] The first dummy hole (DH1) may be arranged in the first direction (1D) on the first side of the central axis (CA). For example, the first dummy hole (DH1) may be positioned on the first side of the central axis (CA) to absorb or disperse stress applied to the smart IC substrate (100) in the first direction (1D).

[0134] At this time, the first dummy hole (DH1) may be provided discontinuously in the first direction (1D). For example, the first dummy hole (DH1) may include a plurality of first sub-dummy holes (DH11, DH12, DH13) spaced apart from each other in the first direction (1D). Here, the first dummy hole (DH1) is illustrated as including three first sub-dummy holes (DH11, DH12, DH13), but is not limited thereto. For example, the first dummy hole (DH1) may include two sub-dummy holes, or may include four or more sub-dummy holes, taking into consideration the intensity of stress applied to the smart IC substrate (100), the direction of the stress, or the plane size of the smart IC substrate (100). At this time, when the first dummy hole (DH1) includes a plurality of first sub-dummy holes (DH11, DH12, DH13) having a discontinuous structure, the stress applied to the smart IC substrate (100) can be efficiently distributed and / or absorbed while securing the rigidity of the smart IC substrate (100) in the area where the first dummy hole (DH1) is provided.

[0135] Additionally, the dummy hole (DH) may include a second dummy hole (DH2) arranged on the second side of the central axis (CA). For example, in a plan view, the first dummy hole (DH1) may be provided on the left side of the central axis (CA) of the other surface (110S2) of the substrate (110).

[0136] The second dummy hole (DH2) may be arranged in the first direction (1D) on the second side of the central axis (CA). For example, the second dummy hole (DH2) may be positioned on the second side of the central axis (CA) to absorb or disperse stress applied to the smart IC substrate (100) in the first direction (1D).

[0137] At this time, the second dummy hole (DH2) may be provided discontinuously in the first direction (1D). For example, the second dummy hole (DH2) may include a plurality of second sub-dummy holes (DH21, DH22, DH23) spaced apart from each other in the first direction (1D). Here, the second dummy hole (DH2) is illustrated as including three second sub-dummy holes (DH21, DH22, DH23), but is not limited thereto. For example, the second dummy hole (DH2) may include two sub-dummy holes, or may include four or more sub-dummy holes, taking into consideration the intensity of stress applied to the smart IC substrate (100), the direction of the stress, or the plane size of the smart IC substrate (100). At this time, when the second dummy hole (DH2) includes a plurality of second sub-dummy holes (DH21, DH22, DH23) having a discontinuous structure, the stress applied to the smart IC substrate (100) can be efficiently distributed and / or absorbed while securing the rigidity of the smart IC substrate (100) in the area where the second dummy hole (DH2) is provided.

[0138] At this time, the first dummy hole (DH1) and the second dummy hole (DH2) may have different widths in the first direction (1D) and the second direction (2D) from a planar viewpoint.

[0139] For example, the first dummy hole (DH1) and the second dummy hole (DH2) are each positioned on the first side and the second side of the central axis (CA) to function to disperse and / or absorb stress acting in the first direction (1D). Accordingly, the width of the first dummy hole (DH1) and the second dummy hole (DH2) in the first direction (1D) may be greater than the width in the second direction (2D). Through this, the embodiment can efficiently disperse and / or absorb stress acting on the smart IC substrate (100) through the first dummy hole (DH1) and the second dummy hole (DH2), thereby further improving the physical reliability and / or electrical reliability of the smart IC substrate (100).

[0140] In addition, the pad of the conductive pattern portion (120) exposed through at least one of the first dummy hole (DH1) and the second dummy hole (DH2) may be the same as the pad exposed through at least one bonding hole (BH) of the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6). For example, depending on the design of the conductive pattern portion (120), the first pad (121) of the conductive pattern portion (120) may include an inner portion arranged in an area overlapping the chip attachment area (CAR) in the third direction (3D), and an outer portion extended from the inner portion and arranged in an outer area of ​​the chip attachment area (CAR). And, the first bonding hole (BH1) can overlap with the outer side of the first pad (121) along the third direction (3D), and the first dummy hole (DH1) and the second dummy hole (DH2) can overlap with the inner side of the first pad (121) along the third direction (3D).

[0141] Accordingly, one side of the first pad (121) may include a plurality of exposed surfaces exposed through each of the first bonding hole (BH1), the first dummy hole (DH1), and the second dummy hole (DH2). At this time, among the plurality of exposed surfaces of the first pad (121), the surface exposed through the first bonding hole (BH1) may function as a bonding portion, and the surfaces exposed through the first dummy hole (DH1) and the second dummy hole (DH2) may not function as bonding portions (for example, may function as dummy portions).

[0142] The conductive pattern portion (120) may be arranged on one side (110S1) of the substrate (110). Preferably, the conductive pattern portion (120) may be in direct contact with the one side (110S1) of the substrate (110). For example, in the smart IC substrate (100) of the first embodiment, no additional configuration may be interposed between the one side (110S1) of the substrate (110) and the lower surface of the conductive pattern portion (120).

[0143] That is, the metal layer (for example, a copper layer) constituting the conductive pattern portion (120) can be directly attached onto the substrate (110). For example, a resin laminate in which the metal layer constituting the conductive pattern portion (120) is directly attached onto the substrate (110) through a direct bonding method can be provided, and the smart IC substrate of the embodiment can be manufactured using the above-described resin laminate. As another example, the substrate (110) can be a prepreg, and the prepreg can be directly molded onto the metal layer constituting the conductive pattern portion (120). In this case, the above-described resin laminate can be a CCL (Copper Clad Laminate).

[0144] The conductive pattern portion (120) may refer to a pattern placed on the contact surface of the substrate (110).

[0145] The conductive pattern portion (120) may include a plurality of electrode patterns. For example, the conductive pattern portion (120) has a plurality of pads spaced apart from each other along a horizontal direction. For example, the conductive pattern portion (120) may include a plurality of pads. At this time, the number of the plurality of pads of the conductive pattern portion (120) may correspond to the number of the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6). For example, the number of the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) may be six, and accordingly, the conductive pattern portion (120) may include first to sixth pads (121, 122, 123, 124, 125, 126) spaced apart from each other along a horizontal direction. One surface of the first to sixth pads (121, 122, 123, 124, 125, 126) may be a contact surface that makes contact or does not make contact with an external terminal to transmit information of the smart IC substrate (100) to the outside. In addition, the other surface of the first to sixth pads (121, 122, 123, 124, 125, 126) may be a bonding surface that is wire-bonded to a terminal of a chip mounted on the smart IC substrate (100). Preferably, the other surface of the first to sixth pads (121, 122, 123, 124, 125, 126) exposed through a plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) may function as a bonding surface that is wire-bonded.

[0146] The first to sixth pads (121, 122, 123, 124, 125, 126) may also be referred to as upper pads.

[0147] Each of the first to sixth pads (121, 122, 123, 124, 125, 126) may be provided with multiple layers. The first to sixth pads (121, 122, 123, 124, 125, 126) may have the same layer structure.

[0148] Referring to FIG. 3, each of the first to sixth pads (121, 122, 123, 124, 125, 126) may include a metal layer (120a) disposed on one surface of the substrate (110) and a cover layer covering an exposed surface of the metal layer (120a). At this time, the cover layer may also be referred to as a surface treatment layer disposed on the surface of the metal layer (120a). The cover layer may include a first cover layer (120b) and a second cover layer (120ca, 120cb) depending on the position. The first cover layer (120b) may be referred to as an upper cover layer, and the second cover layers (120ca, 120cb) may be referred to as a lower cover layer.

[0149] The metal layer (120a) is disposed on one surface (110S1) of the substrate (110). The metal layer (120a) may include at least one material selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the metal layer (120a) may be a copper foil layer attached to the substrate (110), and thus may include copper.

[0150] The metal layer (120a) may have a thickness within a set range. For example, the thickness of the metal layer (120a) may be 20 μm to 75 μm, 22 μm to 65 μm, or 25 μm to 60 μm. When the thickness of the metal layer (120a) is less than 20 μm, the resistance of the metal layer (120a) may increase, and thus the resistance of the conductive pattern portion (120) may increase, resulting in deterioration of signal characteristics. When the thickness of the metal layer (120a) exceeds 75 μm, the thickness of the smart IC substrate may increase, and the thickness of the smart IC card may increase. Furthermore, when the thickness of the metal layer (120a) exceeds 75 μm, the time for forming the conductive pattern portion (120) may increase, which may lower process efficiency and lower product yield. For example, the conductive pattern portion (120) can be manufactured by patterning a metal layer (120a) having a certain thickness placed on a substrate (110) using an etching method. In addition, as the thickness of the metal layer (120a) increases, the etching time of the metal layer (120a) can increase, and thus the manufacturing time can increase.

[0151] The first cover layer (120b) and the second cover layer (120ca, 120cb) may be disposed on the surface of the above-described patterned metal layer (120a). That is, a portion of the surface of the metal layer (120a) may not be covered by the substrate (110). In addition, the first cover layer (120b) and the second cover layer (120c) may be provided to cover the surface of the metal layer (120a) that is not covered by the substrate (110).

[0152] In addition, the first cover layer (120b) and the second cover layer (120c) can enable the contact surface and / or bonding surface of the conductive pattern portion (120) to satisfy a certain level of required characteristics. For example, the first cover layer (120b) and the second cover layer (120c) can enable the contact surface and / or bonding surface of the conductive pattern portion (120) to have a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, hardness, gloss, and wire bonding properties.

[0153] The contact surface and bonding surface of the conductive pattern portion (120) may be required to have different characteristics. The contact surface of the conductive pattern portion (120) may be a surface exposed to the outside, and thus may be required to have a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness for continuous connection with an external device. In addition, the bonding surface of the conductive pattern portion (120) may be a surface electrically connected to the terminal of the chip, and thus may be required to have a certain level of wire bondability.

[0154] The first cover layer (120b) may be disposed on the surface of the metal layer (120a) corresponding to the contact surface of the conductive pattern portion (120). The first cover layer (120b) may satisfy the required characteristics that the contact surface of the conductive pattern portion (120) should have. For example, the first cover layer (120b) may have a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, and hardness. At this time, the metal layer (120a) may be disposed on the upper surface corresponding to one side (110S1) of the substrate (110). Accordingly, the first cover layer (120b) may cover the upper surface of the metal layer (120a). In addition, the first cover layer (120b) may not be provided on the side of the metal layer (120a) that is not substantially used as a contact surface. However, the embodiment is not limited thereto. The first cover layer (120b) may extend from the upper surface of the metal layer (120a) and cover at least a portion of the side surface of the metal layer (120a), according to an embodiment.

[0155] The first cover layer (120b) may be provided with multiple layers. For example, the first cover layer (120b) may include a first layer (120b1) and a second layer (120b2). The first layer (120b1) of the first cover layer (120b) may be disposed on the conductive pattern portion (120). In addition, the second layer (120b2) of the first cover layer (120b) may be disposed on the first layer (120b1) of the first cover layer (120b). In this case, the second layer (120b2) of the first cover layer (120b) may also impart a certain level of hardness and glossiness or higher to the conductive pattern portion (120).

[0156] The first cover layer (120b) may include nickel. The first cover layer (120b) may refer to a seed layer for forming the second layer (120b2). The first cover layer (120b) may be a barrier layer that prevents the metal material constituting the metal layer (120a) from diffusing into the second layer (120b2). In addition, the first cover layer (120b) may be an oxidation prevention layer that prevents oxidation of the metal layer (120a).

[0157] The second layer (120b2) of the first cover layer (120b) may be disposed on the upper surface and side surface of the first layer (120b1). The second layer (120b2) of the first cover layer (120b) may include at least one of gold (Au) and silver (Ag).

[0158] However, the embodiment is not limited thereto, and the first cover layer (120b) may be a nitride having a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, and hardness. For example, the first cover layer (120b) may include at least one of titanium nitride (TiNx) and tantalum nitride (TaNx). For example, titanium nitride (TiNx) and tantalum nitride (TaNx) have a gold color. Therefore, when the first cover layer (120b) is provided with at least one of titanium nitride (TiNx) and tantalum nitride (TaNx), mechanical resistance can be improved compared to a cover layer using gold (Au), and the product cost can be reduced while improving design satisfaction.

[0159] Additionally, the second cover layer (120ca, 120cb) may be placed at a different location from the location where the first cover layer (120b) is placed.

[0160] For example, the second cover layer (120ca, 120cb) may be provided on the other surface of the metal layer (120a) that is not covered by the first cover layer (120b). That is, the second cover layer (120ca, 120cb) may be disposed on the lower surface of the metal layer (120a).

[0161] That is, at least a portion of the lower surface of the metal layer (120a) of each of the first to sixth pads (121, 122, 123, 124, 125, 126) can be exposed through a plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6), the first dummy hole (DH1), and the second dummy hole (DH2). Accordingly, the lower surface of the metal layer (120a) can be arranged on the lower surface of the metal layer (120a) that overlaps the bonding hole (BH) and the dummy hole (DH) in the third direction (3D).

[0162] At this time, the second cover layer (120ca, 120cb) may include a 2-1 cover layer (120ca) and a 2-2 cover layer (120cb) depending on the position. Preferably, the 2-1 cover layer (120ca) may be disposed within the bonding hole (BH). In addition, the 2-2 cover layer (120cb) may be disposed within the dummy hole (DH). Preferably, the 2-1 cover layer (120ca) may be disposed on the lower surface of the metal layer (120a) overlapping the bonding hole (BH) along the third direction (3D). In addition, the 2-2 cover layer (120cb) may be disposed on the lower surface of the metal layer (120a) overlapping the dummy hole (DH) along the third direction (3D). The 2-1 cover layer (120ca) can be referred to as the first lower cover layer, and the 2-2 cover layer (120cb) can be referred to as the second lower cover layer.

[0163] Each of the second cover layers (120ca, 120cb) may include a first layer (120c1a, 120c1b) and a second layer (120c2a, 120c2b) containing nickel.

[0164] In the embodiment, the second cover layer (120ca, 120cb) can be arranged not only on the lower surface of the metal layer (120a) exposed through the bonding hole (BH), but also on the lower surface of the metal layer (120a) exposed through the dummy hole (DH). Therefore, the embodiment can prevent the lower surface of the metal layer (120a) exposed through the bonding hole (BH) from being corroded in a subsequent process after the smart IC substrate (100) is manufactured, thereby further improving the electrical reliability and / or mechanical reliability of the smart IC substrate (100).

[0165]

[0166] Meanwhile, referring to FIG. 5, the smart IC substrate according to the second embodiment may further include a first adhesive layer (140). The first adhesive layer (140) may be disposed between one surface (110S1) of the substrate (110) and the conductive pattern portion (120). For example, the first adhesive layer (140) may be disposed between one surface of the substrate (110) and the lower surface of the metal layer (120a).

[0167] The first adhesive layer (140) may be provided for bonding between the conductive pattern portion (120) and the substrate (110). The first adhesive layer (140) may be referred to as a bonding sheet. The first adhesive layer (140) may be provided for bonding a copper foil layer (not shown), which is a metal layer prior to implementing a circuit such as the conductive pattern portion (120), to one surface (110S1) of the substrate (110).

[0168] For example, as in the first embodiment, the conductive pattern portion (120) may be placed directly on one surface of the substrate (110) without the first adhesive layer (140). However, in order to further improve the adhesion between the substrate (110) and the conductive pattern portion (120), a first adhesive layer (140) may be additionally placed between the substrate (110) and the conductive pattern portion (120).

[0169] The first adhesive layer (140) comprises a resin material. For example, the first adhesive layer (140) may comprise at least one of an epoxy resin, an acrylic resin, and a polyimide resin. In addition, the first adhesive layer (140) may comprise at least one additive selected from the group consisting of natural rubber, a plasticizer, a curing agent, and a phosphorus-based flame retardant. In this case, the flexibility of the first adhesive layer (140) may be improved.

[0170] The first adhesive layer (140) may have a thickness within a set range. For example, the thickness of the first adhesive layer (140) may be 8 μm to 35 μm, 10 μm to 30 μm, or 12 μm to 25 μm. If the thickness of the first adhesive layer (140) is less than 8 μm, the adhesive strength of the first adhesive layer (140) may decrease, thereby causing the conductive pattern portion (120) to be separated from the first adhesive layer (140). In addition, if the thickness of the first adhesive layer (140) exceeds 35 μm, the thickness of the smart IC substrate or the thickness of the smart IC card may increase.

[0171] At this time, a plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6), a first dummy hole (DH1), and a second dummy hole (DH2) may be provided so as to penetrate the substrate (110) and the first adhesive layer (140). For example, a plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6), a first dummy hole (DH1), and a second dummy hole (DH2) may penetrate from one surface of the first adhesive layer (140) to the other surface (110S2) of the substrate (110). For example, each of the plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6), the first dummy hole (DH1), and the second dummy hole (DH2) can be formed through a process such as punching while the first adhesive layer (140) is placed on the substrate (110), thereby commonly penetrating the substrate (110) and the first adhesive layer (140).

[0172] The planar area of ​​the first adhesive layer (140) may correspond to the planar area of ​​the substrate (110). For example, the first adhesive layer (140) may entirely cover one side (110S1) of the substrate (110). Accordingly, the rigidity of the substrate (110) may be further improved.

[0173] Accordingly, by additionally placing a first adhesive layer (140) between the substrate (110) and the conductive pattern portion (120), the adhesion between the substrate (110) and the conductive pattern portion (120) can be further improved. Accordingly, the physical reliability and / or electrical reliability of the smart IC substrate can be further improved.

[0174]

[0175] Below, various embodiments of the dummy hole (DH) provided in the embodiment are described.

[0176] Referring to FIG. 6, a plurality of bonding holes (BH1, BH2, BH3, BH4, BH5, BH6) may be provided to penetrate the entire substrate (110) and the first adhesive layer (140). In contrast, the first dummy hole (DH1) and the second dummy hole (DH2) may penetrate the entire substrate (110) but not the first adhesive layer (140).

[0177] For example, the first dummy hole (DH1) and the second dummy hole (DH2) may partially penetrate the first adhesive layer (140), or may be provided only in the substrate (110) and not in the first adhesive layer (140). In this case, although the drawing illustrates that the first dummy hole (DH1) and the second dummy hole (DH2) are not provided in the first adhesive layer (140), the present invention is not limited thereto. For example, the first dummy hole (DH1) and the second dummy hole (DH2) may be provided so as to penetrate at least a portion of the first adhesive layer (140) while entirely penetrating the substrate (110).

[0178] Through this, the embodiment prevents the lower surface of the metal layer (120a) from being exposed through the first dummy hole (DH1) and the second dummy hole (DH2), and thus, the 2-2 cover layer (120cb) that should be provided on the lower surface of the metal layer (120a) exposed through the first dummy hole (DH1) and the second dummy hole (DH2) can be omitted.

[0179]

[0180] Referring to FIG. 7, the first dummy hole (DH) and the second dummy hole (DH2) may partially penetrate the substrate (110) from the other surface (110S2) toward the one surface (110S1) of the substrate (110). For example, the depth (T1) of the first dummy hole (DH1) and the second dummy hole (DH2) in the third direction (3D) may be smaller than the thickness of the substrate (110) in the third direction (3D).

[0181] For example, the depth (T1) of the first dummy hole (DH1) and the second dummy hole (DH2) in the third direction (3D) can satisfy a range of 70% to 95% of the thickness of the substrate (110) in the third direction (3D). Preferably, the depth (T1) of the first dummy hole (DH1) and the second dummy hole (DH2) in the third direction (3D) can satisfy a range of 72% to 93% of the thickness of the substrate (110) in the third direction (3D). More preferably, the depth (T1) of the first dummy hole (DH1) and the second dummy hole (DH2) in the third direction (3D) can satisfy a range of 75% to 90% of the thickness of the substrate (110) in the third direction (3D).

[0182] If the depth (T1) of the first dummy hole (DH1) and the second dummy hole (DH2) in the third direction (3D) is less than 70% of the thickness of the substrate (110) in the third direction (3D), the stress dispersing / absorbing effect, the elasticity-providing effect, and / or the flow control effect of the molding member exhibited by the first dummy hole (DH1) and the second dummy hole (DH2) may be insufficient. If the depth (T1) of the first dummy hole (DH1) and the second dummy hole (DH2) in the third direction (3D) exceeds 95% of the thickness of the substrate (110) in the third direction (3D), the first dummy hole (DH1) and the second dummy hole (DH2) may penetrate the substrate (110) due to a process error in the process of forming the first dummy hole (DH1) and the second dummy hole (DH2). At this time, in the embodiment of FIG. 7, the first dummy hole (DH1) and the second dummy hole (DH2) are made to not penetrate the substrate (110), so that the 2-2 cover layer (120cb) described in FIG. 4 can be omitted. However, if the first dummy hole (DH1) and the second dummy hole (DH2) penetrate the entire substrate (110) due to the process error described above, the 2-2 cover layer (120cb) cannot be omitted, and further, since the 2-2 cover layer (120cb) is omitted without recognizing that the first dummy hole (DH1) and the second dummy hole (DH2) have penetrated the substrate (110), reliability problems such as corrosion of the conductive pattern portion (120) may occur.

[0183] Through this, the embodiment prevents the lower surface of the metal layer (120a) from being exposed through the first dummy hole (DH1) and the second dummy hole (DH2), and thus, the 2-2 cover layer (120cb) that should be provided on the lower surface of the metal layer (120a) exposed through the first dummy hole (DH1) and the second dummy hole (DH2) can be omitted.

[0184]

[0185] Referring to FIG. 8, the conductive pattern portion (120) of the embodiment may include a plurality of pads (121, 122, 123, 124, 125, 126). At this time, depending on the specifications of the chip attached to the smart IC substrate (100), at least one pad among the plurality of pads (121, 122, 123, 124, 125, 126) may not function as an electrode electrically connected to the chip.

[0186] For example, the chip may include a first chip including five terminals and a second chip including six terminals. In addition, the smart IC substrate (100) of the embodiment may be a substrate that can be commonly used for the first chip and the second chip.

[0187] At this time, when a second chip is attached on the above-described smart IC substrate (100), all of the plurality of pads (121, 122, 123, 124, 125, 126) can function as electrodes electrically connected to the second chip.

[0188] In contrast, when the first chip is attached on the above-described smart IC substrate (100), any one of the plurality of pads (121, 122, 123, 124, 125, 126) can function as a dummy pad (DP).

[0189] The plurality of pads (121, 122, 123, 124, 125, 126) may include electrode pads electrically connected to the chip and dummy pads (DP) not electrically connected to the chip.

[0190] For example, when a first chip is attached on a smart IC substrate (100), a plurality of pads (121, 122, 123, 124, 125, 126) can be divided into electrode pads and dummy pads (DP) and function as such. As another example, when a first chip is attached on a smart IC substrate (100), a plurality of pads (121, 122, 123, 124, 125, 126) can function only as electrode pads.

[0191] When multiple pads (121, 122, 123, 124, 125, 126) function as dummy pads (DP), holes provided in an area overlapping the dummy pads (DP) along the vertical direction can function as auxiliary dummy holes (DHP) rather than as bonding holes (DH6) as in FIG. 2.

[0192] In this case, the planar shape of the auxiliary dummy hole (DHP) may be different from the planar shapes of the first dummy hole (DH1) and the second dummy hole (DH2). For example, the planar shape of the auxiliary dummy hole (DHP) may be the same as the planar shape of the bonding hole (BH).

[0193] However, the embodiment is not limited thereto. For example, a bonding hole (BH) and a dummy hole (DH) may be formed on the smart IC substrate (100) depending on the chip to be attached. In this case, when the first chip is attached on the smart IC substrate (100), a bonding hole (BH) and a dummy hole (DH) may not be formed in an area overlapping the dummy pad (DP) in the third direction (3D).

[0194]

[0195] Referring to FIG. 9, the conductive pattern portion (120) of the embodiment may include a plurality of pads (121, 122, 123, 124, 125, 126). At this time, depending on the specifications of the chip attached to the smart IC substrate (100), at least one pad among the plurality of pads (121, 122, 123, 124, 125, 126) may not function as an electrode electrically connected to the chip.

[0196] For example, the chip may include a first chip including five terminals and a second chip including six terminals. In addition, the smart IC substrate (100) of the embodiment may be a substrate that can be commonly used for the first chip and the second chip.

[0197] At this time, when a second chip is attached on the above-described smart IC substrate (100), all of the plurality of pads (121, 122, 123, 124, 125, 126) can function as electrodes electrically connected to the second chip.

[0198] In contrast, when the first chip is attached on the above-described smart IC substrate (100), any one of the plurality of pads (121, 122, 123, 124, 125, 126) may function as a dummy pad (DP). In this case, an auxiliary dummy hole (DHP) may be provided in an area overlapping the dummy pad (DP) in a vertical direction. The auxiliary dummy hole (DHP) may be arranged on the third side or the upper side of the chip attachment area (CAR). In this case, the auxiliary dummy hole (DHP) may have a function of absorbing and / or dispersing stress applied in the second direction (2D). Accordingly, the auxiliary dummy hole (DHP) may be provided to extend in the second direction (2D). For example, the auxiliary dummy hole (DHP) may have a width greater in the second direction (2D) than in the first direction (1D).

[0199]

[0200] Meanwhile, the first pad (121) in the previous embodiment includes an inner portion provided in the chip attachment area (CAR) and an outer portion provided in the outer region of the chip attachment area (CAR), and the first bonding hole (BH1) may be provided in the outer portion of the first pad (121), and the first dummy hole (DH1) and the second dummy hole (DH2) may be provided in the inner portion of the first pad (121).

[0201] In contrast, the first pad (121) may be provided with the inner and outer portions separated and not electrically connected.

[0202] Referring to FIG. 10, the conductive pattern portion (120) of the embodiment may include a dummy pattern (DP). The dummy pattern (DP) may be provided in an area overlapping the chip attachment area (CAR) along the third direction (3D). In addition, unlike the previous embodiment, the dummy pattern (DP) may not be connected to the first pad (121). For example, the dummy pattern (DP) may correspond to the inner portion of the first pad (121) of the previous embodiment.

[0203] In this case, the conductive pattern portion (120) exposed through the first dummy hole (DH1) and the second dummy hole (DH2) can be provided as a dummy pattern (DP) rather than a pad that functions as an electrode, thereby further improving the design freedom of the first dummy hole (DH1) and the second dummy hole (DH2).

[0204]

[0205] Below, various modified examples of dummy holes according to embodiments are described.

[0206] Fig. 11 is a plan view showing a dummy hole according to a first modified example, Fig. 12 is a plan view showing a dummy hole according to a second modified example, Fig. 13 is a plan view showing a dummy hole according to a third modified example, and Fig. 14 is a plan view showing a dummy hole according to a fourth modified example.

[0207] Before explaining the modified example, the dummy hole (DH) in the previous embodiment may include a first dummy hole (DH1) and a second dummy hole (DH2), and the first dummy hole (DH1) and the second dummy hole (DH2) may have shapes that are symmetrical with respect to the central axis (CA).

[0208] In contrast, the first dummy hole (DH1) and the second dummy hole (DH2) may have shapes that are asymmetrical with respect to the central axis (CA).

[0209] Referring to (a) of FIG. 11, the dummy hole (DH) may include a first dummy hole (DH1) and a second dummy hole (DH2). At this time, the first dummy hole (DH1) may be provided to extend continuously along the first direction (1D). For example, the first dummy hole (DH1) may include a single dummy hole extending along the first direction (1D). Alternatively, the second dummy hole (DH2) may be formed discontinuously along the first direction (1D). For example, the second dummy hole (DH2) may include a plurality of second sub-dummy holes (DH21, DH22, DH23) extending along the first direction (1D) and spaced apart from each other along the first direction (1D). Through this, the embodiment can efficiently distribute and / or absorb stress acting in various bending environments.

[0210] Referring to (b) of FIG. 11, at this time, the second dummy hole (DH2) may be formed to extend continuously along the first direction (1D). For example, the second dummy hole (DH1) may include a single dummy hole extending along the first direction (1D). Alternatively, the first dummy hole (DH1) may be formed discontinuously along the first direction (1D). For example, the first dummy hole (DH1) may include a plurality of first sub-dummy holes (DH11, DH12, DH13) extending along the first direction (1D) and spaced apart from each other along the first direction (1D). Through this, the embodiment can efficiently distribute and / or absorb stress acting in various bending environments.

[0211] In addition, referring to (a) of FIG. 12, the dummy hole (DH) may include a first dummy hole (DH1) and a second dummy hole (DH2). At this time, the first dummy hole (DH1) may include a plurality of first sub-dummy holes (DH11, DH12, DH13). In addition, the second dummy hole (DH2) may include a plurality of second sub-dummy holes (DH21, DH22, DH23).

[0212] At this time, the width of the first dummy hole (DH1) in the second direction (2D) may be different from the width of the second dummy hole (DH2) in the second direction (2D). For example, the width of the first dummy hole (DH1) in the second direction (2D) may be greater than the width of the second dummy hole (DH2) in the second direction (2D). Through this, the embodiment can efficiently distribute and / or absorb stress acting in various bending environments.

[0213] In addition, referring to (b) of FIG. 12, the dummy hole (DH) may include a first dummy hole (DH1) and a second dummy hole (DH2). At this time, the first dummy hole (DH1) may include a plurality of first sub-dummy holes (DH11, DH12, DH13). In addition, the second dummy hole (DH2) may include a plurality of second sub-dummy holes (DH21, DH22, DH23).

[0214] At this time, the width of the first dummy hole (DH1) in the second direction (2D) may be different from the width of the second dummy hole (DH2) in the second direction (2D). For example, the width of the first dummy hole (DH1) in the second direction (2D) may be smaller than the width of the second dummy hole (DH2) in the second direction (2D). Through this, the embodiment can efficiently distribute and / or absorb stress acting in various bending environments.

[0215] Referring to (a) of Fig. 13, the dummy hole (DH) may include a first dummy hole (DH1), a second dummy hole (DH2), and a third dummy hole (DH3). The third dummy hole (DH3) may be provided on the third side of the central axis (CA), and, for example, may be arranged on the upper side of the central axis (CA) in a planar view. The third dummy hole (DH3) may be provided to extend long in the second direction (2D), thereby efficiently distributing and / or absorbing stress applied in the second direction (2D).

[0216] Referring to (b) of Fig. 13, the dummy hole (DH) may include a first dummy hole (DH1), a second dummy hole (DH2), and a fourth dummy hole (DH4). The fourth dummy hole (DH4) may be provided on the fourth side of the central axis (CA), and, for example, may be arranged on the lower side of the central axis (CA) in a plan view. The third dummy hole (DH3) may be provided to extend in the second direction (2D), thereby efficiently distributing and / or absorbing stress applied in the second direction (2D).

[0217] Additionally, the dummy hole (DH) may have a structure including a first dummy hole (DH1), a second dummy hole (DH2), a third dummy hole (DH3), and a fourth dummy hole (DH4), respectively.

[0218] Also, referring to (a) of FIG. 14, the dummy hole (DH) may include a first dummy hole (DH1), a second dummy hole (DH2), and a third dummy hole (DH3). The third dummy hole (DH3) may be provided on the third side of the central axis (CA), and for example, may be disposed on the upper side of the central axis (CA) in a plan view. The third dummy hole (DH3) may be provided to extend long in the second direction (2D), thereby efficiently distributing and / or absorbing stress applied in the second direction (2D). At this time, at least a portion of the first dummy hole (DH1) may be connected to the third dummy hole (DH3). For example, the dummy hole (DH) may include a first connection area (DH5) in which the first dummy hole (DH1) and the third dummy hole (DH3) are connected to each other. Through this, the embodiment can efficiently distribute and / or absorb stress applied in a diagonal direction between the first direction (1D) and the second direction (2D), rather than in both.

[0219] Referring to (b) of FIG. 14, the dummy hole (DH) may include a first dummy hole (DH1), a second dummy hole (DH2), and a fourth dummy hole (DH4). The fourth dummy hole (DH4) may be provided on the fourth side of the central axis (CA), and for example, may be disposed on the lower side of the central axis (CA) in a plan view. The third dummy hole (DH3) may be provided to extend in the second direction (2D), thereby efficiently distributing and / or absorbing stress applied in the second direction (2D). At this time, at least a portion of the second dummy hole (DH2) may be connected to the fourth dummy hole (DH4). For example, the dummy hole (DH) may include a second connection area (DH6) in which the second dummy hole (DH2) and the fourth dummy hole (DH4) are connected to each other. Through this, the embodiment can efficiently distribute and / or absorb stress applied in a diagonal direction between the first direction (1D) and the second direction (2D), rather than in both.

[0220] The dummy hole (DH) according to the embodiment described above may include at least one of the first dummy hole (DH1), the second dummy hole (DH2), the third dummy hole (DH3), and the fourth dummy hole (DH4), thereby increasing the opening area on the other surface (110S2) of the substrate (110) by the dummy hole (DH). Therefore, the embodiment may make the opening area on the other surface of the substrate (110) opened by the dummy hole (DH) larger than the opening area on the other surface of the substrate (110) opened by the plurality of bonding holes (BH). Through this, the embodiment may more efficiently distribute the stress acting on the smart IC substrate (100), and further prevent the stress from being applied to the bonding hole (BH). Therefore, the embodiment may prevent the disconnection of the connecting member (1200) bonded to the chip through the bonding hole (BH).

[0221]

[0222] Fig. 15 is a plan view of the other surface of a smart IC substrate according to the seventh embodiment, and Fig. 16 is a cross-sectional view taken along the AA' direction of Fig. 15.

[0223] Referring to FIGS. 15 and 16, the smart IC substrate may be provided in a dual type. For example, the smart IC substrate may have a structure in which conductive pattern portions are provided on each side of the substrate (110). For example, the smart IC substrate may be disposed on one side (110S1) of the substrate (110) and may include the conductive pattern portion (120) described with reference to FIGS. 1 to 14. In this case, the conductive pattern portion (120) described with reference to FIGS. 1 to 14 may be referred to as a first conductive pattern portion (120) or an upper conductive pattern portion (120) in the dual type smart IC substrate.

[0224] In addition, the smart IC substrate may further include a second conductive pattern portion (130, 135) or a lower conductive pattern portion (130, 135) arranged on the other surface (110S2) of the substrate (110). Hereinafter, this will be described as a second conductive pattern portion.

[0225] The second conductive pattern portion (130, 135) may be spaced apart from the first conductive pattern portion (120) with the substrate (110) interposed therebetween. The second conductive pattern portion (130, 135) may be an antenna pad for antenna function. For example, the second conductive pattern portion (130, 135) may be an antenna pad that electrically connects a chip mounted on a smart IC substrate (100) and an antenna pattern.

[0226] At this time, the second conductive pattern portion (130, 135) may be formed in a different manner from the first conductive pattern portion (120). For example, the first conductive pattern portion (120) may be formed by etching the metal layer (120a) through an exposure and development process. For example, the first conductive pattern portion (120) may be formed through a photolithography process.

[0227] In contrast, the second conductive pattern portion (130, 135) may be attached to the other surface (110S2) of the substrate (110) in a pick and place manner. For example, the second conductive pattern portion (130, 135) may be formed on a separate structure and then attached to the other surface (110S2) of the substrate (110).

[0228] To this end, a second adhesive layer (150) may be provided between the other surface (110S2) of the substrate (110) and the second conductive pattern portion (130, 135). The second adhesive layer (150) may provide adhesive strength for attaching the pre-manufactured second conductive pattern portion (130, 135) to the other surface (110S2) of the substrate (110).

[0229] In this way, the embodiment can form the first conductive pattern portion (120) and the second conductive pattern portion (130, 135) on one side (110S1) and the other side (110S2) of the substrate (110) in different ways, respectively. Therefore, the embodiment can solve the problem that the manufacturing process of the double-sided wiring structure is complicated due to the product structure characteristics of the smart IC substrate (100), and the manufacturing cost increases as the product yield decreases. That is, the embodiment can simplify the manufacturing process of the smart IC substrate (100) by forming the antenna pattern by attaching the second conductive pattern portion (130, 135) manufactured in advance to the substrate (110). Furthermore, the embodiment can easily adjust the attachment position of the second conductive pattern portion (130, 135) according to various product designs, can be applied to products of various designs, and can improve the design freedom accordingly. Furthermore, the embodiment can reduce manufacturing costs by simplifying the process, and further improve product yield.

[0230] By virtue of the characteristics described above, the second adhesive layer (150) can have the structure and / or properties of the first adhesive layer (140).

[0231] The second adhesive layer (150) may be selectively provided on the other surface (110S2) of the substrate (110). The second adhesive layer (150) may be selectively provided only in the area where the second conductive pattern portion (130, 135) is to be arranged on the other surface (110S2) of the substrate (110). Through this, the embodiment can reduce the plane area of ​​the second adhesive layer (150) and further reduce the manufacturing cost by reducing the amount of the second adhesive layer (150). Through this, the other surface (110S2) of the substrate (110) may include a portion covered with the second adhesive layer (150) and a portion not covered with the second adhesive layer (150). In addition, the portion not covered with the second adhesive layer (150) can provide a space for a separate adhesive material to be arranged in a later process of assembling the smart IC card. Therefore, in the embodiment, it is possible to increase the thickness of the above-described adhesive material in a smart IC substrate (100) having the same thickness as the comparative example, thereby improving process characteristics in the assembly process and enabling the smart IC substrate (100) to be more stably bonded.

[0232] In addition, the second adhesive layer (150) may have a predetermined thickness. For example, the second adhesive layer (150) may be greater than the thickness of the first adhesive layer (140). For example, the thickness of the second adhesive layer (150) may satisfy a range of 105% to 220% of the thickness of the first adhesive layer (140), or a range of 110% to 210%, or a range of 115% to 200%. That is, the embodiment allows the thickness of the second adhesive layer (150) to be greater than the thickness of the first adhesive layer (140), so that the second conductive pattern portion (130, 135) can be more stably attached to the other surface (110S2) of the substrate (110), thereby improving product reliability. Furthermore, the embodiment can reduce the height difference between the terminal of the chip and the second conductive pattern portion (130, 135) by the difference in the thicknesses (T1, T2) described above by making the thickness of the second adhesive layer (150) greater than that of the first adhesive layer (140). Therefore, the embodiment can improve the process characteristics in the process of wire-bonding the terminal of the chip and the second conductive pattern portion (130, 135), and can further improve the wire bonding reliability accordingly. At this time, if the thickness of the second adhesive layer (150) is less than 105% of the thickness of the first adhesive layer (140), the product reliability improvement effect and the process characteristic improvement effect as described above may be insufficient. In addition, if the thickness of the second adhesive layer (150) exceeds 200% of the thickness of the first adhesive layer (140), the thickness of the smart IC substrate (100) may increase.

[0233] The second adhesive layer (150) can be formed of various adhesive materials by being selectively disposed only in the area where the second conductive pattern portion (130, 135) is disposed. For example, the second adhesive layer (150) can be provided as a paste having adhesive properties. For example, the second adhesive layer (150) can be provided as a conductive paste or a non-conductive paste.

[0234] The second conductive pattern portion (130, 135) can be attached to the other surface (110S2) of the substrate (110) by adhesive force provided through the second adhesive layer (150). The second conductive pattern portion (130, 135) can have a predetermined width and thickness.

[0235] At this time, the embodiment can form the second conductive pattern portion (130, 135) by attaching a pre-manufactured conductive pattern as described above, and accordingly, formation is possible without restrictions on the width of the second conductive pattern portion (130, 135).

[0236] In addition, the embodiment can increase the contact area between the second conductive pattern portion (130, 135) and the second adhesive layer (150) by making the width of the second conductive pattern portion (130, 135) larger than the width of the first conductive pattern portion (120), thereby increasing the bonding strength thereof, thereby allowing the second conductive pattern portion (130, 135) to be more stably attached to the other surface (110S2) of the substrate (110). Through this, the embodiment can further improve product reliability. In addition, the embodiment can increase the allowable current of the second conductive pattern portion (130, 135) by making the width of the second conductive pattern portion (130, 135) larger than the width of the first conductive pattern portion (120), thereby improving the antenna characteristics.

[0237] At this time, the second conductive pattern portion (130, 135) may be provided as an alloy. For example, the second conductive pattern portion (130, 135) may be provided as a Cu / Sn / Ag alloy, a Fe / Ni / Ag alloy, or a Cu / Sn / Ag / Al / Ni alloy.

[0238] The second conductive pattern portion (130, 135) may include a plurality of pads that are electrically spaced apart from each other. For example, the second conductive pattern portion (130, 135) may include a first antenna pad (130) and a second antenna pad (135) that is electrically spaced apart from the first antenna pad (130). For example, the first antenna pad (130) may be a pad to which positive polarity power is applied, and the second antenna pad (135) may be a pad to which negative polarity power is applied.

[0239]

[0240] Hereinafter, the same reference numerals are given to configurations that are substantially the same as the configuration of the smart IC substrate described with reference to FIGS. 1 to 16.

[0241] FIG. 17 is a plan view of one side of a smart IC substrate according to a first embodiment, FIG. 18 is a plan view of the other side of a smart IC substrate according to an eighth embodiment, FIG. 19 is a cross-sectional view taken along the AA' direction of FIG. 18 according to the eighth embodiment, FIG. 20 is a cross-sectional view taken along the AA' direction of FIG. 18 according to the ninth embodiment, FIG. 21 is a cross-sectional view taken along the AA' direction of FIG. 18 according to the tenth embodiment, FIG. 22 is a cross-sectional view taken along the AA' direction of FIG. 18 according to the eleventh embodiment, FIG. 23 is a cross-sectional view taken along the AA' direction of FIG. 18 according to the twelfth embodiment, FIG. 24 is a cross-sectional view taken along the AA' direction of FIG. 18 according to the thirteenth embodiment, FIG. 25 is a plan view of the other side of a smart IC substrate according to another embodiment, and FIG. 16 is a cross-sectional view of a smart IC substrate according to yet another embodiment. This is a plan view of the other side of the IC substrate.

[0242] Referring to FIGS. 17 and 18, the smart IC substrate (100) includes a substrate (110), a first conductive pattern portion (120), and a second conductive pattern portion (130).

[0243] At this time, the overall structural characteristics of the substrate (110), the first conductive pattern portion (120), and the second conductive pattern portion (130) have been described in the previous embodiment, so a detailed description thereof is omitted.

[0244] The substrate (110) may have through holes. For example, the substrate (110) may include a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) spaced apart from each other in the horizontal direction.

[0245] The plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be regions for electrically connecting the first conductive pattern portion (120) arranged on the first surface (110S1) of the substrate (110) and the terminal of the chip. Preferably, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be regions for wire bonding between the terminal of the chip and the first conductive pattern portion (120).

[0246] The first conductive pattern portion (120) may include a plurality of pads, and the number of the plurality of pads may correspond to the number of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the number of the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be eight, and accordingly, the first conductive pattern portion (120) may include first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) spaced apart from each other along the horizontal direction. One surface of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be a contact surface that makes contact or does not make contact with an external terminal in order to transmit information of the smart IC substrate (100) to the outside. In addition, the other surface of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may be a bonding surface that is wire-bonded to a terminal of a chip mounted on the smart IC substrate (100). The first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may also be referred to as an upper pad.

[0247] Referring to FIG. 19, each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may include a metal layer (120a) disposed on one surface of the substrate (110), and a cover layer covering an exposed surface of the metal layer (120a).

[0248] At this time, the cover layer may refer to a surface treatment layer disposed on the surface of the metal layer (120a). The cover layer may include a first cover layer (120b) and a second cover layer (120c).

[0249] The metal layer (120a) is disposed on the first surface (110S1) of the substrate (110). The metal layer (120a) may include at least one material selected from the group consisting of gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Preferably, the metal layer (120a) may be a copper foil layer or a rolled copper layer attached to the substrate (110), and thus may include copper.

[0250] The metal layer (120a) may have a thickness within a set range. For example, the thickness of the metal layer (120a) may be 20 μm to 75 μm, 22 μm to 65 μm, or 25 μm to 60 μm. When the thickness of the metal layer (120a) is less than 20 μm, the resistance of the metal layer (120a) may increase, and thus the resistance of the first conductive pattern portion (120) may increase, resulting in deterioration of signal characteristics. When the thickness of the metal layer (120a) exceeds 75 μm, the thickness of the smart IC substrate may increase, and the thickness of the smart IC card may increase. Furthermore, when the thickness of the metal layer (120a) exceeds 75 μm, the time for forming the first conductive pattern portion (120) may increase, resulting in deterioration of process efficiency and deterioration of product yield. For example, the first conductive pattern portion (120) can be manufactured by patterning a metal layer (120a) having a certain thickness disposed on a substrate (110) using an etching method. In addition, as the thickness of the metal layer (120a) increases, the etching time of the metal layer (120a) can increase, and thus the manufacturing time can increase.

[0251] The first cover layer (120b) and the second cover layer (120c) may be disposed on the surface of the above-described patterned metal layer (120a). That is, a portion of the surface of the metal layer (120a) may not be covered by the substrate (110). In addition, the first cover layer (120b) and the second cover layer (120c) may be provided to cover the surface of the metal layer (120a) that is not covered by the substrate (110).

[0252] In addition, the first cover layer (120b) and the second cover layer (120c) can enable the contact surface and / or bonding surface of the first conductive pattern portion (120) to satisfy a certain level of required characteristics. For example, the first cover layer (120b) and the second cover layer (120c) can enable the contact surface and / or bonding surface of the first conductive pattern portion (120) to have a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, hardness, gloss, and wire bonding properties.

[0253] The contact surface and bonding surface of the first conductive pattern portion (120) may be required to have different characteristics. The contact surface of the first conductive pattern portion (120) may be a surface exposed to the outside, and thus may be required to have a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness for continuous connection with an external device. In addition, the bonding surface of the first conductive pattern portion (120) may be a surface electrically connected to a terminal of the chip, and thus may be required to have a certain level of wire bondability.

[0254] The first cover layer (120b) may be disposed on the surface of the metal layer (120a) corresponding to the contact surface of the first conductive pattern portion (120). The first cover layer (120b) may satisfy the required characteristics that the contact surface of the first conductive pattern portion (120) should have. For example, the first cover layer (120b) may have a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, and hardness. At this time, the metal layer (120a) may be disposed on the upper surface corresponding to the first surface (110S1) of the substrate (110). Accordingly, the first cover layer (120b) may cover the upper surface of the metal layer (120a). In addition, the first cover layer (120b) may not be provided on the side surface of the metal layer (120a) that is not substantially used as a contact surface. However, the embodiment is not limited thereto. The first cover layer (120b) may extend from the upper surface of the metal layer (120a) and cover at least a portion of the side surface of the metal layer (120a), according to an embodiment.

[0255] At this time, the first cover layer according to the comparative example has a silver color. For example, the first cover layer according to the comparative example includes a metal having a silver color while satisfying the above-described characteristics. Preferably, the comparative example provides the first cover layer using any one of palladium (Pd), platinum (Pt), and rhodium (Rh). As a result, the first cover layer of the comparative example has a silver color. However, palladium (Pd), platinum (Pt), and rhodium (Rh) are expensive precious metals. Accordingly, when the first cover layer is provided using palladium (Pd), platinum (Pt), and rhodium (Rh), there is a problem that the manufacturing cost increases.

[0256] Accordingly, the embodiment provides a novel cover layer capable of solving the above-described problems of the first cover layer using palladium (Pd), platinum (Pt) and rhodium (Rh) having a silver color on the existing contact surface.

[0257] Specifically, the embodiment provides a new first cover layer having a color identical or similar to that of the first cover layer of the comparative example, while reducing manufacturing costs or unit product prices.

[0258] The first cover layer (120b) may have the same color as the first cover layer of the comparative example. For example, the first cover layer (120b) may have a silver color.

[0259] Additionally, the first cover layer (120b) may satisfy a certain level or higher of required characteristics. For example, the first cover layer (120b) may have a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0260] Specifically, the first cover layer (120b) may have a silver color while having a certain level or higher of corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0261] For this purpose, the first cover layer (120b) may include an alloy. For example, the first cover layer (120b) may be an alloy layer including copper. For example, the first cover layer (120b) may include copper (Cu), tin (Sn), and manganese (Mn).

[0262] That is, the embodiment may allow the first cover layer (120b) to include an alloy including copper (Cu), tin (Sn), and manganese (Mn), and thus have a silver color. Through this, the embodiment may provide a first conductive pattern portion (120) having the same color as the color of the contact surface of an existing smart IC substrate, thereby improving customer satisfaction.

[0263] In addition, the first cover layer (120b) has a silver color and can adjust the content of copper (Cu), tin (Sn), and manganese (Mn) in the alloy to satisfy a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0264] For example, the content of copper (Cu) in the first cover layer (120b) may be 45 wt% to 65 wt%. Preferably, the content of copper (Cu) in the first cover layer (120b) may be 48 wt% to 62 wt%. More preferably, the content of copper (Cu) in the first cover layer (120b) may be 50 wt% to 60 wt%.

[0265] If the content of copper (Cu) in the first cover layer (120b) is less than 45 wt%, the adhesion between the first cover layer (120b) and the metal layer (120a) may decrease. This may result in a problem of reduced reliability in separating the first cover layer (120b) from the metal layer (120a). In addition, if the content of copper (Cu) in the first cover layer (120b) is less than 45 wt%, the first cover layer (120b) may not satisfy at least one or more of a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness. In addition, if the content of copper (Cu) in the first cover layer (120b) exceeds 65 wt%, the content of tin (Sn) and / or manganese (Mn) in the first cover layer (120b) may decrease. Due to this, the first cover layer (120b) may not satisfy a certain level of corrosion resistance, oxidation resistance, wear resistance, and hardness.

[0266] The tin (Sn) content in the first cover layer (120b) may be 15 wt% to 35 wt%. Preferably, the tin (Sn) content in the first cover layer (120b) may be 17 wt% to 32 wt%. More preferably, the tin (Sn) content in the first cover layer (120b) may be 20 wt% to 30 wt%.

[0267] If the tin (Sn) content in the first cover layer (120b) is less than 15 wt%, the solid solution strengthening effect of the first cover layer (120b) is insufficient, and as a result, the corrosion resistance, oxidation resistance, wear resistance, and hardness of the first cover layer (120b) may deteriorate. In addition, if the tin (Sn) content in the first cover layer (120b) is less than 15 wt%, in a process of manufacturing an alloy including copper (Cu), tin (Sn), and manganese (Mn), the metal elements of copper (Cu), tin (Sn), and manganese (Mn) may not mix well with each other. As a result, it may be difficult to achieve the crystal structure of the above-described alloy, and thus, a problem may occur in which the crystal phase of the alloy becomes larger (for example, a problem in which it is difficult to refine the crystal phase). Additionally, if the content of tin (Sn) in the first cover layer (120b) exceeds 35 wt%, the resistance of the first conductive pattern portion (120) may increase, which may result in increased signal loss.

[0268] Additionally, the content of manganese (Mn) in the first cover layer (120b) may be 5 wt% to 20 wt%. Preferably, the content of manganese (Mn) in the first cover layer (120b) may be 7 wt% to 18 wt%. More preferably, the content of manganese (Mn) in the first cover layer (120b) may be 10 wt% to 15 wt%.

[0269] If the manganese (Mn) content in the first cover layer (120b) is less than 5 wt%, the first cover layer (120b) may not have a silver color. This may result in a decrease in customer satisfaction. In addition, if the manganese (Mn) content in the first cover layer (120b) exceeds 20 wt%, the corrosion resistance, oxidation resistance, wear resistance, and hardness of the first cover layer (120b) may decrease.

[0270] Additionally, the content of each metal element in the first cover layer (120b) may vary along the thickness direction. For example, the content of copper (Cu) in the first cover layer (120b) may vary along the thickness direction in the first cover layer (120b).

[0271] Preferably, the content of copper (Cu) in the first cover layer (120b) may increase toward the metal layer (120a). For example, the first cover layer (120b) may include a lower surface in contact with the metal layer (120a) and an upper surface opposite to the lower surface. In addition, the content of copper (Cu) in the first cover layer (120b) may decrease from the lower surface toward the upper surface. Alternatively, the content of copper (Cu) in the first cover layer (120b) may increase from the upper surface toward the lower surface. For example, the content of copper (Cu) in a region adjacent to the lower surface of the first cover layer (120b) may be greater than the content of copper (Cu) in a region adjacent to the upper surface of the first cover layer (120b). Through this, the embodiment can further improve the adhesion between the first cover layer (120b) and the metal layer (120a), and thus further improve the electrical reliability and / or mechanical reliability of the smart IC substrate.

[0272] In addition, the tin (Sn) content in the first cover layer (120b) may change as it goes toward the metal layer (120a). For example, the tin (Sn) content in the first cover layer (120b) may increase as it goes from the bottom to the top. That is, the tin (Sn) content in the first cover layer (120b) in an area adjacent to the metal layer (120a) may be lower than the tin (Sn) content in an area adjacent to the top surface of the first cover layer (120b). Therefore, the embodiment can improve the corrosion resistance, oxidation resistance, wear resistance, and hardness of the first cover layer (120b) while making the first cover layer (120b) have a silver color that is the same as or similar to the color of the cover layer of the comparative example.

[0273] In addition, the content of manganese (Mn) in the first cover layer (120b) may change as it goes toward the metal layer (120a). For example, the content of manganese (Mn) in the first cover layer (120b) may increase as it goes from the lower surface to the upper surface. That is, the content of manganese (Mn) in the region adjacent to the metal layer (120a) in the first cover layer (120b) may be lower than the content of manganese (Mn) in the region adjacent to the upper surface of the first cover layer (120b). Therefore, the embodiment can improve the corrosion resistance, oxidation resistance, wear resistance, and hardness of the first cover layer (120b) while making the first cover layer (120b) have a silver color that is the same as or similar to the color of the cover layer of the comparative example.

[0274] Additionally, the alloy comprising copper (Cu), tin (Sn), and manganese (Mn) that constitutes the first cover layer (120b) exhibits excellent wear resistance and, furthermore, exhibits no color change even when scratched. Consequently, even if scratches occur on the first cover layer (120b), they may not be recognized externally. Therefore, the embodiment can further improve product reliability and, furthermore, customer satisfaction.

[0275] The second cover layer (120c) may be positioned at a different location from the location where the first cover layer (120b) is positioned. For example, the second cover layer (120c) may be provided on the bonding surface of the metal layer (120a) that is not covered by the first cover layer (120b). The second cover layer (120c) may be positioned on the lower surface of the metal layer (120a).

[0276] That is, at least a portion of the lower surface of the metal layer (120a) of each of the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) may overlap with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction. Accordingly, the region of the lower surface of the metal layer (120a) that overlaps with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction may not be covered by the first cover layer (120b) and the substrate (110). In addition, the second cover layer (120c) can be placed on the lower surface of the metal layer (120a) that is vertically overlapped with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0277] That is, the second cover layer (120c) can be placed within the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). For example, the second cover layer (120c) can be placed within the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) to cover the lower surface of the metal layer (120a).

[0278] The second cover layer (120c) may include a metal material different from the metal material constituting the first cover layer (120b). The second cover layer (120c) may include a metal material having a hardness different from the hardness of the metal material constituting the first cover layer (120b). For example, the second cover layer (120c) may include a first layer (120c1) and a second layer (120c2).

[0279] The first layer (120c1) and the second layer (120c2) of the second cover layer (120c) are arranged on the lower surface of the metal layer (120a), thereby providing a wire bonding property of a certain level or higher required to the bonding surface of the first conductive pattern portion (120).

[0280] The first layer (120c1) of the second cover layer (120c) may be disposed on the lower surface of the metal layer (120a). The first layer (120c1) of the second cover layer (120c) may be in direct contact with the lower surface of the metal layer (120a). The first layer (120c1) of the second cover layer (120c) may include nickel. The first layer (120c1) of the second cover layer (120c) may mean a seed layer for forming the second layer (120c2). The first layer (120c1) of the second cover layer (120c) may be a barrier layer that prevents the metal material constituting the metal layer (120a) from diffusing into the second layer (120c2). Additionally, the first layer (120c1) of the second cover layer (120c) may be an oxidation prevention layer that prevents oxidation of the metal layer (120a).

[0281] The second layer (120c2) of the second cover layer (120c) may be disposed on the lower surface of the first layer (120c1) of the second cover layer (120c). The second layer (120c2) of the second cover layer (120c) may provide a wire bonding property of a certain level or higher required for the bonding surface of the first conductive pattern portion (120). The second layer (120c2) of the second cover layer (120c) may include at least one of gold (Au) and silver (Ag).

[0282] A dummy pattern portion (DP) may be further provided on the first surface (110S1) of the substrate (110). The dummy pattern portion (DP) may include the same material as the first conductive pattern portion (120), and preferably, may have the same layer structure as the first conductive pattern portion (120). The dummy pattern portion (DP) may be electrically spaced from the first conductive pattern portion (120), thereby improving the rigidity of the smart IC substrate (100). In addition, the dummy pattern portion (DP) may be provided at a corner region of the first surface (110S1) of the substrate (110) to improve process characteristics in the assembly process of the smart IC substrate (100). For example, the dummy pattern portion (DP) may include first to fourth dummy patterns (DP1, DP2, DP3, DP4) respectively provided at a corner region of the first surface (110S1) of the substrate (110).

[0283] Meanwhile, referring to FIG. 20, the smart IC substrate may further include a first adhesive layer (140). The first adhesive layer (140) may be disposed between the first surface (110S1) of the substrate (110) and the first conductive pattern portion (120). For example, the first adhesive layer (140) may be disposed between one surface of the substrate (110) and the lower surface of the metal layer (120a).

[0284] The first adhesive layer (140) may be provided for bonding strength between the first conductive pattern portion (120) and the substrate (110). The first adhesive layer (140) may be referred to as a bonding sheet. The first adhesive layer (140) may be provided for bonding a copper foil layer or a rolled metal layer, which is a metal layer prior to implementing a circuit such as the first conductive pattern portion (120), to the first surface (110S1) of the substrate (110).

[0285] For example, as in the first embodiment, the first conductive pattern portion (120) may be placed directly on one surface of the substrate (110) without the first adhesive layer (140). However, in order to further improve the adhesion between the substrate (110) and the first conductive pattern portion (120), a first adhesive layer (140) may be additionally placed between the substrate (110) and the first conductive pattern portion (120).

[0286] The first adhesive layer (140) comprises a resin material. For example, the first adhesive layer (140) may comprise at least one of an epoxy resin, an acrylic resin, and a polyimide resin. In addition, the first adhesive layer (140) may comprise at least one additive selected from the group consisting of natural rubber, a plasticizer, a curing agent, and a phosphorus-based flame retardant. In this case, the flexibility of the first adhesive layer (140) may be improved.

[0287] The first adhesive layer (140) may have a thickness (T1) within a set range. For example, the thickness (T1) of the first adhesive layer (140) may be 8 μm to 35 μm, 10 μm to 30 μm, or 12 μm to 25 μm. If the thickness (T1) of the first adhesive layer (140) is less than 8 μm, the adhesive strength of the first adhesive layer (140) may decrease, thereby causing the first conductive pattern portion (120) to be separated from the first adhesive layer (140). In addition, if the thickness (T1) of the first adhesive layer (140) exceeds 35 μm, the thickness of the smart IC substrate or the thickness of the smart IC card may increase.

[0288] At this time, a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be provided to penetrate the substrate (110) and the first adhesive layer (140). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate from one surface of the first adhesive layer (140) to the second surface (110S2) of the substrate (110). For example, the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be formed through a process such as punching while the first adhesive layer (140) is disposed on the substrate (110), thereby commonly penetrating the substrate (110) and the first adhesive layer (140).

[0289] The planar area of ​​the first adhesive layer (140) may correspond to the planar area of ​​the substrate (110). For example, the first adhesive layer (140) may entirely cover the first surface (110S1) of the substrate (110). Accordingly, the rigidity of the substrate (110) may be further improved.

[0290] At this time, when the smart IC substrate includes the first adhesive layer (140), the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may be provided to penetrate the first adhesive layer (140) together with the substrate (110). For example, in the case of the second embodiment, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may include a first portion penetrating the substrate (110) and a second portion penetrating the first adhesive layer (140) while being connected to the first portion described above.

[0291] According to the second embodiment, by additionally disposing a first adhesive layer (140) between the substrate (110) and the first conductive pattern portion (120), the adhesion between the substrate (110) and the first conductive pattern portion (120) can be further improved. Accordingly, the physical reliability and / or electrical reliability of the smart IC substrate can be further improved.

[0292] Additionally, a second conductive pattern portion (130) may be arranged on the second surface (110S2) of the substrate (110).

[0293] The second conductive pattern portion (130) may be spaced apart from the first conductive pattern portion (120) in the thickness direction with the substrate (110) interposed therebetween. The second conductive pattern portion (130) may be an antenna pad for antenna function. For example, the second conductive pattern portion (130) may be an antenna pad that electrically connects a chip mounted on a smart IC substrate (100) and an antenna pattern.

[0294] In addition, the thickness (T3) of the second conductive pattern portion (130) may be different from the thickness of the first conductive pattern portion (120). Preferably, the thickness (T3) of the second conductive pattern portion (130) may satisfy a range of 105% to 220% of the thickness of the first conductive pattern portion (120). At this time, the thickness of the first conductive pattern portion (120) may mean the thickness of the metal layer (120a), or may mean the sum of the thicknesses of the metal layer (120a), the first conductive layer (120b), and the second conductive layer (120c) in the vertical direction. In the embodiment, the thickness (T3) of the second conductive pattern portion (130) is made larger than the thickness of the first conductive pattern portion (120), thereby improving the allowable current of the second conductive pattern portion (130), and further improving the antenna characteristics accordingly. In addition, the embodiment can reduce the step between the second conductive pattern portion (130) and the terminal of the chip by making the thickness (T3) of the second conductive pattern portion (130) greater than the thickness of the first conductive pattern portion (120), thereby improving the wire bonding process characteristics. Accordingly, the embodiment can improve the product reliability of the smart IC substrate (100).

[0295] At this time, the second conductive pattern portion (130) may be provided as an alloy. For example, the second conductive pattern portion (130) may be provided as a Cu / Sn / Ag alloy, a Fe / Ni / Ag alloy, or a Cu / Sn / Ag / Al / Ni alloy.

[0296] The second conductive pattern portion (130) can be divided into a plurality of parts. For example, the second conductive pattern portion (130) includes a pad portion (131), an extension portion (132), a partition wall portion (133), and a bonding portion (134).

[0297] The pad portion (131) of the second conductive pattern portion (130) may be a portion electrically connected to an antenna pattern to be described later. For example, the pad portion (131) of the second conductive pattern portion (130) may be a terminal region connected to the antenna pattern. The pad portion (131) of the second conductive pattern portion (130) may have a constant width. For example, the pad portion (131) of the second conductive pattern portion (130) may have a constant width so as to enable stable electrical connection with the antenna pattern while enabling stable signal transmission.

[0298] The second conductive pattern portion (130) may include an extension portion (132) extending from the pad portion (131). The extension portion (132) may extend from the pad portion (131) along the perimeter of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0299] For example, the extension portion (132) of the second conductive pattern portion (130) may be provided at a position spaced apart from the area in the outer direction from the area in which the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are provided, extending along the circumferential direction of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0300] That is, the extension portion (132) of the second conductive pattern portion (130) may be connected to the pad portion (131) and may be provided to surround the outer side of the area where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged.

[0301] For example, the extension portion (132) of the second conductive pattern portion (130) may extend along the circumferential direction of the other surface (110S2) of the substrate (110) between the circumference of the other surface (110S2) of the substrate (110) and the area where the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged.

[0302] At this time, the extension portion (132) of the second conductive pattern portion (130) may be arranged in a square shape around the area where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged, as shown in FIG. 2. However, the embodiment is not limited thereto, and the extension portion (132) of the second conductive pattern portion (130) may be provided in a circular shape or a polygonal shape along the shape of the area where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged.

[0303] In addition, the area where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged may mean an area that connects the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) that are arranged adjacent to each other, and the extension portion (132) may extend along the circumferential direction of the area where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged at a position spaced apart from the area where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged.

[0304] At this time, the area where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged may refer to a molding area where the molding member is to be arranged. For example, the inner area of ​​the extension portion (132) surrounded by the extension portion (132) of the second conductive pattern portion (130) may refer to a molding area where the molding member is to be arranged.

[0305] The extension portion (132) of the second conductive pattern portion (130) can prevent the molding member from flowing out to an area other than the designated area described above during the molding process of the chip that is performed later. For example, the extension portion (132) of the second conductive pattern portion (130) can function as a dam to prevent the molding member of the chip from flowing out of the designated area while ensuring that the molding member is placed only in the designated area. Through this, the embodiment can ensure that the chip and the connecting member (to be described later) connecting the chip and the pads are stably molded through the molding member, thereby improving the operating characteristics of the chip. Therefore, the embodiment can prevent external moisture or foreign substances from penetrating into the molding area of ​​the chip, thereby further improving the operating reliability.

[0306] Furthermore, the embodiment can improve the processability in the process of forming a molding member by using the extension portion (132) of the second conductive pattern portion (130), and thus improve the product yield.

[0307] In addition, the embodiment can use the extension portion (132) of the second conductive pattern portion (130) to make the molding member formed in the inner region of the extension portion (132) have a constant thickness, thereby further improving product reliability.

[0308] The extension portion (132) of the second conductive pattern portion (130) may have a certain width (W2). The width (W2) of the extension portion (132) of the second conductive pattern portion (130) may be smaller than the width (W3) of the bonding portion (134) and the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0309] For example, the width (W2) of the extension portion (132) of the second conductive pattern portion (130) may be 100 μm to 200 μm. Preferably, the width (W2) of the extension portion (132) of the second conductive pattern portion (130) may be 120 μm to 180 μm. More preferably, the width (W2) of the extension portion (132) of the second conductive pattern portion (130) may be 125 μm to 175 μm.

[0310] If the width (W2) of the extension portion (132) of the second conductive pattern portion (130) is less than 100 μm, the adhesion between the second conductive pattern portion (130) and the substrate (110) may be reduced. In addition, if the width (W2) of the extension portion (132) of the second conductive pattern portion (130) is less than 100 μm, it may be difficult for the extension portion (132) to function as a dam that controls the flow of the molding member. In addition, if the width (W2) of the extension portion (132) of the second conductive pattern portion (130) exceeds 200 μm, the process time or process cost in the process of forming the second conductive pattern portion (130) may increase.

[0311] Additionally, the second conductive pattern portion (130) may further include a partition wall portion (133) extending from the extension portion (132) toward the area where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged. The partition wall portion (133) may extend from the extension portion (132) toward the area between the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0312] For example, a plurality of bulkheads (133) may be provided. The partition wall portion (133) may include a first partition wall portion extending to an area between the first through hole (TH1) and the second through hole (TH2), a second partition wall portion extending to an area between the second through hole (TH2) and the third through hole (TH3), a third partition wall portion extending to an area between the third through hole (TH3) and the fourth through hole (TH4), a fourth partition wall portion extending to an area between the fourth through hole (TH4) and the fifth through hole (TH5), a fifth partition wall portion extending to an area between the fifth through hole (TH5) and the sixth through hole (TH6), a sixth partition wall portion extending to an area between the sixth through hole (TH6) and the seventh through hole (TH7), a seventh partition wall portion extending to an area between the seventh through hole (TH7) and the eighth through hole (TH8), and an eighth partition wall portion extending to an area between the first through hole (TH1) and the eighth through hole (TH8).

[0313] The partition wall portion (133) can further improve the processability in the process of forming the molding member, and further improve the processability in the process of wire bonding the chip and the second conductive pattern portion (130).

[0314] For example, the partition wall portion (133) can partition the area between the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). Through this, the embodiment can stably protect the wires connected to the inside of each of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) by using the partition wall portion (133). For example, the partition wall portion (133) can partition each of the areas where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged, thereby enabling stable molding to be performed in each of the partitioned areas.

[0315] Additionally, the second conductive pattern portion (130) may further include a bonding portion (134) arranged at the end of the partition wall portion (133). The bonding portion (134) may have a constant diameter. The bonding portion (134) may function as a bonding pad for electrically connecting the terminal of the chip and the second conductive pattern portion (130).

[0316] At this time, the embodiment can provide a bonding portion (134) in an area adjacent to the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) by using the partition wall portion (133), thereby improving the processability in the process of wire-bonding the chip and the second conductive pattern portion (130), and thereby enabling the molding of the wire connected to the bonding portion (134) by using the extension portion (132) to be performed more stably. Therefore, the embodiment can further improve product reliability, and further enable the smart IC substrate to operate more stably.

[0317] The bonding portion (134) may have a certain width (W3). At this time, the width (W3) of the bonding portion (134) may be greater than the width (W2) of the extension portion (132) and the partition wall portion (133). In addition, the width (W3) of the bonding portion (134) may be smaller than the width (W1) of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0318] For example, the width (W3) of the bonding portion (134) may be 300 μm to 650 μm. Preferably, the width (W3) of the bonding portion (134) may be 320 μm to 630 μm. More preferably, the width (W3) of the bonding portion (134) may be 350 μm to 600 μm.

[0319] If the width (W3) of the bonding portion (134) is less than 300 ㎛, the processability may be degraded in the bonding process of the wire for electrical connection with the terminal of the chip. In addition, if the width (W3) of the bonding portion (134) exceeds 650 ㎛, it may be difficult to secure an area where the bonding portion (134) is to be placed in the area between the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), and thus reliability problems such as electrical short circuits may occur.

[0320] Here, in the embodiment, the partition wall portion (133) is provided in multiple numbers, and accordingly, the bonding portion (134) may be provided on each of the multiple partition walls (133). In addition, the embodiment may perform a wire bonding process for electrical connection with the terminals of the chip using at least two of the bonding portions among the multiple bonding portions (134). That is, the embodiment may selectively use at least two of the bonding portions among the multiple bonding portions as wire bonding pads depending on the design of the terminals provided on the chip. Through this, the embodiment may perform the wire bonding process without being significantly restricted by the design of the chip.

[0321] At this time, the second conductive pattern portion (130) may be provided in multiple pieces that are electrically separated from each other. For example, the second conductive pattern portion (130) may include a first portion (130-1) and a second portion (130-2).

[0322] In addition, the first part (130-1) and the second part (130-2) of the second conductive pattern portion (130) may be a plurality of antenna patterns spaced apart from each other. For example, the first part (130-1) of the second conductive pattern portion (130) may be an antenna pattern to which positive polarity power is applied, and the second part (130-2) of the second conductive pattern portion (130) may be a pad to which negative polarity power is applied.

[0323] In addition, each of the first part (130-1) and the second part (130-2) of the second conductive pattern part (130) may include the pad part (131), the extension part (132), the partition wall part (133), and the bonding part (134) described above.

[0324] For example, the first portion (130-1) of the second conductive pattern portion (130) may include a pad portion (131-1), an extension portion (132-1), a partition wall portion (133-1), and a bonding portion (134-1). In addition, the second portion (130-2) of the second conductive pattern portion (130) may include a pad portion (131-2), an extension portion (132-2), a partition wall portion (133-2), and a bonding portion (134-2).

[0325] For example, the extension (132-1) of the first portion (130-1) of the second conductive pattern portion (120) may be arranged to surround a portion of the perimeter of the area where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged. In addition, the extension (132-2) of the second portion (130-2) of the second conductive pattern portion (120) may be arranged to surround a portion of the remaining perimeter of the area where the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged.

[0326] In addition, the partition wall portion (133-1) of the first part (130-1) of the second conductive pattern portion (120) may protrude into an area between some of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). The partition wall portion (133-2) of the second part (130-2) of the second conductive pattern portion (120) may protrude into an area between some of the remaining through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0327] At this time, the first part (130-1) and the second part (130-2) of the second conductive pattern part (130) may be spaced apart from each other. For example, one end of the extension part (132-1) of the first part (130-1) of the second conductive pattern part (130) and one end of the extension part (132-2) of the second part (130-2) may be spaced apart from each other by a certain distance (D1). In addition, the other end of the extension part (132-1) of the first part (130-1) of the second conductive pattern part (130) and the other end of the extension part (132-2) of the second part (130-2) may be spaced apart from each other by a certain distance (D1).

[0328] Here, the above-described distance (D1) may have a range of 50 μm to 200 μm. Preferably, the above-described distance (D1) may have a range of 55 μm to 190 μm. More preferably, the above-described distance (D1) may have a range of 60 μm to 180 μm.

[0329] If the above-described distance (D1) is less than 50 μm, a reliability problem may occur in which the first portion (130-1) and the second portion (130-2) are electrically connected to each other depending on the process capability in the process of forming the second conductive pattern portion (130). In addition, if the above-described distance (D1) exceeds 200 μm, a problem may occur in which the molding member leaks into the gap between the first portion (130-1) and the second portion (130-2).

[0330] Referring to FIG. 21, the smart IC substrate includes a metal layer (120a) disposed on a first surface (110S1) of a substrate (110). At this time, the metal layer (120a) may include a binary alloy or a ternary alloy, unlike the metal layers of the first to third embodiments. For example, the metal layer (120a) may include an alloy including nickel (Ni), iron (Fe), and chromium (Cr). For example, the metal layer (120a) may include a Monel series alloy or an Inconel series alloy. In detail, the metal layer (120a) may be a nickel (Ni)-chromium (Cr)-iron (Fe) alloy that includes nickel as a main component and chromium and iron. In the alloy, the main component is defined as a metal having the largest weight percent among a plurality of metals constituting the alloy.

[0331] Alternatively, the metal layer (120a) may include a sus series alloy. Specifically, the metal layer (120a) may be an iron (Fe)-chromium (Cr)-nickel (Ni) alloy containing iron as a main component and chromium and nickel.

[0332] When the metal layer (120a) is formed of a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy as described above, a portion of the cover layer disposed on the metal layer (120a) may be omitted. For example, the metal layer (120a) including a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy may have a certain level or higher of corrosion resistance, wear resistance, oxidation resistance, and hardness. Therefore, when the metal layer (120a) includes a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy, the first cover layer (120b) described in the previous embodiment may be omitted.

[0333] However, when the metal layer (120a) includes a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy and the first cover layer (120b) is omitted, the contact surface of the first conductive pattern portion (120) may not have a silver color. In this case, design satisfaction may be reduced, and thus user satisfaction may be reduced.

[0334] Accordingly, the embodiment can provide the first cover layer (120b) even if the metal layer (120a) includes a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy. This can improve design satisfaction and further enhance user comfort.

[0335] At this time, if the metal layer (120a) includes a nickel (Ni)-chromium (Cr)-iron (Fe) alloy or an iron (Fe)-chromium (Cr)-nickel (Ni) alloy, the metal layer (120a) may be provided by a rolling process. In this case, the surface roughness of the metal layer (120a) may be reduced, thereby lowering the adhesion with the substrate (110).

[0336] Accordingly, a buffer layer (160) may be disposed between the first surface (110S1) of the substrate (110) and the metal layer (120a). The buffer layer (160) may include a first buffer layer (161) and a second buffer layer (162). The first buffer layer (161) may be disposed on the first surface (110S1) of the substrate (110). The second buffer layer (162) may be disposed on the first buffer layer (161). That is, the second buffer layer (162) is disposed between the first buffer layer (161) and the metal layer (120a).

[0337] The first buffer layer (161) may include a metal. For example, the first buffer layer (161) may include copper (Cu). The adhesion between the metal layer (120a) and the substrate (110) is improved by the first buffer layer (161).

[0338] Additionally, the second buffer layer (162) may include a metal. For example, the second buffer layer (162) may include nickel. The adhesion between the metal layer (120a) and the first buffer layer (161) may be improved by the second buffer layer (162).

[0339] The first buffer layer (161) may be divided into a plurality of regions along the thickness direction. For example, the first buffer layer (161) may be divided into an upper region adjacent to the second buffer layer (162), and a lower region adjacent to the first surface (110S1) of the substrate (110).

[0340] The upper region of the first buffer layer (161) may include a metal. That is, the upper region of the first buffer layer (161) is a metal layer. For example, the upper region of the first buffer layer (161) may include copper. The lower region of the first buffer layer (161) may include a metal oxide. That is, the lower region of the first buffer layer (161) is a metal oxide layer. For example, the lower region of the first buffer layer (161) may include copper oxide.

[0341] The lower region of the first buffer layer (161) may be formed by oxidizing a portion of the first buffer layer (161). The surface roughness of the lower region of the first buffer layer (161) may be increased by the oxidation process. That is, the surface roughness of the lower region of the first buffer layer (161) facing the first surface (110S1) of the substrate (110) may be greater than the surface roughness of the upper region of the first buffer layer (161). In detail, the surface roughness of the lower region of the first buffer layer (161) may be greater than the surface roughness of the metal layer (120a). In addition, the surface roughness of the lower region of the first buffer layer (161) may be greater than the surface roughness of the first buffer layer.

[0342] The thickness of the lower region of the first buffer layer (161) may be smaller than the thickness of the upper region of the first buffer layer (161). For example, the thickness of the lower region of the first buffer layer (161) may be 20% or less, 10% or less, or 5% or less of the total thickness of the first buffer layer (161). In addition, the adhesion between the first buffer layer (161) and the first surface (110S1) of the substrate (110) may be further improved by utilizing the lower region of the first buffer layer (161c).

[0343] At this time, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) of the smart IC substrate of the third embodiment may further penetrate the buffer layer (160). For example, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may include a first portion penetrating the substrate (110) and a second portion penetrating the buffer layer (160). According to an embodiment, a first adhesive layer may further be disposed between the buffer layer (160) and the substrate (110), and in this case, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate the first adhesive layer.

[0344] In addition, the second cover layer (120c) of the smart IC substrate according to the third embodiment may be disposed within the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8). At this time, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate the buffer layer (160) and have a second portion, and the second cover layer (120c) may be disposed within the second portion of the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0345] At this time, the first cover layer (120b) in one embodiment may be disposed only on the upper surface of the metal layer (120a). Alternatively, the first cover layer (120b) in another embodiment may extend from the upper surface of the metal layer (120a) to cover at least a portion of the side surface of the metal layer (120a) and at least a portion of the side surface of the buffer layer (160).

[0346] Referring to FIG. 22, the smart IC substrate may be different from the smart IC substrate of the previous embodiment in that the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are not provided in the buffer layer (160).

[0347] The lower surface of the buffer layer (160) may overlap with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction. For example, the buffer layer (160) in the region that overlaps with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction may not be removed. In this case, a part of the lower surface of the buffer layer (160) may be exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), and the second cover layer (120c) may be disposed on the lower surface of the buffer layer (160) exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0348] Referring to FIG. 23, the smart IC substrate may be different from the smart IC substrate of the previous embodiment in that through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are provided in a portion of the buffer layer (160).

[0349] The lower surface of the buffer layer (160) may overlap with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction. For example, a part of the buffer layer (160) in the region that overlaps with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the vertical direction may be removed.

[0350] That is, the buffer layer (160) may include a first buffer layer (161) and a second buffer layer (162). In addition, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate the first buffer layer (161) but not penetrate the second buffer layer (162). In this case, a part of the lower surface of the second buffer layer (162) may be exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8), and the second cover layer (120c) may be disposed on the lower surface of the second buffer layer (162) exposed through the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0351] Referring to FIG. 24, the smart IC substrate can penetrate at least a portion of the metal layer (120a) while the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) penetrate the buffer layer (160) compared to the smart IC substrate of the previous embodiment.

[0352] For example, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) can penetrate the first buffer layer (161) and the second buffer layer (162) together with the substrate (110).

[0353] Additionally, the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) may penetrate a portion of the metal layer (120a). For example, the metal layer (120a) may include a recess (not shown) provided in an area that overlaps the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) along the vertical direction.

[0354] And, the second cover layer (120c) can be placed in the recess of the metal layer (120a) that is vertically overlapped with the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0355]

[0356] Meanwhile, referring to FIG. 25, the smart IC substrate (100A) may differ from the structure of the previous embodiment in terms of the arrangement structure of the second conductive pattern portion (130).

[0357] For example, the extension portions (132-1, 132-2) of the first portion (130-1) and the second portion (130-2) of the second conductive pattern portion (130) each have a circular shape and may be provided to surround the periphery of an area in which a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) are arranged.

[0358] At this time, the structure has only one partition wall between two adjacent through holes among the plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) in the previous embodiment.

[0359] In contrast, referring to FIG. 25, two partition walls may be provided between two adjacent through holes. For example, the first part (130-1) of the second conductive pattern part (130) may include a partition wall part (133-1) provided between the first through hole (TH1) and the eighth through hole (TH8), and the second part (130-2) of the second conductive pattern part (130) may include a partition wall part (133-2) provided between the first through hole (TH1) and the eighth through hole (TH8).

[0360] Through this, the embodiment allows the first part (130-1) and the second part (130-2) of the second conductive pattern part (130) to be wire-bonded to the terminal of the chip in adjacent areas, thereby further improving wire bondability.

[0361] Meanwhile, referring to FIG. 26, the smart IC substrate (100B) may differ from the structure of the previous embodiment in terms of the arrangement structure of the second conductive pattern portion (130).

[0362] For example, the second conductive pattern portion (130) may include a first portion (130-1) and a second portion (130-2). In addition, the pad portions (131-1, 131-2) of each of the first portion (130-1) and the second portion (130-2) may include a plurality of coupling holes (131TH).

[0363] Specifically, the pad portions (131-1, 131-2) of the first portion (130-1) and the second portion (130-2) may include a plurality of coupling holes (131TH) penetrating the upper and lower surfaces of each pad portion (131-1, 131-2).

[0364] The plurality of bonding holes (131TH) can allow a bonding member (e.g., solder) to be stably placed in the process of bonding the pad portion (131) of the second conductive pattern portion (130) and the antenna pattern.

[0365] For example, the bonding hole (131TH) may be an area for forming a hot melting agent during solder bonding or bonding using ACF, thereby preventing the hot melting agent and the bonding agent from adhering to each other and interfering with each other. Accordingly, the bonding hole (131TH) may be concentratedly arranged at the edge of the pad portion (131) to prevent the bonding agent from being lifted from the outside.

[0366] That is, the pad portion (131) of the second conductive pattern portion (130) described above includes a central region and an outer region, and the opening ratio in the outer region by the plurality of coupling holes (131TH) may be greater than the opening ratio in the central region by the plurality of coupling holes (131TH). Through this, the embodiment may enable more stable coupling.

[0367]

[0368] Fig. 27 is a plan view illustrating a smart IC module according to an embodiment, and Fig. 28 is a cross-sectional view illustrating a smart IC module according to an embodiment. Preferably, Fig. 27 may be a plan view illustrating the other side of the smart IC module in a state where the molding member (1300) is not arranged.

[0369] Referring to FIGS. 27 and 28, the smart IC module (1000) may include the smart IC substrate described in the previous embodiment. For example, the smart IC module (1000) may include any one of the smart IC substrates illustrated in FIGS. 1 to 26.

[0370] A smart IC module (1000) may include a chip (1100) placed in a chip mounting area. Here, the chip mounting area may be an inner area of ​​an area surrounded by a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) on a second surface (110S2) of a substrate (110).

[0371] At this time, an adhesive member (not shown) may be placed in the inner region described above, and the chip (1100) may be attached on the adhesive member described above.

[0372] The chip (1100) may include a plurality of terminals (not shown). For example, the chip (1100) may include first to eighth terminals.

[0373] In addition, it may include a connecting member (1200) that connects the terminals of the chip (1100) and the pads of the smart IC substrate (100). The connecting member (1200) may be a wire, but is not limited thereto. The connecting member (1200) may include first to eighth connecting members. For example, the connecting member (1200) may include first to eighth connecting members that connect the first to eighth pads (121, 122, 123, 124, 125, 126, 127, 128) exposed through a plurality of through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8) to the first to eighth terminals of the chip (1100), respectively.

[0374] Additionally, the connecting member (1200) may further include ninth and tenth connecting members that connect the first part (130-1) and the second part (130-2) of the second conductive pattern part (120) and the terminal of the chip (1100) to each other.

[0375] At this time, the smart IC module (1000) may further include a molding member (1200). The molding member (1200) may mold the chip (1100). In addition, the molding member (1200) may mold the connection member (1200). Accordingly, the molding member (1200) may be provided to cover the chip (1100) and the connection member (1200) while filling the through holes (TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8).

[0376]

[0377] Fig. 29 is a perspective view showing a smart IC card according to an embodiment, and Fig. 30 is a cross-sectional view schematically showing the smart IC card of Fig. 29.

[0378] Referring to FIGS. 29 and 30, a smart IC card (3000) according to an embodiment may include a main body (3100), a first protective layer (3210), and a second protective layer (3220).

[0379] The main body (3100) includes a receiving portion (3110). At this time, any one smart IC module (2000) according to FIGS. 1 to 26 can be manufactured, and the manufactured smart IC module (2000) can be placed inside the receiving portion (3110).

[0380] The receiving portion (3110) may have a step. For example, the inner wall of the receiving portion (3110) may have a step. Preferably, the receiving portion (3110) may have a width in an area corresponding to the upper portion of the smart IC card (3000) greater than a width in an area corresponding to the lower portion of the smart IC card (3000). Accordingly, the receiving portion (3110) may include a first portion having a first width and a second portion having a second width greater than the first width. In addition, the second portion of the receiving portion (3110) may receive a chip (1100) and a molding member (1200) provided in the smart IC module, and the remaining components of the smart IC module excluding at least a portion of the chip (1100) and the molding member (1200) may be received in the first portion of the receiving portion (3110). Accordingly, the embodiment can further dramatically reduce the thickness of the smart IC card and enable the chip (1100) to be inserted more stably into the smart IC card.

[0381] At this time, an antenna pattern (not shown) may be arranged on the main body (3100). Specifically, the antenna pattern may be arranged in a coil shape on the edge of the main body (3100). The second portion (132, 137) of the antenna pads provided in the smart IC module (2000) may be connected to the antenna pattern (AP) arranged on the main body (3100) described above. An IC card including a smart IC module according to this operates as a contactless card, a combination card, or a hybrid card.

[0382] The smart IC module (2000) is inserted into the receiving portion (3110). The smart IC module (2000) and the main body (3100) are bonded by an adhesive layer (3120). As a result, the smart IC module (2000) is inserted into and fixed in the receiving portion (3110).

[0383] The first protective layer (3210) is disposed on the upper portion of the main body (3100). The first protective layer (3210) may include a transparent material. The first protective layer (3210) may include a transparent resin material. The first protective layer (3210) may be disposed as at least one layer. That is, the first protective layer (3210) may include multiple layers.

[0384] The second protective layer (3220) is disposed at the lower portion of the main body (3100). A magnetic stripe may be disposed on the second protective layer (3220). The second protective layer (3220) may include a transparent material. The second protective layer (3220) may include a transparent resin material. The second protective layer (3220) may be disposed as at least one layer. That is, the second protective layer (3220) may include a plurality of layers.

[0385]

[0386] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the present invention.

[0387] In addition, although the above description focuses on embodiments, these are merely examples and do not limit the present invention. Those skilled in the art to which the present invention pertains will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the present invention defined in the appended claims.

Claims

1. A substrate including one side and a side opposite to said one side; and Including a conductive pattern portion arranged on the above surface of the above-mentioned device; The above substrate comprises a plurality of holes penetrating at least a portion of the substrate along the thickness direction of the substrate, A smart IC substrate, wherein the plurality of holes include a plurality of bonding holes and dummy holes spaced apart from the plurality of bonding holes.

2. In paragraph 1, The above-mentioned surface of the above-mentioned description defines a chip attachment area where the chip is attached, The above plurality of bonding holes are arranged spaced apart from each other along the circumferential direction of the chip attachment area in the peripheral area of ​​the chip attachment area, A smart IC substrate, wherein the above dummy hole is arranged on the inner side of the above peripheral area.

3. In paragraph 2, A smart IC substrate, wherein a horizontal distance from the dummy hole to the central axis of the chip attachment area in the horizontal direction is smaller than a horizontal distance from each of the plurality of bonding holes to the central axis.

4. In paragraph 1, The above conductive pattern portion, A metal layer disposed on the above surface of the above-mentioned substrate; An upper cover layer disposed on the above metal layer; A first lower cover layer disposed under the metal layer exposed through the bonding hole, and A smart IC substrate comprising a second lower cover layer disposed under the metal layer exposed through the dummy hole.

5. In paragraph 1, The above plurality of bonding holes penetrate the entire substrate along the thickness direction, A smart IC substrate, wherein the dummy hole partially penetrates the substrate along the thickness direction.

6. In paragraph 1, At least one of the planar shape of the dummy hole, the width of the dummy hole in the first horizontal direction, and the width of the dummy hole in the second horizontal direction perpendicular to the first horizontal direction, A smart IC substrate, wherein at least one of the planar shape of the bonding hole, the width of the bonding hole in the first horizontal direction, and the width of the bonding hole in the second horizontal direction is different.

7. In paragraph 2, The conductive pattern portion includes a plurality of pads spaced apart from each other on the one surface of the substrate, A smart IC substrate, wherein each of the plurality of bonding holes overlaps each of the plurality of pads along the thickness direction.

8. In paragraph 7, The plurality of pads include a first pad overlapping the chip attachment area along the thickness direction, A smart IC substrate, wherein the first pad includes an outer portion overlapping one of the plurality of bonding holes along the thickness direction, and an inner portion overlapping the dummy hole along the thickness direction.

9. In paragraph 7, The conductive pattern portion further includes a dummy pattern overlapping the chip attachment area along the thickness direction, A smart IC substrate, wherein the dummy pattern overlaps the dummy hole along the thickness direction and does not overlap the bonding hole along the thickness direction.

10. In paragraph 7, At least one of the plurality of pads includes a dummy pad, A smart IC substrate, wherein the dummy pad and the bonding hole overlapping the dummy pad along the thickness direction are auxiliary dummy holes.

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