Method for testing circuit designs

Abstract

A method for testing a first circuit design on an FPGA system, the first circuit design being compartmentalized into a plurality of interacting sub-designs. The method comprises a step in which a first sub-design of the first circuit design is mapped onto a first FPGA unit. Furthermore, a second sub-design of the first circuit design is mapped onto a second FPGA unit. In another step, a status variable for the first and second sub-design of the first circuit design are generated. The status variables are configured to indicate a readiness status of the corresponding sub-design for testing. In yet another step of the disclosed method, the status-variables of the first and second sub-design of the first circuit design are connected to a first superordinate FPGA unit each through a separate data channel.

Description

DescriptionMETHOD FOR TESTING CIRCUIT DESIGNSTECHNICAL FIELD

[0001] The present disclosure relates to a method for testing a first circuit design on an Field Programmable Gate Array (FPGA) system and to a computer program product that is configured to perform such a method. The present disclosure also relates to an FPGA system that is configured for testing a first circuit design.BACKGROUND

[0002] US 11,113,441 Bl discloses a reconfigurable hardware modeling device that comprises a plurality of reconfigurable hardware modeling circuits. The reconfigurable hardware modeling device also comprises a network subsystem with network circuitry that is configured to perform a signal broadcast operation and a signal reduction operation.

[0003] FPGA systems are used to emulate the functioning of electronic systems described by circuit designs of all degrees of complexity. An increasing complexity of a circuit design typically comes with an increasing demand for computing power in order to perform the desired emulation, e.g. for testing the circuit design. There is a need for a method that allows for testing complex circuit designs in a quick and reliable manner. It is an object of the present disclosure to provide a method for testing a circuit design that offers an improvement in at least one of the aspects outlined above.SUMMARY

[0004] The object described above is achieved by a method for testing a first circuit design on an FPGA system. The first circuit design may be compartmentalized into a plurality of sub-designs. The sub-designs are configured to interact with each other when the first circuit design is being tested. The disclosed method comprises a step in which a first sub-design of the first circuit design is mapped onto a first FPGA unit. Correspondingly, a second sub-design of the first circuit design is mapped onto a second FPGA unit. The disclosed method also comprises that a status variable for each the first sub-design and the second sub-design of the first circuit design are generated. The status variables are configured to indicate a readiness status of the corresponding sub-design for testing. Thedisclosed method also comprises a step in which the status variables of the first and second sub-design of the first circuit design are connected to a first superordinate FPGA unit. Each of the first and second sub-design are connected to the first superordinate FPGA unit through a separate data channel. Still further, the disclosed method comprises another step in which the content of each status variable pertaining to the sub-designs of the first circuit designs is transmitted to the first superordinate FPGA unit. The testing of the first circuit design is initiated when all status variables pertaining to the sub-designs of the first circuit design indicate a positive readiness of the corresponding sub-designs.

[0005] The object described above is also achieved by an FPGA system according to the present disclosure. The FPGA system comprises a plurality of FPGA units. At least one of the FPGA units is optimized to perform scalar reduce / broadcast operations. Furthermore, the FPGA system is configured to perform the following.

[0006] The disclosed FPGA system is configured to load a first circuit design that is to be tested. The loaded first circuit design is compartmentalized into at least a first and a second sub-design. The disclosed FPGA system is also configured to generate a status variable for the first and second sub-design of the first circuit design. The status variables are configured to indicate a readiness status of the corresponding sub-design for testing. Furthermore, the disclosed FPGA system is configured to connect the status variables of the first and second sub-design of the first circuit design to a first superordinate FPGA unit. Each of the status variables is connected to the first superordinate FPGA unit through a separate data channel. Still further, the disclosed FPGA system is configured to transmit the content of each status variable pertaining to the sub-designs of the first circuit design to the first superordinate FPGA unit. The disclosed FPGA system is also configured to initiate the testing of the first circuit design when all status variables pertaining to the sub-designs of the first circuit design indicate a positive readiness of the corresponding sub-designs. The at least one FPGA unit optimized to perform scalar reduce / broadcast operations is utilized as the first superordinate FPGA unit.BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following, the present disclosure is described in more detail in several figures. The figures are to be construed as mutually complementary. Particularly, identical numerals are to be construed as having the same technical meaning. The features of theembodiments shown in the figures may be combined with each other. Additionally, the features of the embodiments shown in the figures may also be combined with the embodiments outlined above and below. In particular, the figures show:

[0008] FIG. 1 illustrates a schematic overview of a first embodiment of the disclosed FPGA system on which a first embodiment of the disclosed method may be performed;

[0009] FIG. 2 a schematic overview of a second embodiment of the disclosed FPGA system on which a second embodiment of the disclosed method may be performed;

[0010] FIG. 3 a schematic overview of a third embodiment of the disclosed FPGA system on which a third embodiment of the disclosed method may be performed;

[0011] FIG. 4 a schematic overview of a fourth embodiment of the disclosed FPGA system on which a fourth embodiment of the disclosed method may be performed;

[0012] FIG. 5 a schematic overview of the first embodiment of the disclosed method.DETAILED DESCRIPTION

[0013] The disclosed method is configured for testing a first circuit design on an FPGA system. The first circuit design may be a design of a chip or any other complex extensive circuit. The testing comprises an emulation of the functioning of the first circuit design.The first circuit design is compartmentalized into a plurality of interacting sub-designs. For testing the first circuit design, the sub-designs may be emulated and their interaction is implemented on the FPGA system, thus emulating the functioning of the first circuit design. The first circuit design may be compartmentalized into sub-designs by a compiler which receives corresponding data.

[0014] The disclosed method comprises a ?? a first sub-design of the first circuit design is mapped onto a first FPGA unit. Furthermore, a second sub-design of the first circuit design is mapped onto a second FPGA unit. Thus, the first circuit design is configured to emulate the functioning of the first sub-design of the first circuit design and the second FPGA unit is configured to emulate the functioning of the second sub-design of the first circuit design. The mapping of the first and second sub-designs may be performed by the compiler. In another step of the disclosed method, a status variable is generated for each of the first and second sub-design of the first circuit design. The status variables are each configured to indicate a readiness status of the corresponding sub-designs. The status variablesmay be a logical component of the first and second sub-design respectively. The readiness status expressed by each of the status variables indicates if the associated sub-design is ready to process an emulated stimulation transmitted to the corresponding sub-design. The emulated stimulations may be part of the testing program that is to be performed on the first circuit design. Furthermore, the emulated stimulations may at least partially be outputs from other sub-designs which interact with the first or second sub-design respectively.

[0015] In a further step of the disclosed method, the status variables of the first and second sub-design of the first circuit design are each connected to a first superordinate FPGA unit through a separate data channel. The separate data channels may each be configured to transmit the content of the corresponding status variable to the first superordinate FPGA unit. The separate data channels may also each be configured to transmit an instruction from the first superordinate FPGA unit to the corresponding status variable, requesting it to transmit its content to the first superordinate FPGA unit.

[0016] Additionally, the disclosed method comprises a step in which the content of each status variable pertaining to the sub-designs of the first circuit design are transmitted to the first superordinate FPGA unit. Contents of the status variables are received and processed by the first superordinate FPGA unit to determine an aggregated readiness of a plurality of sub-designs, for example all sub-designs of the first circuit design. When all status variables pertaining to the sub-designs of the first circuit design indicate a positive readiness a positive aggregated readiness of the first circuit design is determined and the testing of the first circuit design is initiated. The testing may be initiated by the first superordinate FPGA unit which may transmit a corresponding instruction to the sub-systems of the first circuit design.

[0017] The data channels utilized in the disclosed method only require a reduced data width since the readiness of a sub-design may be expressed with a reduced amount of information. Furthermore, the disclosed method allows for avoiding situations in which the testing of the first circuit design has already begun with a subsystem that is not ready. The disclosed method allows for quickly verifying the readiness of multiple sub-designs. This results in a more reliable and cost-efficient testing of complex circuit designs.

[0018] In an embodiment of the disclosed method, at least one of the data channels hasa data width of one bit. Consequently, the data channel is configured to only carry one bit at a time. Thus, at least one of the data channels has the smallest possible data width. Correspondingly, to status variable may also only contain one bit. Such status variables may be automatically detected by the compiler when it processes and compartmentalizes the first circuit design. The compiler may be configured to automatically generate the corresponding data channels which may be operated independently of the associated sub-design of the first circuit design. As a result, the data channels may form a fast network that is separate from the current operation of the associated sub-designs. When the readiness status of the sub-designs of the first circuit design is probed, the pertinent data from the status variables may be quickly transmitted to the first superordinate FPGA unit. Therefore, the readiness of the first circuit design for testing may be established rapidly. A negative readiness of one of the sub-designs may also be detected reliably based on such data channels.

[0019] In another embodiment of the disclosed method, the contents of the status variables of the first and second sub-design are being acquired independently of each other. The status variable and the data channels may be embodied to form a logical structure in which no status variable needs to wait for another status variable to be processed. That allows for accelerating a check if all sub-designs are ready for testing. Additionally, the content of at least one of the status variables may be acquired continuously. The content of at least one of the status variables may be sent to the first superordinate FPGA unit.

[0020] Furthermore, at least one of the data channels may be configured to operate independently of the testing of the sub-design associated with the data channel. As a consequence, the data channel is still operational when the corresponding sub-design comes to a halt during the testing or before the testing. . When the design is halted due to at least one sub-design reflecting that it is not ready via its status variable, it necessary for the communication channel to continue to operate to be able to transmit positive readiness once that occurs and thereby enable the design to proceed with testing.

[0021] Still further, the first superordinate FPGA unit may be optimized to perform scalar reduce / broadcast operations. Reduce / broadcast operations, also referred to as R / B operations, are configured to combine many one -bit variables into a single one -bit variable and to return a combined value to all participating FPGA units, the combined value reflecting the aggregated readiness of the first circuit design. The superordinate FPGA maycontain a dedicated datapath for the reduction computation and a multiplicity of data channels allowing to receive the one -bit variables, i.e. the status variables, and to return the combined value.

[0022] In the disclosed method, at least one of the status variables may be configured to reflect an aggregated readiness status of portions of the corresponding sub-design. Portions of the sub-design may each comprise a status variable that is configured to indicate the readiness status of the corresponding portion of the sub-design. The contents of the status variables of each portion of the sub-design may be aggregated, the result of that aggregation reflecting the readiness status of the respective sub-design. Such an aggregated value may then be treated as the value for the full sub-design and sent to the first superordinate FPGA for further combination with variables from other sub-designs. The function that combines the status variable for each portion of the sub-design may be the same function that combines the variables from different sub-designs in one of the circuit designs.

[0023] The disclosed method may further comprise a step in which a third sub-design of the first circuit design is mapped to a third FPGA unit. In that step, also a fourth sub-design of the first circuit design is mapped to a fourth FPGA unit. For each of the third and fourth sub-design, a status variable is generated which is configured to indicate a readiness status of the corresponding sub-design. In another step of the disclosed method, the status variables of the third and fourth sub-design are connected to a second superordinate FPGA unit. Each of the status variables of the third and fourth sub-design are connected to the second superordinate FPGA unit through a separate data channel. In yet another step, the content of each status variable of the third and fourth sub-design in the first circuit design is transmitted to the second superordinate FPGA unit through the data channels. A testing of the first circuit design is initiated when all status variables pertaining to the sub-designs of the first circuit design indicate a positive readiness of the corresponding sub-designs of the first circuit design.

[0024] To that end, the first and second superordinate FPGA unit may be configured to communicate with each other. Particularly, the first superordinate FPGA may be configured to determine an aggregate readiness status for the first and second sub-design and the second superordinate FPGA unit may be configured to determine an aggregate readiness status for the third and fourth sub-design. Furthermore, at least one of the first and secondsuperordinate FPGA unit may be configured to transmit the respective determined aggregate readiness status to the second or first superordindate FPGA unit respectively. Based on them, an aggregate readiness status of the first circuit design may be determined. The disclosed method is scalable to be performed with complex circuit designs with more subdesigns that can be handled by a single superordinate FPGA unit. That allows for utilizing the whole bandwidth of the first superordinate FPGA unit with data channels. Additional data channels may be connected to the second superordinate FPGA unit.

[0025] Since the readiness status of the sub-designs may be polled essentially in parallel, the disclosed method is essentially scalable without loss of speed. Instead of aggregating the contents of several status variables into intermediate status variables which still fit the bandwidth of the first superordinate FPGA, a second superordinate FPGA unit is utilized. Such intermediate status variables slow down a scalar reduce / broadcast operation. The disclosed method avoids that and is capable of high speeds even with an increased number of sub-designs. Furthermore, the disclosed method may also be accordingly performed with further sub-designs and further superordinate FPGA units.

[0026] In the disclosed method, a second circuit design may be provided which is also to be tested. The second circuit design comprises a plurality of sub-designs. The second circuit design may be compartmentalized to the sub-designs analogous to the first circuit design. In a further step of the disclosed method, a first sub-design of the second circuit design may be mapped onto a fifth FPGA unit. Correspondingly, a second sub-design of the second circuit design may be mapped onto a sixth FPGA unit. For the first and second subdesign of the second circuit design, status variables are generated which are configured to reflect a readiness status of the corresponding sub-designs. In a further step, the status variables of the first and second sub-design of the second circuit design are connected to the first superordinate FPGA unit. Each of the first and second sub-design of the second circuit design is connected to the first superordinate FPGA unit through a separate data channel. In yet another step, the content of each status variable is submitted to the first superordinate FPGA unit. Furthermore, the testing of the second circuit design is initiated when all status variables pertaining to the sub-designs of the second circuit indicate a positive readiness of the corresponding sub-designs of the second circuit design. That allows for testing the first and second circuit design independently from each other on distinct FPGA resources of a single FPGA system.

[0027] A specific set of FPGA units numbering several 10s to several 100s may be connected to each superordinate FPGA. When the first and second circuit design are configured to run on FPGA resources connected to the same superordinate FPGA the superordinate FPGA may be configured to perform the computations required for each of the circuit designs independently. The corresponding superordinate FPGA unit may be configured to combine the status variables from the pertaining sub-designs of the first circuit design and send the corresponding aggregated readiness status to the sub-designs of the first circuit design. The first superordinate FPGA unit may also be configured to combine the status variables from the sub-designs of the second sub-design and send corresponding aggregated readiness status to the sub-designs of the second sub-designThe first superordinate FPGA unit may be configured to keep the status variables from the first and second circuit design separate. Additionally, when different circuit designs are connected to the same superordinate FPGA unit, that FPGA unit may be requested to communicate to multiple different superordinate FPGA units at the same time. Furthermore, communication pertaining to the first and second circuit design may have to be interwoven in such cases.

[0028] As a result, the testing of the first circuit design may have to wait for a communication of the second circuit design to finish before it can proceed. In the disclosed method, such situations may be avoided, resulting in an increased speed of the testing. That allows for testing multiple circuit designs at the same time on one FPGA system without a loss of speed. Such a configuration of the data channels may automatically be determined by the compiler that also maps the sub-design to the different FPGA units. Consequently, the disclosed method is relatively easy to implement. Additionally, the disclosed method may be performed accordingly with a third, fourth, etc. circuit design.

[0029] In another embodiment of the disclosed method, the data channels are generated by the compiler that is configured to detect data channels with a required data with of one bit. Such data channels may be combined with similar variables, e.g status variables in further sub-designs. The compiler may be configured to to recognize such variables and computations which use these variables. Furthermore, the compiler may be configured to map such variables in an automated manner to use an superordinate FPGA unit and dedicated data channels.

[0030] In yet another embodiment, the disclosed method comprises a step in which thetesting of the first circuit design is halted when at least one of the status variables indicates a negative readiness of one of the sub-designs of the first circuit design. Halting the testing may comprise interrupting an ongoing testing or delaying a commencement procedure of the testing. As a result, the disclosed method prevents a testing from running into a situation in which it could generate incorrect results due to at least one sub-design not being ready. This allows for a more efficient use of the FPGA system on which the disclosed method is performed. Since the data channels which carry the status variables are fast, the testing may be halted and then resumed quickly. That allows for an appropriate reaction even to unexpected errors which render a sub-design not ready. In such situations, the testing may be brought to a halt in a controlled manner in which loss of data may be avoided.

[0031] Additionally, the first superordinate FPGA unit utilized in the disclosed method may have at least 40 data channels in each direction to connect to distinct FPGA units. In yet another embodiment of the disclosed method, the first superordinate FPGA unit may have at least 60 data channels in each direction to connect to distinct FPGA units. With these numbers of channels a corresponding number of sub-designs may be connected to one super ordinate FPGA unit and be checked for their respective readiness for testing at essentially the same time, i.e. in parallel. Consequently, the disclosed method is scalable to complex circuit designs with a high number of sub-designs.

[0032] Moreover, the object outlined above is also achieved by a disclosed computer program product that comprises program code that is stored on a non-transitory memory and that is executable by a processor. The program code of the disclosed computer program product is configured to perform at least one embodiment of the disclosed method when it is loaded. Thus, the features and benefits of the disclosed method also apply to the disclosed computer program product correspondingly. The disclosed method may be a computer-implemented method that is implemented based on the disclosed computer program product.

[0033] Furthermore, the disclosed computer program product may comprise an FPGA system compiler that is configured to compartmentalize circuit designs into sub-designs and to map the sub-designs to different FPGA units of an FPGA system. The compiler may also be configured to detect variables with a data width of one bit. The FPGA system compiler may also be configured to identify computations combining the variables fromdifferent sub-designs and map these computations to a superordinate FPGA and the data channels connecting a superordinate FPGA with other FPGA units.The FPGA system compiler may be configured to generate corresponding data channels for such variables. In the event of circuit designs with sub-design counts exceeding the number of data channels of a single super-ordinate FPGA the compiler can be configured to automatically use a second or third or etc. additional superordinate FPGA to be sufficient to reach all FPGA units needed for the sub-designs of the circuit design.

[0034] The object outlined above is also achieved by a disclosed FPGA system that comprises a plurality of FPGA units. At least one of the FPGA units is optimized to perform scalar reduce / broadcast operations. The disclosed FPGA system is configured to perform a step in which a first circuit design is loaded, which is to be tested. In that step, the first circuit design is compartmentalized into at least a first and a second sub-design. The disclosed FPGA system is also configured to perform a step in which a status variable is generated for the first and second sub-design of the first circuit design. The status variables are configured to indicate a readiness status of the corresponding sub-design for testing. In yet another step, the status variables of the first and second sub-design are connected to a first superordinate FPGA unit. Each of the first and second sub-design are connected to the first superordinate FPGA through a separate data channel. Still further, the disclosed FPGA system is configured to perform a step in which the content of each status variable pertaining to the sub-designs of the first circuit design is transmitted to the first superordinate FPGA unit. The testing of the first circuit design is initiated when all status variables pertaining to the sub-designs of the first circuit design indicate a positive readiness of the corresponding sub-designs.

[0035] In the disclosed FPGA system, at least one of the FPGA units is optimized to perform scalar reduce / broadcast operations. That optimized FPGA unit is utilized as the first superordinate FPGA unit. The disclosed FPGA system may be configured to perform at least one embodiment of the disclosed method. To that end, the disclosed FPGA system may be equipped with the disclosed computer program product. The features and benefits of the disclosed method and the disclosed computer program product also apply to the disclosed FPGA unit.

[0036] FIG 1 shows a first embodiment of the disclosed FPGA system 10 on which afirst embodiment of the disclosed method 100 is performed. The FPGA system 10 comprises a plurality of FPGA units 13, which can be connected to a first superordinate FPGA unit 12. In the embodiment shown in FIG 1, a first step 110 of the disclosed method 100 is already concluded. The first step 110 comprises that a first circuit design 20 is loaded which is to be tested based on the disclosed method 100. During the first step 110, the first circuit design 20 is compartmentalized into several sub-designs 34, comprising at least a first sub-design 21 and a second sub-design 22. In the first step, each of the sub-designs 34 is mapped to a separate FPGA unit 13.

[0037] Particularly, the first sub-design 21 is mapped to a first FPGA unit 15 and the second sub-design 22 is mapped to a second FPGA unit 16 of the FPGA system 10. During the testing of the first circuit design 20, the sub-designs 34 interact with each other to emulate the functioning of the first circuit design 10. The compartmentalization of the first circuit design 20 is symbolized by the broken lines dividing rectangle 20 in FIG 1. The compartmentalization may be performed by a compiler 55 which belongs to a computer program product 50 with program code 52, based on which the disclosed method 100 is performed. The further aspects of the first step 110 may be performed by the computer program product 50.

[0038] In a second step 120 of the disclosed method 100, a status variable 25 is generated for each sub-design 34 of the first circuit design 20. The status variables 25 may be derived from the compartmentalization of the first circuit design 20 by the computer program product 50, particularly by the compiler 55. The status variables 25 are each configured to reflect the readiness status of the corresponding sub-designs 34. When a sub-design 34 is ready for testing according to a test schedule 45, the corresponding status variable 25 shows a positive readiness 26. The disclosed method 100 is performed in cycles which occur independent of the test schedule 45. Since the readiness status of a sub-design 34 is a binary information, the status variables 25 have a data width of one bit. In some embodiments, the status variables 25 can each be configured to reflect a single binary information.

[0039] The disclosed method 100 also comprises a third step 130, in which each of the status variables 25 pertaining to sub-designs 34 of the first circuit design 20 are connected to the first superordinate FPGA unit 12. To that end, for each status variable 25, and in turn for each sub-design 34, a data channel 27 is generated that connects to the firstsuperordinate FPGA unit 12. In some embodiments, the data channels 27 also can have a data width of one bit, thus being adapted to the data width requirements of the connected status variables 25. The data channels 27 are connected to the first superordinate FPGA 12 in parallel, which is not depicted in FIG 1 for the sake of overview. The first superordinate FPGA unit 12 has a bandwidth 11 that is at least sufficient to connect each data channel 27 in parallel.

[0040] The disclosed method 100 also comprises a fourth step 140 in which the first superordinate FPGA unit 12 receives the contents of the status variables 25 of each subdesign 34, comprising the first sub-design 21 and the second sub-design 22. The content of each status variable 25 is substantially continuously transmitted to the first superordinate FPGA unit 12. The transmissions 29 of the readiness statuses 26 are received by the first superordinate FPGA unit 12. To evaluate the contents of the status variables 25 of the first circuit design 25, the first superordinate FPGA unit 12 is optimized to perform scalar re- duce / broadcast operations. With a scalar reduce operation 39, a plurality of one-bit inputs may be processed resulting in a single one-bit information. A scalar broadcast operation 38 constitutes the opposite of a scalar reduce operation 39, as shown schematically in FIG 1. When all status variables 25, and in turn, all sub-design 34, indicate a positive readiness 26, the testing of the first circuit design 20 is initiated. To that end, the first superordinate FPGA unit 12 is configured to generate a corresponding instruction 46, which may be duplicated multiple times through a scalar broadcast operation 38. The testing of the first circuit design 20 follows the test schedule 45. The method 100 shown in FIG 1 is a computer- implemented method based on the computer program product 50 which is configured to be run on the FPGA system 10.

[0041] FIG 2 shows a second embodiment of the disclosed FPGA system 10 on which a second embodiment of the disclosed method 100 is performed. The FPGA system 10 comprises a plurality of FPGA units 13 which are connected to a first superordinate FPGA unit 12 and a second superordinate FPGA unit. In the embodiment shown in FIG 2, a first step 110 of the disclosed method 100 is already concluded. The first step 110 comprises that a first circuit design 20 is loaded which is to be tested based on the disclosed method 100. During the first step 110, the first circuit design 20 is compartmentalized into several sub-designs 34, comprising at least a first sub-design 21 and a second sub-design 22. In the first step, each of the sub-designs 34 is mapped to a separate FPGA unit 13. Particularly,the first sub-design 21 is mapped to a first FPGA unit 15 and the second sub-design 22 is mapped to a second FPGA unit 16 of the FPGA system 10. Furthermore, a third sub-design 23 is mapped to a third FPGA unit 17 and a fourth sub-design 24 is mapped to a fourth FPGA unit 18. During the testing of the first circuit design 20, the sub-designs 34 interact with each other to emulate the functioning of the first circuit design 10. The compartmentalization of the first circuit design 20 is symbolized by the broken lines dividing rectangle 20 in FIG 2. The compartmentalization may be performed by a compiler 55 which belongs to a computer program product 50 with program code 52, based on which the disclosed method 100 is performed.

[0042] In a second step 120 of the disclosed method 100, a status variable 25 is generated for each sub-design 34 of the first circuit design 20. The status variables 25 may be derived from the compartmentalization of the first circuit design 20 by the computer program product 50, particularly by the compiler 55. The status variables 25 are each configured to reflect the readiness status of the corresponding sub-designs 34. When a sub-design 34 is ready for testing according to a test schedule 45, the corresponding status variable 25 shows a positive readiness 26. The disclosed method 100 is performed in cycles which occur independent of the test schedule 45. Since the readiness status of a sub-design 34 is a binary information, the status variables 25 have a data width of one bit. Thus, the status variables 25 are each configured to reflect only a single binary information.

[0043] The disclosed method 100 also comprises a third step 130, in which each of the status variables 25 pertaining to sub-designs 34 of the first circuit design 20 are connected to the first superordinate FPGA unit 12 or the second superordinate FPGA unit 14. In the embodiment according to FIG 2, a first group of sub-designs 34, including the first and second sub-design 21, 22 are mapped onto the first superordinate FPGA unit 12. Correspondingly, a second group of sub-designs 34, including the third and fourth sub-design 23, 24 are mapped onto the second superordinate FPGA unit 14. To that end, for each status variable 25, and in turn for each sub-design 34, a data channel 27 is generated that connects to the first or second superordinate FPGA unit 12, 14 respectively. The data channels 27 also have a data width of one bit, thus being adapted to the data width requirements of the connected status variables 25. The data channels 27 are connected to the first and second superordinate FPGA 12, 14 in parallel, which is not depicted in FIG 2 for the sake of overview. Both the first and second superordinate FPGA unit 12, 14 have a bandwidth 11that is at least sufficient to connect each data channel 27 pertaining to the corresponding sub-designs 34 in parallel.

[0044] The disclosed method 100 also comprises a fourth step 140 in which the first and second superordinate FPGA unit 12, 14 receive the contents of the status variables 25 of each sub-design 34 connected to it, comprising the first sub-design 21, the second subdesign 22, the third sub-design 23 and the fourth sub-design 24. the content of each status variable 25 is substantially continuously transmitted to the first and second superordinate FPGA unit 12, 14 respectively. The transmissions 29 of the readiness statuses 26 are received by the first and second superordinate FPGA units 12, 14. To evaluate the contents of the status variables 25 of the first circuit design 25, the first and second superordinate FPGA units 12. 14 are each optimized to perform scalar reduce / broadcast operations. With a scalar reduce operation 39, a plurality of one-bit inputs may be processed resulting in a single one-bit information. A scalar broadcast operation 38 constitutes the opposite of a scalar reduce operation 39, as shown schematically in FIG 2.

[0045] When all status variables 25, and in turn, all sub-design 34, indicate a positive readiness 26, the testing of the first circuit design 20 is initiated. To that end, the first and second superordinate FPGA units 12. 14 are configured to generate a corresponding instruction 46, which may be duplicated multiple times through a scalar broadcast operation 38. The first superordinate FPGA unit 12 and the second superordinate FPGA unit 14 are configured to communicate with each other. Such an FPGA communication is symbolized by the double arrows 19. The FPGA communication 19 allows for exchanging information about the readiness status of the status variables 25 connected to the first or second superordinate FPGA unit 12, 14. The testing of the first circuit design 20 follows the test schedule 45, which may be stored on at least one of the first and second superordinate FPGA unit 12, 14. The method 100 shown in FIG 2 is a computer-implemented method based on the computer program product 50 which is configured to be run on the FPGA system 10.

[0046] FIG 3 shows a third embodiment of the disclosed FPGA system 10 on which a third embodiment of the disclosed method 100 is performed. The FPGA system 10 comprises a plurality of FPGA units 13 which are connected to a first superordinate FPGA unit 12. In the embodiment shown in FIG 3, a first step 110 of the disclosed method 100 is already concluded. The first step 110 comprises that a first circuit design 20 is loaded whichis to be tested based on the disclosed method 100. During the first step 110, the first circuit design 20 is compartmentalized into several sub-designs 34, comprising at least a first subdesign 21 and a second sub-design 22. In addition to that, a second circuit design 30 is loaded which is to be tested. Like the first circuit design 20, the second circuit design 30 is compartmentalized into several sub-designs 34, comprising at least a first sub-design 31 and a second sub-design 32. The second circuit design 30 is independent of the first circuit design 20 and may be tested individually.

[0047] In the first step, each of the sub-designs 34 is mapped to a separate FPGA unit 13 of the disclosed FPGA system 10. Particularly, the first sub-design 21 of the first circuit design 20 is mapped to a first FPGA unit 15 and the second sub-design 22 of the first circuit design 20 is mapped to a second FPGA unit 16 of the FPGA system 10. The first subdesign 31 of the second circuit design 30 is mapped to a fifth FPGA unit 41 of the disclosed FPGA system 10. Correspondingly, the second sub-design 32 of the second circuit design 30 is mapped to a sixth FPGA unit 42 of the disclosed FPGA system 10. During the testing of the first circuit design 20, the sub-designs 34 interact with each other to emulate the functioning of the first circuit design 20 and the second circuit design 30 respectively. The compartmentalization of the first and second circuit design 20, 30 is symbolized by the broken lines dividing the rectangles 20 and 30 in FIG 3. The compartmentalization may be performed by a compiler 55 which belongs to a computer program product 50 with program code 52, based on which the disclosed method 100 is performed.

[0048] In a second step 120 of the disclosed method 100, a status variable 25 is generated for each sub-design 34 of the first and second circuit design 20, 30. The status variables 25 may be derived from the compartmentalization of the first and second circuit design 20, 30 by the computer program product 50, particularly by the compiler 55. The status variables 25 are each configured to reflect the readiness status of the corresponding sub-designs 34. When a sub-design 34 is ready for testing according to a test schedule 45, the corresponding status variable 25 shows a positive readiness 26. The disclosed method 100 is performed in cycles which occur independent of the test schedule 45. Since the readiness status of a sub-design 34 is a binary information, the status variables 25 have a data width of one bit. Thus, the status variables 25 are each configured to reflect only a single binary information.

[0049] The disclosed method 100 also comprises a third step 130, in which each of the status variables 25 pertaining to sub-designs 34 of the first and second circuit design 20, 30 are connected to the first superordinate FPGA unit 12. To that end, for each status variable 25, and in turn for each sub-design 34, a data channel 27 is generated that connects to the first superordinate FPGA unit 12. The data channels 27 also have a data width of one bit, thus being adapted to the data width requirements of the connected status variables 25. The data channels 27 are connected to the first superordinate FPGA 12 in parallel, which is not depicted in FIG 3 for the sake of overview. The first superordinate FPGA unit 12 has a bandwidth 11 that is at least sufficient to connect each data channel 27 in parallel.

[0050] The disclosed method 100 also comprises a fourth step 140 in which the first superordinate FPGA unit 12 receives the contents of the status variables 25 of each subdesign 34 of at least one of the first and second circuit design 20, 30. The sub-designs 34 of the first circuit design 20 comprise the first sub-design 21 and the second sub-design 22. The sub-designs 34 of the second circuit design 30 comprise at least the first sub-design 31 and the second sub-design 32. The content of each status variable 25 is substantially continuously transmitted to the first superordinate FPGA unit 12. The transmissions 29 of the readiness statuses 26 are received by the first superordinate FPGA unit 12. To evaluate the contents of the status variables 25 of the first circuit design 20, the first superordinate FPGA unit 12 is optimized to perform scalar reduce / broadcast operations. With a scalar reduce operation 39, a plurality of one-bit inputs may be processed resulting in a single one- bit information. A scalar broadcast operation 38 constitutes the opposite of a scalar reduce operation 39, as shown schematically in FIG 3. When all status variables 25 of at least one of the first and second circuit designs 20, 30 and in turn, all corresponding sub-designs 34, indicate a positive readiness 26, the testing of the corresponding at least one of the first and second circuit design 20, 30 is initiated. To that end, the first superordinate FPGA unit 12 is configured to generate a corresponding distinct instruction 46 for at least one of the first and second circuit designs 20, 30, which may be duplicated multiple times through a scalar broadcast operation 38. The testing of the first circuit design 20 follows the test schedule 45. The method 100 shown in FIG 3 is a computer-implemented method based on the computer program product 50 which is configured to be run on the FPGA system 10.

[0051] In FIG 4, a fourth embodiment of the disclosed method 100 is shown schematically. The disclosed method 100 is performed on an FPGA system 10 similar to the onesshown in FIG 1, 2, 3. According to the embodiment in FIG 4, the FPGA system 10 comprises a first superordinate FPGA unit 12, a second superordinate FPGA unit 14 and several further superordinate FPGA units 36. Each of the superordinate FPGA units 12, 14, 36 is connected to several FPGA units 13 through data channels 27. The data channels 27 are configured to carry the contents of a status variable 25, as for in FIG 1, 2, 3, to evaluate if at least one of the first and second circuit design 20, 30 is ready for testing. A sub-design 34 of the first or second circuit design 20, 30 respectively is mapped to each of the FPGA units 13 that are connected to the first, second or one of the further superordinate FPGA units 12, 14, 36. Furthermore, the first, second and the further superordinate FPGA units 12, 14, 36 are connected to each other through superordinate channels 40. Particularly, the first, second and the further superordinate FPGA units 12, 14, 36 are connected to each other in pairs. For the sake of better overview, not all superordinate channels 40 are shown.

[0052] The superordinate channels 40 are configured to carry the communication 19 between the different superordinate FPGA units 12, 14, 36. FPGA units 13 with the subdesigns 34 of the first circuit design 20 are mapped to the first and second superordinate FPGA unit 12, 14, occupying their entire bandwidth 11. Correspondingly, the FPGA units 13 with sub-designs 34 of the second circuit design 30 are mapped to further superordinate FPGA units 36, occupying their respective entire bandwidth 11, as shown on the righthand side of FIG 3. Furthermore, FPGA units 13 pertaining to sub-designs 34 of both the first circuit design 20 and the second circuit design 30 are connected to the further superordinate FPGA unit 36 through data channels 27, as shown in the middle of FIG 4. Thus, subdesigns from 34 belonging to the first and second circuit design 20, 30 each occupy a portion of the bandwidth 11 of the corresponding further superordinate FPGA unit 36. When both the first and second circuit design 20, 30 are being tested according to the test schedule 45, the first and second superordinate FPGA units 12, 14 communicate with the further superordinate FPGA unit 36 to which also sub-designs 34 of the second circuit design 30 are connected. The compiler 55, which is utilized to generate the data channels 27 is configured to group sub-designs 34 of the first circuit design 20 to superordinate FPGA units 12, 14, 26, which are essentially adjacent to each other. The same applies to the second circuit design 30 accordingly.

[0053] Furthermore, the compiler 55 is configured to minimize the number of superordinate FPGA units 12, 14, 36 which connect to multiple circuit designs 20, 30. Within theFPGA system 10, that accomplishes an increased degree of separation 53 among the circuit designs 20, 30 that are to be tested. That results in an acceleration of the respective FPGA communications, allowing for a speedy testing of all circuit designs 20, 30 involved. The compiler 55 belongs to a computer program product 50 through which the disclosed method 100 is performed. Consequently, the disclosed method 100 also accelerates the testing of the underlying circuit designs 20, 30.

[0054] A schematic overview of the first embodiment of the disclosed method 100 is shown in FIG 5. The method 100 is performed based on a computer program product 50 that is run on a FPGA system 10 that comprises a plurality of FPGA units 13. During the first step 110, a first circuit design 20 is loaded, which is to be tested. Furthermore, the first circuit design 20 is compartmentalized into several sub-designs 34, which comprise at least a first sub-design 21 and a second sub-design 22. The compartmentalization in the first step 110 is performed by a compiler 55, which is part of the computer program product 50. The sub-design 34 are mapped to separate FPGA units 13 of the FPGA system 10. During the first step 110, the first sub-design 21 is mapped to a first FPGA unit 15 and the second sub-design 22 is mapped to a second FPGA unit 16. During the testing of the first circuit design 20, the sub-designs 34 interact with each other to emulate the functioning of the first circuit design 20.

[0055] In a subsequent second step 120, a status variable 25 is generated for each subdesign 34 of the first circuit design 20. The status variables 25 are generated by the compiler 55 based on the compartmentalization of the first circuit design 20. Each status variable 25 is configured to reflect the readiness status of its corresponding sub-design 34 for testing. The status variable 25 has a data width of exactly one bit, since the readiness status is a binary information. In a subsequent third step 130, each of the status variables 25 that pertains to a sub-design 34 of the first circuit design 20 is connected to a first superordinate FPGA unit 12. To that end, for each status variable 25 a data channel 27 is generated. The actions in the second and third step 120, 130 are performed by the computer program product 50 which performs the disclosed method 100.

[0056] The fourth step 140 of the disclosed method 100 comprises that the first superordinate FPGA unit 12 polls the readiness status of at least the first and second sub-design 21, 22 of the first circuit design 20. As a response, the content of each status variable 25 istransmitted to the first superordinate FPGA unit 12. The first superordinate FPGA unit 12 is optimized to perform scalar reduce / broadcast operations. Through a scalar reduce operation 39, the plurality of one-bit inputs from the status variables 25 are processed quickly. The first superordinate FPGA unit 12 evaluates the contents of the status variables 25 to check if all of them show a positive readiness status 26. Depending on that evaluation, the disclosed method 100 bifurcates. In FIG 5, that bifurcation is symbolized by the diamond shape 135. If all status variables 25 indicate a positive readiness status 26, the testing of the first circuit design 20 according to the test schedule 45 proceeds. That proceeding is symbolized by the rectangle 136. If at least one of the status variables 25 indicates a negative readiness status, the disclosed method 100 is put to a halt 137.

Claims

CLAIMS1. A method for testing a first circuit design on an FPGA system, the first circuit design being compartmentalized into a plurality of interacting sub-designs, the method comprising:Mapping a first sub-design of the first circuit design onto a first FPGA unit and mapping a second sub-design of the first circuit design onto a second FPGA unit,Creating a status variable for the first and second sub-design of the first circuit design, the status variables being configured to indicate a readiness status of the corresponding subdesign for testing;Connecting the status-variables of the first and second sub-design of the first circuit design to a first superordinate FPGA unit each through a separate data channel; and- Transmitting the content of each status variable pertaining to the sub-designs of the first circuit design to the first superordinate FPGA unit and initiating the testing of the first circuit design when all status variables pertaining to the sub-designs of the first circuit design indicate a positive readiness of the corresponding sub-designs.

2. The method according to claim 1 , wherein at least one of the data channels has a data width of one bit.

3. The method according to claim 1, wherein the contents of the status variables of the first and second sub-design of the first circuit design are being acquired independently of each other.

4. The method according to claim 1 , wherein at least one of the data channels is configured to operate independently of the testing of the sub-design associated with the data channel.

5. The method according to claim 1, wherein the first superordinate FPGA unit is optimized to perform scalar reduce / broadcast operations.

6. The method according to claim 1 , wherein at least one of the status variables is configured to reflect an aggregated readiness status of portions of the corresponding sub-design.

7. The method according to claim 1, the method further comprising:Mapping a third sub-design of the first circuit design to a third FPGA-unit, mapping a fourth sub-design of the first circuit design to a fourth FPGA unit and creating a status variable for each of the third and fourth sub-design of the first circuit design;Connecting the status variables of the third and fourth sub-design of the first circuit design to a second superordinate FPGA unit each through a separate data channel;- Transmitting the content of each status variable to the first and second superordinate FPGA unit and initiating the testing of the first circuit design when all status variables pertaining to the sub-designs of the first circuit design indicate a positive readiness of the corresponding sub-designs of the first circuit design.

8. The method according to claim 1, wherein a second circuit design is provided comprising a plurality of sub-designs, the method further comprising:Mapping a first sub-design of the second circuit design to a fifth FPGA unit, mapping a second sub-design of the second circuit design to a sixth FPGA unit and creating a status variable for each of the first and second sub-design of the second circuit design;Connecting the status variables to the first superordinate FPGA unit each through a separate data channel;- Transmitting the content of each status variable to the first superordinate FPGA unit and initiating the testing of the second circuit design when all status variables pertaining to the sub-designs of the second circuit design indicate a positive readiness of the corresponding sub-designs of the second circuit design.

9. The method according to claim 1, wherein the data channels are generated by a compiler, the compiler being configured to detect data channels with a required data width of one bit.

10. The method according to claim 1, the method further comprising:Halting the testing of the first circuit design when at least one of the status variables indicates a negative readiness of one of the sub-designs of the first circuit design.

11. The method according to claim 1 , wherein the first superordinate FPGA unit has a connection bandwidth for at least 40 data channels.

12. A computer program product, comprising program code that is stored on a non-transitory memory and that is executable by a processor, the program code being configured to perform the method according to claim 1 when it is loaded.

13. The computer program product according to claim 12, the computer program product comprising an FPGA system compiler that is configured to detect data channels with a data width of one bit and to map the functioning of the detected data channels to the first or second superordinate FPGA unit.

14. An FPGA system, comprising a plurality of FPGA units, wherein at least one of the FPGA units is optimized to perform scalar reduce / broadcast operations, the FPGA system being configured to perform the following:Loading a first circuit design that is to be tested and compartmentalizing the first circuit design into at least a first and a second sub-design;Creating a status variable for the first and second sub-design of the first circuit design, the status variables being configured to indicate a readiness status of the corresponding subdesign for testing;Connecting the status-variables of the first and second sub-design of the first circuit design to a first superordinate FPGA unit each through a separate data channel;- Transmitting the content of each status variable pertaining to the sub-designs of the first circuit design to the first superordinate FPGA unit and initiating the testing of the first circuit design when all status variables pertaining to the sub-designs of the first circuit design indicate a positive readiness of the corresponding sub-designs, wherein the at least one FPGA unit optimized to perform scalar reduce / broadcast operations is utilized as the first superordinate FPGA unit.

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