Multi-chip system and method of operating a multi-chip system

Abstract

The present application provides a multi-chip system and an operating method of the multi-chip system. The multi-chip system includes a first chip and at least one second chip. The first chip and the at least one second chip are disposed on a routing layer. The first chip includes a first selection pin, a first test circuit, and a plurality of first input / output pins. The first selection pin receives a first selection signal. The first test circuit is coupled to the first selection pin. Each second chip includes a second selection pin and a second test circuit. The second selection pin receives a second selection signal. The second test circuit is coupled to the second selection pin and includes a plurality of second test units. The plurality of first input / output pins are coupled to the plurality of second test units of each second chip through a plurality of die-to-die traces. The multi-chip system and the operating method of the multi-chip system of the present application can effectively save the number of solder balls and provide good testability design test functions.

Description

Technical Field

[0001] This invention relates to an integrated system, and more particularly to a multi-chip system and a method of operating the multi-chip system. Background Technology

[0002] To meet the design-for-testability (DFT) requirements in the manufacturing process of high-speed chips, each chip in a multi-chip system currently requires corresponding test circuits and multiple input / output pins for DFT testing functions. This results in the integrated size of the multi-chip system being affected by the large number of solder balls used to connect to the multiple input / output pins, leading to excessive board space usage and hindering the reduction of the system's overall size. Summary of the Invention

[0003] This invention relates to a multi-chip system and a method for operating a multi-chip system, which can effectively save the number of solder balls and demonstrate good Design for Testing (DFT) testing capabilities.

[0004] According to an embodiment of the present invention, the multi-chip system of the present invention includes a first chip and at least one second chip. The first chip is disposed on a circuit layer. The first chip includes a first select pin, a first test circuit, and a plurality of first input / output pins. The first select pin receives a first select signal. The first test circuit is coupled to the first select pin. Each second chip is disposed on a circuit layer. Each second chip includes a second select pin and a second test circuit. The second select pin receives a second select signal. The second test circuit is coupled to the second select pin and includes a plurality of second test units. The plurality of first input / output pins are coupled to the plurality of second test units of each second chip through a plurality of die-to-die traces.

[0005] According to embodiments of the present invention, the operating method of the present invention is applicable to a multi-chip system. The multi-chip system includes a first chip and at least one second chip. The first chip includes a first selection pin, a first test circuit, and a plurality of first input / output pins. The first test circuit is coupled to the first selection pin. Each second chip includes a second selection pin and a second test circuit. The second test circuit is coupled to the second selection pin. The second test circuit includes a plurality of second test units. The first chip and at least one second chip are disposed on a line layer. The plurality of first input / output pins are coupled to the plurality of second test units of each second chip through a plurality of die-to-die traces. The operating method includes the following steps: receiving a first selection signal through the first selection pin and receiving a second selection signal through the second selection pin; when the first chip operates in test mode according to the first selection signal, acquiring first input data of the first chip or sending first output data of the first chip through the plurality of first input / output pins of the first chip; and when the first chip operates in high-impedance mode according to the first selection signal, acquiring second input data of one of the at least one second chip under test or sending second output data of the second chip under test through the plurality of first input / output pins.

[0006] Based on the above, the multi-chip system and its operation method of the present invention can connect multiple chips of the multi-chip system through die-to-die routing between the chips, thereby effectively reducing circuit complexity, saving the number of solder balls (effectively saving the size of the multi-chip system), and demonstrating good testability design and testing capabilities.

[0007] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a circuit diagram of a multi-chip system according to an embodiment of the present invention;

[0009] Figure 2 This is a flowchart of an operation method of a multi-chip system according to an embodiment of the present invention;

[0010] Figure 3 This is a circuit diagram of a multi-chip system according to another embodiment of the present invention;

[0011] Figure 4 This is a schematic diagram of the structure of a multi-chip system according to an embodiment of the present invention. Detailed Implementation

[0012] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0013] Figure 1 This is a circuit diagram of a multi-chip system according to an embodiment of the present invention. (Reference) Figure 1 The multi-chip system 100 includes multiple chips 110_1 to 101_M, where M is an integer greater than 1. The number of chips 110_1 to 101_M is at least two. In other words, in one embodiment, the multi-chip system 100 may include chip 110_1 (i.e., a first chip) and chip 110_2 (i.e., at least one second chip). In this embodiment, chip 110_1 includes a selection pin 111_1, multiple input / output pins 112_1 to 112_N, and a test circuit 113_1, where N is an integer greater than or equal to 1. The test circuit 113_1 may include a test unit group 114_1 and a test unit group 115_1. The test unit group 114_1 may include multiple test units (or sub-test circuits), and the multiple test units correspond to the multiple input / output pins 112_1 to 112_N respectively. The test unit group 115_1 may include another multiple test units. The other plurality of test units in test unit group 115_1 correspond to the plurality of test units in test unit group 114_1, respectively.

[0014] It should be noted that the test units described in the various embodiments of the present invention can be of the same circuit structure, and each test unit may include an output enable (OE) terminal, a data output terminal (DATA_OUT), a data input terminal (DATA_C), and an input / output terminal (PAD) coupled to the input / output pins.

[0015] In this embodiment, chip 110_2 includes a selection pin 111_2 and a test circuit 113_2. Test circuit 113_2 may include test unit group 114_2 and test unit group 115_2. Test unit group 114_2 may include multiple test units. Test unit group 115_1 may include another multiple test units. The other multiple test units of test unit group 115_2 correspond to the multiple test units of test unit group 114_2. In this embodiment, the other multiple test units of test unit group 115_1 of chip 110_1 are coupled to the multiple test units of test unit group 114_2 of chip 110_2 via multiple die-to-die (D2D) traces 120_1 to 120_N.

[0016] Similarly, chip 110_M includes a selection pin 111_M and a test circuit 113_M. Test circuit 113_M may include at least a test unit group 114_M. Test unit group 114_M may include multiple test units. In this embodiment, the multiple test units of test unit group 114_M of chip 110_M can be coupled to other multiple test units of test unit group 115_(M-1) of the previous chip 110_(M-1) via multiple die-to-die traces.

[0017] In other words, after the relevant functional circuits in the test circuits 113_1 to 113_M of chips 110_1 to 110_M are switched, the input / output pins 112_1 to 112_N can be coupled to multiple test units in each test unit group of chips 110_2 to 110_M through multiple die-to-die traces between chips.

[0018] In this embodiment, the multi-chip system 100 can transmit multiple input data Di1 to DiN and / or multiple output data Do1 to DoN through the input / output pins 112_1 to 112_N (at least a portion of the input / output pins) of chip 110_1, and use them for design-testability testing of chip 110_1. Alternatively, chip 110_2 can transmit multiple input data Di1 to DiN and / or multiple output data Do1 to DoN through multiple die-to-die traces 120_1 to 120_N (at least a portion of the die-to-die traces) connected between chip 110_1 and chip 110_2, and use them for design-testability testing of chip 110_2. Alternatively, chip 110_2 can transmit multiple input data Di1 to DiN and / or multiple output data Do1 to DoN via multiple die-to-die traces (at least a portion of which) connected between chip 110_2 and chip 110_3, and use them for design-for-test functionality of chip 100_3. Similarly, chips 110_1 to 110_M can use input / output pins 112_1 to 112_N (at least a portion of which) in a time-division multiplexing or simultaneous manner to transmit data. Therefore, the multi-chip system 100 of the present invention can effectively save the number of solder balls and the size of the multi-chip system 100, and can also demonstrate good design-for-test functionality.

[0019] Figure 2 This is a flowchart illustrating an operation method of a multi-chip system according to an embodiment of the present invention. (See reference...) Figure 1 as well as Figure 2 , Figure 1The multi-chip system 100 can perform the following steps S210 to S230. In step S210, a first selection pin (selection pin 111_1) receives a first selection signal (selection signal SS1), and a second selection signal (selection signal SS2) is received through a second selection pin (selection pin 111_2). In step S220, when the first chip (chip 110_1) operates in test mode according to the first selection signal (selection signal SS1), the first input data of the first chip (chip 110_1) is obtained or the first output data of the first chip (chip 110_1) is sent through a plurality of first input / output pins (input / output pins 112_1 to 112_N). In some examples, the first input data of the first chip can be obtained or the first output data of the first chip can be sent through at least a portion of the plurality of first input / output pins (input / output pins 112_1 to 112_N). When the first chip (chip 110_1) operates in high-impedance mode according to the first selection signal (selection signal SS1), it acquires second input data of at least one of the second chips under test (one of chips 110_2 to 110_M) or transmits second output data of the second chip under test (one of chips 110_2 to 110_M) through a plurality of first input / output pins (input / output pins 112_1 to 112_N). In some examples, the second input data of at least one of the second chips under test can be acquired or the second output data of the second chip under test can be transmitted through at least a portion of the first input / output pins (input / output pins 112_1 to 112_N). Therefore, the multi-chip system 100 and operating method of the present invention can perform effective design-testability testing functions for multiple chips.

[0020] Figure 3 This is a circuit diagram of a multi-chip system according to another embodiment of the present invention. (See reference) Figure 3 The following description uses a test circuit for one first chip and a test circuit for two second chips as examples (i.e., corresponding to...). Figure 1 The chip system of the present invention includes chip 110_1 and two chips 110_2 and 110_3, and communication between each test circuit is exemplified by one input / output pin and one test unit (implementations with multiple input / output pins and multiple test units can be deduced similarly). However, in practice, the test circuit of each of the multiple chips in the chip system of the present invention may include multiple test units and multiple AND gate units, multiple routing units, and at least one test operation unit corresponding to the multiple test units (for example, one test operation unit may be coupled to multiple test units, or multiple test operation units may be coupled to multiple test units respectively), and is not limited to this. Figure 3 As shown.

[0021] In this embodiment, the multi-chip system 300 includes chips 310 to 330. The test circuit of chip 310 includes test units 311 and 313, AND gate units 312 and 314, a routing unit 315, a test operation unit 316, input / output pins 317, and a D2D pad 318. Test unit 311 includes an output enable terminal, a data output terminal, and a data input terminal. The first input terminal of AND gate unit 312 receives the main control signal MA1. The second input terminal of AND gate unit 312 receives the test control (DFTIO (Design for Testability Input / Output) test OE control) signal TCA1. The output terminal of AND gate unit 312 is coupled to the output enable terminal of test unit 311. The first input terminal of routing unit 315 is coupled to the data input terminal of test unit 311. The first output terminal of routing unit 315 is coupled to the data output terminal of test unit 311. The first control terminal of routing unit 315 receives a selection signal SS1. The second control terminal of routing unit 315 receives the control signal SPE1 from the pipeline. Test operation unit 316 is coupled to the bidirectional data transmission terminal of routing unit 315. Test unit 313 includes an output enable terminal, a data input terminal, and a data output terminal. Test unit 313 is connected to the pad 327 of chip 320 and the test unit 321 of the test circuit via pad 318 and die-to-die traces. The data input terminal of test unit 313 is coupled to the second input terminal of routing unit 315. The data output terminal of test unit 313 is coupled to the second output terminal of routing unit 315. The first input terminal of AND gate unit 314 receives the control signal SPE1 from the pipeline. The second input terminal of AND gate unit 314 receives the test control (D2D PAD test OEcontrol) signal TCB1. The output terminal of AND gate unit 314 is coupled to the output enable terminal of test unit 313.

[0022] In this embodiment, the test circuit of chip 320 includes test units 321 and 323, AND gate units 322 and 324, routing unit 325, test operation unit 326, and pads 327 and 328. Test unit 321 includes an output enable terminal, a data output terminal, and a data input terminal. The first input terminal of AND gate unit 322 receives a selection signal SS2. The second input terminal of AND gate unit 322 receives a test control signal TCA2. The output terminal of AND gate unit 322 is coupled to the output enable terminal of test unit 321. The first input terminal of routing unit 325 is coupled to the data input terminal of test unit 321. The first output terminal of routing unit 325 is coupled to the data output terminal of test unit 321. The first control terminal of routing unit 325 receives the selection signal SS2. The second control terminal of routing unit 324 receives a control signal SPE2 from the pipeline. Test operation unit 225 is coupled to the bidirectional data transmission terminal of routing unit 325. Test unit 323 includes an output enable terminal, a data output terminal, and a data input terminal. Test unit 323 is connected to chip 330's pad 337 and test unit 331 of the test circuit via pad 328 and die-to-die traces. The data input terminal of test unit 323 is coupled to the second input terminal of routing unit 325. The data output terminal of test unit 323 is coupled to the second output terminal of routing unit 325. The first input terminal of AND gate unit 324 receives the pipeline control signal SPE2. The second input terminal of AND gate unit 324 receives the test control (D2D PAD test OE control) signal TCB2. The output terminal of AND gate unit 324 is coupled to the output enable terminal of test unit 323.

[0023] In this embodiment, chip 330 includes a test unit 331, an AND gate unit 332, a routing unit 334, and a test operation unit 335. Test unit 331 includes an output enable terminal, a data output terminal, and a data input terminal. The first input terminal of AND gate unit 332 receives a selection signal SS3. The second input terminal of AND gate unit 332 receives a test control signal TCA3. The output terminal of AND gate unit 332 is coupled to the output enable terminal of test unit 331. The first input terminal of routing unit 335 is coupled to the data input terminal of test unit 331. The first output terminal of routing unit 335 is coupled to the data output terminal of test unit 331. The first control terminal of routing unit 335 receives the selection signal SS3. Test operation unit 336 is coupled to the bidirectional data transmission terminal of routing unit 335. It should be understood that chip 330 can adopt the same structure as chip 320, which will not be described in detail here. The structure of chip 330 is not limited to... Figure 3 The above is the limit.

[0024] Please refer to Table 1 below for the signal values ​​applied to the test chip 310. A signal value of 1 may correspond to a signal with a high voltage level, and a signal value of 0 may correspond to a signal with a low voltage level.

[0025] Taking the test operation unit 316, whose test source is input / output pin 317 and whose test target is chip 310, as an example, when the output enable terminal of test unit 311 is disabled (i.e., the value of main control signal MA1 is 1 and the value of test control signal TCA1 is 0), the output enable terminal of test unit 313 is disabled (i.e., the value of pipe control signal SPE1 is 0 and the value of test control signal TCB1 is 0), the first control terminal of routing unit 315 is enabled (i.e., the value of selection signal SS1 is 1), and the second control terminal of routing unit 315 is disabled (i.e., the value of pipe control signal SPE1 is 0), test unit 311 receives input data from input / output pin 317, outputs input data from the data input terminal of test unit 311, and provides it to test operation unit 316 through routing unit 315. In this way, the aforementioned operation can put the chip 310 into test mode, so as to perform signal input tests on the testability design of the chip 310 through the data signal transmission path 301 in the test circuit.

[0026] Taking the test operation unit 316 of chip 310 as the test source and the input / output pin 317 as the test target as an example, when the output enable terminal of test unit 311 is enabled (i.e., the value of main control signal MA1 is 1 and the value of test control signal TCA1 is 1), the output enable terminal of test unit 313 is disabled (i.e., the value of selection signal SS1 is 1 and the value of test control signal TCB1 is 0), the first control terminal of routing unit 315 is enabled (i.e., the value of selection signal SS1 is 1), and the second control terminal of routing unit 315 is disabled (i.e., the value of pipe control signal SPE1 is 0), test unit 311 receives the output data provided by test operation unit 316 from the data output terminal through routing unit 315, and outputs the output data from input / output pin 317. In this way, the aforementioned operation can put chip 310 into test mode, so as to perform signal output testing of chip 310's testability design through data signal transmission path 301 in the test circuit.

[0027]

[0028] Table 1

[0029] Please refer to Tables 2 and 3 below for the signal values ​​of the test circuit applied to the test chip 320.

[0030] Taking the test source as input / output pin 317, and the die-to-die routing via pads 318 and 327, with the test target being the test operation unit 326 of chip 320, as an example: When the output enable terminal of test unit 311 is disabled (i.e., the value of main control signal MA1 is 1, and the value of test control signal TCA1 is 0), the output enable terminal of test unit 313 is enabled (i.e., the value of pipe control signal SPE1 is 1, and the value of test control signal TCB1 is 1), and the first control terminal of routing unit 315 is disabled (i.e., the value of selection signal SS1 is 0), and the second control terminal of routing unit 315 is enabled (i.e., the value of pipe control signal SPE1 is 1), test unit 311 receives input data from input / output pin 317, and outputs input data from the data input terminal of test unit 311 to the data output terminal of test unit 313. Furthermore, the data input terminal of test unit 313 provides input data to pad 318, so as to provide input data to test unit 321 through pad 318, die-to-die routing, and pad 327. Next, when the output enable terminal of test unit 321 is disabled (i.e., the value of selection signal SS2 is 1 and the value of test control (D2D PAD test OE control) signal TCA2 is 0), the output enable terminal of test unit 323 is disabled (i.e., the value of pipeline control signal SPE2 is 0 and the value of test control signal TCB1 is 0), and the first control terminal of routing unit 325 is enabled (i.e., the value of selection signal SS2 is 1) and the second control terminal of routing unit 325 is disabled (i.e., the value of pipeline control signal SPE2 is 0), test unit 321 receives input data from die-to-die routing and outputs input data from the data input terminal of test unit 321 to test operation unit 326. In this way, the aforementioned operation can operate chip 310 in high-impedance mode and chip 320 in test mode, so as to perform signal input test of the testability design of chip 320 through the data signal transmission path 302 in the test circuit.

[0031] Taking the test processing unit 326 of chip 320 as the test source, and the die-to-die routing between pads 318 and 327 as the test target, and the input / output pin 317 as an example, when the output enable terminal of test unit 321 is enabled (i.e., the value of selection signal SS2 is 1, and the value of test control signal TCA2 is 1), the output enable terminal of test unit 323 is disabled (i.e., the value of pipeline control signal SPE2 is 0, and the value of test control signal TCB1 is 0), and the first control terminal of routing unit 325 is enabled (i.e., the value of selection signal SS2 is 1), and the second control terminal of routing unit 325 is disabled (i.e., the value of pipeline control signal SPE2 is 0), test unit 321 receives the output data provided by test processing unit 326 from the respective data output terminals, and outputs the output data from pad 327, multiple die-to-die routings, and pad 318 to test unit 313. Next, when the output enable terminal of test unit 311 is enabled (i.e., the value of main control signal MA1 is 1, and the value of test control signal TCA1 is 1), the output enable terminal of test unit 313 is disabled (i.e., the value of pipeline control signal SPE1 is 1, and the value of test control signal TCB1 is 0), and the first control terminal of routing unit 315 is disabled (i.e., the value of selection signal SS1 is 0), and the second control terminal of routing unit 315 is enabled (i.e., the value of pipeline control signal SPE1 is 1), test unit 311 receives output data provided by the data input terminal of test unit 313 from the respective data output terminals, and outputs output data from input / output pin 317. In this way, the aforementioned operation can operate chip 310 in high-impedance mode and chip 320 in test mode, so as to perform signal output testing of the testability design of chip 320 through the data signal transmission path 302 in the test circuit.

[0032]

[0033] Table 2

[0034]

[0035]

[0036] Table 3

[0037] Please refer to Tables 4 to 6 below for the signal values ​​of the test circuit applied to the test chip 330.

[0038] Taking the input / output pin 317 as the test source, and the die-to-die traces between pads 318 and 327 and between pads 328 and 337 as the test target, and the test operation unit 336 of chip 330 as the test target, when the output enable terminal of test unit 311 is disabled (i.e., the value of main control signal MA1 is 1 and the value of test control signal TCA1 is 0), the output enable terminal of test unit 313 is enabled (i.e., the value of pipe control signal SPE1 is 1 and the value of test control signal TCB1 is 1), and the first control terminal of routing unit 315 is disabled (i.e., the value of selection signal SS1 is 0) and the second control terminal of routing unit 315 is enabled (i.e., the value of pipe control signal SPE1 is 1), test unit 311 receives input data from input / output pin 317 and outputs input data from the data input terminal of test unit 311 to the data output terminal of test unit 313. Furthermore, the data input terminal of test unit 313 provides input data to pad 318, so as to provide input data to test unit 321 through pad 318, die-to-die routing, and pad 327. Next, when the output enable terminal of test unit 321 is disabled (i.e., the value of selection signal SS2 is 1 and the value of test control signal TCA2 is 0), the output enable terminal of test unit 323 is enabled (i.e., the value of pipeline control signal SPE2 is 1 and the value of test control signal TCB1 is 1), and the first control terminal of routing unit 325 is enabled (i.e., the value of selection signal SS2 is 1) and the second control terminal of routing unit 325 is enabled (i.e., the value of pipeline control signal SPE2 is 1), test unit 321 receives input data from pad 327 and die-to-die routing, and outputs input data from the data input terminal of the second test unit to the data output terminal of test unit 323. Furthermore, the data input terminal of test unit 323 provides input data to pad 328, so as to provide input data to test unit 331 through pad 328, die-to-die routing, and pad 337. Next, when the output enable terminal of test unit 331 is disabled (i.e., the value of selection signal SS3 is 1 and the value of test control (D2D PAD test OEcontrol) signal TCA3 is 0), and the first control terminal of routing unit 335 is enabled (i.e., the value of selection signal SS3 is 1) and the second control terminal of routing unit 335 is disabled (i.e., the value of pipeline control signal SPE3 is 0), test unit 331 receives input data from die-to-die routing and outputs input data from the data input terminal of test unit 331 to test operation unit 336. In this way, the aforementioned operation can operate chips 310 and 320 in high-impedance mode and chip 330 in test mode, so as to perform signal input test of the testability design of chip 330 through the data signal transmission path 303 in the test circuit.

[0039] Taking the test processing unit 336 of chip 330 as the test source, and the die-to-die traces between pads 318 and 327 and between pads 328 and 337 as the test target, and the input / output pin 317 as an example. When the output enable terminal of test unit 331 is enabled (i.e., the value of selection signal SS3 is 1 and the value of test control signal TCA3 is 1), and the first control terminal of routing unit 335 is enabled (i.e., the value of selection signal SS3 is 1), test unit 331 receives the output data provided by test processing unit 336 from the respective data output terminals, and outputs the output data from pad 337, multiple die-to-die traces, and pad 338 to test unit 323. Next, when the output enable terminal of test unit 321 is enabled (i.e., the value of selection signal SS2 is 1 and the value of test control signal TCA2 is 1), the output enable terminal of test unit 323 is disabled (i.e., the value of pipeline control signal SPE2 is 1 and the value of test control signal TCB1 is 0), and the first control terminal of routing unit 325 is enabled (i.e., the value of selection signal SS2 is 1) and the second control terminal of routing unit 325 is enabled (i.e., the value of pipeline control signal SPE2 is 1), test unit 321 receives the output data provided by the data input terminal of test unit 323 from the data output terminal, and outputs the output data from pad 327, multiple die-to-die traces and pad 318 to test unit 313. Next, when the output enable terminal of test unit 311 is enabled (i.e., the value of main control signal MA1 is 1, and the value of test control signal TCA1 is 1), the output enable terminal of test unit 313 is disabled (i.e., the value of pipeline control signal SPE1 is 1, and the value of test control signal TCB1 is 0), and the first control terminal of routing unit 315 is disabled (i.e., the value of selection signal SS1 is 0), and the second control terminal of routing unit 315 is enabled (i.e., the value of pipeline control signal SPE1 is 1), test unit 311 receives the output data provided by the data input terminal of test unit 313 from the data output terminal, and outputs the output data from the input / output pin 317. In this way, the aforementioned operation can operate chips 310 and 320 in high-impedance mode and chip 330 in test mode, so as to perform signal output testing of the testability design of chip 330 through the data signal transmission path 303 in the test circuit.

[0040]

[0041] Table 4

[0042]

[0043] Table 5

[0044]

[0045]

[0046] Table 6

[0047] Therefore, the multi-chip system 300 package can effectively realize the design testability function of individual chips 310 to 330 by switching the above signals.

[0048] Figure 4 This is a schematic diagram of a multi-chip system according to another embodiment of the present invention. (See reference) Figure 4 , Figure 4 Multi-chip system 400 Figure 1 An exemplary implementation architecture of a multi-chip system 100. The multi-chip system 400 includes a first chip 410 and a second chip 420 (i.e., Figure 1 Chips 110_1 and 110_2). In this embodiment, a first chip 410 and at least one second chip 420 are disposed on a circuit layer 430, wherein the circuit layer 430 may be a silicon interposer. For example, the first chip 410 and (at least one) second chip 420 may be disposed side by side on the circuit layer 430. The circuit layer 430 is disposed on a substrate 440. The select pin of the first chip 410 may be disposed on the circuit layer 430 by solder balls 414, and multiple input / output pins of the first chip 410 may be disposed on the circuit layer 430 by solder balls 415_1 to 415_N. The select pin of the second chip 420 may be disposed on the circuit layer 430 by solder balls 426, and multiple input / output pins of the second chip 420 may be disposed on the circuit layer 430 by multiple die-to-die traces. Figure 4(Not shown) is connected to the first chip 410. The second chip 420 can also be disposed on the circuit layer 430 via multiple other solder balls (not shown in the figure for simplicity). Solder balls 414 and 426 can be connected to solder balls 434 and 435 on the other side of the circuit layer 430 via traces 431 and 432 disposed in the circuit layer 430 (or, for example, vias and through silicon vias). Solder balls 415_1 to 415_N can be connected to solder balls 436_1 to 436_N on the other side of the circuit layer 430 via traces 433_1 to 433_N disposed in the circuit layer 430 (or, for example, vias and through silicon vias). The circuit layer 430 can be disposed on the substrate 440 via solder balls 434, 435, and 436_1 to 436_N. Solder balls 434, 435, 436_1 to 436_N can be connected to solder balls 444, 445, 446_1 to 446_N on the other side of substrate 440 via traces 441, 442, 443_1 to 443_N provided in substrate 440 (or, for example, vias and through-silicon vias). Solder balls 444, 445, 446_1 to 446_N can be connected to other circuit boards, other external traces, or other external circuits.

[0049] For example, solder balls 414, 415_1 to 415_N and 426 can be microbumps (μbumps) formed by connecting upper and lower micro copper pillars and solder (e.g., solder). Solder balls 434, 435 and 436_1 to 436_N can be formed using controlled collapse chip connection (C4) process technology, and solder balls 444, 445 and 446_1 to 446_N can be formed using ball grid array (BGA) process technology.

[0050] In the above embodiments, the number of solder balls 434, 435, 436_1 to 436_N (or solder balls 444, 445, 446_1 to 446_N) is equal to the sum of the number of chips (including the first chip 410 and at least one second chip 420) in the chip system 400 and the number of multiple input / output pins of the first chip 410.

[0051] Similarly, in other embodiments of the present invention, the multi-chip system 400 may further include a plurality of second chips (i.e., Figure 1The chips 110_3 to 110_M in the system are connected in the same way as described above for the wiring configuration and connection method between the first chip 410 and the second chip 420 (connected by die-to-die wiring). Therefore, compared with the case where no shared wiring is used, the multi-chip system 400 of the present invention can effectively save the number of solder balls (and can effectively save the volume of the multi-chip system 400).

[0052] In summary, the multi-chip system and its operation method of the present invention simplify circuit complexity through multiple die-to-die wiring connections between chips, and further reduce the number of chip pins and solder balls, thereby effectively saving chip system size or increasing chip density. Therefore, the multi-chip system of the present invention can integrate more chips and provides excellent design-testable functionality.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-chip system, characterized in that, include: The first chip, located on the circuit layer, includes: The first selection pin receives the first selection signal. A first test circuit is coupled to the first selection pin; and Multiple first input / output pins; and At least one second chip is disposed on the circuit layer, each second chip comprising: The second selection pin receives the second selection signal; and The second test circuit is coupled to the second selection pin and includes multiple second test units; The plurality of first input / output pins are coupled to the plurality of second test units of each second chip via a plurality of die-to-die traces; The first test circuit further includes: Multiple first test units are respectively corresponding to the multiple first input / output pins, and each first test unit includes an output enable terminal, a data output terminal, and a data input terminal; A plurality of first AND gate units, wherein the first input terminal of the plurality of first AND gate units receives a main control signal, the second input terminal of the plurality of first AND gate units receives a first test control signal, and the output terminals of the plurality of first AND gate units are respectively coupled to the output enable terminal of the plurality of first test units; A plurality of first routing units, wherein the first output terminals of the plurality of first routing units are respectively coupled to the data output terminals of the plurality of first test units, the first input terminals of the plurality of first routing units are respectively coupled to the data input terminals of the plurality of first test units, the first control terminals of the plurality of first routing units receive the first selection signal, and the second control terminals of the plurality of first routing units receive the first slave control signal; The plurality of first test units correspond to the plurality of first test units respectively. Each of the plurality of first test units includes an output enable terminal, a data output terminal, and a data input terminal. The data output terminal of the plurality of first test units is coupled to the second output terminal of the plurality of first routing units respectively. The data input terminal of the plurality of first test units is coupled to the second input terminal of the plurality of first routing units respectively. Each of the plurality of first test units is coupled to one of the plurality of die-to-die traces. A plurality of first AND gate units, wherein the first input terminal of the plurality of first AND gate units receives the first slave control signal, the second input terminal of the plurality of first AND gate units receives another first test control signal, and the output terminals of the plurality of first AND gate units are respectively coupled to the output enable terminals of the plurality of first test units; and At least one first test operation unit is coupled to the bidirectional data transmission end of the plurality of first routing units respectively.

2. The multi-chip system according to claim 1, characterized in that, When the output enable terminals of the plurality of first test units are disabled, the output enable terminals of the other plurality of first test units are disabled, and the first control terminals of the plurality of first routing units are enabled and the second control terminals of the plurality of first routing units are disabled, the plurality of first test units receive first input data from the plurality of first input / output pins and output the first input data from the data input terminals of the plurality of first test units to the at least one first test operation unit.

3. The multi-chip system according to claim 1, characterized in that, When the output enable terminals of the plurality of first test units are enabled, the output enable terminals of the other plurality of first test units are disabled, and the first control terminals of the plurality of first routing units are enabled and the second control terminals of the plurality of first routing units are disabled, the plurality of first test units receive first output data provided by the at least one first test operation unit from the data output terminal, and output the first output data from the plurality of first input / output pins.

4. The multi-chip system according to claim 1, characterized in that, When the output enable terminals of the plurality of first test units are disabled, the output enable terminals of the other plurality of first test units are enabled, and the first control terminals of the plurality of first routing units are disabled and the second control terminals of the plurality of first routing units are enabled, the plurality of first test units receive second input data from the plurality of first input / output pins, and output the second input data from the data input terminals of the plurality of first test units to the data output terminals of the other plurality of first test units.

5. The multi-chip system according to claim 1, characterized in that, When the output enable terminals of the plurality of first test units are enabled, the output enable terminals of the other plurality of first test units are disabled, and the first control terminals of the plurality of first routing units are disabled and the second control terminals of the plurality of first routing units are enabled, the plurality of first test units receive second output data provided by the data input terminals of the other plurality of first test units from the data output terminals of the plurality of first test units, and output the second output data from the plurality of first input / output pins.

6. The multi-chip system according to claim 1, characterized in that, The second test circuit also includes: Multiple second test units are respectively corresponding to the other multiple first test units. Each second test unit includes an output enable terminal, a data output terminal, and a data input terminal. Each second test unit is coupled to one of the multiple die-to-die traces. A plurality of second AND gate units, wherein the first input terminal of the plurality of second AND gate units receives the second selection signal, the second input terminal of the plurality of second AND gate units receives the second test control signal, and the output terminals of the plurality of second AND gate units are respectively coupled to the output enable terminal of the plurality of second test units; A plurality of second routing units, wherein the first input terminals of the plurality of second routing units are respectively coupled to the data input terminals of the plurality of second test units, the first output terminals of the plurality of second routing units are respectively coupled to the data output terminals of the plurality of second test units, the first control terminals of the plurality of second routing units receive the second selection signal, and the second control terminals of the plurality of second routing units receive the second slave control signal; A plurality of second test units are provided, each corresponding to one of the plurality of second test units. Each of the plurality of second test units includes an output enable terminal, a data output terminal, and a data input terminal. The data input terminals of the plurality of second test units are respectively coupled to the second input terminals of the plurality of second routing units, and the data output terminals of the plurality of second test units are respectively coupled to the second output terminals of the plurality of second routing units. Each of the plurality of second test units is coupled to one of the plurality of die-to-die traces. A plurality of second AND gate units, wherein the first input terminal of the plurality of second AND gate units receives the second slave control signal, the second input terminal of the plurality of second AND gate units receives another second test control signal, and the output terminals of the plurality of second AND gate units are respectively coupled to the output enable terminals of the plurality of second test units; and At least one second test operation unit is coupled to the bidirectional data transmission end of the plurality of second routing units.

7. The multi-chip system according to claim 6, characterized in that, When the output enable terminals of the plurality of second test units are disabled, the output enable terminals of the other plurality of second test units are disabled, and the first control terminal of the plurality of second routing units is enabled and the second control terminal of the plurality of second routing units is disabled, the plurality of second test units receive second input data from the plurality of die-to-die traces and output the second input data from the data input terminals of the plurality of second test units to the at least one second test operation unit.

8. The multi-chip system according to claim 6, characterized in that, When the output enable terminals of the plurality of second test units are enabled, and the output enable terminals of the plurality of other second test units are disabled, and the first control terminal of the plurality of second routing units is enabled, and the second control terminal of the plurality of second routing units is disabled, the plurality of second test units receive second output data provided by the at least one second test operation unit from the data output terminal of the plurality of second test units, and output the second output data from the plurality of die-to-die traces.

9. The multi-chip system according to claim 6, characterized in that, When the output enable terminals of the plurality of second test units are disabled, the output enable terminals of the other plurality of second test units are enabled, and the first control terminal of the plurality of second routing units is enabled, and the second control terminal of the plurality of second routing units is enabled, the plurality of second test units receive another second input data from the plurality of die-to-die traces, and output the other second input data from the data input terminal of the plurality of second test units to the data output terminal of the other plurality of second test units.

10. The multi-chip system according to claim 6, characterized in that, When the output enable terminals of the plurality of second test units are enabled, the output enable terminals of the other plurality of second test units are disabled, and the first control terminal of the plurality of second routing units is enabled, and the second control terminal of the plurality of second routing units is enabled, the plurality of second test units receive another second output data provided by the data input terminals of the other plurality of second test units from the data output terminals of the plurality of second test units, and output the other second output data from the plurality of die-to-die traces.

11. The multi-chip system according to claim 1, characterized in that, The first chip and the at least one second chip are arranged side by side on the circuit layer.

12. A method for operating a multi-chip system, characterized in that, The multi-chip system includes a first chip and at least one second chip. The first chip includes a first selection pin, a first test circuit, and multiple first input / output pins. The first test circuit is coupled to the first selection pin. Each second chip includes a second selection pin and a second test circuit, which is coupled to the second selection pin. The second test circuit includes multiple second test units. The first chip and the at least one second chip are disposed on a line layer. The multiple first input / output pins are coupled to the multiple second test units of each second chip via multiple die-to-die traces. The first test circuit further includes: multiple first test units, each corresponding to one of the multiple first input / output pins; each first test unit includes an output enable terminal, a data output terminal, and a data input terminal; multiple first AND gate units, wherein the first input terminals of the multiple first AND gate units receive a main control signal, the second input terminals of the multiple first AND gate units receive a first test control signal, and the output terminals of the multiple first AND gate units are respectively coupled to the output enable terminals of the multiple first test units; and multiple first routing units, wherein the first output terminals of the multiple first routing units are respectively coupled to the data output terminals of the multiple first test units. A plurality of first routing units have their first input terminals respectively coupled to the data input terminals of the plurality of first test units. The first control terminals of the plurality of first routing units receive the first selection signal, and the second control terminals of the plurality of first routing units receive a first slave control signal. A plurality of other first test units, corresponding to the plurality of first test units, each of the plurality of other first test units includes an output enable terminal, a data output terminal, and a data input terminal. The data output terminals of the plurality of other first test units are respectively coupled to the second output terminals of the plurality of first routing units. The input terminals are respectively coupled to the second input terminals of the plurality of first routing units, wherein each of the plurality of first test units is coupled to one of the plurality of die-to-die traces; a plurality of first AND gate units, wherein the first input terminals of the plurality of first AND gate units receive the first slave control signal, the second input terminals of the plurality of first AND gate units receive another first test control signal, and the output terminals of the plurality of first AND gate units are respectively coupled to the output enable terminals of the plurality of first test units; and at least one first test operation unit is respectively coupled to the bidirectional data transmission terminals of the plurality of first routing units; The operation method includes: The first selection signal is received through the first selection pin, and the second selection signal is received through the second selection pin; When the first chip operates in test mode according to the first selection signal, it acquires first input data of the first chip or sends first output data of the first chip through the plurality of first input / output pins; and When the first chip operates in high-impedance mode according to the first selection signal, it obtains the second input data of one of the at least one second chips under test or sends the second output data of the second chip under test through the plurality of first input / output pins.

Images