FPGA-based emulation of RTL designs

Abstract

A system and method for FPGA-based emulation for verification of an RTL design. A first part of an FPGA is configured to realize user logic according to user RTL received by a network, and a second part of the FPGA is configured to realize control and interface logic that enables remote control and interaction with the user logic. The first portion of the FPGA may further realize emulated off-chip components and interfaces to real off-chip components to provide a realistic environment for the user logic. The second portion of the FPGA may further realize logic-analyzer logic for probing internal signals of the user logic and for capturing and storing signal traces. Memory elements that are coupled to the user logic are expunged at the end of an emulation session prevent data leaks between sessions.

Description

FPGA-BASED EMULATION OF RTL DESIGNSFIELD

[0001] This disclosure generally relates to emulation of designs for microchips, and more specifically, to emulation by field-programmable gate arrays (FPGAs) of register-transfer level (RTL) designs.BRIEF DESCRIPTION OF THE DRAWINGS

[0002] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to-scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity.

[0003] FIG. l is a block diagram of an example of a remote RTL emulation system.

[0004] FIG. 2 is a block diagram of an example internal configuration of a computing device of a remote RTL emulation system.

[0005] FIG. 3 is a block diagram of an example internal configuration of an RTL emulation system.

[0006] FIG. 4 is a block diagram of an example internal configuration of an FPGA of an RTL emulation system.

[0007] FIG. 5 is a flowchart of an example of a technique for remote RTL emulation.

[0008] FIG. 6 is a flowchart of an example of a technique for sequential multitenant remoteRTL emulation.

[0009] FIG. 7 is a flowchart of an example of a technique for expunging data between sessions for multitenant remote RTL emulation.DETAILED DESCRIPTION

[0010] Designing and manufacturing semiconductor electronic devices involves many steps and processes. Tape-out is a process where final design files for an integrated circuit (IC) or microchip are transferred to a physical medium, e.g., as a set of photomasks for patterningtransistors and interconnects onto a semiconductor wafer. To avoid costly re-spins (i.e., repeated tape-outs) of the design, it is important to thoroughly verify correct functionality of the design prior to tape-out to identify, for example, design flaws, timing violations, logic errors, and so on.

[0011] Traditional verification for digital designs utilizes an event-driven computer-based simulation of the design. However, even with parallel processing and powerful multicore and multi-threaded computers, event-driven simulation can be slow compared to the operating speed of the microchip that will eventually realize the design. Consequently, fully verifying all aspects or functionality of a design by event-driven simulation is impractical, if not impossible, for most system-on-chip (SoC) and application-specific integrated circuit (ASIC) designs. As a result, event-driven simulation of only certain edge cases or critical portions of the design is usually performed.

[0012] An FPGA is a configurable microchip that can be configured to realize arbitrary digital designs. FPGAs have been used to speed up design verification by enabling designs to be emulated by hardware, rather than simulated by software, at a speed that can match or approximately match the operating speed of the microchip that will eventually realize the design. This may be referred to as real-time hardware emulation, FPGA-based emulation, or simply emulation of RTL designs.

[0013] For hardware emulation, a design to be verified is mapped to specific circuit elements of an FPGA, for example, combinational logic elements, sequential logic elements, IP blocks, macro blocks, interconnects, and so on. The FPGA (or a portion thereof) is programmed, or configured, with the mapped design, and then the FPGA (or a portion thereof) is placed in an operational mode to execute the design. The FPGA has input / output (I / O) pins for receiving input signals from various electronic devices and for transmitting output signals to various electronic devices. Input signals may include control signals or data signals that exercise various functionalities of the design, and output signals may include data signals, response signals, or probed signals that can indicate whether the design functions as expected.

[0014] There are several issues that have prevented wider adoption of FPGA-based emulation for verification of digital designs. First, FPGA-emulation usually requires specialized laboratory equipment — such as oscilloscopes, logic analyzers, and test-pattern generators — to provide input signals to the FPGA and to observe output signals from the FPGA. Such equipment can be expensive to own or lease and difficult to operate effectively. Second, aspects of FPGAsthat include hardware architectures, performance capabilities, and programming tools can vary widely between FPGA vendors, FPGA platforms, FPGA array sizes, and so on. Specialized knowledge is often required to select and effectively utilize an FPGA to realize an RTL design. Moreover, complex test logic and interface logic may need to be custom-developed and realized by the FPGA to adequately verify the design. The time required for such development can be excessive with respect to time-to-market requirements of the microchip being designed and manufactured.

[0015] There are some services that offer a more streamlined process for FPGA-based emulation of digital designs, such as various cloud-based services and design-consulting services. Limitations of such services can include: requiring limited brands and platforms of FPGAs and / or development tools; requiring custom development of complex test logic and interface logic; providing limited observability of internal signals within a design during runtime; lack of realistic FPGA operating environments that includes interfacing the FPGA with various off-chip components; lack of support for emulation of various off-chip components; inability to interact with the emulated design in real time; and so on. The embodiments disclosed herein address many issues of FPGA-based emulation including one or more of the aforementioned issues.

[0016] The embodiments disclosed herein provide for simplified and streamlined FPGA- emulation of RTL designs that can be carried out over a network, such that the FPGA and its supporting components and laboratory equipment can be programmed and operated remotely. In some embodiments, FPGA-agnostic design processes are provided to decouple one or more of design verification processes, synthesis, and implementation from FPGA-specific primitives. In some embodiments, custom logic-analyzer logic is automatically generated and / or implemented in the FPGA to simplify design verification. In some embodiments, logic that emulates off-chip components are automatically generated and / or implemented in the FPGA to enable a more realistic operating environment for the design.

[0017] To describe some implementations in greater detail, reference is first made to examples of hardware and software structures that can be used to implement the FPGA-based emulation of RTL designs disclosed herein.

[0018] FIG. 1 is a block diagram of an example of a remote RTL emulation system 100, which can include or be a part of an FPGA-based emulation system. A client device 104, such asa computer or workstation, communicates with an RTL emulation system 112 via a network 108. The network may be, for example, a local-area network (LAN) or a wide-area network (WAN), such as one or more of a wireless or a wired network.

[0019] FIG. 2 is a block diagram of an example internal configuration of a computing device 200 of a remote RTL emulation system, such as the remote RTL emulation system 100 of FIG. 1. In some embodiments, the computing device 200 may implement the client device of FIG. 1, or a portion thereof. In some embodiments, the computing device 200 may implement the RTL emulation system 112 of FIG. 1, or a portion thereof. The computing device 200 includes components or units, such as a processor 202, a memory 204, a bus 206, a power source 208, peripherals 210, a user interface 212, a network interface 214, other suitable components, or a combination thereof. One or more of the memory 204, the power source 208, the peripherals 210, the user interface 212, or the network interface 214 can communicate with the processor 202 via the bus 206.

[0020] The processor 202 is a central processing unit, such as a microprocessor, and can include single or multiple processors having single or multiple processing cores. Alternatively, the processor 202 can include another type of device, or multiple devices, configured for manipulating or processing information. As an example, the processor 202 can include multiple processors interconnected in one or more manners, including hardwired or networked. As another example, the processor 202 can include hardware-configurable devices such as an FPGA, a complex programmable logic device (CPLD), an erasable programmable logic device (EPLD), a programmable logic array (PLA), a programmable array logic (PAL), a generic array logic (GAL), and so on. The operations of the processor 202 can be distributed across multiple devices or units that can be coupled directly or across a local area or other suitable type of network. The processor 202 can include a cache, or cache memory, for local storage of operating data or instructions.

[0021] The memory 204 includes one or more memory components, which may each be volatile memory or non-volatile memory. For example, the volatile memory can be RAM (e.g., a DRAM module, such as DDR SDRAM). In another example, the non-volatile memory of the memory 204 can be a disk drive, a solid-state drive, flash memory, or phase-change memory. In some embodiments, the memory 204 can be distributed across multiple devices. For example, the memory 204 can include network-based memory or memory in multiple clients or serversperforming the operations of those multiple devices.

[0022] The memory 204 can include data for immediate access by the processor 202. For example, the memory 204 can include executable instructions 216, application data 218, and an operating system 220. The executable instructions 216 can include one or more application programs, which can be loaded or copied, in whole or in part, from non-volatile memory to volatile memory to be executed by the processor 202. For example, the executable instructions 216 can include instructions for performing some or all of the techniques of this disclosure. The application data 218 can include user data, database data (e.g., database catalogs or dictionaries), or the like. In some embodiments, the application data 218 can include functional programs, such as a web browser, a web server, a database server, another program, or a combination thereof. The operating system 220 can be, for example, Microsoft Windows®, Mac OS X®, or Linux®; an operating system for a mobile device, such as a smartphone or tablet device; or an operating system for a non-mobile device, such as a mainframe computer.

[0023] The power source 208 provides power to the computing device 200. For example, the power source 208 can be an interface to an external power distribution system. In another example, the power source 208 can be a battery, such as where the computing device 200 is a mobile device or is otherwise configured to operate independently of an external power distribution system. In some embodiments, the computing device 200 may include or otherwise use multiple power sources. In some such embodiments, the power source 208 can be a backup battery.

[0024] The peripherals 210 includes one or more sensors, detectors, or other devices configured for monitoring the computing device 200 or the environment around the computing device 200. For example, the peripherals 210 can include a geolocation component, such as a global positioning system location unit. In another example, the peripherals can include a temperature sensor for measuring temperatures of components of the computing device 200, such as the processor 202. In some embodiments, the computing device 200 can omit the peripherals 210.

[0025] The user interface 212 includes one or more input interfaces and / or output interfaces. An input interface may, for example, be a positional input device, such as a mouse, touchpad, touchscreen, or the like; a keyboard; or another suitable human or machine interface device. An output interface may, for example, be a display, such as a liquid crystal display, a cathode-raytube, a light emitting diode display, or other suitable display.

[0026] The network interface 214 provides a connection or link to a network (e.g., the network 108 of FIG. 1). The network interface 214 can be a wired network interface or a wireless network interface. The computing device 200 can communicate with other devices via a network interface 214 using one or more network protocols, such as using Ethernet, transmission control protocol (TCP), internet protocol (IP), power line communication, an IEEE 802. X protocol (e.g., Wi-Fi, Bluetooth, or ZigBee), infrared, visible light, general packet radio service (GPRS), global system for mobile communications (GSM), code-division multiple access (CDMA), Z-Wave, another protocol, or a combination thereof.

[0027] FIG. 3 is a block diagram of an example system 300 of an RTL emulation system 304 of a remote RTL emulation system, such as the remote RTL emulation system 100 of FIG. 1. The RTL emulation system 304 comprises a host 308 (e.g., a host device) and an FPGA board 312. The host 308 may be implemented, for example, as the computing device 200 of FIG. 2. The FPGA board 312 may comprise a printed circuit board (PCB) on which one or more components are mounted. In some embodiments, the host 308 may be implemented on the FPGA board 312. The host 308 includes a network interface 324, such as the network interface 214 of FIG. 2, for interfacing with a network, such as the network 108 of FIG. 1. The host 308 includes local interface 328, such as a bus interface and / or a bus, for example the bus 206 of FIG. 2, for interfacing with the FPGA board 312 and / or components thereon. In some embodiments, the local interface 328 is implemented by a high-speed serial interface link, such as a peripheral component interconnect express (PCIe) link.

[0028] The FPGA board 312 includes one or more FPGAs 316 and one or more external integrated circuits (ICs) 320. The FPGA 316 and the external ICs 320 can communicate via one or more channels 332. The channels 332 may comprise point-to-point links, shared buses, a switched router network, and so on, and may utilize suitable transmission media, such as wired, wireless, and optical media. The FPGA 316 may instead be, include, or cooperate with a CPLD, an EPLD, an PLA, a PAL, a GAL, and / or other suitable configurable devices. The external ICs 320 may be or include: (1) ICs that support configuration or other operations of the FPGA 316; and (2) ICs that support or otherwise interact with logic designs realized by the FPGA 316, for example, Flash memory, dynamic random-access memory (DRAM), sensors, processors, and so on.

[0029] FIG. 4 is a block diagram of an example system 400 that comprises an FPGA 404 for use in a remote RTL emulation system, such as the remote RTL emulation system 100 of FIG. 1. The FPGA 404 may be, for example, the FPGA 316 of FIG. 3. The FPGA may be partitioned into multiple parts, segments, or regions, such as a static region 408 and a dynamic region 412, which can be independently configured, for example, via partial reconfiguration capabilities of the FPGA 404. As explained more fully later herein, during a session of remote RTL emulation, the static region 408 is or has been configured with various control logic and interface logic and the dynamic region 412 is or has been configured with user logic 444 and various peripheral logic that will be discussed later herein. Included in the control logic and interface logic of the static region 408 is a bus controller 420 for enabling communication to a host 499, such as the host 308 of FIG. 3, via a channel 416, such as the local interface 328 of FIG. 3. More specifically, the bus controller 420 enables simplex, half duplex, and / or full duplex communication between the host 499 and various logic blocks realized in the static region 408 and the dynamic region 412. The host 499 is, in turn, communicatively coupled to a client device (not shown in FIG. 4), such as the client device 104 of FIG 1, via a network (not shown in FIG. 4), such as the network 108 of FIG. 1, such that the client device can send information to the FPGA 404 via the host 499, and the client device can receive information from the FPGA 404 via the host 499. Such information may include, for example, commands, instructions, raw data, formatted or compressed data, and so on.

[0030] During a session of remote RTL emulation, the static region 408 comprises hardware resource elements that realize control logic and interface logic, where control logic and interface logic may be logic that utilizes some or all of the same hardware resources of the FPGA 404. The static region 408 realizes logic blocks that are accessible to the host using various address spaces. For example, a first address space, e.g., base address register 0 (BAR0), may be reserved primarily for FPGA management functions; a second address space, e.g., BARI, may be reserved primarily for user-accessible ports to the user logic 444; and a third address space, e.g., BAR2, may be reserved primarily for peripheral logic for controlling and / or observing the user logic 444 components or modules coupled thereto. Examples of logic blocks for each of the address spaces are described briefly below.

[0031] The first address space, reserved primarily for the host 499 to access FPGA management functions, includes a board management controller (BMC) interface 428, aconfiguration port 432 (which may also be referred to as a reconfiguration port), and a multitenancy manager 436. The BMC interface 428 communicates with various monitoring and sensor components 490 peripheral to the FPGA404 via a channel 476, such as temperature sensors, power sensors, and so on. The configuration port 432 receives configuration bitstreams for reconfiguring the various parts, segments, or regions, of the FPGA, for example the dynamic region 412. The multitenancy manger 436 performs inter-session management, e.g., expunging of user data between sessions and / or reconfigurations of the dynamic region, which will be explained in more detail later herein.

[0032] The second address space, reserved primarily for the host 499 to access the user logic 444, includes interfaces 424 that may realize various user-facing protocol controllers, such as a reset port 424a, a general-purpose input / output (GPIO) port 424b, a universal asynchronous receiver and transmitter (UART) port 424c, and a Joint Test Access Group (JTAG) port 424d. Various control-status registers (CSRs) may be mapped to this second address space and therefore accessible by the host 499 thereby. The various ports and / or protocol controllers of the interfaces 424 enable a remote client device, such as the client device 104 of FIG. 1, to issue I / O tasks directly to the user design realized by the user logic 444. In some embodiments, the I / O tasks may comprise hypertext transfer protocol (HTTP) requests. In some embodiments, the reset port 424a may comprise an active-low RESETN port to affect a global reset of the user logic 444; the GPIO port may comprise a 32-bit data and / or address bus (GPIO[31:0]); the UART port 424c may comprise UART_RX and UART_TX ports; and the JTAG port 424d may comprise TCK, TDI, TDO, TMS, and TRST ports. The various ports and / or protocol controllers of the interfaces 424 may be capable of issuing interrupts to the host 499 for various notifications, such as when the user logic 444 provides certain output signals. In some embodiments, an on-chip debugger, for example OpenOCD, can be attached to the JTAG port for exporting a debugging session, for example a GNU debugger GDB session.

[0033] The third address space, reserved primarily for the host 499 to interact with logic analyzer controller 460 that may be realized in the static region 408. The logic analyzer controller 460 is coupled to a logic analyzer 456 and / or the trace processor 464, which may be realized in the dynamic region 412. The logic analyzer controller 460 may provide control signals to the logic analyzer 456 and / or the trace processor 464 based on information the logic analyzer controller 460 receives from the host 499 via the bus controller 420. The logic analyzer456 may add pipeline registers to reduce place-and-route difficulty during bitstream implementation and it may add certain modules to perform signal alignment and arrangement into contiguous buses that can be provided to the trace processor 464 for compact packing (e.g., formatting, compressing, compacting, and so on) of trace data and for triggering of events. The trace processor 464 may interface with one or more memories, such as an internal memory 468 and / or an external memory 497, for storing of trace data. In some embodiments, the internal memory 468 and / or the external memory 497 may comprise a high-bandwidth memory (HBM). The trace processor 464 may interface with a high-speed (PHY) interface 472 for transmitting trace data off-chip via a channel 484 to one or more board ICs 498, such as various memories and / or processors. In some embodiments, the logic analyzer 456, the trace processor 464, the internal memory 468, and the PHY interface 472 (circumscribed by a dash-dot rectangle in FIG. 4) may be realized as high-speed logic that operates at a higher frequency than the other logic realized in the dynamic region 412, for example, the user logic 444. The higher operating frequency of the high-speed logic enables super-sampling of signals on various nodes of the user logic 444. In some embodiments, the user logic 444 operates at a frequency of F and the highspeed logic operates at a frequency of F*N, where N > 1, and typically N is an integer. For example, the user logic 444 may operate at F=100 MHz and the high-speed logic may operate at F*N = 100 MHz * 3 = 300 MHz, allowing the high-speed logic to capture up to three samples per clock period of the 100 MHz user logic 444.

[0034] The user logic 444 is clocked by one or more clock signals provided by clock logic 440 that is realized in the static region 408. The clock logic 440 may comprise one or more phase-locked loops (PLLs), delay-locked loops (DLLs), ring oscillators, phase shifters, and so on. In some embodiments, the clock logic 440 can provide a plurality of frequencies, and in some such embodiments, some of the plurality of frequencies are integer multiples of each other.

[0035] Depending on the requirements of the user design, the dynamic region 412 may also include emulated off-chip IC logic 448 that emulates certain ICs for use by the user logic 444. For example, the emulated off-chip IC logic 448 may emulate a sensor IC or a small DRAM or Flash IC. The size and scope of the external ICs that can be fully emulated by the emulated off- chip IC logic 448 depends in part on the size and type of FPGA 404 used for the remote RTL emulation session. For external ICs that are too large or complex to be fully emulated by the emulated off-chip IC logic 448, an off-chip IC controller and PHY interface 452 can be realizedin the static region 408 that serves as an interface between the user logic 444 and one or more off-chip ICs 494 (e.g., ICs external to the FPGA404) via a channel 480, such as large DRAM or Flash memory, a complex sensor, a microprocessor, and so on. In such case, the emulated off- chip IC logic 448 and / or the off-chip IC controller and PHY interface 452 can provide an interface to the user logic 444 that emulates the interface of an off-chip component. For example, a sensor IC could be emulated by an off-chip memory IC that stores a look-up table for providing simulated data according to a given distribution. The emulated off-chip IC logic 448 and / or the off-chip IC controller and PHY interface 452 could emulate an interface for the user logic 444 that behaves like a specified sensor IC so that the actual look-up table emulation of the sensor IC is invisible to the user logic 444.

[0036] In some embodiments, the host 499 may provide a library of external ICs that can be selected for utilization by the user design realized by the FPGA 404, such as by the emulated off- chip IC logic 448 (e.g., fully emulated) and / or by the off-chip IC controller and PHY interface 452 (e.g., an interface to an off-chip IC 494 that may be mounted on a same printed circuit board (PCB) as the FPGA 404). The library may be stored in a memory, such as the memory 204 of FIG. 2 and / or in a cloud storage device.

[0037] Referring again FIG. 1, the RTL emulation system 112 is configured to provide one or more emulation sessions in sequence or simultaneously. The RTL emulation system 112 may receive session requests from one or more client devices 104, and the RTL emulation system 112 may schedule sessions according to a suitable scheduling or arbitration mechanism depending on, for example, how many FPGAs are available for emulation, priorities of the various requests, subscription levels of the various requestors, and so on. For secure sequential multitenancy of an FPGA (e.g., using the same FPGA for different clients), it is important to expunge, scrub, delete, overwrite, or otherwise destroy data stored in data storage elements after one session ends and another session begins (collectively referred to herein as “expunging” data) to prevent possible leakage of sensitive, proprietary, or confidential data between sessions. Data storage elements that require expunging may include external memory, such as off-chip IC 494, board IC 498, and external memory 497 of FIG. 4; on-chip memories, such as SRAM and / or internal memory 468 of FIG. 4; and sequential storage elements, such as D flip-flops. Expunging processes for each of these data storage elements are discussed later herein.

[0038] To further describe some embodiments in greater detail, reference is next made to anexample of techniques 500, 600, and 700 that may be performed by or using one or more components of a system for remote FPGA-based RTL emulation. FIGS. 5, 6, and 7 are respective flowcharts of examples of techniques for remote RTL emulation.

[0039] The techniques 500, 600, and 700 can be executed using computing devices, such as the systems, hardware, and software described or referenced with respect to FIGS. 1-4. The techniques 500, 600, and 700 can be performed, for example, by executing a machine-readable program or other computer-executable instructions, such as routines, instructions, programs, or other code. The steps, or operations, of the techniques 500, 600, and 700, or another technique, method, process, or algorithm described in connection with the embodiments disclosed herein can be implemented directly in hardware, firmware, software executed by hardware, circuitry, or a combination thereof.

[0040] For simplicity of explanation, the techniques 500, 600, and 700 are depicted and described herein as a series of steps or operations. However, the steps or operations of the techniques 500, 600, and 700 in accordance with this disclosure can occur in various orders and / or concurrently. Additionally, other steps or operations not presented and described herein may be used. Furthermore, not all illustrated steps or operations may be required to implement a technique in accordance with the disclosed subject matter. The techniques 500, 600, and 700 may be performed by one or more components of a remote RTL emulation system, which may include the client device 104, the network 108, and the RTL emulation system 112 of FIG. 1.

[0041] Referring to FIG. 5, the step 502 comprises configuring a second part of the FPGAto realize control logic and interface logic. The second part of the FPGA may be the static region 408 of FIG. 4. The control logic and interface logic may comprise one or more of the bus controller 420, the BMC interface 428, the configuration port 432, the multitenancy manager 436, the interfaces 424, the logic analyzer controller 460, the internal memory 468, the PHY interface 472, the off-chip IC controller and PHY interface 452, and the clock logic 440 of FIG.4. In some embodiments, an RTL emulation system, such as the RTL emulation system 112 of FIG. 1, performs the configuration of the second part of the FPGA.

[0042] The step 504 comprises configuring a first part of an FPGAto realize first user logic based on first user RTL received from a first client device by a network. The client device may be the client device 104 of FIG 1; the network may be the network 108 of FIG. 1; the first user RTL may be received by the RTL emulation system 304 of FIG. 3, which includes the host 308;the first user logic may be the user logic 444 of FIG. 4; and the first part of the FPGA may be the dynamic region 412 of FIG. 4. In some embodiments, an RTL emulation system, such as the RTL emulation system 112 of FIG. 1, performs the configuration of the first part of the FPGA. Independent configuration of the first part of the FPGA and the second part of the FPGA may be achieved via partial reconfiguration features of the FPGA.

[0043] The first user RTL may describe a user design that is a digital design, such as a design of an ASIC, an application-specific standard product, (ASSP), a processor, and so on. The first user RTL may comprise hardware description language (HDL) instructions, such as Verilog or VHDL instructions. In some embodiments, the first user RTL may comprise functional implementations and / or structural implementations from which a gate-level netlist may be synthesized. In some embodiments, an initial FPGA-agnostic synthesizability check is performed on the first user RTL. In some embodiments, the first user RTL may include generic pragmas to perform an FPGA-agnostic synthesis mapping to generate the first user logic. In some embodiments, the first user RTL may include vendor-specific pragmas, in which case the first user RTL may be transpiled to perform an FPGA-specific synthesis mapping to generate the first user logic. Transpilation is similar to compilation because both involve transforming source code, but compilation may transform source code into an immutable binary while transpilation may transform source code into other valid source code in either the same language or another language. In some embodiments, an RTL emulation system, such as the RTL emulation system 112 of FIG. 1, selects the FPGA, such as a particular platform, family, and / or size thereof, based on at least one of a quantity of primitive logic elements in a netlist synthesized from the first user RTL and / or a performance requirement of the netlist.

[0044] In some embodiments, the first part of the FPGA may be further configured to realize microchip-emulation logic based on an indication of a microchip received from the first client device by the network. The microchip-emulation logic may be, for example, the emulated off- chip IC logic 448 of FIG. 4. The microchip-emulation logic may comprise logic that fully emulates an external microchip, such as a DRAM or Flash memory, a microprocessor, a sensor, and so on. In some embodiments, the indication may comprise an instantiation of a microchip component in the user RTL. In some embodiments, the indication may comprise an automated selection or a manual (e.g., user) selection from a library of external microchip components capable of being fully emulated within the first part of the FPGA. An automated selection maycomprise a computer-based analysis of the user RTL, e g., according to an artificial intelligence (Al) model; a manual selection may comprise user selection from a pull-down menu in a graphical user interface (GUI) that may be displayed, for example, by a graphical display of a client device. The microchip-emulation logic is communicatively coupled to the first user logic such that the first user logic can perform transactions with the mi crochip -emulation logic (e.g., read requests, write requests, execution requests, and so on).

[0045] In some embodiments, the indication of a microchip received from the first client by the network may indicate a microchip component that may be too large or complex to be fully emulated within the FPGA, and more specifically, within the first part of the FPGA. Is such case, the indication may indicate a physical microchip that is communicatively coupled to the FPGA, where the first user logic can perform transactions with the external microchip via external microchip interface logic, such as the off-chip IC controller and PHY interface 452 of FIG. 4, that is realized in the FPGA, and more specifically, within a second part of the FPGA, such as the static region 408 of FIG. 4. The external microchip may include DRAM or Flash memory, a microprocessor, a sensor, and so on.

[0046] In some embodiments, the RTL emulation system can determine whether the indication of a microchip will result in emulated-microchip logic or external microchip interface logic based on a size of the user logic 444, a size and / or complexity of the indicated microchip, performance capabilities of the FPGA, and so on.

[0047] In some embodiments, the first user RTL may include annotations indicating signals (e g., nodes) of the design to be made available for probing by a logic analyzer, such as the logic analyzer 456 of FIG. 4. In some embodiments, the annotations are provided in the first user RTL as received via the network, and in some embodiments, the first user RTL is annotated after being received, where a host device, such as the host 308 of FIG. 3, may perform some or all of the annotation. In some embodiments, certain default nodes of the first user RTL are annotated, for example, based on fan-in or fan-out properties. In some embodiments, certain nodes of the first user RTL are annotated based on a computer-based analysis of the first user RTL, for example, according to an Al model. When probe annotations are present in the first user RTL, and accordingly, the first user logic includes nodes to be probed the first part of the FPGA is further configured with logic-analyzer logic, such as the logic analyzer 456 of FIG. 4, and traceprocessor logic, such as the trace processor 464 of FIG. 4. The logic analyzer logic may performlogic analysis functions of probed signals of the first user logic, and the trace-processor logic may perform formatting, preprocessing, compressing, or compacting operations on data collected by the logic-analyzer logic.

[0048] In some embodiments, the trace-processor logic realized in the first part of the FPGA can store trace data to an on-chip trace memory realized in the second part of the FPGA, for example the internal memory 468 of FIG. 4, and / or to an off-chip trace memory, such as the external memory 497 of FIG. 4. In some embodiments, the trace-processor logic realized in the first part of the FPGA can transmit trace data off-chip via a PHY interface, such as the PHY interface 472 of FIG. 4. The logic-analyzer logic and the trace-processor logic may receive control signals from logic analyzer controller logic, such as the logic analyzer controller 460 of FIG. 4. The logic analyzer control logic is configured to receive commands or instructions from the client device via the network.

[0049] In some embodiments, the logic-analyzer logic, the trace-processor logic, the trace memory, and the PHY interface operate at a higher clock frequency than the user logic, which operates at a lower clock frequency. In some embodiments, the higher clock frequency is an integer multiple of the lower clock frequency.

[0050] The step 506 comprises conveying first information between the first client device and the first user logic using the network and at least one of the control logic and the interface logic. In some embodiments, the information comprises commands, instructions, control signals, data, test patterns, and so on. In some embodiments, a host device, such as the host 308 of FIG. 3, serves as an intermediary between the client device and the first user logic.

[0051] The step 508 comprises reconfiguring the first part of the FPGA to realize expunging logic. The expunging logic expunges data that is stored in data storage elements that were accessible or otherwise exposed to the first user logic either directly or indirectly. In some embodiments, an RTL emulation platform, such as the RTL emulation system 112 of FIG. 1, performs the reconfiguration of the first part of the FPGA.

[0052] The step 510 comprises causing the expunging logic to expunge first user data stored in a first user memory realized by or coupled to the first user logic. In some embodiments, the first user memory comprises at least one of: a memory or sequential storage element within the first part of the FPGA; a memory or sequential storage element within the second part of the FPGA; or a memory or sequential storage element external to the FPGA.

[0053] After the step 510, the FPGA may be made available for another remote FPGA emulation session, with may comprise configuring the first part of the FPGA to realize second user logic based on second user RTL received from a second client device by the network.

[0054] FIG. 6 is a flowchart of an example of a technique for sequential multitenant remote RTL emulation. The step 602 comprises configuring a second part of an FPGA with control logic and interface logic. The FPGA may be the FPGA 404 of FIG. 4; the second part may be the static region 408 of FIG. 4; and the control logic and interface logic may comprise one or more of the bus controller 420, the BMC interface 428, the configuration port 432, the multitenancy manager 436, the interfaces 424, the logic analyzer controller 460, the internal memory 468, the PHY interface 472, the off-chip IC controller and PHY interface 452, and the clock logic 440 of FIG. 4.

[0055] The step 604 comprises starting an emulation session. In some embodiments, a session may begin when the FPGA (and supporting hardware and software resources) is available for user use, for example, for receiving user RTL, for configuring the FPGA with user logic, for conveying data or information between a client device and the user logic, and so on.

[0056] The step 606 comprises configuring a first part of the FPGA with user logic and associated peripheral logic. The user logic may be the user logic 444 of FIG. 4 and the peripheral logic may include the emulated off-chip IC logic 448, the logic analyzer 456, and the trace processor 464 of FIG. 4.

[0057] The step 608 comprises conveying information between a client device and the user logic. The client device may be the client device 104 of FIG. 1, which may send information to, or receive information from, the user logic via a network, such as the network 108 of FIG. 1.

[0058] The step 610 comprises ending first emulation session. In some embodiments, a session may end when the FPGA (and supporting hardware and software resources) is no longer available for user use, for example, for receiving user RTL, for configuring the FPGA with user logic, for conveying data or information between a client device and the user logic, and so on.

[0059] The step 612 comprises configuring the first part of the FPGA with expunging logic. The expunging logic is described in more detail with reference to FIG. 7 below.

[0060] The step 614 comprises expunging data from memories accessible or exposed to the user logic. Data storage elements that require expunging may include external memory, such as off-chip IC 494, Board IC 498, and external memory 497 of FIG. 4; on-chip memories, such asSRAM and / or internal memory 468; and sequential storage elements, such as D flip-flops.

[0061] FIG. 7 is a flowchart of an example of a technique 700 for expunging data between sessions for multitenant remote RTL emulation. Expunging of data between sessions of an FPGA may comprise sequentially reconfiguring a first part of the FPGA, for example the dynamic region 412 of FIG. 4, with the different data-expunging paradigms. For example, following termination of an emulation session, the first part of the FPGA may be reconfigured with a first expunging logic to expunge all off-chip memories that were accessible to or otherwise exposed to the user logic, then the first part of the FPGA may be reconfigured with a second expunging logic to expunge all on-chip memories that were realized in the dynamic region, and finally, the first part of the FPGA may be reconfigured with a third expunging logic to expunge all sequential storage elements within the dynamic region.

[0062] The step 702 comprises configuring a first part of an FPGA with first expunging logic for off-chip memories. External, or off-chip, memories include memories that were accessible to or otherwise exposed to user logic, such as the user logic 444 of FIG. 4, either directly or indirectly (e.g., via the off-chip IC controller and PHY interface 452 or the PHY interface 472 of FIG. 4). Off-chip memories, such as those accessible via the off-chip IC controller and PHY interface 452, may store, for example, proprietary user data, information, images, applications, and so on. Off-chip memories, such as the external memory 497 and those accessible via the PHY interface 472, may store, for example, trace data that includes information about nodes in the user logic 444 that were probed.

[0063] The step 704 comprises expunging off-chip memories using the first expunging logic. In some embodiments, the expunging logic is adapted to realize a pseudorandom number generator that fills the external memories with pseudorandom data (other data patterns may also be used, such as all-zeros, all-ones, march-C, and so on). Further, the expunging logic is adapted to read back written pseudorandom data to ensure that both input and output queues, or buffers, of the external memories and any emulated interfaces thereto, are flushed from any user data. In some embodiments, the first expunging logic will report progress or completion to a multitenancy manager, such as the multitenancy manager 436 of FIG. 4, realized in a second part of the FPGA, such as the static region 408 of FIG. 4. In some embodiments, the multitenancy manager may report progress or completion to a host device, such as the host 499 of FIG. 4.

[0064] The step 706 comprises configuring the first part of the FPGA with second expunginglogic for on-chip memories. On-chip memories, such as internal memory 468, may include SRAM, which may be a row-based memory where data is written to or read from the memory one or several rows at a time.

[0065] The step 708 comprises expunging on-chip memories using the second expunging logic. In some embodiments, the expunging logic is adapted to realize a finite state machine (FSM) for each on-chip memory in the dynamic region of the FPGAthat will systematically clear and read back every word in the memory, for example, by cycling through each addressable memory location. Each FSM may implement a pseudorandom number generator that fills the external memories with pseudorandom data (other data patterns may also be used, such as allzeros, all-ones, march-C, and so on). In some embodiments, the second expunging logic will report progress or completion to a multitenancy manager, such as the multitenancy manager 436 of FIG. 4, realized in a second part of the FPGA, such as the static region 408 of FIG. 4. In some embodiments, the multitenancy manager may report progress or completion to a host device, such as the host 499 of FIG. 4.

[0066] The step 710 comprises configuring the first part of the FPGA with third expunging logic for sequential storage elements. The sequential storage elements may include, for example, flip-flops, latches, and registers. D flip-flops are commonly associated with combinational circuit elements in an FPGA.

[0067] The step 712 comprises expunging sequential storage elements using the third expunging logic. In some embodiments, the third the expunging logic is adapted to realize one or more shift registers that incorporate the sequential storage elements in the first part of the FPGA, such as the dynamic region 412 of FIG. 4, and to shift pseudo-random data through each shift register (other data patterns may also be used, such as all-zeros, all-ones, march-C, and so on). In some embodiments, the third expunging logic will report progress or completion to a multitenancy manager, such as the multitenancy manager 436 of FIG. 4, realized in a second part of the FPGA, such as the static region 408 of FIG. 4. In some embodiments, the multitenancy manager may report progress or completion to a host device, such as the host 499 of FIG. 4.

[0068] Some embodiments of remote FPGA-based emulation of RTL designs disclosed herein include a method, comprising: configuring a second part of an FPGA to realize control logic and interface logic; configuring a first part of the FPGA to realize first user logic based on first user RTL received from a first client device by a network; conveying first informationbetween the first client device and the first user logic using the network and at least one of the control logic and the interface logic; reconfiguring the first part of the FPGA to realize expunging logic; and causing the expunging logic to expunge first user data stored in a first user memory realized in or coupled to the first user logic.

[0069] In some embodiments, the method further comprises: configuring the first part of the FPGA to realize microchip-emulation logic based on a first indication of a microchip received from the first client device by the network; and causing at least one of the control logic or the interface logic to convey second information between the first user logic and the microchipemulation logic.

[0070] In some embodiments, the method further comprises: receiving a first indication of a microchip from the first client device by the network; and causing at least one of the control logic or the interface logic to convey second information between the first user logic and a microchip communicatively coupled to the FPGA.

[0071] In some embodiments, the method further comprises: configuring the first part of the FPGA to realize the first user logic that includes a probe annotation of a node; configuring the second part of the FPGA to realize logic-analyzer logic; and causing the logic-analyzer logic to store a logic value of the node in a trace memory that is realized in the FPGA, external to the FPGA, or both.

[0072] In some embodiments, the method further comprises, after causing the expunging logic to expunge the first user data: configuring the first part of the FPGA to realize second user logic based on second user RTL received from a second client device by the network.

[0073] In some embodiments, the first user memory comprises at least one of: a memory or sequential storage element within the first part of the FPGA; a memory or sequential storage element within the second part of the FPGA; or a memory or sequential storage element external to the FPGA.

[0074] In some embodiments, the control logic comprises at least one of: peripheral component interconnect (PCI) logic; board management controller (BMC) logic; reconfiguration logic; multitenancy logic; port logic; interface logic; or logic-analyzer logic.

[0075] In some embodiments, the control logic comprises port logic that comprises at least one of: a reset port; a general-purpose input-output (GPIO) port; a universal asynchronous receiver and transmitter (UART) port; a Joint Test Access Group (JTAG) port; or a clock port.

[0076] In some embodiments, the first indication of the microchip indicates at least one of a memory microchip; a sensor microchip; a processor microchip; or a transceiver microchip.

[0077] In some embodiments, the method further comprises: receiving the first user RTL from the first client device by a local area network (LAN) or a wide area network (WAN).

[0078] In some embodiments, the method further comprises at least one of receiving the first indication as an instantiation in the user RTL; or receiving the first indication as a user selection from a library.

[0079] In some embodiments, the method further comprises at least one of: mapping a non FPGA-specific component instantiated in the first user RTL to an FPGA-specific RTL component; or mapping a first FPGA-specific RTL component instantiated in the first user RTL to a second FPGA-specific RTL component.

[0080] In some embodiments, the method further comprises at least one of: synthesizing a first user netlist based on at least the first user RTL; or selecting the FPGA based on at least one of a quantity of primitive logic elements in the first user netlist or a performance requirement of the first user netlist.

[0081] In some embodiments, the method further comprises at least one of: receiving the user RTL comprising the probe annotation; annotating the user RTL with the probe annotation based on received user input; or annotating the user RTL with the probe annotation based on an automated analysis of the user RTL.

[0082] Some embodiments of remote FPGA-based emulation of RTL designs disclosed herein include a non-transitory computer-readable medium storing instructions operable to cause one or more processors to perform operations comprising: configuring a second part of an FPGA to realize control logic and interface logic; configuring a first part of the FPGA to realize first user logic based on first user RTL received from a first client device by a network; conveying first information between the first client device and the first user logic using the network and at least one of the control logic and the interface logic; reconfiguring the first part of the FPGA to realize expunging logic; and causing the expunging logic to expunge first user data stored in a first user memory realized in the first user logic, coupled to the first user logic, or both.

[0083] In some embodiments, the operations further comprise: receiving a first indication of a microchip from the first client device by the network; in response to determining that resources within the FPGA are sufficient to realize an emulation of the microchip: configuring the first partof the FPGA to realize microchip-emulation logic based on the first indication, and causing at least one of the control logic or the interface logic to convey second information between the first user logic and the microchip-emulation logic; and in response to determining that resources within the FPGA are not sufficient to realize an emulation of the microchip: causing at least one of the control logic or the interface logic to convey second information between the first user logic and a microchip communicatively coupled to the FPGA.

[0084] In some embodiments, the operations further comprise: configuring the first part of the FPGA to realize the first user logic that includes a probe annotation of a node; configuring the second part of the FPGA to realize logic-analyzer logic; and causing the logic-analyzer logic to store a logic value of the node in a trace memory that is realized in the FPGA, external to the FPGA, or both.

[0085] Some embodiments of remote FPGA-based emulation of RTL designs disclosed herein include a system, comprising: one or more memories; and one or more processors configured to execute instructions stored in the one or more memories to: configure a second part of an FPGA to realize control logic and interface logic; configure a first part of the FPGA to realize first user logic based on first user RTL received from a first client device by a network; convey first information between the first client device and the first user logic using the network and at least one of the control logic and the interface logic; reconfigure the first part of the FPGA to realize expunging logic; and cause the expunging logic to expunge first user data stored in a first user memory realized in the first user logic, coupled to the first user logic, or both.

[0086] In some embodiments, the one or more processors are configured to execute the instructions to: receive a first indication of a microchip from the first client device by the network; in response to determining that resources within the FPGA are sufficient to realize an emulation of the microchip: configure the first part of the FPGA to realize microchip-emulation logic based on the first indication, and cause at least one of the control logic or the interface logic to convey second information between the first user logic and the microchip-emulation logic; and in response to determining that resources within the FPGA are not sufficient to realize an emulation of the microchip: cause at least one of the control logic or the interface logic to convey second information between the first user logic and a microchip communicatively coupled to the FPGA.

[0087] In some embodiments, the one or more processors are configured to execute theinstructions to: configure the first part of the FPGA to realize the first user logic that includes a probe annotation of a node; configure the second part of the FPGA to realize logic-analyzer logic; and cause the logic-analyzer logic to store a logic value of the node in a trace memory that is realized in the FPGA, external to the FPGA, or both.

[0088] While the disclosure has been described in connection with certain implementations, it is to be understood that the disclosure is not to be limited to the disclosed implementations but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures as is permitted under the law.

Claims

What is claimed is:

1. A method, comprising: configuring a second part of an FPGA to realize control logic and interface logic; configuring a first part of the FPGA to realize first user logic based on first user RTL received from a first client device by a network; conveying first information between the first client device and the first user logic using the network and at least one of the control logic and the interface logic; reconfiguring the first part of the FPGA to realize expunging logic; and causing the expunging logic to expunge first user data stored in a first user memory realized in or coupled to the first user logic.

2. The method of claim 1, further comprising: configuring the first part of the FPGA to realize microchip-emulation logic based on a first indication of a microchip received from the first client device by the network; and causing at least one of the control logic or the interface logic to convey second information between the first user logic and the microchip-emulation logic.

3. The method of any one of claims 1 or 2, further comprising: receiving a first indication of a microchip from the first client device by the network; and causing at least one of the control logic or the interface logic to convey second information between the first user logic and a microchip communicatively coupled to the FPGA.

4. The method of any one of claims 1 through 3, further comprising: configuring the first part of the FPGA to realize the first user logic that includes a probe annotation of a node; configuring the second part of the FPGA to realize logic-analyzer logic; and causing the logic-analyzer logic to store a logic value of the node in a trace memory that is realized in the FPGA, external to the FPGA, or both.

5. The method of any one of claims 1 through 4, comprising, after causing the expunging logic toexpunge the first user data: configuring the first part of the FPGA to realize second user logic based on second user RTL received from a second client device by the network.

6. The method of claim 1, wherein the first user memory comprises at least one of: a memory or sequential storage element within the first part of the FPGA; a memory or sequential storage element within the second part of the FPGA; or a memory or sequential storage element external to the FPGA.

7. The method of claim 1, wherein the control logic comprises at least one of: peripheral component interconnect (PCI) logic; board management controller (BMC) logic; reconfiguration logic; multitenancy logic; port logic; interface logic; or logic-analyzer logic.

8. The method of claim 1, wherein the control logic comprises port logic that comprises at least one of: a reset port; a general-purpose input-output (GPIO) port; a universal asynchronous receiver and transmitter (UART) port; a Joint Test Access Group (JTAG) port; or a clock port.

9. The method of claim 2, wherein the first indication of the microchip indicates at least one of: a memory microchip; a sensor microchip; a processor microchip; or a transceiver microchip.

10. The method of any one of claims 1 through 9, further comprising: receiving the first user RTL from the first client device by a local area network (LAN) or a wide area network (WAN).

11. The method of claim 3, further comprising at least one of: receiving the first indication as an instantiation in the first user RTL; or receiving the first indication as a user selection from a library.

12. The method of claim 1, further comprising at least one of: mapping a non FPGA-specific component instantiated in the first user RTL to an FPGA- specific RTL component; or mapping a first FPGA-specific RTL component instantiated in the first user RTL to a second FPGA-specific RTL component.

13. The method of claim 1, further comprising at least one of: synthesizing a first user netlist based on at least the first user RTL; or selecting the FPGA based on at least one of a quantity of primitive logic elements in the first user netlist or a performance requirement of the first user netlist.

14. The method of claim 4, further comprising at least one of: receiving the first user RTL comprising the probe annotation; annotating the first user RTL with the probe annotation based on received user input; or annotating the first user RTL with the probe annotation based on an automated analysis of the first user RTL.

15. A non-transitory computer-readable medium storing instructions operable to cause one or more processors to perform operations comprising: configuring a second part of an FPGA to realize control logic and interface logic; configuring a first part of the FPGA to realize first user logic based on first user RTL received from a first client device by a network;conveying first information between the first client device and the first user logic using the network and at least one of the control logic and the interface logic; reconfiguring the first part of the FPGA to realize expunging logic; and causing the expunging logic to expunge first user data stored in a first user memory realized in the first user logic, coupled to the first user logic, or both.

16. The non-transitory computer-readable medium of claim 15, the operations further comprising: receiving a first indication of a microchip from the first client device by the network; in response to determining that resources within the FPGA are sufficient to realize an emulation of the microchip: configuring the first part of the FPGA to realize microchip-emulation logic based on the first indication, and causing at least one of the control logic or the interface logic to convey second information between the first user logic and the microchip-emulation logic; and in response to determining that resources within the FPGA are not sufficient to realize an emulation of the microchip: causing at least one of the control logic or the interface logic to convey second information between the first user logic and a microchip communicatively coupled to the FPGA.

17. The non-transitory computer-readable medium of claim 15, the operations further comprising: configuring the first part of the FPGA to realize the first user logic that includes a probe annotation of a node; configuring the second part of the FPGA to realize logic-analyzer logic; and causing the logic-analyzer logic to store a logic value of the node in a trace memory that is realized in the FPGA, external to the FPGA, or both.

18. A system, comprising: one or more memories; andone or more processors configured to execute instructions stored in the one or more memories to: configure a second part of an FPGA to realize control logic and interface logic; configure a first part of the FPGA to realize first user logic based on first user RTL received from a first client device by a network; convey first information between the first client device and the first user logic using the network and at least one of the control logic and the interface logic; reconfigure the first part of the FPGA to realize expunging logic; and cause the expunging logic to expunge first user data stored in a first user memory realized in the first user logic, coupled to the first user logic, or both.

19. The system of claim 18, wherein the one or more processors are configured to execute the instructions to: receive a first indication of a microchip from the first client device by the network; in response to determining that resources within the FPGA are sufficient to realize an emulation of the microchip: configure the first part of the FPGA to realize microchip-emulation logic based on the first indication, and cause at least one of the control logic or the interface logic to convey second information between the first user logic and the microchip-emulation logic; and in response to determining that resources within the FPGA are not sufficient to realize an emulation of the microchip: cause at least one of the control logic or the interface logic to convey second information between the first user logic and a microchip communicatively coupled to the FPGA.

20. The system of claim 18, wherein the one or more processors are configured to execute the instructions to: configure the first part of the FPGA to realize the first user logic that includes a probe annotation of a node; configure the second part of the FPGA to realize logic-analyzer logic; andcause the logic-analyzer logic to store a logic value of the node in a trace memory that is realized in the FPGA, external to the FPGA, or both.

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