Display panel and display device

Abstract

The present invention relates to the technical field of display, and provides a display panel and a display device. The display panel comprises: a substrate, a plurality of light-emitting units, and a plurality of pixel driving circuits, wherein the orthographic projections of the plurality of pixel driving circuits on the substrate are arranged in an array in row and column directions, the plurality of pixel driving circuits form a plurality of pixel driving circuit row groups, and each pixel driving circuit row group comprises two adjacent rows of pixel driving circuits. The pixel driving circuits comprise driving transistors, wherein the driving transistors are used for providing a driving current to the light-emitting units on the basis of a gate-source voltage difference of the driving transistors; the driving transistors comprise channel regions, and the orthographic projections of the channel regions of the driving transistors on the substrate are bent and extend in the row direction to form protrusions in the column direction; in two pixel driving circuits that are located in the same pixel driving circuit row group and in the same column, the protrusion directions of the orthographic projections of the channel regions of the driving transistors on the substrate are opposite; and in the same row of pixel driving circuits, the protrusion directions of the orthographic projections of the channel regions of the driving transistors in at least some different pixel driving circuits are opposite. The display panel can mitigate the problem of horizontal stripes of the display panel.

Description

Display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, the driving transistors in different rows of pixel driving circuits have different characteristics, which can cause horizontal stripes to appear on the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0004] Summary of the Invention

[0005] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0006] Substrate;

[0007] Multiple light-emitting units;

[0008] Multiple pixel driving circuits, the orthogonal projections of the multiple pixel driving circuits on the substrate are arranged in an array along the row and column direction, the multiple pixel driving circuits form multiple pixel driving circuit row groups, the pixel driving circuit row group includes two adjacent rows of pixel driving circuits.

[0009] The pixel driving circuit includes a driving transistor for providing a driving current to the light-emitting unit according to its gate-source voltage difference. The driving transistor includes a channel region, and the orthogonal projection of the channel region of the driving transistor on the substrate is bent and extended along the row direction to form a protrusion in the column direction.

[0010] In two pixel driving circuits located in the same row group and in the same column, the channel regions of the driving transistors on the substrate have opposite convex directions of their orthogonal projections.

[0011] In the same row of pixel driving circuits, the convex directions of the channel regions of the driving transistors in at least some different pixel driving circuits on the substrate are opposite.

[0012] In one exemplary embodiment of this disclosure, the pixel driving circuit row group includes a plurality of repeating units distributed in the row direction, and the repeating unit includes two rows and multiple columns of the pixel driving circuit;

[0013] In the same row of pixel driving circuits of the same repeating unit, the convex directions of the channel regions of the driving transistors in at least some of the pixel driving circuits on the substrate are opposite.

[0014] In one exemplary embodiment of this disclosure, the display panel includes light-emitting units of multiple colors, and the channel regions of the driving transistors connected to at least one light-emitting unit of the same color have the same convex direction as the orthogonal projection on the substrate.

[0015] In one exemplary embodiment of this disclosure, the display panel includes light-emitting units of multiple colors. In the same repeating unit, the convex directions of the channel regions of the driving transistors connected to at least one light-emitting unit of the same color on the substrate are opposite.

[0016] In one exemplary embodiment of this disclosure, the number of driving transistors with opposite convex directions of the orthographic projection of the channel region onto the substrate is the same in the same repeating unit.

[0017] In one exemplary embodiment of this disclosure, in the same row of pixel driving circuits, the convex directions of the channel regions of the driving transistors in any two adjacent pixel driving circuits on the substrate are opposite.

[0018] In one exemplary embodiment of this disclosure, the same row of pixel driving circuits forms multiple pixel driving circuit groups distributed in the row direction, and the pixel driving circuit group includes n adjacent pixel driving circuits.

[0019] The channel regions of the driving transistors located in the same pixel driving circuit group have the same convex direction when projected onto the substrate.

[0020] The convex directions of the channel regions of the driving transistors located in the adjacent two pixel driving circuit groups on the substrate are opposite.

[0021] n is a positive integer greater than or equal to 2.

[0022] In one exemplary embodiment of this disclosure, the display panel further includes:

[0023] An electrode layer is located on one side of the substrate, and the electrode layer includes a plurality of electrode portions, which are used to form the first electrode of the light-emitting unit;

[0024] The plurality of electrode portions include: a plurality of first electrode portions, a plurality of second electrode portions, and a plurality of third electrode portions;

[0025] In the multiple electrode sections connected to the same row of pixel driving circuits, the first electrode section, the second electrode section, the third electrode section, and the second electrode section are alternately distributed in the row direction by their orthogonal projections on the substrate.

[0026] In two adjacent columns of pixel driving circuits, a plurality of first electrode portions and a plurality of third electrode portions are connected to the same column of pixel driving circuits, and the orthographic projections of the first electrode portions and third electrode portions connected to the same column of pixel driving circuits on the substrate are alternately distributed in the column direction, and a plurality of second electrode portions are connected to another column of pixel driving circuits.

[0027] In one exemplary embodiment of this disclosure, the pixel driving circuit row group includes a plurality of repeating units distributed in the row direction, and each repeating unit includes two rows and m columns of the pixel driving circuit;

[0028] In the same row of pixel driving circuits of the same repeating unit, the convex directions of the channel regions of the driving transistors in at least some of the pixel driving circuits on the substrate are opposite.

[0029] m is an integer multiple of 4.

[0030] In one exemplary embodiment of this disclosure, the orthographic projections of two pixel driving circuits located in the same column of the pixel driving circuit row group on the substrate are at least partially mirror-symmetrically arranged along a first axis of symmetry, which extends along the row direction.

[0031] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a plurality of transistors. In two pixel driving circuits located in the same row group and in the same column, the channel regions of the same type of transistor are mirror-symmetrically arranged along the first axis of symmetry when projected onto the substrate.

[0032] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a seventh transistor, the first electrode of which is connected to a second initial signal line, and the second electrode of which is connected to the first electrode of the light-emitting unit;

[0033] The display panel also includes:

[0034] An active layer is located on one side of the substrate. The active layer includes a seventh active portion and a twelfth active portion. The seventh active portion is used to form the channel region of the seventh transistor. In two pixel driving circuits located in the same row group and in the same column of the same pixel driving circuit, the two seventh active portions are connected through the twelfth active portion.

[0035] The second initial signal line extends along the row direction in the orthogonal projection of the second initial signal line on the substrate, and the second initial signal line is connected to the twelfth active part through a via.

[0036] In one exemplary embodiment of this disclosure, the display panel further includes:

[0037] A first gate layer is located on the side of the active layer opposite to the substrate. The first gate layer includes a second reset signal line. The orthographic projection of the second reset signal line on the substrate extends in the row direction, and a portion of the structure of the second reset signal line is used to form the gate of the seventh transistor.

[0038] Furthermore, within the same pixel driving circuit row group, the orthographic projection of the second initial signal line on the substrate is located between the orthographic projections of the two second reset signal lines on the substrate.

[0039] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes an eighth transistor, the first terminal of which is connected to a third initial signal line, and the second terminal of which is connected to the first terminal of the driving transistor;

[0040] The display panel also includes:

[0041] An active layer is located on one side of the substrate. The active layer includes an eighth active portion and a tenth active portion. The eighth active portion is used to form the channel region of the eighth transistor. In two pixel driving circuits located in the same row group and in the same column, the two eighth active portions are connected through the tenth active portion.

[0042] The third initial signal line extends along the row direction in the orthogonal projection of the third initial signal line on the substrate, and the third initial signal line is connected to the tenth active part through a via.

[0043] In one exemplary embodiment of this disclosure, the display panel further includes:

[0044] A first gate layer is located on the side of the active layer opposite to the substrate. The first gate layer includes a second reset signal line. The orthographic projection of the second reset signal line on the substrate extends in the row direction, and a portion of the structure of the second reset signal line is used to form the gate of the seventh transistor.

[0045] In the same row of pixel driving circuits, the orthographic projection of the third initial signal line on the substrate is located between the orthographic projections of the two second reset signal lines on the substrate.

[0046] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, wherein a first terminal of the first transistor is connected to a first initial signal line and a second terminal is connected to the gate of the driving transistor;

[0047] The display panel also includes:

[0048] An active layer includes a first active portion and a first initial signal line. The first active portion is used to form the channel region of the first transistor. The first initial signal line extends along the row direction and is connected to the first active portion by its orthogonal projection on the substrate.

[0049] In one exemplary embodiment of this disclosure, the orthographic projections of two adjacent pixel driving circuits located in the same row on the substrate are at least partially mirror-symmetrically arranged along a second axis of symmetry, which extends along the column direction.

[0050] In one exemplary embodiment of this disclosure, the display panel further includes:

[0051] A data line, which provides data signals to a pixel driving circuit, extends along a column direction.

[0052] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0053] The first transistor has a first terminal connected to a first initial signal line and a second terminal connected to the gate of the driving transistor.

[0054] The second transistor has a first terminal connected to the gate of the driving transistor and a second terminal connected to the second terminal of the driving transistor;

[0055] The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor.

[0056] The fifth transistor has its first terminal connected to the power supply line and its second terminal connected to the first terminal of the driving transistor.

[0057] The sixth transistor has its first electrode connected to the second electrode of the driving transistor, and the second electrode connected to the first electrode of the light-emitting unit.

[0058] The seventh transistor has its first electrode connected to the second initial signal line and its second electrode connected to the first electrode of the light-emitting unit.

[0059] The eighth transistor has its first terminal connected to the third initial signal line and its second terminal connected to the first terminal of the driving transistor.

[0060] The capacitor has its first electrode connected to the gate of the driving transistor and its second electrode connected to the power supply line.

[0061] In an exemplary embodiment of this disclosure, the first transistor and the second transistor are P-type transistors;

[0062] The first transistor and the second transistor are dual-gate structures.

[0063] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0064] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0065] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0066] Figure 1 is a schematic diagram of the structure of an exemplary embodiment of the display panel of this disclosure;

[0067] Figure 2 is a structural layout of the active layer in the display panel shown in Figure 1;

[0068] Figure 3 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0069] Figure 4 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0070] Figure 5 is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0071] Figure 6 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0072] Figure 7 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0073] Figure 8 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0074] Figure 9 is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0075] Figure 10 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0076] Figure 11 is a structural layout of the shielding layer in the display panel shown in Figure 10;

[0077] Figure 12 is a structural layout of the active layer in the display panel shown in Figure 10;

[0078] Figure 13 is a structural layout of the first gate layer in the display panel shown in Figure 10;

[0079] Figure 14 is a structural layout of the second gate layer in the display panel shown in Figure 10;

[0080] Figure 15 is a structural layout of the first source / drain layer in the display panel shown in Figure 10;

[0081] Figure 16 is a structural layout of the second source / drain layer in the display panel shown in Figure 10;

[0082] Figure 17 is a structural layout of the electrode layer in the display panel shown in Figure 10;

[0083] Figure 18 is a structural layout of the shielding layer and active layer in the display panel shown in Figure 10;

[0084] Figure 19 is a structural layout of the shielding layer, active layer, and first gate layer in the display panel shown in Figure 10;

[0085] Figure 20 is a structural layout of the shielding layer, active layer, first gate layer and second gate layer in the display panel shown in Figure 10;

[0086] Figure 21 is a structural layout of the shielding layer, active layer, first gate layer, second gate layer, and first source / drain layer in the display panel shown in Figure 10;

[0087] Figure 22 is a structural layout of the shielding layer, active layer, first gate layer, second gate layer, first source / drain layer, and second source / drain layer in the display panel shown in Figure 10.

[0088] Figure 23 is a partial cross-sectional view of the display panel shown in Figure 10, cut along the dashed line CC.

[0089] Figure 24 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0090] Figure 25 is a structural layout of the active layer in the display panel shown in Figure 24;

[0091] Figure 26 is a structural layout of the first gate layer in the display panel shown in Figure 24;

[0092] Figure 27 is a structural layout of the second gate layer in the display panel shown in Figure 24;

[0093] Figure 28 is a structural layout of the first source / drain layer in the display panel shown in Figure 24;

[0094] Figure 29 is a structural layout of the second source / drain layer in the display panel shown in Figure 24;

[0095] Figure 30 is a structural layout of the electrode layer in the display panel shown in Figure 24;

[0096] Figure 31 is a structural layout of the active layer and the first gate layer in the display panel shown in Figure 24;

[0097] Figure 32 is a structural layout of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 24.

[0098] Figure 33 is a structural layout of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 24;

[0099] Figure 34 is a structural layout of the display panel shown in Figure 24, which includes an active layer, a first gate layer, a second gate layer, a first source / drain layer, and a second source / drain layer.

[0100] Figure 35 is a partial cross-sectional view of the display panel shown in Figure 24, cut along the dashed line DD.

[0101] Figure 36 is a schematic diagram of the electrode layer in another exemplary embodiment of the display panel of this disclosure;

[0102] Figure 37 is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0103] Figure 38 is a structural layout of the active layer in another exemplary embodiment of the display panel of this disclosure;

[0104] Figures 39-41 are schematic diagrams of the pixel driving circuit in another exemplary embodiment of the display panel of this disclosure. Detailed Implementation

[0105] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0106] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0107] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0108] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0109] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0110] This exemplary embodiment provides a display panel, as shown in Figures 1 and 2. Figure 1 is a structural schematic diagram of an exemplary embodiment of the display panel of this disclosure, and Figure 2 is a structural layout of the active layer in the display panel shown in Figure 1. The display panel includes: a substrate, multiple light-emitting units, and multiple pixel driving circuits Pix. The orthographic projections of the multiple pixel driving circuits Pix on the substrate are arranged in an array along the row and column directions. The multiple pixel driving circuits Pix form multiple pixel driving circuit row groups Phz, and each pixel driving circuit row group Phz includes two adjacent rows of pixel driving circuits. Each pixel driving circuit Pix includes a driving transistor, which provides a driving current to the light-emitting unit based on its gate-source voltage difference. The driving transistor includes a channel region. As shown in FIG2, a third active portion 73 in the active layer can be used to form the channel region of the driving transistor. The orthographic projection of the channel region of the driving transistor on the substrate bends and extends along the row direction X to form a protrusion in the column direction Y. The protrusion directions of the orthographic projections of the channel regions of the driving transistors in two pixel driving circuits located in the same pixel driving circuit row group and in the same column are opposite. In the same row of pixel driving circuits, the protrusion directions of the orthographic projections of the channel regions of the driving transistors on the substrate are opposite in at least some different pixel driving circuits.

[0111] In this exemplary embodiment, by performing ELA (Excimer Laser Annealing) on the amorphous silicon layer, the amorphous silicon layer can be converted into a polysilicon active layer. Since in the excimer laser annealing process, the scanning direction of the laser annealing is consistent, and at the same time, since the protruding directions of the channel regions of the driving transistors in two pixel driving circuits located in the same row group of the pixel driving circuit and in the same column with respect to the scanning direction of the laser annealing are opposite on the substrate, there are differences in the characteristics of the driving transistors with opposite protruding directions of the channel regions. For example, characteristics such as the threshold voltage and turn-on voltage of the driving transistors are different, which can easily cause horizontal stripes to appear in the display panel. In this exemplary embodiment, in the same row of pixel driving circuits, the protruding directions of the channel regions of the driving transistors in at least some different pixel driving circuits with respect to the substrate are opposite. This setting can prevent the pixel units formed by the same row of pixel driving circuits from forming complete dark / bright stripes, that is, this setting can dot the horizontal bright / dark stripe points in the display panel.

[0112] It should be noted that in this exemplary embodiment, the row direction X and the column direction Y are two intersecting directions. For example, the row direction X and the column direction Y can be perpendicular. When the display panel is in use, the row direction can be parallel to the user's interpupillary distance direction or intersect with the user's interpupillary distance direction.

[0113] As shown in FIG. 2, in this exemplary embodiment, the third active portion 73 has a "ji" - shaped structure. It should be understood that in other exemplary embodiments, the third active portion 73 can also have other structures. The protruding portion of the third active portion on the column direction Y can be one or more, and the protruding directions of the multiple protruding portions are the same.

[0114] In this exemplary embodiment, as shown in FIG. 2, in the same row of pixel driving circuits, there is one or more groups of adjacent two pixel driving circuits in which the protruding directions of the channel regions of the driving transistors with respect to the substrate are opposite. This setting can prevent an excessive number of adjacent driving transistors with the same protruding direction of the channel regions in the same row of pixel driving circuits, thereby preventing short horizontal stripes from appearing in the display panel. In this exemplary embodiment, the protruding directions of the channel regions of the driving transistors in any two adjacent pixel driving circuits with respect to the substrate are opposite.

[0115] Figure 3 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. R / (lower) represents a pixel driving circuit Pix connected to the red light-emitting unit, wherein the convex direction of the driving transistor channel region faces downwards; R / (upper) represents a pixel driving circuit Pix connected to the red light-emitting unit, wherein the convex direction of the driving transistor channel region faces upwards; G / (upper) represents a pixel driving circuit Pix connected to the green light-emitting unit, wherein the convex direction of the driving transistor channel region faces upwards; G / (lower) represents a pixel driving circuit Pix connected to the green light-emitting unit, wherein the convex direction of the driving transistor channel region faces downwards; B / (lower) represents a pixel driving circuit Pix connected to the blue light-emitting unit, wherein the convex direction of the driving transistor channel region faces downwards; B / (upper) represents a pixel driving circuit Pix connected to the blue light-emitting unit, wherein the convex direction of the driving transistor channel region faces upwards. The convex direction of the driving transistor channel region facing downwards can be understood as the convex direction of the driving transistor channel region pointing towards the next row of pixel driving circuits in the column direction Y. Specifically, the distance between the orthogonal projections of the channel regions of the upward-protruding driving transistors in the previous row of pixel driving circuits and the channel regions of the downward-protruding driving transistors in the adjacent next row of pixel driving circuits on the substrate is greater than the distance between the orthogonal projections of the channel regions of the downward-protruding driving transistors in the previous row of pixel driving circuits and the channel regions of the upward-protruding driving transistors in the adjacent next row of pixel driving circuits on the substrate.

[0116] As shown in Figure 3, among the multiple light-emitting units connected to the same row pixel driving circuit, red light-emitting units, green light-emitting units, blue light-emitting units, and green light-emitting units are alternately distributed in the row direction; in two adjacent columns of pixel driving circuits, multiple red light-emitting units and multiple blue light-emitting units are connected to the same column of pixel driving circuits, and the red light-emitting units and blue light-emitting units connected to the same column of pixel driving circuits are alternately distributed in the column direction, while multiple green light-emitting units are connected to another column of pixel driving circuits.

[0117] In this exemplary embodiment, as shown in FIG3, the pixel driving circuit row group includes a plurality of repeating units Pc distributed in the row direction. Each repeating unit Pc may include two rows and four columns of pixel driving circuits Pix. In the pixel driving circuits connected to the green light-emitting units in the same repeating unit Pc, the bulge directions of the driving transistors in the two pixel driving circuits located in the same column are opposite. The green light-emitting units connected to the two pixel driving circuits with opposite bulge directions in the channel region can complement each other in brightness, thereby further reducing the horizontal stripe problem.

[0118] It should be understood that, in other exemplary embodiments, the display panel includes light-emitting units of multiple colors. Within the same repeating unit Pc, as long as the channel regions of the driving transistors connected to the same color light-emitting units have opposite projection directions on the substrate, the light-emitting units of that color can achieve brightness complementarity, thereby further reducing the horizontal stripe problem. The types of light-emitting units of the same color with opposite projection directions of the channel regions of the driving transistors within the same repeating unit Pc can be one or more.

[0119] Furthermore, in other exemplary embodiments, the light-emitting units and pixel driving circuits may have other corresponding relationships. For example, as shown in FIG4, it is a schematic diagram of the structure of another exemplary embodiment of the display panel of this disclosure. In the pixel driving circuit above the repeating unit Pc, the protrusion direction of the driving transistor channel region connected to the red light-emitting unit is downward.

[0120] Figure 5 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. R / below represents the pixel driving circuit Pix connected to the red light-emitting unit, wherein the driving transistor channel region protrudes downward; G / above represents the pixel driving circuit Pix connected to the green light-emitting unit, wherein the driving transistor channel region protrudes upward; G / below represents the pixel driving circuit Pix connected to the green light-emitting unit, wherein the driving transistor channel region protrudes downward; B / above represents the pixel driving circuit Pix connected to the blue light-emitting unit, wherein the driving transistor channel region protrudes upward.

[0121] As shown in Figure 5, among the multiple light-emitting units connected to the same row pixel driving circuit, red light-emitting units, green light-emitting units, blue light-emitting units, and green light-emitting units are alternately distributed in the row direction; in two adjacent columns of pixel driving circuits, multiple red light-emitting units and multiple blue light-emitting units are connected to the same column of pixel driving circuits, and the red light-emitting units and blue light-emitting units connected to the same column of pixel driving circuits are alternately distributed in the column direction, while multiple green light-emitting units are connected to another column of pixel driving circuits.

[0122] As shown in Figure 5, multiple pixel driving circuit groups Px are formed in the same row and distributed in the row direction. Each pixel driving circuit group Px includes two adjacent pixel driving circuits. The convex directions of the channel regions of the driving transistors located in the same pixel driving circuit group Px on the substrate are the same. The convex directions of the channel regions of the driving transistors located in two adjacent pixel driving circuit groups Px on the substrate are opposite. It should be understood that in other exemplary embodiments, the pixel driving circuit group Px may also include other numbers of adjacent pixel driving circuits.

[0123] In this exemplary embodiment, as shown in FIG5, the protrusion direction of the driving transistor channel area in the pixel driving circuit connected to all red light-emitting units is the same; the protrusion direction of the driving transistor channel area in the pixel driving circuit connected to all blue light-emitting units is the same. This setting can facilitate data compensation for light-emitting units of the same color through data signals to avoid color shift problems in the display panel.

[0124] In this exemplary embodiment, as shown in FIG5, the pixel driving circuit row group includes a plurality of repeating units Pc distributed in the row direction. Each repeating unit Pc may include two rows and four columns of pixel driving circuits Pix. In the pixel driving circuits connected to the green light-emitting units in the same repeating unit Pc, the protrusion directions of the driving transistors in the two pixel driving circuits located in the same column are opposite. The green light-emitting units connected to the two pixel driving circuits with opposite channel region protrusion directions can complement each other in brightness, thereby further reducing the horizontal stripe problem.

[0125] Furthermore, in other exemplary embodiments, the light-emitting units and pixel driving circuits may have other corresponding relationships. For example, as shown in FIG6, which is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure, in this display panel, the correspondence between the pixel driving circuits and the light-emitting units in the upper row of the repeating unit Pc is R / up, G / up, B / down, G / down. As another example, as shown in FIG7, which is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure, in this display panel, the correspondence between the pixel driving circuits and the light-emitting units in the upper row of the repeating unit Pc is R / down, G / up, B / up, G / down. As yet another example, as shown in FIG8, which is a structural schematic diagram of another exemplary embodiment of the display panel of this disclosure, in this display panel, the correspondence between the pixel driving circuits and the light-emitting units in the upper row of the repeating unit Pc is R / up, G / down, B / down, G / up.

[0126] As shown in Figures 3-8, the repeating unit Pc includes two rows and four columns of pixel driving circuits. It should be understood that in other exemplary embodiments, each repeating unit may include two rows and m columns of pixel driving circuits, where m may be an integer multiple of 4.

[0127] In this exemplary embodiment, as long as at least some of the pixel driving circuits in the same row of the repeating unit have opposite projection directions of the channel regions of the driving transistors on the substrate, this arrangement can avoid an excessive number of adjacent driving transistors with the same projection direction of the channel regions in the same row of pixel driving circuits, thereby preventing short horizontal lines from appearing in the display panel.

[0128] Meanwhile, in other exemplary embodiments, the arrangement of the light-emitting units in the display panel may not be limited to the arrangement shown in Figures 3-8.

[0129] As shown in Figures 5-8, the protrusion directions of the driving transistor channel regions in the pixel driving circuits connected to the red light-emitting units are the same, and the protrusion directions of the driving transistor channel regions in the pixel driving circuits connected to the blue light-emitting units are also the same. It should be understood that in other exemplary embodiments, as long as the protrusion directions of the channel regions of the driving transistors connected to the same color light-emitting units on the substrate are the same, it is convenient to compensate for the brightness of the same color light-emitting units through data signals.

[0130] In this exemplary embodiment, the number of driving transistors with opposite convex directions in the orthographic projection of the channel region onto the substrate is the same in the same repeating unit. This arrangement can reduce the brightness difference between different repeating units at the same grayscale, thereby improving the uniformity of the display panel.

[0131] Figure 9 shows a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. In this configuration, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to node N; the first electrode of the second transistor T2 is connected to node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate drive signal terminal G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, and the gate is connected to the enable signal terminal EM; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to node N, the first electrode is connected to the first initial signal terminal Vinit1, and the gate is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to node N, and the second electrode is connected to the first power supply terminal VDD; the first electrode of the eighth transistor T8 is connected to the third initial signal line Vinit3, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the second reset signal terminal Re2. The pixel driving circuit can be connected to an OLED light-emitting unit. The pixel driving circuit is used to drive the OLED to emit light. The OLED can be connected between the second terminal and the second power supply terminal VSS of the sixth transistor T6. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type transistors.

[0132] The pixel driving circuit driving method can include a reset stage, a data writing stage, and a light-emitting stage. In the reset stage, the first reset signal terminal Re1 outputs a low-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on, the first initial signal terminal Vinit1 inputs a first initial signal to node N, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. In the data writing stage, the first gate driving signal terminal G1 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and simultaneously the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. In the light-emitting stage: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in capacitor C. In this pixel driving circuit, the output current of the driving transistor is I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth). 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the driving transistor threshold voltage.

[0133] This exemplary embodiment also provides a display panel, which may include a substrate, a shielding layer, an active layer, a first gate layer, a second gate layer, a first source / drain layer, a second source / drain layer, and an electrode layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 10-21, Figure 10 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 11 is a structural layout diagram of the shielding layer in the display panel shown in Figure 10; Figure 12 is a structural layout diagram of the active layer in the display panel shown in Figure 10; Figure 13 is a structural layout diagram of the first gate layer in the display panel shown in Figure 10; Figure 14 is a structural layout diagram of the second gate layer in the display panel shown in Figure 10; Figure 15 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 10; Figure 16 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 10; and Figure 17 is a structural layout diagram of the electrode layer in the display panel shown in Figure 10. The structural layouts are shown in Figures 18, 19, 20, 21, 22, and 23. Figure 18 shows a partial structural layout of the display panel shown in Figure 5, which includes the pixel driving circuit shown in Figure 9.

[0134] As shown in Figure 22, the display panel may include multiple pixel driving circuits arrayed in the row direction X and column direction Y. These multiple pixel driving circuits form multiple pixel driving circuit row groups Phz, each comprising two adjacent rows of pixel driving circuits. The orthographic projections of two pixel driving circuits located in the same column within a pixel driving circuit row group onto the substrate are at least partially mirror-symmetrically arranged along a first axis of symmetry AA. Specifically, the orthographic projections of the channel regions of the same type of transistors in two pixel driving circuits located in the same column within a pixel driving circuit row group onto the substrate are mirror-symmetrically arranged along the first axis of symmetry AA. For example, the orthographic projections of the channel regions of driving transistors in two pixel driving circuits located in the same column within a pixel driving circuit row group onto the substrate are mirror-symmetrically arranged along the first axis of symmetry AA, and the orthographic projections of the channel regions of the first transistors in two pixel driving circuits located in the same column within a pixel driving circuit row group onto the substrate are mirror-symmetrically arranged along the first axis of symmetry AA, which extends along the row direction.

[0135] As shown in Figure 22, the orthographic projections of two adjacent pixel driving circuits located in the same row on the substrate are at least partially mirror-symmetrical along the second axis of symmetry BB. The orthographic projections of the channel regions of the same type of transistors in the two adjacent pixel driving circuits located in the same row on the substrate are mirror-symmetrical along the second axis of symmetry BB. For example, the orthographic projection of the channel region of the first transistor in the two adjacent pixel driving circuits located in the same row on the substrate is mirror-symmetrical along the second axis of symmetry BB, which extends along the column direction.

[0136] As shown in Figure 22, the plurality of pixel driving circuits include a first pixel driving circuit P1, a second pixel driving circuit P2, and a third pixel driving circuit P3. The orthogonal projections of the first pixel driving circuit P1 and the second pixel driving circuit P2 on the substrate are at least partially mirror-symmetrically arranged along the second axis of symmetry BB. The orthogonal projections of the first pixel driving circuit P1 and the third pixel driving circuit P3 on the substrate are at least partially mirror-symmetrically arranged along the first axis of symmetry AA.

[0137] As shown in Figures 10, 11, and 18, the occlusion layer includes multiple occlusion portions 81 distributed in an array along the row direction X and the column direction Y, and the occlusion portions 81 are interconnected.

[0138] As shown in Figures 10, 12, and 19, the active layer may include: a first active section 71, a second active section 72, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, and a first initial signal line Vinit1. The first active portion 71 is used to form the channel region of the first transistor T1, wherein the first active portion 71 includes a first sub-active portion 731 and a second sub-active portion 732; the second active portion 72 is used to form the channel region of the second transistor T2, wherein the second active portion 72 includes a third sub-active portion 723 and a fourth sub-active portion 724; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected to the first active portion. The first active part 71 is connected to the second active part 72; the tenth active part 710 and the eleventh active part 711 are connected to the two ends of the eighth active part 78; the twelfth active part 712 is connected to the end of the seventh active part 77 away from the sixth active part 76; the thirteenth active part 713 is connected between the seventh active part 77 and the sixth active part 76; the fourteenth active part 714 is connected to the end of the fifth active part 75 away from the third active part 73; the fifteenth active part 715 is connected between the fifth active part 75 and the third active part 73; the sixteenth active part 716 is connected to the end of the fourth active part 74 away from the third active part 73; the seventeenth active part 717 is connected between the third sub-active part 723 and the fourth sub-active part 724; the first initial signal line Vinit1 is connected to the end of the first active part 71 away from the second active part 72. The active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polycrystalline silicon thin-film transistors. In this exemplary embodiment, both the first transistor and the second transistor have two spaced-apart channel regions. Correspondingly, both the first transistor and the second transistor have two gates, i.e., the first transistor and the second transistor are dual-gate structures. The dual-gate structure transistor has a smaller turn-off leakage current. This configuration can reduce the leakage current through the first transistor and the second transistor at the gate of the driving transistor, thereby improving the voltage stability of the gate of the driving transistor.

[0139] As shown in Figures 10 and 18, the orthographic projection of the shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can block light from the third active portion 73 to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source. The shielding layer can act as a signal shield for the pixel driving circuit, and the shielding layer can be connected to stable voltage sources such as the first initial signal terminal, the second initial signal terminal, the third initial signal terminal, the first power supply terminal, and the second power supply terminal in Figure 9.

[0140] As shown in Figures 10, 13, and 19, the first gate layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The first gate line G1 can be used to provide the first gate drive signal terminal in Figure 9; the enable signal line EM can be used to provide the enable signal terminal in Figure 9; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 9; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 9. The orthographic projections of the first gate line G1, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 on the substrate can all extend along the row direction X. The orthographic projection of the first gate line G1 on the substrate covers the orthographic projections of the fourth active portion 74 and the second active portion 72 on the substrate. A portion of the structure of the first gate line G1 is used to form the gate of the fourth transistor T4, and a portion of the structure of the first gate line G1 is used to form the gate of the second transistor T2. The orthographic projection of the enable signal line EM onto the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 onto the substrate covers the orthographic projections of the seventh active portion 77 and the eighth active portion 78 onto the substrate. A portion of the structure of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to conduct the active layer, that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductor structure.

[0141] As shown in Figures 10, 14, and 20, the second gate layer may include: a second conductive portion 22, a third conductive portion 23, and a second initial signal line Vinit2. The orthographic projection of the second conductive portion 22 on the substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 is used to form the second electrode of the capacitor C. The orthographic projection of the third conductive portion 23 on the substrate may at least partially overlap with the orthographic projection of the seventeenth active portion 717 on the substrate, and the third conductive portion 23 may be connected to a stable power supply terminal. The third conductive portion 23 may regulate the voltage of the seventeenth active portion 717 to improve the problem of leakage to the source / drain of the second transistor T2 caused by voltage fluctuations in the seventeenth active portion 717. The third conductive portion 23 may be connected to stable voltage sources such as the first initial signal terminal, the second initial signal terminal, the third initial signal terminal, the first power supply terminal, and the second power supply terminal in Figure 9. The orthographic projection of the second initial signal line Vinit2 on the substrate extends along the row direction X, and the second initial signal line Vinit2 may be used to provide the second initial signal terminal in Figure 9. In the same pixel driving circuit row group, the orthographic projection of the second initial signal line Vinit2 on the substrate is located between the orthographic projections of the two second reset signal lines Re2 on the substrate.

[0142] As shown in Figures 10, 15, and 21, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a seventh bridging portion 47, an eighth bridging portion 48, a ninth bridging portion 49, a third initial signal line Vinit3, and a first fan-out line FIPH. The first bridging portion 41 is connected to the third conductive portion 23 via a via. The second bridging portion 42 can be connected to the first conductive portion 11 and the ninth active portion 79 via vias, connecting the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2. A through-hole 221 is formed on the second conductive portion 22, and the through-hole connecting the first conductive portion 11 and the second bridging portion 42 can be disposed through the through-hole 221. The third bridging portion 43 is connected to the second conductive portion 22 and the fourteenth active portion 714 via vias, connecting the second electrode of the capacitor C and the first electrode of the fifth transistor. The fourth bridging section 44 can be connected to the thirteenth active section 713 via vias to connect the second terminals of the sixth and seventh transistors. The fifth bridging section 45 can be connected to the twelfth active section 712 and the second initial signal line Vinit2 via vias to connect the first terminal and the second initial signal terminal of the seventh transistor T7. The sixth bridging section 46 can be connected to the sixteenth active section 716 via vias to connect the first terminal of the fourth transistor T4. The eighth bridging section 48 can be connected to the fifteenth active section 715 and the eleventh active section 711 via vias to connect the second terminal of the eighth transistor T8 and the first terminal of the driving transistor T3. The ninth bridging section 49 can be connected to the first initial signal line Vinit1 via vias. The orthographic projection of the third initial signal line Vinit3 on the substrate can extend along the row direction X, and the third initial signal line Vinit3 can be used to provide the third initial signal terminal in FIG. 9. In the same pixel driving circuit row group, the orthographic projection of the third initial signal line Vinit3 on the substrate is located between the orthographic projections of the two second reset signal lines Re2 on the substrate. The orthographic projection of the first fan-out line FIPH on the substrate can extend along the row direction X, and the first fan-out line FIPH can serve as a row direction fan-out line connecting data lines in the FIP (Fanout In Pixel).

[0143] As shown in Figures 10, 16, and 22, the second source / drain layer may include a data line Da, a power line VDD, a second fan-out line FIPV, a first initial signal connection line 5Vinit1, a second initial signal connection line 5Vinit2, a third initial signal connection line 5Vinit3, and a tenth bridge section 510. The orthographic projections of the data line Da, power line VDD, second fan-out line FIPV, first initial signal connection line 5Vinit1, second initial signal connection line 5Vinit2, and third initial signal connection line 5Vinit3 onto the substrate all extend along the column direction Y. The data line Da provides the data signal terminal shown in Figure 9. The data line Da can be connected to the sixth bridge section 46 via vias to connect the data signal terminal and the first terminal of the fourth transistor T4. The power line VDD can provide the first power terminal shown in Figure 7. The power line VDD can be connected to the third bridge section 43 and the first bridge section 41 via vias to connect the first power terminal and the first terminal of the fifth transistor T5 and the second terminal of the capacitor C. The first initial signal connection line 5Vinit1 can be connected via a via to the ninth bridging part 49 to connect to the intersecting first initial signal line Vinit1. The first initial signal connection line 5Vinit1 and the first initial signal line Vinit1 can form a grid structure. The second initial signal connection line 5Vinit2 can be connected via a via to the fifth bridging part 45 to connect to the intersecting second initial signal line Vinit2. The second initial signal connection line 5Vinit2 and the second initial signal line Vinit2 can form a grid structure. The third initial signal connection line 5Vinit3 can be connected via a via to the intersecting third initial signal line Vinit3. The third initial signal connection line 5Vinit3 and the third initial signal line Vinit3 can form a grid structure. The grid structure of the initial signal lines can reduce the voltage difference on the initial signal lines at different positions on the display panel, thereby providing display uniformity of the display panel. Specifically, one initial signal connection line is set for every two columns of pixel driving, and three initial signal connection lines can be set for every six adjacent columns of pixel driving circuits: the first initial signal connection line 5Vinit1, the second initial signal connection line 5Vinit2, and the third initial signal connection line 5Vinit3. The second fan-out line FIPV can serve as a column-direction fan-out line connecting data lines within a FIP (Fanout In Pixel). The second fan-out line FIPV can include multiple fan-out line segments spaced apart in the column direction, and adjacent fan-out line segments can be bridged via the seventh bridging part 47. The tenth bridging part 510 can be connected to the fourth bridging part 44 via a via.

[0144] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in other conductive layers. For example, any one of the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in any one of the active layer, the second gate layer, the first source / drain layer, and the second source / drain layer.

[0145] As shown in Figures 10 and 17, the electrode layer may include multiple electrode portions: the multiple electrode portions include a first electrode portion R, a second electrode portion B, and a third electrode portion G. Each electrode portion can be connected to the tenth bridge portion 510 through a via to connect to the second electrode of the sixth transistor. Among the multiple electrode portions connected to the same row of pixel driving circuits, the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are alternately distributed in the row direction. In two adjacent columns of pixel driving circuits, multiple first electrode portions R and multiple second electrode portions B are connected to the same column of pixel driving circuits, and the first electrode portions R and second electrode portions B connected to the same column of pixel driving circuits are alternately distributed in the column direction. Multiple third electrode portions G are connected to another column of pixel driving circuits. The orthographic projection of the first electrode portion R on the substrate coincides with the orthographic projection of its corresponding opening on the pixel definition layer on the substrate. The orthographic projection of the third electrode portion G on the substrate coincides with the orthographic projection of its corresponding opening on the pixel definition layer on the substrate. The orthographic projection of the second electrode portion B on the substrate coincides with the orthographic projection of its corresponding opening on the pixel definition layer on the substrate. The third electrode portion G can serve as the first electrode of the green light-emitting unit, the first electrode portion R can serve as the first electrode of the red light-emitting unit, and the second electrode portion B can serve as the first electrode of the blue light-emitting unit. Furthermore, as shown in Figures 10 and 17, the edges of the third electrode portion G, the first electrode portion R, and the second electrode portion B are all provided with extension portions. These extension portions can be redundantly provided so as to form electrode portions that coincide with the pixel opening.

[0146] As shown in Figures 10 and 17, the minimum distance S1 between the orthogonal projections of two third electrode portions connected to adjacent row pixel driving circuits and connected to the same column pixel driving circuit on the substrate in the column direction is greater than the dimension S2 of the orthogonal projection of the first electrode portion on the substrate in the column direction; or, the minimum distance S1 between the orthogonal projections of two third electrode portions connected to adjacent row pixel driving circuits and connected to the same column pixel driving circuit on the substrate in the column direction is greater than the dimension S3 of the orthogonal projection of the second electrode portion on the substrate in the column direction.

[0147] Figure 23 shows a partial cross-sectional view of the display panel shown in Figure 10, taken along the dashed line CC. The display panel may further include a buffer layer 101, a first insulating layer 102, a second insulating layer 103, a dielectric layer 104, a passivation layer 105, a first planarization layer 106, and a second planarization layer 107. The substrate 100, shielding layer, buffer layer 101, active layer, first insulating layer 102, first gate layer, second insulating layer 103, second gate layer, dielectric layer 104, first source / drain layer, passivation layer 105, first planarization layer 106, second source / drain layer, second planarization layer 107, and electrode layer are sequentially stacked. The buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 104 can be a silicon nitride layer; the materials of the first planarization layer 106 and the second planarization layer 107 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 105 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer and the second gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of either the first or second source / drain layer can be less than the sheet resistance of either the first or second gate layer.

[0148] This exemplary embodiment also provides another display panel, which may include a substrate, an active layer, a first gate layer, a second gate layer, a first source / drain layer, a second source / drain layer, and an electrode layer stacked sequentially. An insulating layer may be disposed between adjacent layers. As shown in Figures 24-34, Figure 24 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure, Figure 25 is a structural layout diagram of the active layer in the display panel shown in Figure 24, Figure 26 is a structural layout diagram of the first gate layer in the display panel shown in Figure 24, Figure 27 is a structural layout diagram of the second gate layer in the display panel shown in Figure 24, Figure 28 is a structural layout diagram of the first source / drain layer in the display panel shown in Figure 24, Figure 29 is a structural layout diagram of the second source / drain layer in the display panel shown in Figure 24, Figure 30 is a structural layout diagram of the electrode layer in the display panel shown in Figure 24, Figure 31 is a structural layout diagram of the active layer and the first gate layer in the display panel shown in Figure 24, Figure 32 is a structural layout diagram of the active layer, the first gate layer, and the second gate layer in the display panel shown in Figure 24, Figure 33 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, and the first source / drain layer in the display panel shown in Figure 24, and Figure 34 is a structural layout diagram of the active layer, the first gate layer, the second gate layer, the first source / drain layer, and the second source / drain layer in the display panel shown in Figure 24. Figure 24 shows a partial structural layout of the display panel shown in Figure 3, which includes the pixel driving circuit shown in Figure 9.

[0149] As shown in Figure 34, the display panel may include multiple pixel driving circuits arrayed in the row direction X and column direction Y. These multiple pixel driving circuits form multiple pixel driving circuit row groups Phz, each comprising two adjacent rows of pixel driving circuits. The orthographic projections of two pixel driving circuits located in the same column within a pixel driving circuit row group onto the substrate are at least partially mirror-symmetrical along a first axis of symmetry AA. Specifically, the orthographic projections of the channel regions of the same type of transistors in two pixel driving circuits located in the same column within a pixel driving circuit row group onto the substrate are mirror-symmetrical along the first axis of symmetry AA. For example, the orthographic projections of the channel regions of driving transistors in two pixel driving circuits located in the same column within a pixel driving circuit row group onto the substrate are mirror-symmetrical along the first axis of symmetry AA, and the orthographic projections of the channel regions of the first transistors in two pixel driving circuits located in the same column within a pixel driving circuit row group onto the substrate are mirror-symmetrical along the first axis of symmetry AA, which extends along the row direction.

[0150] As shown in Figure 34, the plurality of pixel driving circuits include a first pixel driving circuit P1 and a third pixel driving circuit P3. The orthogonal projections of the first pixel driving circuit P1 and the third pixel driving circuit P3 on the substrate are at least partially mirror-symmetrically arranged along the first axis of symmetry AA.

[0151] As shown in Figures 24, 25, and 31, the active layer may include: a first active section 71, a second active section 72, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a ninth active section 79, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, and a first initial signal line Vinit1. The first active portion 71 is used to form the channel region of the first transistor T1, wherein the first active portion 71 includes a first sub-active portion 731 and a second sub-active portion 732; the second active portion 72 is used to form the channel region of the second transistor T2, wherein the second active portion 72 includes a third sub-active portion 723 and a fourth sub-active portion 724; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected to the first active portion. The first active part 71 is connected to the second active part 72; the tenth active part 710 and the eleventh active part 711 are connected to the two ends of the eighth active part 78; the twelfth active part 712 is connected to the end of the seventh active part 77 away from the sixth active part 76; the thirteenth active part 713 is connected between the seventh active part 77 and the sixth active part 76; the fourteenth active part 714 is connected to the end of the fifth active part 75 away from the third active part 73; the fifteenth active part 715 is connected between the fifth active part 75 and the third active part 73; the sixteenth active part 716 is connected to the end of the fourth active part 74 away from the third active part 73; the seventeenth active part 717 is connected between the third sub-active part 723 and the fourth sub-active part 724; the first initial signal line Vinit1 is connected to the end of the first active part 71 away from the second active part 72. The active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be P-type low-temperature polycrystalline silicon thin-film transistors. In this exemplary embodiment, the first transistor and the second transistor are also dual-gate structures. The dual-gate structure transistor has a smaller turn-off leakage current. This setting can reduce the leakage current through the first transistor and the second transistor at the gate of the driving transistor, thereby improving the voltage stability of the gate of the driving transistor.

[0152] As shown in Figures 24, 26, and 31, the first gate layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The first gate line G1 can be used to provide the first gate drive signal terminal in Figure 9; the enable signal line EM can be used to provide the enable signal terminal in Figure 9; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 9; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 9. The orthographic projections of the first gate line G1, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 on the substrate can all extend along the row direction X. The orthographic projection of the first gate line G1 on the substrate covers the orthographic projections of the fourth active portion 74 and the second active portion 72 on the substrate. A portion of the structure of the first gate line G1 is used to form the gate of the fourth transistor T4, and a portion of the structure of the first gate line G1 is used to form the gate of the second transistor T2. The orthographic projection of the enable signal line EM onto the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 onto the substrate. A portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. A portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 onto the substrate covers the orthographic projections of the seventh active portion 77 and the eighth active portion 78 onto the substrate. A portion of the structure of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The display panel can use the first gate layer as a mask to conduct the active layer, that is, the area of ​​the active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the first gate layer forms a conductor structure.

[0153] As shown in Figures 24, 27, and 32, the second gate layer may include: a second conductive portion 22, a third conductive portion 23, and a second initial signal line Vinit2. The orthographic projection of the second conductive portion 22 on the substrate may at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 is used to form the second electrode of the capacitor C. The orthographic projection of the third conductive portion 23 on the substrate and the orthographic projection of the seventeenth active portion 717 on the substrate may at least partially overlap, and the third conductive portion 23 may be connected to a stable power supply terminal, and the third conductive portion 23 may regulate the voltage of the seventeenth active portion 717 to improve the problem of leakage to the source / drain of the second transistor T2 due to voltage fluctuations of the seventeenth active portion 717. The orthographic projection of the second initial signal line Vinit2 on the substrate extends along the row direction X, and the second initial signal line Vinit2 may be used to provide the second initial signal terminal in Figure 9. In the same pixel driving circuit row group, the orthographic projection of the second initial signal line Vinit2 on the substrate is located between the orthographic projections of the two second reset signal lines Re2 on the substrate.

[0154] As shown in Figures 24, 28, and 33, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a seventh bridging portion 47, an eighth bridging portion 48, a ninth bridging portion 49, a third initial signal line Vinit3, and a first fan-out line FIPH. The first bridging portion 41 is connected to the third conductive portion 23 via a via. The second bridging portion 42 can be connected to the first conductive portion 11 and the ninth active portion 79 via vias, respectively, to connect the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2. A through-hole 221 is formed on the second conductive portion 22, and the through-hole connecting the first conductive portion 11 and the second bridging portion 42 can be disposed through the through-hole 221. The third bridging portion 43 is connected to the second conductive portion 22 and the fourteenth active portion 714 via vias, respectively, to connect the second electrode of the capacitor C and the first electrode of the fifth transistor. The fourth bridging section 44 can be connected to the thirteenth active section 713 via vias to connect the second terminals of the sixth and seventh transistors. The fifth bridging section 45 can be connected to the twelfth active section 712 and the second initial signal line Vinit2 via vias to connect the first terminal and the second initial signal terminal of the seventh transistor T7. The sixth bridging section 46 can be connected to the sixteenth active section 716 via vias to connect the first terminal of the fourth transistor T4. The eighth bridging section 48 can be connected to the fifteenth active section 715 and the eleventh active section 711 via vias to connect the second terminal of the eighth transistor T8 and the first terminal of the driving transistor T3. The ninth bridging section 49 can be connected to the first initial signal line Vinit1 via vias. The orthographic projection of the third initial signal line Vinit3 on the substrate can extend along the row direction X. The third initial signal line Vinit3 can be used to provide the third initial signal terminal in FIG9. In the same pixel driving circuit row group, the orthographic projection of the third initial signal line Vinit3 on the substrate is located between the orthographic projections of the two second reset signal lines Re2 on the substrate. The orthographic projection of the first fan-out line FIPH on the substrate can extend along the row direction X. The first fan-out line FIPH can serve as a row direction fan-out line connecting data lines in the FIP (Fanout In Pixel).

[0155] As shown in Figures 24, 29, and 34, the second source / drain layer may include a data line Da, a power line VDD, a second fan-out line FIPV, a first initial signal connection line 5Vinit1, a second initial signal connection line 5Vinit2, a third initial signal connection line 5Vinit3, and a tenth bridge section 510. The orthographic projections of the data line Da, power line VDD, second fan-out line FIPV, first initial signal connection line 5Vinit1, second initial signal connection line 5Vinit2, and third initial signal connection line 5Vinit3 onto the substrate all extend along the column direction Y. The data line Da provides the data signal terminal shown in Figure 9. The data line Da can be connected to the sixth bridge section 46 via vias to connect the data signal terminal and the first terminal of the fourth transistor T4. The power line VDD provides the first power terminal shown in Figure 9. The power line VDD can be connected to the third bridge section 43 and the first bridge section 41 via vias to connect the first power terminal and the first terminal of the fifth transistor T5 and the second terminal of the capacitor C. The first initial signal connection line 5Vinit1 can be connected via a via to the ninth bridging part 49 to connect to the intersecting first initial signal line Vinit1. The first initial signal connection line 5Vinit1 and the first initial signal line Vinit1 can form a grid structure. The second initial signal connection line 5Vinit2 can be connected via a via to the fifth bridging part 45 to connect to the intersecting second initial signal line Vinit2. The second initial signal connection line 5Vinit2 and the second initial signal line Vinit2 can form a grid structure. The third initial signal connection line 5Vinit3 can be connected via a via to the intersecting third initial signal line Vinit3. The third initial signal connection line 5Vinit3 and the third initial signal line Vinit3 can form a grid structure. The grid structure of the initial signal lines can reduce the voltage difference on the initial signal lines at different positions on the display panel, thereby providing display uniformity of the display panel. Specifically, one initial signal connection line is set for every two columns of pixel driving, and three initial signal connection lines can be set for every six adjacent columns of pixel driving circuits: the first initial signal connection line 5Vinit1, the second initial signal connection line 5Vinit2, and the third initial signal connection line 5Vinit3. The second fan-out line FIPV can serve as a column-direction fan-out line connecting data lines within a FIP (Fanout In Pixel). The second fan-out line FIPV can include multiple fan-out segments spaced apart in the column direction, and adjacent fan-out segments can be bridged via the seventh bridging part 47. The second initial signal connection line 5Vinit2 can include multiple second initial signal connection segments spaced apart in the column direction, and adjacent second initial signal connection segments can also be bridged via the seventh bridging part 47. The tenth bridging part 510 can be connected to the fourth bridging part 44 via a via.

[0156] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in other conductive layers. For example, any one of the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in any one of the active layer, the second gate layer, the first source / drain layer, and the second source / drain layer.

[0157] As shown in Figures 24 and 30, the electrode layer may include multiple electrode portions: the multiple electrode portions include a first electrode portion R, a second electrode portion B, and a third electrode portion G. Each electrode portion can be connected to the tenth bridge portion 510 through a via to connect to the second electrode of the sixth transistor. Among the multiple electrode portions connected to the same row of pixel driving circuits, the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are alternately distributed in the row direction. In two adjacent columns of pixel driving circuits, multiple first electrode portions R and multiple second electrode portions B are connected to the same column of pixel driving circuits, and the first electrode portions R and second electrode portions B connected to the same column of pixel driving circuits are alternately distributed in the column direction. Multiple third electrode portions G are connected to another column of pixel driving circuits. The orthographic projection of the first electrode portion R on the substrate coincides with the orthographic projection of its corresponding opening on the pixel definition layer on the substrate. The orthographic projection of the third electrode portion G on the substrate coincides with the orthographic projection of its corresponding opening on the pixel definition layer on the substrate. The orthographic projection of the second electrode portion B on the substrate coincides with the orthographic projection of its corresponding opening on the pixel definition layer on the substrate. The third electrode portion G can serve as the first electrode of the green light-emitting unit, the first electrode portion R can serve as the first electrode of the red light-emitting unit, and the second electrode portion B can serve as the first electrode of the blue light-emitting unit. In addition, as shown in Figures 24 and 30, the edges of the third electrode portion G, the first electrode portion R, and the second electrode portion B are all provided with extension portions. The extension portions can be redundantly provided so as to form electrode portions that coincide with the pixel opening.

[0158] As shown in Figures 24 and 30, the minimum distance S1 of the orthogonal projection of two third electrode portions connected to adjacent row pixel driving circuits and connected to the same column pixel driving circuit on the substrate in the column direction is greater than the dimension S2 of the orthogonal projection of the first electrode portion on the substrate in the column direction, or the minimum distance S1 of the orthogonal projection of two third electrode portions connected to adjacent row pixel driving circuits and connected to the same column pixel driving circuit on the substrate in the column direction is greater than the dimension S3 of the orthogonal projection of the second electrode portion on the substrate in the column direction.

[0159] Figure 35 shows a partial cross-sectional view of the display panel shown in Figure 24, taken along the dashed line DD. The display panel may further include a buffer layer 101, a first insulating layer 102, a second insulating layer 103, a dielectric layer 104, a passivation layer 105, a first planarization layer 106, and a second planarization layer 107. The substrate 100, shielding layer, buffer layer 101, active layer, first insulating layer 102, first gate layer, second insulating layer 103, second gate layer, dielectric layer 104, first source / drain layer, passivation layer 105, first planarization layer 106, second source / drain layer, second planarization layer 107, and electrode layer are sequentially stacked. The buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the first insulating layer 102, and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 104 can be a silicon nitride layer; the materials of the first planarization layer 106 and the second planarization layer 107 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 105 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer and the second gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of either the first or second source / drain layer can be less than the sheet resistance of either the first or second gate layer.

[0160] In this exemplary embodiment, as shown in Figures 22 and 34, in two pixel driving circuits located in the same pixel driving circuit row group and mirror-symmetrically arranged along the first axis of symmetry AA, the two seventh active units 77 are connected through the twelfth active unit 712. The two pixel driving circuits located in the same pixel driving circuit row group and mirror-symmetrically arranged along the first axis of symmetry AA can share the same second initial signal line Vinit2. The second initial signal line Vinit2 is connected to the twelfth active unit 712 through a via, thereby simultaneously connecting the seventh transistors in the two mirror-symmetrical pixel driving circuits. This arrangement can improve the integration density of the pixel driving circuits in the display panel.

[0161] In this exemplary embodiment, as shown in Figures 22 and 34, in two pixel driving circuits located in the same pixel driving circuit row group and mirror-symmetrically arranged along the first axis of symmetry AA, the two eighth active units 78 are connected through a tenth active unit 710. The two pixel driving circuits located in the same pixel driving circuit row group and mirror-symmetrically arranged along the first axis of symmetry AA can share the same third initial signal line Vinit3. The third initial signal line Vinit3 is connected to the tenth active unit 710 through a via, thereby simultaneously connecting the eighth transistors in the two mirror-symmetrical pixel driving circuits. This arrangement can also improve the integration density of the pixel driving circuits in the display panel.

[0162] It should be understood that in other exemplary embodiments, the electrode layer in the display panel shown in Figures 10 and 24 may also have other structures. For example, as shown in Figure 36, which is a schematic diagram of the electrode layer structure in another exemplary embodiment of the display panel of this disclosure, the electrode layer may include multiple electrode portions, which may be used to form the first electrode of the light-emitting unit. The multiple electrode portions include: multiple first electrode portions R, multiple third electrode portions G, and multiple second electrode portions B. Among the multiple electrode portions connected to the same row pixel driving circuit, the first electrode portions, third electrode portions, and second electrode portions are alternately distributed in the row direction. In two adjacent column pixel driving circuits, multiple first electrode portions and multiple second electrode portions are connected to the same column pixel driving circuit, and the first electrode portions and second electrode portions connected to the same column pixel driving circuit are alternately distributed in the column direction. The multiple third electrode portions are connected to another column pixel driving circuit. Specifically, the minimum distance S1 between the orthographic projections of two third electrode portions connected to adjacent row pixel driving circuits and connected to the same column pixel driving circuit on the substrate in the column direction is less than the dimension S2 of the orthographic projection of the first electrode portion R on the substrate in the column direction; or, the minimum distance S1 between the orthographic projections of two third electrode portions G connected to adjacent row pixel driving circuits and connected to the same column pixel driving circuit on the substrate in the column direction is less than the dimension S3 of the orthographic projection of the second electrode portion B on the substrate in the column direction. The display panel may further include a pixel definition layer located on the side of the electrode layer facing away from the substrate, where the orthographic projection of the first electrode portion on the substrate coincides with the orthographic projection of its corresponding opening on the substrate; the orthographic projection of the third electrode portion on the substrate coincides with the orthographic projection of its corresponding opening on the substrate; and the orthographic projection of the second electrode portion on the substrate coincides with the orthographic projection of its corresponding opening on the substrate.

[0163] It should be understood that in other exemplary embodiments, the projection directions of the channel regions of the driving transistors in two pixel driving circuits located in the same row and column of the pixel driving circuit can also be the same on the substrate. For example, as shown in FIG37, it is a schematic diagram of the structure in another exemplary embodiment of the display panel of this disclosure. In the diagram, R / upper represents the pixel driving circuit Pix connected to the red light-emitting unit and in which the projection direction of the driving transistor channel region is upward; G / lower represents the pixel driving circuit Pix connected to the green light-emitting unit and in which the projection direction of the driving transistor channel region is downward; and B / upper represents the pixel driving circuit Pix connected to the blue light-emitting unit and in which the projection direction of the driving transistor channel region is upward. In this display panel, the projection directions of the driving transistor channel regions in the pixel driving circuits connected to the same color light-emitting unit are the same. This arrangement can facilitate data compensation for the same color light-emitting unit through data compensation to improve the color shift problem. At the same time, this display panel can also improve the problem of horizontal stripes on the display panel. Furthermore, in other exemplary embodiments, the protrusion direction of the driving transistor channel region in the pixel driving circuit to which all red light-emitting units in the display panel shown in FIG37 are connected may also be downward, the protrusion direction of the driving transistor channel region in the pixel driving circuit to which all green light-emitting units in the display panel shown in FIG37 are connected may also be upward, and the protrusion direction of the driving transistor channel region in the pixel driving circuit to which all blue light-emitting units in the display panel shown in FIG37 are connected may also be downward.

[0164] It should be understood that in other exemplary embodiments, the display panel shown in FIG10 can achieve different display panels by adjusting the protrusion direction of the driving transistors and / or the arrangement of the light-emitting units in the active layer. For example, the display panel shown in FIG10 can achieve the display panels shown in FIG3, 4, 6, 7, 8, and 37 by adjusting the protrusion direction of the driving transistors and / or the arrangement of the light-emitting units in the active layer. For example, the display panel shown in FIG10 can adjust the active layer to the structure shown in FIG2 to achieve the display panel shown in FIG3.

[0165] Furthermore, in other exemplary embodiments, the display panel shown in FIG24 can achieve different display panels by adjusting the protrusion direction of the driving transistors and / or the arrangement of the light-emitting units in the active layer. For example, the display panel shown in FIG24 can achieve the display panels shown in FIG4, 5, 6, 7, 8, and 37 by adjusting the protrusion direction of the driving transistors and / or the arrangement of the light-emitting units in the active layer. For example, as shown in FIG38, which is a structural layout of the active layer in another exemplary embodiment of the display panel of this disclosure, the display panel shown in FIG24 can adjust the active layer to the structure shown in FIG38 to achieve the display panel shown in FIG5.

[0166] Furthermore, in other exemplary embodiments, the pixel driving circuit in the display panel may also have other structures, as shown in Figures 39-41, which are schematic diagrams of the structure of the pixel driving circuit in another exemplary embodiment of the display panel of this disclosure.

[0167] It should be noted that, as shown in Figure 10-34, the black squares with chamfers drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the black circles drawn on the side of the electrode layer away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Vias at different positions can penetrate different insulating layers.

[0168] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0169] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0170] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0171] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

A display panel, wherein, The display panel comprises: a substrate substrate; a plurality of light emitting units; a plurality of pixel driving circuits, the orthographic projections of the plurality of pixel driving circuits on the substrate substrate are arrayed in a row-column direction, the plurality of pixel driving circuits form a plurality of pixel driving circuit row groups, and each pixel driving circuit row group comprises two adjacent rows of pixel driving circuits; The pixel driving circuit comprises a driving transistor, the driving transistor is used to provide a driving current to the light emitting unit according to a gate-source voltage difference thereof, the driving transistor comprises a channel region, and the orthographic projection of the channel region of the driving transistor on the substrate substrate extends in a bending manner in a row direction to form a protrusion in a column direction. The protruding directions of the orthographic projections of the channel regions of the driving transistors in two pixel driving circuits in the same pixel driving circuit row group and in the same column on the substrate substrate are opposite. In the same row of pixel driving circuits, the protruding directions of the orthographic projections of the channel regions of the driving transistors in at least some of the pixel driving circuits are opposite. The display panel of claim 1, wherein, The pixel driving circuit row group comprises a plurality of repeating units distributed in the row direction, and each repeating unit comprises two rows of multiple columns of pixel driving circuits. In the same row of pixel driving circuits in the same repeating unit, the protruding directions of the orthographic projections of the channel regions of the driving transistors in at least some of the pixel driving circuits are opposite. The display panel according to claim 1 or 2, wherein, The display panel comprises light emitting units of multiple colors, and the protruding directions of the orthographic projections of the channel regions of the driving transistors connected to light emitting units of at least one same color on the substrate substrate are the same. The display panel according to claim 2, wherein, The display panel comprises light emitting units of multiple colors, and in the same repeating unit, the protruding directions of the orthographic projections of the channel regions of the driving transistors connected to light emitting units of at least one same color on the substrate substrate are opposite. The display panel according to claim 2, wherein, In the same repeating unit, the number of driving transistors whose orthographic projections of channel regions on the substrate substrate have opposite protruding directions is the same. The display panel according to claim 1 or 2, wherein, In the same row of pixel driving circuits, the protruding directions of the orthographic projections of the channel regions of the driving transistors in any two adjacent pixel driving circuits on the substrate substrate are opposite. The display panel according to claim 1 or 2, wherein, The same row of pixel driving circuits forms a plurality of pixel driving circuit groups distributed in the row direction, and each pixel driving circuit group comprises n adjacent pixel driving circuits. The protruding directions of the orthographic projections of the channel regions of the driving transistors in the same pixel driving circuit group on the substrate substrate are the same. The protruding directions of the orthographic projections of the channel regions of the driving transistors in adjacent pixel driving circuit groups on the substrate substrate are opposite. n is a positive integer greater than or equal to 2. The display panel according to any one of claims 1-7, wherein The display panel further comprises: an electrode layer located on one side of the substrate substrate, the electrode layer comprising a plurality of electrode portions, and the electrode portions being used to form first electrodes of the light emitting units; The plurality of electrode portions comprise a plurality of first electrode portions, a plurality of second electrode portions, and a plurality of third electrode portions. In the plurality of electrode portions connected to the same row of pixel driving circuits, the orthographic projections of the first electrode portions, the second electrode portions, the third electrode portions, and the second electrode portions on the substrate substrate are sequentially and alternately distributed in the row direction. In adjacent two pixel driving circuit columns, the first electrode parts and the third electrode parts are connected to the same column pixel driving circuit, and the normal projections of the first electrode parts and the third electrode parts connected to the same column pixel driving circuit on the substrate are alternately distributed in the column direction, and the second electrode parts are connected to another column pixel driving circuit. The display panel according to claim 8, wherein, The pixel driving circuit row group comprises a plurality of repeating units distributed in the row direction, each of the repeating units comprising two rows of m columns of pixel driving circuits; In the same row of pixel driving circuits in the same repeating unit, the convex directions of the normal projections of the channel regions of the driving transistors in at least part of the pixel driving circuits are opposite; m is an integer multiple of 4. The display panel according to any one of claims 1-9, wherein The normal projections of the two pixel driving circuits in the same column in the pixel driving circuit row group on the substrate are at least partially arranged in mirror symmetry along a first symmetry axis, and the first symmetry axis extends in the row direction; The pixel driving circuit comprises a plurality of transistors, and in the two pixel driving circuits in the same pixel driving circuit row group and in the same column, the normal projections of the channel regions of the same kind of transistors on the substrate are arranged in mirror symmetry along the first symmetry axis. The display panel according to claim 9 or 10, wherein The pixel driving circuit comprises a seventh transistor, the first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light emitting unit; The display panel further comprises: An active layer located on one side of the substrate, the active layer comprising a seventh active part and a twelfth active part, the seventh active part being used to form a channel region of the seventh transistor, and in the two pixel driving circuits in the same pixel driving circuit row group and in the same column, the two seventh active parts are connected through the twelfth active part; A second initial signal line, the normal projection of the second initial signal line on the substrate extends in the row direction, and the second initial signal line is connected to the twelfth active part through a via hole. The display panel of claim 11, wherein, The display panel further comprises: A first gate layer located on the side of the active layer away from the substrate, the first gate layer comprising a second reset signal line, the normal projection of the second reset signal line on the substrate extending in the row direction, and part of the structure of the second reset signal line being used to form a gate of the seventh transistor; And in the same pixel driving circuit row group, the normal projection of the second initial signal line on the substrate is located between the normal projections of the two second reset signal lines on the substrate. The display panel according to claim 9 or 10, wherein The pixel driving circuit further comprises an eighth transistor, the first electrode of the eighth transistor is connected to a third initial signal line, and the second electrode of the eighth transistor is connected to the first electrode of the driving transistor; The display panel further comprises: An active layer located on one side of the substrate, the active layer comprising an eighth active part and a tenth active part, the eighth active part being used to form a channel region of the eighth transistor, and in the same pixel driving circuit row group and in the same column, the two eighth active parts are connected through the tenth active part; The normal projection of the second initial signal line on the substrate is located between the normal projections of the two second reset signal lines on the substrate. A third initial signal line, a projection of the third initial signal line on the substrate substrate extends along a row direction, and the third initial signal line is connected to the tenth active part through a via hole. The display panel according to claim 13, wherein The pixel driving circuit further includes a seventh transistor, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to a first electrode of the light emitting unit. The display panel further includes: A first gate layer is located on a side of the active layer away from the substrate substrate, and the first gate layer includes a second reset signal line, a projection of the second reset signal line on the substrate substrate extends along a row direction, and part of a structure of the second reset signal line is used to form a gate of the seventh transistor. In the same row group of pixel driving circuits, a projection of the third initial signal line on the substrate substrate is located between projections of two second reset signal lines on the substrate substrate. The display panel according to any one of claims 1-14, wherein The pixel driving circuit further includes a first transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a gate of the driving transistor. The display panel further includes: An active layer includes a first active part, the first initial signal line, the first active part is used to form a channel region of the first transistor, and the first initial signal line extends along a row direction and is connected to the first active part. The display panel according to any one of claims 1-15, wherein, Projections of two pixel driving circuits located in the same row of pixel driving circuits and adjacent to each other on the substrate substrate are at least partially arranged in mirror symmetry along a second symmetry axis, and the second symmetry axis extends along a column direction. The display panel according to any one of claims 1-16, wherein The display panel further includes: A data line is used to provide a data signal to a pixel driving circuit, and the data line extends along a column direction. The display panel according to any one of claims 1-17, wherein The pixel driving circuit further includes: A first transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to a gate of the driving transistor. A second transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor. A fourth transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor. A fifth transistor, a first electrode of the fifth transistor is connected to a power supply line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor. A sixth transistor, a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to a first electrode of the light emitting unit. A seventh transistor, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to the first electrode of the light emitting unit. An eighth transistor, a first electrode of the eighth transistor is connected to a third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor. A capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the power supply line. The first transistor and the second transistor are P-type transistors. The display panel of claim 18, wherein, The first transistor and the second transistor are double-gate structures. The display device includes the display panel of any one of claims 1-18. A display device, wherein, ​

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