Semiconductor structure and manufacturing method therefor, and semiconductor device

Abstract

A semiconductor structure and a manufacturing method therefor, and a semiconductor device. The semiconductor structure comprises a substrate, wherein the substrate comprises a memory region, a peripheral region, and a transition region located between the memory region and the peripheral region, a first isolation structure being provided in the transition region; and a first trench, which is located in the isolation structure and extends in a first direction, wherein the depth of the first trench is less than the depth of the isolation structure. The semiconductor structure has a good performance.

Description

Semiconductor structure, manufacturing method thereof, and semiconductor device

[0001] The present application claims priority to the Chinese patent application No. 202411022419.7, filed on July 26, 2024, and entitled "Semiconductor structure, manufacturing method thereof, and semiconductor device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular to a semiconductor structure, a manufacturing method thereof, and a semiconductor device. BACKGROUND

[0003] Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory widely used in computer systems.

[0004] With the continuous development of semiconductor process technology, the size of semiconductor memory is also getting smaller and smaller. Especially with the process node of DRAM getting smaller and smaller, the feature size of the word line is continuously shrinking, and the manufacturing process of the word line becomes more and more complex, and the word line end distortion is also generated, which further adversely affects the performance of the DRAM.

[0005] SUMMARY

[0006] According to a first aspect of embodiments of the present disclosure, a semiconductor structure is provided, comprising:

[0007] a substrate comprising a storage area, a peripheral area, and a transition area between the storage area and the peripheral area, the transition area having a first isolation structure therein;

[0008] a first trench in the isolation structure, the first trench extending along a first direction; the depth of the first trench is less than the depth of the isolation structure.

[0009] In some embodiments, the first trench comprises:

[0010] a first sidewall close to the storage area;

[0011] a second sidewall close to the peripheral area;

[0012] wherein the width of the first sidewall is greater than the width of the second sidewall.

[0013] In some embodiments, the semiconductor structure further comprises:

[0014] a second trench extending along a second direction from the storage area into the transition area;

[0015] The first trench and the second trench are in communication.

[0016] In some embodiments, the first trench has a depth greater than a depth of the second trench.

[0017] In some embodiments, the semiconductor structure further comprises:

[0018] A second isolation structure, the second trench passing through the second isolation structure;

[0019] In the second direction, the first trench has a width greater than a width of the second isolation structure.

[0020] In some embodiments, the first trench has a depth less than a depth of the second isolation structure.

[0021] In some embodiments, a top surface of the first sidewall is lower than a top surface of the second sidewall, a top surface of the first sidewall is higher than a bottom surface of the second trench, and the top surface of the first sidewall is flush with a top surface of the storage region.

[0022] According to a second aspect of the embodiments of the present disclosure, a semiconductor device is provided, comprising:

[0023] A substrate comprising a storage region, a peripheral region, and a transition region between the storage region and the peripheral region, the transition region having a first isolation structure therein;

[0024] A first trench in the first isolation structure, the first trench extending along a first direction; the first trench has a depth less than a depth of the isolation structure;

[0025] A second trench extending along a second direction, the second trench extending from the storage region into the transition region;

[0026] A word line conductive layer in the second trench;

[0027] The first trench and the second trench are in communication.

[0028] In some embodiments, the semiconductor device further comprises:

[0029] An insulating layer substantially filling in the first trench;

[0030] A top surface of the insulating layer is higher than a top surface of the word line conductive layer.

[0031] In some embodiments, the semiconductor device further comprises:

[0032] A word line contact layer in the first trench;

[0033] The word line contact layer is connected with the word line conductive layer.

[0034] In some embodiments, in parallel to the first direction, the width of the word line contact layer is greater than the width of the word line conductive layer.

[0035] In some embodiments, in parallel to the first direction, the gap between adjacent word line contact layers is less than the width of adjacent word line conductive layers.

[0036] In some embodiments, the bottom surface of the word line contact layer is lower than the bottom surface of the word line conductive layer.

[0037] In some embodiments, the top surface of the word line contact layer is higher than the top surface of the word line conductive layer.

[0038] In some embodiments, the first trench comprises:

[0039] a first sidewall close to the storage region;

[0040] a second sidewall away from the storage region;

[0041] In parallel to the second direction, the width of the first sidewall is greater than the width of the second sidewall.

[0042] In some embodiments, the word line contact layer is located between the first sidewall and the second sidewall, the top surface of the word line contact layer is higher than the first sidewall and lower than the second sidewall.

[0043] According to a third aspect of the embodiments of the present disclosure, a manufacturing method of a semiconductor structure is provided, comprising:

[0044] providing a substrate comprising a storage region, a peripheral region, and a transition region between the storage region and the peripheral region, wherein the transition region has a first isolation structure;

[0045] forming a first trench in the first isolation structure, wherein the depth of the first trench is less than the depth of the first isolation structure.

[0046] In some embodiments, further comprising:

[0047] etching the storage region and part of the first isolation structure to form a second trench, wherein the second trench extends along a second direction from the storage region to the transition region;

[0048] wherein the first trench and the second trench are in communication, the first trench and the second trench are substantially perpendicular, and the depth of the second trench is less than the depth of the first trench.

[0049] In some embodiments, further comprising:

[0050] forming a word line conductive layer in the second trench;

[0051] forming an insulating layer in the first trench;

[0052] wherein a top surface of the insulating layer is higher than a top surface of the word line conductive layer.

[0053] In some embodiments, further comprising:

[0054] forming a word line conductive layer in the second trench;

[0055] forming a word line contact layer in the first trench;

[0056] wherein the word line conductive layer connects the word line contact layer;

[0057] wherein in the first direction, a width of the word line contact layer is greater than a width of the word line conductive layer.

[0058] In summary, the embodiments of the present disclosure propose a semiconductor structure, a manufacturing method thereof, and a semiconductor device. Due to the first isolation structure in the transition region, by setting the first trench in the first isolation structure, the first trench extends along the first direction, and the depth of the first trench is less than the depth of the first isolation structure. Therefore, when the second trench is formed on the substrate, the second trench extends from the storage region to the transition region, so that the end of the second trench communicates with the first trench, thereby releasing the stress of the end of the second trench, improving the bending of the end of the second trench, and thus ensuring the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0059] FIG. 1 is an electron microscope image of a trench in the related art, according to an example embodiment;

[0060] FIG. 2 is a flow chart of a manufacturing method of a semiconductor structure, according to an example embodiment;

[0061] FIG. 3 is a top view of a substrate, according to an example embodiment;

[0062] FIG. 4 is a cross-sectional view of FIG. 3 in the AA direction, according to an example embodiment;

[0063] FIG. 5 is a schematic diagram of a patterned photoresist layer, according to an example embodiment;

[0064] FIG. 6 is another schematic diagram of a substrate, according to an example embodiment;

[0065] FIG. 7A is a cross-sectional view of FIG. 6 in the AA direction, according to an example embodiment;

[0066] FIG. 7B is a schematic view of the first trench, according to an exemplary embodiment;

[0067] FIG. 8 is another schematic view of the substrate, according to an exemplary embodiment;

[0068] FIG. 9 is a cross-sectional view of FIG. 9 in the AA direction, according to an exemplary embodiment;

[0069] FIG. 10 is a cross-sectional view of FIG. 9 in the BB direction, according to an exemplary embodiment;

[0070] FIG. 11 is another schematic view of the first trench, according to an exemplary embodiment;

[0071] FIG. 12 is another schematic view of the substrate, according to an exemplary embodiment;

[0072] FIG. 13 is a cross-sectional view of FIG. 12 in the AA direction, according to an exemplary embodiment;

[0073] FIG. 14 is another schematic view of the substrate, according to an exemplary embodiment;

[0074] FIG. 15 is a cross-sectional view of FIG. 14 in the AA direction, according to an exemplary embodiment;

[0075] FIG. 16 is another schematic view of the substrate, according to an exemplary embodiment;

[0076] FIG. 17 is a cross-sectional view of FIG. 16 in the AA direction, according to an exemplary embodiment;

[0077] FIG. 18 is another cross-sectional view of FIG. 16 in the AA direction, according to an exemplary embodiment;

[0078] FIG. 19 is a schematic view of forming a protective layer, according to an exemplary embodiment;

[0079] FIG. 20 is an electron microscope view of FIG. 8, according to an exemplary embodiment. DETAILED DESCRIPTION

[0080] The technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0081] The present disclosure will be described with respect to the following drawings in order to explain the present disclosure by way of example. The advantages and features of the present disclosure will become clear to those skilled in the art from the following description and the claims. It should be noted that the drawings are very simplified and are not drawn to precise scale, and are merely intended to assist in understanding the embodiments of the present disclosure.

[0082] It can be understood that the meanings of "on", "over", and "above" of the present disclosure should be interpreted in the broadest way, so that the meaning of "on" not only means the meaning of "on" with no intervening features or layers therebetween (i.e., directly on), but also includes the meaning of "on" with intervening features or layers therebetween.

[0083] In the embodiments of the present disclosure, the terms "first", "second", "third" and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0084] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Further, the layer can be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0085] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0086] As shown in FIG. 1, FIG. 1 shows a scanning electron microscope image of a trench in the related art. The scanning electron microscope image of the trench formed in the substrate 100. The substrate 100 can include a storage area 101, a transition area 102, and a peripheral area 103. The trench on the substrate 100 extends from the storage area 101 into the transition area 102, i.e., the end of the trench is located in the transition area 102. As can be seen from FIG. 1, the trench in the storage area 101 is neat and straight. The trench in the transition area 102 is distorted, i.e., the end of the trench is deformed, which will affect the performance of the device.

[0087] The present disclosure found that during the process of forming the trench, the etching gas gradually consumes the substrate, thereby gradually forming the trench. Near the end of the trench, due to the blocking effect of the un-consumed substrate, the etching gas above the end of the trench is disturbed and concentrated, which in turn causes the etching rate of the end of the trench to be different, thereby causing the end of the trench to be deformed. Secondly, since the end of the trench is closed, the end of the trench will also have a greater stress concentration, which in turn exacerbates the deformation of the end of the trench.

[0088] Therefore, as shown in FIG. 2, the embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, which can improve the deformation of the end of the trench and improve the performance of the semiconductor structure.

[0089] S1: providing a substrate, the substrate including a storage area, a peripheral area, and a transition area between the storage area and the peripheral area, and a first isolation structure in the transition area;

[0090] S2: forming a first trench in the first isolation structure, the depth of the first trench being less than the depth of the first isolation structure.

[0091] As shown in FIGS. 3-4, FIG. 3 shows a top view of the substrate 100, and FIG. 4 shows a cross-sectional view of FIG. 3 in the AA direction. The substrate 100 can include a storage area 101, a transition area 102, and a peripheral area 103 in sequence. The substrate 100 can be a single-layer structure or a multi-layer structure. For example, the substrate 100 can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrate or II / VI semiconductor substrate. Alternatively, the substrate 100 can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium on insulator. The storage area 101 has an active area 104. The storage area 101 can be used to form a word line structure, a bit line structure, and a capacitor structure, etc. The peripheral area 103 is used to form a peripheral circuit structure.

[0092] As shown in FIG. 4, the transition region 102 can be used to separate the storage region 101 and the peripheral region 103, and thus the first isolation structure 105 is formed in the transition region 102. Meanwhile, in order to form the active region 104 in the storage region 101, the second isolation structure 106 and the third isolation structure 107 are formed in the storage region 101. In the AA direction, the width of the first isolation structure 105 is greater than the width of the second isolation structure 106, and the width of the second isolation structure 106 is greater than the width of the third isolation structure 107. In the vertical direction, the depth of the first isolation structure 105 is greater than the depth of the second isolation structure 106, and the depth of the second isolation structure 106 is greater than the depth of the third isolation structure 107. Due to the wide width and the deep depth of the first isolation structure 105, the storage region 101 and the peripheral region 103 are effectively isolated. Meanwhile, due to the wide width of the first isolation structure 105, the end of the subsequently formed trench can be located in the first isolation structure 105, effectively preventing the end of the trench from extending into the peripheral region 103. In some embodiments, the first isolation structure 105, the second isolation structure 106, and the third isolation structure 107 can all be shallow trench isolation structures. The first isolation structure 105 can be filled with silicon oxide, the second isolation structure 106 can be filled with silicon nitride, and the third isolation structure 107 can be filled with silicon oxide.

[0093] As shown in FIGS. 5-7A, in step S2, a patterned photoresist layer 108 is first formed on the substrate 100, covering the storage region 101 and the peripheral region 103, and the patterned photoresist layer 108 has an opening 109 exposing the first isolation structure 105. Then, the etching gas is etched through the opening 109 to the first isolation structure 105, thereby forming a first trench 110 in the first isolation structure 105. Since the first isolation structure 105 extends along the first direction, the first trench 110 extends along the first direction. Meanwhile, since the first isolation structure 105 is not completely etched, in the second direction (AA direction), the width of the first trench 110 is less than the width of the first isolation structure 105, and in the vertical direction, the depth of the first trench 110 is less than the depth of the first isolation structure 105.

[0094] As shown in FIGS. 6-7B, the first trench 110 can include a first sidewall 1101 and a second sidewall 1102. The first sidewall 1101 is close to the storage region 101, and the second sidewall 1102 is close to the peripheral region 103. In the second direction, the width of the first sidewall 1101 is greater than the width of the second sidewall 1102. That is, the first trench 110 is not located at the center of the first isolation structure 105, that is, in the second direction, the first trench 110 is closer to the peripheral region 103. Meanwhile, in the second direction, the opening width W1 of the first trench 110 is greater than the width W2 of the second isolation structure 106. If the opening width W1 of the first trench 110 is small, when the word line trench is formed in the storage region 101 and the transition region 102, the second sidewall 1102 can also block the etching gas, thereby causing the end of the word line trench to be curved. The embodiment of the present disclosure can effectively reduce the influence of the second sidewall 1102 on the etching gas by increasing the opening width W1 of the first trench 110, thereby ensuring the straightness of the end of the word line trench.

[0095] As shown in FIG. 8, FIG. 8 shows a top view of the second trench 111, after the first trench 110 is formed, the second trench 111 can also be formed on the substrate 100. The second trench 111 extends from the storage region 101 to the transition region 102, that is, the end of the second trench 111 is located in the transition region 102. Meanwhile, the end of the second trench 111 extends into the first isolation structure 105 and communicates with the first trench 110. FIG. 8 shows a plurality of second trenches 111, which are insulated from each other and communicate with the first trench 110. In the first direction, the length of the first trench 110 is greater than the length of each second trench 110, and is also greater than the sum of the lengths of all second trenches 110, thereby ensuring that all second trenches 111 communicate with the first trench 110. In the second direction, the second trench 111 is substantially perpendicular to the first trench 110.

[0096] As shown in FIG. 9, FIG. 9 is a cross-sectional view of FIG. 8 in the AA direction. In order to show the relationship between the first trench 110 and the second trench 111, the second trench 111 is shown in FIG. 9, i.e. the position in the dashed line frame in FIG. 9. The etching gas etches the substrate of the storage region 101, and etches the first sidewall 1101 of the first trench 110, thereby forming the second trench 111, and at the same time, the first sidewall 111 is etched, so that the first trench 110 is in communication with the second trench 111. In this embodiment, when the second trench 111 is formed, the first trench 110 has already been formed in the first isolation structure 105, and the second sidewall 1102 is farther away from the first sidewall 1101, so that the first trench 110 can reduce the blocking effect on the etching gas, thereby improving the straightness of the end of the second trench 111. At the same time, since the first trench 110 is in communication with the second trench 111, i.e. the end of the second trench 111 is open, it is beneficial to release the stress of the end of the second trench 111, and further improve the straightness of the end of the second trench 111.

[0097] As shown in FIG. 9, in this embodiment, the bottom surface of the first trench 110 is lower than the bottom surface of the second trench 111, i.e. in the vertical direction, the depth of the first trench 110 is greater than the depth of the second trench 110, thereby preventing the bottom surface of the first trench 110 from blocking the etching gas, and further ensuring the straightness of the second trench 110.

[0098] As shown in FIG. 10, FIG. 10 is a cross-sectional view of FIG. 8 in the BB direction. In the first direction, the second trenches 111 are spaced apart from each other. These second trenches 111 are isolated by the third isolation structure 107. The second trench 111 passes through the second isolation structure 106 and the third isolation structure 107. In the vertical direction, the depth of the second trench 111 is less than the depth of the second isolation structure 106, and the depth of the second trench 111 is less than the depth of the third isolation structure 106, thereby preventing the second trench 111 from extending into the active region and preventing short circuit. In some embodiments, the second trench 111 can be a word line trench.

[0099] As shown in FIG. 11, when the second trench 111 is formed, part of the first sidewall 1101 is etched, so that the height of the first sidewall 1101 is reduced, i.e. in the vertical direction, the top surface of the first sidewall 1101 is lower than the top surface of the second sidewall 1102, the top surface of the first sidewall 101 is higher than the bottom surface of the second trench 111, the top surface of the first sidewall 1101 is flush with the top surface of the storage region 101, and the top surface of the second sidewall 1102 is also flush with the top surface of the peripheral region 103.

[0100] As shown in FIG. 12, FIG. 12 shows a top view after forming the word line conductive layer 114. After forming the second trench 111, the word line conductive layer 112 can be formed in the second trench 111, then the second conductive layer 113 is formed on the word line conductive layer 112, and the protective layer 114 is formed on the second conductive layer 113. The word line conductive layer 112 substantially fills the second trench 111 and the first trench 110. After forming the protective layer 114, the top surface of the protective layer 114 is flush with the top surface of the peripheral region 103.

[0101] As shown in FIG. 13, FIG. 13 shows a cross-sectional view of FIG. 12 in the AA direction. As shown in FIG. 13, the word line conductive layer 112 extends from the memory region 101 into the transition region 102. The word line conductive layer 112 covers the first sidewall 1101, and the top surface of the word line conductive layer 112 is lower than the top surface of the second sidewall 1102. The second conductive layer 113 substantially covers the word line conductive layer 112, and the protective layer 114 substantially covers the second conductive layer 113. In the vertical direction, the thickness of the second conductive layer 113 is less than the thickness of the word line conductive layer 112. The materials of the second conductive layer 113 and the word line conductive layer 112 are different, and their work functions are different. The material of the word line conductive layer 112 can include but is not limited to As (arsenic) or B (boron) doped silicon, P (phosphorus) or As doped germanium, W (tungsten), Ti (titanium), TiN (titanium nitride), or Au (gold). The material of the second conductive layer 113 can include but is not limited to polysilicon. In this embodiment, the thickness of the protective layer 114 is greater than the thickness of the second conductive layer 113, and the top surface of the protective layer 114 is flush with the top surface of the peripheral region 103. The protective layer 114 can be used to protect the second conductive layer 113. The material of the protective layer 114 can include but is not limited to silicon oxide, silicon nitride, or silicon oxynitride.

[0102] As shown in FIGS. 14-15, FIG. 14 shows a top view of forming the insulating layer 115, and FIG. 15 shows a cross-sectional view of FIG. 14 in the AA direction. In order to show the structure of the insulating layer 115, the insulating layer 115 is shown in a dashed box in FIG. 15. In some embodiments, after forming the protective layer 114, the protective layer 114, the second conductive layer 113, and the word line conductive layer 112 in the first trench 110 can be etched, i.e., the protective layer 114, the second conductive layer 113, and the word line conductive layer 112 in the second trench 111 are reserved. After removing the protective layer 114, the second conductive layer 113, and the word line conductive layer 112 in the first trench 110, the insulating layer 115 can be filled in the first trench 110. The top surface of the insulating layer 115 can be flush with the top surface of the peripheral region 103. Since the first trench 110 and the second trench 111 are connected, the word line conductive layers 112 in the first trench 110 and the second trench 111 are also connected. By removing the word line conductive layer 112 in the first trench 110 and reserving the word line conductive layer 112 in the second trench 111, it is ensured that the word line conductive layer 112 is only located in the second trench 111. Since the second trench 112 is isolated, it is ensured that the word line conductive layer 112 located in the second trench 111 is also isolated. Since there is the insulating layer 115 in the first trench 110, the top surface of the insulating layer 115 is higher than the top surface of the word line conductive layer 112, which in turn prevents the connection of these word line conductive layers 112. In this embodiment, the word line conductive layer 112, the second protective layer 113, and the protective layer 114 can be defined as a word line structure.

[0103] As shown in FIG. 16, FIG. 16 shows a top view of forming the word line contact layer 1122. In some embodiments, after forming the word line conductive layer 112, the word line conductive layer 112 in the first trench 110 is etched to form the word line contact layer 116. Meanwhile, the word line conductive layer 112 in the second trench 111 is reserved. As can be seen from FIG. 16, in this embodiment, the word line conductive layer 112 in the first trench 110 is not completely etched. In the first direction, the second trenches 112 are separated by the third isolation structure 107, and in this embodiment, the portion of the word line conductive layer 112 in the first trench 110 corresponding to the third isolation structure 107 is etched to divide the word line conductive layer 112 into a plurality of word line contact layers 116, and then an insulating material is filled in the gap between the word line contact layers 116 to isolate the word line contact layers 116. The word line contact layer 116 is connected with the word line conductive layer 112, and in this embodiment, the word line contact layer 116 and the word line conductive layer 112 can be defined as a word line main body layer 117. Since the word line contact layers 116 are isolated and insulated from each other, and the word line conductive layers 112 are isolated and insulated from each other, the word line main body layers 117 are isolated and independent from each other.

[0104] As shown in FIG. 16, in the first direction, the width of the word line conductive layer 112 etched in the first trench 110 is smaller than the width of the third isolation structure 107, and thus the width of the word line contact layer 116 is greater than the width of the word line conductive layer 112. In the first direction, the gap between the word line contact layers 116 is smaller than the gap between the word line conductive layers 112. In the present embodiment, the gap between the word line conductive layers 112 can be 5-7 nm greater than the gap between the word line contact layers 116. If the gap between the word line contact layers 116 is too small, it is not conducive to filling the insulating material in the word line contact layer 116. The first direction can be perpendicular to the second direction. From the top view, the first direction can be the vertical direction, and the second direction can be the horizontal direction.

[0105] As shown in FIG. 17, FIG. 17 shows the cross-sectional view of FIG. 16 in the AA direction. The word line conductive layer 112 is connected to the word line contact layer 116, and the top surface of the word line conductive layer 112 is flush with the top surface of the word line contact layer 116. Of course, the second conductive layer 113 and the protective layer 114 can also be formed on the word line body layer 117, thereby forming a word line structure.

[0106] As shown in FIG. 15 and FIG. 17, in FIG. 15, the first trench 110 is filled with the insulating layer 115. In FIG. 17, the first trench 110 has the word line contact layer 116, which is connected to the word line conductive layer 112. After forming the word line structure, an interconnection column needs to be formed, which is connected to the word line structure to provide a signal for the word line structure. The present embodiment finds that when the interconnection column is formed in the transition region 102, if the position of the interconnection column is offset, the interconnection column will be offset to the storage region 101. At the same time, since the etching gas will etch part of the word line conductive layer 112, the interconnection column can be in communication with the active region in the storage region 101, thereby forming a short circuit. When the interconnection column is formed using the structure in FIG. 17, the interconnection column can be formed on the word line contact layer 116, which is far away from the storage region 101, so the interconnection column is not easy to offset to the storage region 101. At the same time, the depth of the word line contact layer 116 is greater than the depth of the word line conductive layer 112, and the word line contact layer 116 is below the insulating material, so even if the word line contact layer 116 is etched, it will not be in contact with the active region, thereby preventing the interconnection column from short-circuiting with the active region. Again, in the first direction, the width of the word line contact layer 116 is greater than the width of the word line conductive layer 112, so the offset range of the interconnection column can be increased, and the contact area with the interconnection column can also be increased, thereby reducing the contact resistance.

[0107] As shown in FIGS. 18-19, FIG. 18 shows another cross-sectional view of FIG. 16 in AA direction. In FIG. 18, the word line conductive layer 112 connects the word line contact layer 116, and the top surface of the word line conductive layer 112 is lower than the top surface of the word line contact layer 116. There is also a second conductive layer 113 on the word line conductive layer 112, and the top surface of the second conductive layer 113 is flush with the top surface of the word line contact layer 116. There is also a protective layer 114 on the second conductive layer 113, and the protective layer 114 also covers the word line contact layer 116, so that the top surface of the protective layer 114 is flush with the top surface of the word line contact layer 116. In this embodiment, the word line conductive layer 112 and the word line contact layer 116 can be defined as a word line body layer 117. The word line body layer 117, the second conductive layer 113, and the protective layer 114 can be defined as a word line structure.

[0108] As shown in FIGS. 17-18, in FIG. 17, the top surface of the word line conductive layer 112 is flush with the top surface of the word line contact layer 116. When the interconnection column is formed on the word line contact layer 116, the depth of the interconnection column is large, and the etching time required is long. In FIG. 18, the top surface of the word line conductive layer 112 is lower than the top surface of the word line contact layer 116, so that the depth of the interconnection column can be reduced, the etching time can be reduced, the influence on the sidewall of the interconnection hole can be reduced, and the short circuit between the interconnection columns can be improved.

[0109] As shown in FIG. 20, FIG. 20 shows the electron microscope image of FIG. 8. The rectangular dashed box shows the first trench 110, and the circular dashed box shows the end of the second trench 111. With reference to FIG. 1, the end of the second trench 111 in FIG. 20 communicates with the first trench 110, and the end of the second trench 111 is neat and straight. Therefore, the manufacturing method of the embodiments of the present disclosure can effectively improve the bending of the end of the second trench 111 and improve the performance of the semiconductor structure.

[0110] As shown in FIGS. 8-9, the semiconductor structure according to the embodiments of the present disclosure can include a substrate 100. The substrate 100 can include a storage region 101, a transition region 102 and a peripheral region 103. In the peripheral region 103, there is a first isolation structure 105, and in the first isolation structure 105, there is a first trench 110. The first trench 110 extends along a first direction, and the depth of the first trench 110 is less than the depth of the first isolation structure 105. The first trench 110 can include a first sidewall 1101 and a second sidewall 1102. The first sidewall 1101 is close to the storage region 101, and the second sidewall 1102 is close to the peripheral region 103. The top surface of the first sidewall 1101 is lower than the top surface of the second sidewall 1102. The top surface of the first sidewall 1101 is higher than the bottom surface of the second trench, and the top surface of the second sidewall 1102 is flush with the top surface of the storage region. In the second direction, the width of the first sidewall 1101 is greater than the width of the second sidewall 1102, thereby increasing the distance between the second sidewall 1102 and the storage region 101, and reducing the blocking effect of the second sidewall 1102 on the etching gas. The first trench 110 is formed in the first isolation structure 105 before the second trench 111 is formed, so that when the second trench 111 is formed, the blocking effect of the second sidewall 1102 on the etching gas can be reduced, and the etching gas can be concentrated at the end of the second trench 111, thereby ensuring the straightness of the end of the second trench 111. At the same time, since the end of the second trench 111 is in communication with the first trench 110, the stress at the end of the second trench 111 can be released, and the distortion of the second trench 111 can be reduced. In the substrate 100, there is a second trench 111 extending along the second direction from the storage region 101 to the transition region 102, thereby being in communication with the first trench 110. The first trench 110 is substantially perpendicular to the second trench 111.

[0111] As shown in FIGS. 8-11, in the vertical direction, the depth of the first trench 110 is greater than the depth of the second trench 111, thereby preventing the end of the second trench 111 from being blocked by the bottom surface of the first trench 110, and further improving the straightness of the end of the second trench 111. In the storage region 101, there is also a second isolation structure 106, and the second trench 111 passes through the second isolation structure 106. The width W2 of the second isolation structure 106 is less than the opening width W1 of the first trench 110, thereby reducing the blocking effect of the second sidewall 1102 on the etching gas and improving the flatness of the end of the second trench 111. In the vertical direction, the depth of the first trench 110 is less than the depth of the second isolation structure 106, and the first trench 110 has a certain distance from the underlying active region, thereby preventing short circuit problems.

[0112] As shown in FIG. 15, the embodiment of the disclosure proposes a semiconductor device including a substrate 100, which can include a memory region 101, a transition region 102, and a peripheral region 103. There is a first isolation structure 105 in the transition region 102. A first trench 110 is located in the first isolation structure 105, and a second trench 111 extends along a second direction from the memory region 101 into the transition region 102 to communicate with the first trench 110. There is a word line conductive layer 112 in the second trench 111. An insulating layer 115 is filled in the first trench 110, and a top surface of the insulating layer 115 is higher than a top surface of the word line conductive layer 112. An end of the second trench 111 is neat.

[0113] As shown in FIGS. 16-18, another embodiment of the disclosure proposes a semiconductor device, which is different from that of FIG. 15 in that, in FIGS. 16-18, there is a word line contact layer 116 in the first trench 110, which is connected with the word line conductive layer 112. In the parallel first direction, the width of the word line contact layer 116 is greater than the width of the word line conductive layer 112. In the parallel first direction, the width of the adjacent word line contact layer 116 is less than the width of the adjacent word line conductive layer 112. In FIG. 17, the top surface of the word line conductive layer 112 is flush with the top surface of the word line contact layer 116, and the bottom surface of the word line conductive layer 112 is higher than the bottom surface of the word line contact layer 116. In FIG. 18, the top surface of the word line contact layer 116 is higher than the top surface of the word line conductive layer 112. The word line contact layer 116 is located between the first side wall 1101 and the second side wall 1102, and the top surface of the word line contact layer 116 exceeds the first side wall 1101 and is lower than the second side wall 1102. The function of the word line contact layer 116 can be referred to the above description.

[0114] The above semiconductor device can be applied to an electronic device. The electronic device can include one or more of, for example, a smartphone, a tablet personal computer (PC), a mobile phone, a video phone, an electronic book (e-book) reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MPEG-1 audio layer 3 (MP3) player, a mobile medical device, a camera, a home appliance, a medical device, an Internet of things (IoT) device, and a wearable device. The wearable device can be a type of accessory, a type of fabric or clothing, a type of body attachment, or a type of implantable circuit. The accessory type wearable device can be, for example, a watch, a ring, a bracelet, an anklet, a necklace, glasses, contact lenses, or a head-mounted device (HMD).

[0115] In summary, the present disclosure provides a semiconductor structure and a manufacturing method thereof, and a semiconductor device. The present disclosure forms a first trench in a first isolation structure in a transition region, and then forms a second trench. The first trench can reduce the blocking effect of the etching gas, so that the etching gas near the end of the second trench is relatively uniform, thereby improving the uniformity of the end of the second trench and improving the end distortion problem.

[0116] Secondly, since the second trench is connected with the first trench, the end stress of the second trench can be released, the end bending problem of the second trench can be improved, and the performance of the semiconductor structure can be improved.

[0117] The above merely provides a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate (100) comprising a memory region (101), a peripheral region (103), and a transition region (102) between the memory region and the peripheral region, the transition region having a first isolation structure (105) therein; a first trench (110) in the isolation structure, the first trench extending in a first direction; the first trench having a depth less than a depth of the isolation structure.

2. The semiconductor structure of claim 1, wherein, The first trench comprises: a first sidewall proximate the memory region; a second sidewall proximate the peripheral region; wherein a width of the first sidewall is greater than a width of the second sidewall.

3. The semiconductor structure according to claim 1 or 2, characterized in that Further comprising: a second trench extending in a second direction from the memory region into the transition region; wherein the first trench is in communication with the second trench.

4. The semiconductor structure of claim 3, wherein, The first trench has a depth greater than a depth of the second trench.

5. The semiconductor structure of claim 3, wherein, Further comprising: a second isolation structure, the second trench passing through the second isolation structure; wherein, in the second direction, a width of the first trench is greater than a width of the second isolation structure.

6. The semiconductor structure of claim 5, wherein, The first trench has a depth less than a depth of the second isolation structure.

7. The semiconductor structure of claim 2, wherein, A top surface of the first sidewall is lower than a top surface of the second sidewall, a top surface of the first sidewall is higher than a bottom surface of the second trench, and a top surface of the first sidewall is flush with a top surface of the memory region.

8. A semiconductor device, characterized by Comprising: a substrate (100) comprising a memory region (101), a peripheral region (103), and a transition region (102) between the memory region and the peripheral region, the transition region having a first isolation structure (105) therein; a first trench (110) in the first isolation structure, the first trench extending in a first direction; the first trench having a depth less than a depth of the isolation structure; a second trench (111) extending in a second direction from the memory region into the transition region; a word line conductive layer (112) in the second trench; wherein the first trench is in communication with the second trench.

9. The semiconductor device of claim 8, wherein, Further comprising: an insulating layer substantially filling the first trench; wherein a top surface of the insulating layer is higher than a top surface of the word line conductive layer.

10. The semiconductor device of claim 8, wherein, Further comprising: a word line contact layer in the first trench; wherein the word line contact layer is connected to the word line conductive layer.

11. The semiconductor device of claim 10, wherein, In a direction parallel to the first direction, a width of the word line contact layer is greater than a width of the word line conductive layer.

12. The semiconductor device of claim 10, wherein, In the direction parallel to the first direction, a gap between adjacent word line contact layers is less than a width of adjacent word line conductive layers.

13. The semiconductor device of claim 10, wherein, A bottom surface of the word line contact layer is lower than a bottom surface of the word line conductive layer.

14. The semiconductor device of claim 10, wherein, A top surface of the word line contact layer is higher than a top surface of the word line conductive layer.

15. The semiconductor device of claim 10, wherein, The first trench comprises: a first sidewall proximate the memory region; a second sidewall distal from the memory region; wherein, in a direction parallel to the second direction, a width of the first sidewall is greater than a width of the second sidewall.

16. The semiconductor device of claim 15, wherein, The word line contact layer is between the first sidewall and the second sidewall, a top surface of the word line contact layer is above the first sidewall and below the second sidewall.

17. A method of manufacturing a semiconductor structure, characterized by ； A substrate is provided, which includes a memory region, a peripheral region, and a transition region between the memory region and the peripheral region, and a first isolation structure in the transition region; A first trench is formed in the first isolation structure, and a depth of the first trench is less than a depth of the first isolation structure.

18. The manufacturing method according to claim 17, wherein Further comprising: Etching the memory region and part of the first isolation structure to form a second trench, which extends along a second direction from the memory region into the transition region; Wherein the first trench and the second trench are in communication, the first trench is substantially perpendicular to the second trench, and a depth of the second trench is less than a depth of the first trench.

19. The manufacturing method according to claim 18, wherein Further comprising: Forming a word line conductive layer in the second trench; Forming an insulating layer in the first trench; Wherein a top surface of the insulating layer is higher than a top surface of the word line conductive layer.

20. The manufacturing method according to claim 18, wherein, Further comprising: Forming a word line conductive layer in the second trench, and forming a word line contact layer in the first trench; Wherein the word line conductive layer is connected to the word line contact layer; Wherein in the first direction, a width of the word line contact layer is greater than a width of the word line conductive layer.

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