Semiconductor structure and formation method

Abstract

The present invention provides a semiconductor structure and a formation method. The formation method for the semiconductor structure comprises: providing a substrate, wherein the substrate comprises an SGT device region, a high-voltage device region, and a low-voltage device region, and the high-voltage device region is located between the SGT device region and the low-voltage device region; etching the substrate to form deep trenches at the junction between the SGT device region and the high-voltage device region, at the junction between the high-voltage device region and the low-voltage device region, and in the high-voltage device region; and forming deep trench isolation structures within the deep trenches.

Description

Semiconductor structure and forming method

[0001] The present application claims priority to the Chinese patent application No. 202411022366.9, filed on July 26, 2024, and entitled "Semiconductor structure and forming method", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and forming method. BACKGROUND

[0003] Power integrated ICs are widely used in power management, motor drive, automotive electronics and industrial control fields. BCD refers to the process technology of integrating Bipolar, CMOS, DMOS and various resistors, capacitors and diodes on the same chip, which has the characteristics of low cost, easy packaging, easy design and simpler peripheral chip, and has rapidly developed into the mainstream technology in the field of power ICs. Bipolar transistors in BCD technology have high analog precision and are mainly used in analog circuits, CMOS has high integration and is mainly used in logic circuits, and DMOS has high power (high voltage) characteristics and is often used as a switching function.

[0004] In the prior art, high-voltage devices and low-voltage devices are often integrated in BCD devices, for example, high-voltage devices can be LDMOS devices, high-voltage JFET devices, etc., and low-voltage devices can be low-voltage MOS devices, etc. The discrete gate or shield gate MOSFET is an improved UMOS device, which has faster switching speed and lower switching loss than the UMOS. According to the structure of poly, it can be divided into up and down (UDSGT) and left and right (LRSGT). Among them, the SGT device utilizes the principle of charge balance to reduce the on-resistance by appropriately increasing the doping concentration of the epitaxial layer; the shield gate is used to reduce Cgd / Ciss and improve Dv / dt capability.

[0005] At present, the SGT device and the BCD device are integrated on the same chip in the process technology, and after being integrated together, how to ensure the isolation breakdown voltage between the devices and reduce the difficulty of the process, etc. are the technical problems that need to be solved at present. SUMMARY

[0006] The technical problem solved by the present application is to provide a semiconductor structure and forming method to improve the performance of the semiconductor structure.

[0007] To solve the above problems, the application discloses a forming method of a semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises an SGT device area, a high-voltage device area and a low-voltage device area, and the high-voltage device area is located between the SGT device area and the low-voltage device area; etching the substrate to form a deep trench at the junction of the SGT device area and the high-voltage device area, at the junction of the high-voltage device area and the low-voltage device area and in the high-voltage device area; and forming a deep trench isolation structure in the deep trench.

[0008] Optionally, the method further comprises the following steps: etching the substrate of the SGT device area to form a plurality of gate trenches and a voltage-resistant trench in the substrate of the SGT device area, wherein the voltage-resistant trench is located between the deep trench and the gate trench; forming a voltage-resistant structure in the voltage-resistant trench; and the deep trench structure is the same as the voltage-resistant structure or the deep trench structure is different from the voltage-resistant structure.

[0009] Optionally, the forming method of the deep trench isolation structure comprises the following steps: forming a gate dielectric layer on the sidewall and bottom surface of the gate trench, the sidewall and bottom surface of the voltage-resistant trench and the sidewall and top surface of the deep trench; forming an initial first gate layer on the surface of the gate dielectric layer, wherein the gate dielectric layer and the initial first gate layer fill the gate trench, the voltage-resistant trench and the deep trench, the initial first gate layer and the gate dielectric layer in the deep trench form the deep trench isolation structure, and the initial first gate layer and the gate dielectric layer in the voltage-resistant trench form the voltage-resistant structure.

[0010] Optionally, the method further comprises the following steps: etching back the initial first gate layer in the gate trench to form a first gate layer, wherein the top surface of the first gate layer is lower than the top surface of the gate trench; forming a second isolation layer on the top surface of the first gate layer; and forming a second gate layer on the surface of the second isolation layer, wherein the first gate layer, the second isolation layer and the second gate layer fill the gate trench to form a shielding gate structure.

[0011] Optionally, the forming method of the deep trench isolation structure comprises the following steps: forming a gate dielectric layer on the sidewall and bottom surface of the gate trench, the sidewall and bottom surface of the voltage-resistant trench and in the deep trench, and the gate dielectric layer fills the deep trench to form the deep trench isolation structure.

[0012] Optionally, the method further comprises: forming an initial first gate layer on a surface of the gate dielectric layer in the gate trench and the voltage-resisting trench; the initial first gate layer and the gate dielectric layer filling the gate trench and the voltage-resisting trench, the initial first gate layer and the gate dielectric layer in the voltage-resisting trench forming the voltage-resisting structure; etching back the initial first gate layer in the gate trench to form a first gate layer, a top surface of the first gate layer being lower than a top surface of the gate trench; forming a second isolation layer on the top surface of the first gate layer; and forming a second gate layer on a surface of the second isolation layer, the first gate layer, the second isolation layer, and the second gate layer filling the gate trench.

[0013] Optionally, the method of forming the substrate comprises: providing a substrate; forming a buried oxide layer on a portion of a surface of the substrate in the high-voltage device region; and forming an epitaxial layer on the buried oxide layer and the surface of the substrate.

[0014] Optionally, the method further comprises: forming a deep well region in the substrate in the high-voltage device region, the deep trench isolation structure being between adjacent deep well regions.

[0015] Optionally, the method further comprises: forming a first high-voltage well region in the deep well region, the first high-voltage well region having first doping ions, the deep well region having third doping ions, the first doping ions having a same ion type as the third doping ions; forming a second high-voltage well region on a side of the first high-voltage well region, the second high-voltage well region having second doping ions, the first doping ions having an opposite ion type to the second doping ions, the first high-voltage well region having a smaller doping depth than the second high-voltage well region.

[0016] Optionally, the method further comprises forming an isolation layer in the high-voltage device region and the low-voltage device region, the isolation layer in the high-voltage device region being in the second high-voltage well region on a side of the deep trench isolation structure and in the first high-voltage well region on another side of the deep trench isolation structure.

[0017] Optionally, the method further comprises: forming a first low-voltage well region and a second low-voltage well region adjacent to the first low-voltage well region in the substrate in the low-voltage device region, the first low-voltage well region having fourth doping ions, the second low-voltage well region having fifth doping ions, the fourth doping ions having an opposite ion type to the fifth doping ions, the isolation layer in the low-voltage device region being at a boundary between the first low-voltage well region and the second low-voltage well region.

[0018] Optionally, the method further comprises: forming a first gate structure on the substrate surface of the high-voltage device region, and a part of a bottom surface of the first gate structure is formed on top surfaces of the first high-voltage well region and the second high-voltage well region, and the first gate structure further extends to a top surface of a part of the isolation layer.

[0019] Optionally, the method further comprises: forming a second gate structure on the substrate surface of the low-voltage device region, and the second gate structure is formed on surfaces of the first low-voltage well region and the second low-voltage well region, respectively.

[0020] Correspondingly, the application further provides a semiconductor structure, comprising: a substrate, the substrate comprising an SGT device region, a high-voltage device region and a low-voltage device region, the high-voltage device region being located between the SGT device region and the low-voltage device region; a deep trench located at an intersection of the SGT device region and the high-voltage device region, an intersection of the high-voltage device region and the low-voltage device region and within the high-voltage device region; and a deep trench isolation structure located in the deep trench.

[0021] Optionally, a voltage-withstanding trench is located in the substrate of the SGT device region, and a voltage-withstanding structure is located in the voltage-withstanding trench, and the deep trench structure and the voltage-withstanding structure are the same.

[0022] Compared with the prior art, the technical scheme of the application has the following advantages:

[0023] In the forming method of the semiconductor structure, a deep trench is formed at an intersection of the SGT device region and the high-voltage device region, an intersection of the high-voltage device region and the low-voltage device region and within the high-voltage device region, and a deep trench isolation structure is formed in the deep trench; this arrangement of the deep trench structure at the intersection of the SGT device region and the high-voltage device region, the intersection of the high-voltage device region and the low-voltage device region and within the high-voltage device region replaces the traditional arrangement of a well for isolation at the intersection of the SGT device region and the high-voltage device region, the intersection of the high-voltage device region and the low-voltage device region and within the high-voltage device region, which can reduce the size occupied by the deep trench isolation structure as an isolation and improve the effective area occupancy rate of the chip; on the other hand, the arrangement of the deep trench isolation structure within the high-voltage device region eliminates the risk of the gate structure or the metal layer crossing the same type of well, improves the voltage-withstanding property, and the deep trench and the gate trench and the voltage-withstanding trench in the SGT are formed together, increases the proportion of the number of trenches (the total number of deep trenches, gate trenches and voltage-withstanding trenches), reduces the etching difficulty, improves the stability of etching, and has a wide range of applications.

[0024] Further, the deep trench structure is the same as the voltage-withstanding structure, so that the process flow does not need to be changed, and only the layout design needs to be modified, so that the deep trench is formed at the junction of the SGT device region and the high-voltage device region, the junction of the high-voltage device region and the low-voltage device region, and the high-voltage device region in the process of forming the gate trench and the voltage-withstanding trench in the SGT device region, and the deep trench isolation structure is formed in the deep trench to form isolation, without the need for additional masks, thereby saving cost and simplifying the production process. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1 is a structural schematic diagram of a semiconductor structure in an embodiment;

[0026] FIGS. 2 to 5 are structural schematic diagrams of the semiconductor structure in each step of a forming method of an embodiment of the present application;

[0027] FIG. 6 is a structural schematic diagram of a semiconductor structure in another embodiment of the present application. DETAILED DESCRIPTION

[0028] As described in the background, the performance of the integration of the SGT device and the BCD device in the same chip still needs to be improved.

[0029] Referring to Fig. 1, a semiconductor structure includes a substrate 100, which includes an SGT device region A, a low-voltage device region C, and a high-voltage device region B arranged in sequence; a gate trench 101 in the substrate of the SGT device region A; a first oxide layer 102 on the sidewall of the gate trench 101, a source polysilicon layer 103 in the gate trench 101, an isolation layer 104 on the surface of the source polysilicon layer 103; a gate polysilicon layer 105 on the surface of the isolation layer 104, wherein the gate polysilicon layer 105, the isolation layer 104, and the source polysilicon layer 103 fill the gate trench 101; a voltage-resistant trench 106 in the substrate of the SGT device region A, the sidewall of the voltage-resistant trench 106 having the first oxide layer 102 and the gate polysilicon layer 105 in the voltage-resistant trench 106, the gate polysilicon layer 105 filling the voltage-resistant trench 106; a well region 107 in the substrate of the SGT device region A, the well region 107 being close to the high-voltage device region B; a shallow trench isolation structure 108 in the substrate of the high-voltage device region B, the shallow trench isolation structure 108 being located at the junction of the SGT device region A and the high-voltage device region B and at the junction of the high-voltage device region B and the low-voltage device region C; a deep P well region 109 in the substrate of the high-voltage device region B; a buried oxide layer 110 at the bottom of the deep P well region, the deep P well region 109 having a high-voltage N well region 111 and a high-voltage P well region 112, the high-voltage N well region 111 also being in the substrate of the high-voltage device region B, the bottom of the shallow trench isolation structure 108 having the high-voltage N well region 111; an isolation layer 113 in the high-voltage P well region 112 and the high-voltage N well region 111; the first oxide layer 102 on the high-voltage P well region 112, the gate polysilicon layer 105 on the first oxide layer 102, the gate polysilicon layer 105 also extending to part of the surface of the isolation layer 113; source / drain doped regions 114 in the substrate on both sides of the gate polysilicon layer 105; a low-voltage well region 115 in the substrate of the low-voltage device region C; the first oxide layer 102 on part of the surface of the low-voltage well region 115; the gate polysilicon layer 105 on the surface of the first oxide layer 102, adjacent to the low-voltage well region 115 and separated by the shallow trench isolation structure 108; the source / drain doped regions 114 in the substrate on both sides of the gate polysilicon layer 105.

[0030] The inventors find that the shallow trench isolation structure 108 and the bottom well region 107 (circled in the figure) are used to meet the requirement of isolation breakdown voltage, but the use of well isolation makes the size of the well very large, which results in low chip effective area occupancy rate; meanwhile, the design process prohibits the gate poly or metal layer from crossing the same type of well, and the formation process of the above structure has the problems of etching process difficulty or instability due to the small proportion of the gate trench in the SGT device area A, thereby affecting the final semiconductor structure.

[0031] The inventors find that the deep trench is formed at the junction of the SGT device area and the high-voltage device area, the junction of the high-voltage device area and the low-voltage device area, and within the high-voltage device area, and the deep trench isolation structure is formed in the deep trench; this deep trench structure at the junction of the SGT device area and the high-voltage device area, the junction of the high-voltage device area and the low-voltage device area, and within the high-voltage device area replaces the traditional method of using well isolation at the junction of the SGT device area and the high-voltage device area, the junction of the high-voltage device area and the low-voltage device area, and within the high-voltage device area, which on the one hand can reduce the size of the deep trench isolation structure as isolation, improve the chip effective area occupancy rate; on the other hand, the deep trench isolation structure in the high-voltage device area eliminates the risk of the gate structure or the metal layer crossing the same type of well, improves the withstand voltage, and the deep trench and the gate trench and the withstand voltage trench in the SGT are formed together, which increases the proportion of the total number of trenches (deep trenches, gate trenches and withstand voltage trenches), reduces the etching difficulty, improves the etching stability, and has a wide range of applications.

[0032] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0033] First, please refer to Figure 2, which provides a substrate 200, which includes an SGT device area A, a high-voltage device area B and a low-voltage device area C, the high-voltage device area B is located between the SGT device area A and the low-voltage device area C.

[0034] In this embodiment, the substrate 200 includes a substrate 201, a buried oxygen layer 202 formed in the high-voltage device area B, and an epitaxial layer 203 formed on the surface of the substrate 201 and the surface of the buried oxygen layer 202.

[0035] In the embodiment, the low-voltage device region C can include one or more PMOS regions and NMOS regions, i.e., the low-voltage device region C is a device region including a plurality of CMOS tubes, and the working voltage of the CMOS tubes in the device region can be 5V; the high-voltage device region B can include one or more NLDMOS regions and PLDMOS regions, i.e., the high-voltage device region B is a device region including a plurality of LDMOS tubes, and the working voltage in the device region can be 40V.

[0036] In the embodiment, the material of the substrate 201 is silicon.

[0037] In other embodiments, the material of the substrate 201 can also be germanium (Ge), germanium-silicon (SiGe), silicon carbide (SiC), germanium-silicon-carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, also including a multilayer structure composed of these semiconductors, etc., or can also be a double-side polished wafer (DSP), and can also be a ceramic substrate such as aluminum oxide, a quartz or glass substrate, etc.

[0038] Referring to FIG. 3, the high-voltage device region B is subjected to first ion implantation to form a deep well region (DPW) 204, and second ion implantation is performed in the deep well region (DPW) 204 to form a first high-voltage well region (HVPW) 205, the first high-voltage well region (HVPW) 205 has first doping ions, the deep well region (DPW) 204 has third doping ions, the ion type of the first doping ions is the same as the ion type of the third doping ions; a second high-voltage well region (HVNW) 206 is formed on one side of the first high-voltage well region (HVPW) 205, the second high-voltage well region (HVNW) 206 has second doping ions, the ion type of the first doping ions is opposite to the ion type of the second doping ions, and the doping depth of the first high-voltage well region (HVPW) 205 is less than the doping depth of the second high-voltage well region (HVNW) 206.

[0039] In the embodiment, the third doping ions are P-type ions, the first doping ions are P-type ions, and the second doping ions are N-type ions.

[0040] In the embodiment, at least two deep well regions (DPW) 204 are formed in the high-voltage device region B, one of the deep well regions (DPW) 204 is located above the buried oxide layer 202.

[0041] Please continue to refer to Figure 3, a first low-voltage well region 207 and a second low-voltage well region 208 adjacent to the first low-voltage well region 207 are formed in the substrate 200 of the low-voltage device region C, the first low-voltage well region 207 has fourth doping ions therein, the second low-voltage well region 208 has fifth doping ions therein, the ion type of the fourth doping ions is opposite to the ion type of the fifth doping ions.

[0042] In the embodiment, the fourth doping ions are P-type ions, and the fifth doping ions are N-type ions.

[0043] Please refer to Figure 4, the substrate 200 is etched to form a deep trench 209 at the junction of the SGT device region A and the high-voltage device region B, at the junction of the high-voltage device region B and the low-voltage device region C, and in the high-voltage device region B.

[0044] The deep trench 209 can play a good isolation role, and will not cause the phenomenon of etching through due to etching too deep, and at the same time ensures that the deep trench 209 can be well filled with a medium to form a deep trench isolation structure.

[0045] In the embodiment, please continue to refer to Figure 4, further comprising: etching the substrate 200 of the SGT device region A to form a plurality of gate trenches 210 and a voltage-resistant trench 211 in the substrate 200 of the SGT device region A, the voltage-resistant trench 211 is located between the deep trench 209 and the gate trench 210.

[0046] In the embodiment, the gate trench 210, the voltage-resistant trench 211 and the deep trench 209 are formed in the same mask, so that an additional mask is not needed in the process of forming the deep trench 209, and the cost is not increased, at the same time, the proportion of the number of trenches (the total number of the deep trench 209, the gate trench 210 and the voltage-resistant trench 211) is increased, the process etching difficulty is reduced, the etching stability is improved, and the application range is wider.

[0047] Please refer to Figure 5, a deep trench isolation structure 212 is formed in the deep trench 209, and a voltage-resistant structure 213 is formed in the voltage-resistant trench 211, the deep trench isolation structure 212 is the same as the voltage-resistant structure 213.

[0048] In the embodiment, the forming method of the deep trench isolation structure 212 includes: forming a gate dielectric layer 214 on the sidewall and bottom surface of the gate trench 210, the sidewall and bottom surface of the voltage trench 211, and the sidewall and top surface of the deep trench 209; forming an initial first gate layer 215 on the surface of the gate dielectric layer 214, the gate dielectric layer 214 and the initial first gate layer 215 filling the gate trench 210, the voltage trench 211 and the deep trench 209, the initial first gate layer 215 and the gate dielectric layer 214 in the deep trench 209 forming the deep trench isolation structure 212, and the initial first gate layer 215 and the gate dielectric layer 214 in the voltage trench 211 forming the voltage structure 213; etching back the initial first gate layer 215 in the gate trench 210 to form a first gate layer 216, the top surface of the first gate layer 216 being lower than the top surface of the gate trench 210; forming a second isolation layer 217 on the top surface of the first gate layer 216; forming a second gate layer 218 on the surface of the second isolation layer 217, the first gate layer 216, the second isolation layer 217 and the second gate layer 218 filling the gate trench 210 to form a shielding gate structure.

[0049] In the embodiment, the material of the gate dielectric layer 214 includes silicon oxide.

[0050] In the embodiment, the material of the initial first gate layer 215 and the material of the second gate layer 218 are polysilicon.

[0051] In the embodiment, the forming position of the deep trench 209 is the same as that of the conventional well and shallow trench isolation structure, only the structure as an isolation is changed, so that the process flow does not need to be replaced, and only the layout design needs to be updated.

[0052] In the embodiment, the deep trench isolation structure 212 is between adjacent deep well regions 204, so that the required isolation is formed in the high-voltage device region B.

[0053] In other embodiments, referring to FIG. 6, the deep trench isolation structure 212 is different from the voltage structure 213.

[0054] In the embodiment, the forming method of the deep trench isolation structure 212 includes forming a gate dielectric layer 214 in the sidewall and bottom surface of the gate trench 210, the sidewall and bottom surface of the voltage resistance trench 211 and the deep trench 209, the gate dielectric layer 214 fills the deep trench 209 to form the deep trench isolation structure 212; forming an initial first gate layer 215 on the surface of the gate dielectric layer 214 in the gate trench 210 and the voltage resistance trench 211; the initial first gate layer 215 and the gate dielectric layer 214 fill the gate trench 210 and the voltage resistance trench 211, the initial first gate layer 215 and the gate dielectric layer 214 in the voltage resistance trench 211 form the voltage resistance structure 213; etching back the initial first gate layer 215 in the gate trench 210 to form a first gate layer 216, the top surface of the first gate layer 216 is lower than the top surface of the gate trench 210; forming a second isolation layer 217 on the top surface of the first gate layer 216; forming a second gate layer 218 on the surface of the second isolation layer 217, the first gate layer 216, the second isolation layer 217 and the second gate layer 218 fill the gate trench 210.

[0055] In the embodiment, the deep trench isolation structure 212 is the gate dielectric layer 214 filled in the deep trench 209, and the voltage resistance structure 213 is the gate dielectric layer 214 filled in the bottom and sidewall surface of the voltage resistance trench 211 and the initial first gate layer 215 on the surface of the gate dielectric layer 214, although the deep trench isolation structure 212 and the voltage resistance structure 213 are different, but the deep trench isolation structure 212 and the voltage resistance structure 213 have part of the forming process coincides, so it is not necessary to change the process or add process to form the deep trench isolation structure 212, has the wider application range.

[0056] Please continue to refer to Figure 5, also includes a first isolation layer 219 formed in the high voltage device region B and the low voltage device region C, the first isolation layer 219 of the high voltage device region B is located in the second high voltage well region (HVNW) 206 on one side of the deep trench isolation structure 212 and the first high voltage well region (HVPW) 205 on the other side of the deep trench isolation structure 212.

[0057] In the embodiment, the first isolation layer 219 protrudes from the surface of the epitaxial layer 203, the first isolation layer 219 is also located on the top surface of the deep trench isolation structure 212, the top surface of the voltage resistance structure 213, and between the first low voltage well region 207 and the second low voltage well region 208.

[0058] Please continue to refer to Figure 5, further comprising: forming a first gate structure 220 on the surface of the substrate 200 in the high voltage device region B, part of the bottom surface of the first gate structure 220 is formed on the top surface of the first high voltage well region 205 and the second high voltage well region (HVNW) 206, and the first gate structure 220 also extends to the top surface of part of the first isolation layer 219; forming a second gate structure 221 on the surface of the substrate 200 in the low voltage device region C, and the second gate structure 221 is formed on the surface of the first low voltage well region 207 and the second low voltage well region 208 respectively.

[0059] In the embodiment, a source-drain doped layer 221 is also formed in the substrate on both sides of the first gate structure 220, the second gate structure 221 and the shielding gate structure, and the type of the doped ions in the source-drain doped layer 221 is selected according to actual process requirements.

[0060] Correspondingly, the application also provides a semiconductor structure, comprising a substrate 200, the substrate 200 comprising an SGT device region A, a high voltage device region B and a low voltage device region C, the high voltage device region B being located between the SGT device region A and the low voltage device region C; a deep trench 209 located at the junction of the SGT device region A and the high voltage device region B, the junction of the high voltage device region B and the low voltage device region C and in the high voltage device region B; and a deep trench isolation structure 212 located in the deep trench 209.

[0061] In the embodiment, the deep trench isolation structure 212 is arranged at the junction of the SGT device region A and the high voltage device region B, the junction of the high voltage device region B and the low voltage device region C and in the high voltage device region B, which replaces the traditional method of arranging a well for isolation at the junction of the SGT device region A and the high voltage device region B, the junction of the high voltage device region B and the low voltage device region C and in the high voltage device region B, which on the one hand can reduce the size occupied by the deep trench isolation structure 212 as an isolation and improve the effective area occupancy rate of the chip; on the other hand, arranging the deep trench isolation structure 212 in the high voltage device region B eliminates the risk of the gate structure or the metal layer crossing the same type of well, improves the withstand voltage, and the deep trench 209 and the gate trench 210 and the withstand voltage trench 211 in the SGT are formed together, which increases the proportion of the total number of trenches (the total number of the deep trench 209, the gate trench 210 and the withstand voltage trench 211), reduces the process etching difficulty, improves the etching stability, and has a wide range of applications.

[0062] In the embodiment, the voltage-resisting groove 211 is located in the substrate 200 of the SGT device region A, the voltage-resisting structure 213 is located in the voltage-resisting groove 211, and the deep trench isolation structure 212 is the same as the voltage-resisting structure 213.

[0063] In the embodiment, the deep trench isolation structure 212 is the same as the voltage-resisting structure 213, so that the process flow does not need to be changed, and only the layout design needs to be modified, so that the deep trench 209 is formed at the junction of the SGT device region A and the high-voltage device region B, at the junction of the high-voltage device region B and the low-voltage device region C, and in the high-voltage device region B during the formation of the gate trench 210 and the voltage-resisting groove 211 in the SGT device region A, and the deep trench isolation structure 212 is formed in the deep trench 209 to form isolation, without the need for additional masks, thereby saving costs and simplifying the production process.

[0064] In other embodiments, the deep trench isolation structure 212 and the voltage-resisting structure 213 can also be different, but the deep trench isolation structure 212 can be formed together with the voltage-resisting structure 213, without the need for additional masks and without the need for changing the process flow.

[0065] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a substrate, the substrate comprising an SGT device region, a high-voltage device region, and a low-voltage device region, the high-voltage device region being located between the SGT device region and the low-voltage device region; etching the substrate to form a deep trench at the junction of the SGT device region and the high-voltage device region, at the junction of the high-voltage device region and the low-voltage device region, and within the high-voltage device region; forming a deep trench isolation structure within the deep trench.

2. The method of forming a semiconductor structure of claim 1, wherein, The method further comprises: etching the substrate of the SGT device region to form a plurality of gate trenches and a voltage-withstanding trench within the substrate of the SGT device region, the voltage-withstanding trench being located between the deep trench and the gate trenches, forming a voltage-withstanding structure within the voltage-withstanding trench, the deep trench structure being the same as or different from the voltage-withstanding structure.

3. The method of forming a semiconductor structure of claim 2, wherein, The method of forming the deep trench isolation structure comprises: forming a gate dielectric layer on the sidewall and bottom surface of the gate trench, the sidewall and bottom surface of the voltage-withstanding trench, and the sidewall and top surface of the deep trench, forming an initial first gate layer on the surface of the gate dielectric layer, the gate dielectric layer and the initial first gate layer filling the gate trench, the voltage-withstanding trench, and the deep trench, the initial first gate layer and the gate dielectric layer within the deep trench constituting the deep trench isolation structure, the initial first gate layer and the gate dielectric within the voltage-withstanding trench constituting the voltage-withstanding structure.

4. The method of forming a semiconductor structure of claim 3, wherein The method further comprises: etching back the initial first gate layer within the gate trench to form a first gate layer, the top surface of the first gate layer being lower than the top surface of the gate trench, forming a second isolation layer on the top surface of the first gate layer, forming a second gate layer on the surface of the second isolation layer, the first gate layer, the second isolation layer, and the second gate layer filling the gate trench to form a shield gate structure.

5. The method of forming a semiconductor structure of claim 2, wherein, The method of forming the deep trench isolation structure comprises: forming a gate dielectric layer on the sidewall and bottom surface of the gate trench, the sidewall and bottom surface of the voltage-withstanding trench, and within the deep trench, the gate dielectric layer filling the deep trench to constitute the deep trench isolation structure.

6. The method of forming a semiconductor structure of claim 5, wherein, The method further comprises: forming an initial first gate layer on the surface of the gate dielectric layer within the gate trench and the voltage-withstanding trench; the initial first gate layer and the gate dielectric layer filling the gate trench and the voltage-withstanding trench, the initial first gate layer and the gate dielectric layer within the voltage-withstanding trench constituting the voltage-withstanding structure, etching back the initial first gate layer within the gate trench to form a first gate layer, the top surface of the first gate layer being lower than the top surface of the gate trench, forming a second isolation layer on the top surface of the first gate layer, forming a second gate layer on the surface of the second isolation layer, the first gate layer, the second isolation layer, and the second gate layer filling the gate trench.

7. The method of forming a semiconductor structure of claim 1, wherein, The method of forming the substrate comprises: providing a substrate, forming a buried oxygen layer on a portion of the surface of the substrate in the high-voltage device region, forming an epitaxial layer on the surface of the buried oxygen layer and the substrate.

8. The method of forming a semiconductor structure of claim 3, wherein, The method further comprises: The deep trench isolation structure is located between the deep well regions in the high voltage device region.

9. The method of forming a semiconductor structure of claim 8, wherein, Further comprising: A first high voltage well region is formed in the deep well region, the first high voltage well region has first doping ions, the deep well region has third doping ions, the ion type of the first doping ions is the same as the ion type of the third doping ions; a second high voltage well region is formed on one side of the first high voltage well region, the second high voltage well region has second doping ions, the ion type of the first doping ions is opposite to the ion type of the second doping ions, and the doping depth of the first high voltage well region is less than the doping depth of the second high voltage well region.

10. The method of forming a semiconductor structure of claim 9, wherein, Further comprising an isolation layer formed in the high voltage device region and the low voltage device region, the isolation layer of the high voltage device region is located in the second high voltage well region on one side of the deep trench isolation structure and in the first high voltage well region on the other side of the deep trench isolation structure.

11. The method of forming a semiconductor structure of claim 10, wherein Further comprising: A first low voltage well region and a second low voltage well region adjacent to the first low voltage well region are formed in the substrate of the low voltage device region, the first low voltage well region has fourth doping ions, the second low voltage well region has fifth doping ions, the ion type of the fourth doping ions is opposite to the ion type of the fifth doping ions, and the isolation layer of the low voltage device region is located at the junction of the first low voltage well region and the second low voltage well region.

12. The method of forming a semiconductor structure of claim 10, wherein, Further comprising: A first gate structure is formed on the surface of the substrate of the high voltage device region, part of the bottom surface of the first gate structure is formed on the top surface of the first high voltage well region and the second high voltage well region, and the first gate structure further extends to the top surface of part of the isolation layer.

13. The method of forming a semiconductor structure of claim 11, wherein Further comprising: A second gate structure is formed on the surface of the substrate of the low voltage device region, the second gate structure is formed on the surface of the first low voltage well region and the second low voltage well region respectively.

14. A semiconductor structure, characterized by Comprising: A substrate, the substrate comprising an SGT device region, a high voltage device region and a low voltage device region, the high voltage device region being located between the SGT device region and the low voltage device region; A deep trench located at the junction of the SGT device region and the high voltage device region, the junction of the high voltage device region and the low voltage device region, and the high voltage device region; A deep trench isolation structure located in the deep trench.

15. The semiconductor structure of claim 14, wherein, A voltage resistance groove located in the substrate of the SGT device region, a voltage resistance structure located in the voltage resistance groove, the deep trench structure and the voltage resistance structure are the same.

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