Semiconductor device and manufacturing method therefor

Abstract

The present application relates to the technical field of semiconductors, and in particular to a semiconductor device manufacturing method and a semiconductor device. The method comprises: providing a substrate ingot, and grinding the substrate ingot to obtain a rod-shaped body, the rod-shaped body having a cross section of a predetermined shape; removing impurities on the surface of the rod-shaped body; performing photolithography on the circumferential surface of the rod-shaped body, and depositing a functional film layer; performing electroplating processing at preset positions of the functional film layer to form electroplated electrodes on the surface of the semiconductor functional film layer, and performing electroplating at preset positions of the rod-shaped body to form conductive circuits, thereby forming a plurality of chips on the circumferential surface of the rod-shaped body; stripping the residual impurities and photoresist on the surface of the rod-shaped body; testing the plurality of chips formed on the rod-shaped body; and electrically connecting the chips to a circuit board to obtain a semiconductor device having a plurality of chips formed on the circumferential surface. In the present application, by forming a plurality of chips on the circumferential surface of a rod-shaped body, heat is dissipated to the surroundings during operation of the chips, which is more conducive to solving the problem of heat dissipation of multiple chips.

Description

Semiconductor device and manufacturing method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of chip manufacturing, in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] With the rapid development of technology, often need multi-chip cooperation to achieve higher level of function or larger scale processing capability. The following are some common devices and applications that require multi-chip cooperation. For example, supercomputers are usually composed of thousands or even millions of processor chips for simultaneous large-scale parallel computing tasks. Data center servers require multiple processor chips to support high-performance and high-capacity data processing and storage. Artificial intelligence and machine learning systems usually require multiple chips for parallel computing and model training to provide faster and more accurate results. Network switches and routers require multiple chips to process network data traffic, routing and forwarding, and security functions. Automotive electronics systems: electronic systems in modern cars require multiple chips to support vehicle control, safety features, entertainment systems, etc.

[0003] Currently, for devices that require multiple chips, the single chip is usually packaged first and then integrated onto a circuit board, and the circuit will become complex, so it will occupy a large planar space. Or stack packaging of multiple chips, but heat dissipation is also a problem to be faced, so the manufacturing process of multiple chips is more challenging. SUMMARY

[0004] In order to solve the above problems, the present application provides a semiconductor device manufacturing method.

[0005] The semiconductor device manufacturing method provided by the present application adopts the following technical scheme: grinding: providing a substrate crystal bar, grinding the circumferential surface of the substrate crystal bar to obtain a rod-shaped body, the rod-shaped body has a predetermined shape cross section, and the surface of the rod-shaped body after grinding treatment is a smooth surface; cleaning: removing impurities on the surface of the rod-shaped body; coating: photoetching the circumferential surface of the rod-shaped body and coating a functional film layer; electroplating: electroplating treatment is carried out at a predetermined position of the functional film layer, an electroplating electrode is formed on the surface of the semiconductor functional film layer, and a conductive circuit is formed by electroplating at a predetermined position of the rod-shaped body, thereby obtaining a rod-shaped body with multiple chips on the circumferential surface; surface treatment: stripping the impurities and photoresist remaining on the surface of the rod-shaped body; testing: testing the multiple chips formed on the rod-shaped body; and welding: providing a circuit board, electrically connecting the chips with the circuit board, and obtaining a semiconductor device with multiple chips distributed on the circumference.

[0006] In one of the embodiments, the predetermined shape of the cross section is semi-circular, circular, square, quasi-circular or quasi-square.

[0007] In one of the embodiments, the grinding step is followed by a step of providing a self-tension support frame, the self-tension support frame comprising a base and support heads at opposite ends of the base, the substrate wafer is fixed to the self-tension support frame, and opposite ends of the substrate wafer are clamped to the two support heads respectively.

[0008] By using the above-mentioned solution, the self-tension support frame can keep the substrate wafer in a straightened state all the time, avoiding the problem of stress concentration and reduced processing accuracy.

[0009] In one of the embodiments, the step of providing the carrier further comprises providing a position adjustment mechanism configured to drive the self-tension support frame to move in parallel and rotate.

[0010] In one of the embodiments, in the step of coating, the provided photoetching equipment comprises a laser, a mask and a projection lens group, the mask is arranged between the laser and the projection lens group, and the projection lens group comprises at least three concave mirrors, the diameters of the three concave mirrors are sequentially reduced on the light path of the laser.

[0011] By using the above-mentioned solution, the diffraction phenomenon generated in the photoetching process can be reduced, and the processing accuracy can be improved.

[0012] In one of the embodiments, the functional film layer is used to form any one or a combination of LED light-emitting chips, memory chips, sensor chips or control chips.

[0013] In one of the embodiments, the circumferential surface of the rod-shaped body is defined with a first region and a second region, the first region and the second region are respectively used to form a normal chip and a flip chip.

[0014] In one of the embodiments, the diameter of the substrate wafer is 0.1mm-300mm.

[0015] In summary, the present application includes at least one of the following beneficial technical effects: 1. The present application forms a plurality of chips on the circumferential surface of the rod-shaped body through a chip manufacturing process. When the chips are working, heat is dissipated in all directions. Compared with the semiconductor device formed by the multi-chip layering arrangement in the prior art, the scheme of the present application is more conducive to solving the problem of heat dissipation of multi-chip; 2. The substrate for manufacturing the chip structure in the present application is a substrate crystal bar. Since the diameter is much smaller than the conventional size of the wafer, the vacuum space required for coating is small, which facilitates the realization of a smaller vacuum degree in a smaller space and reduces the coating cost; 3. The substrate for manufacturing the chip structure in the present application is a rod-shaped body formed by grinding the substrate crystal bar. Compared with the wafer sheet body in the prior art, the rod-shaped body has a low degree of dependence on the thermal expansion and contraction of the equipment; 4. The substrate for manufacturing the chip structure in the present application is a substrate crystal bar. Compared with the wafer in the prior art, the arc-shaped surface is easier to achieve the precision requirement of grinding; or in other words, for the arc-shaped surface, the precision will only affect part of the chips; 5. The substrate for manufacturing the chip structure in the present application is a substrate crystal bar. When moving, only the rotation and axial movement of the substrate crystal bar need to be controlled, which is two dimensions. Compared with the related art which uses a wafer to manufacture a chip and needs to control three dimensions, the coating precision and grinding precision of the present application are easier to control. BRIEF DESCRIPTION OF DRAWINGS

[0016] FIG. 1 is a flowchart of a semiconductor device manufacturing method according to an embodiment of the present application; FIG. 2 is a structural diagram of a grinding device according to an embodiment of the present application; FIG. 3 is a structural diagram of a self-tension support frame used in the semiconductor device manufacturing method according to FIG. 1; FIG. 4 is a lithography diagram of the semiconductor device manufacturing method according to FIG. 1; FIG. 5 is a structural diagram of a semiconductor device formed by using the semiconductor device manufacturing method according to FIG. 1;

[0017] FIG. 1 is a flowchart of a semiconductor device manufacturing method according to an embodiment of the present application; FIG. 2 is a structural diagram of a grinding device according to an embodiment of the present application; FIG. 3 is a structural diagram of a self-tension support frame used in the semiconductor device manufacturing method according to FIG. 1; FIG. 4 is a lithography diagram of the semiconductor device manufacturing method according to FIG. 1; FIG. 5 is a structural diagram of a semiconductor device formed by using the semiconductor device manufacturing method according to FIG. 1; DETAILED DESCRIPTION

[0018] The present application will be further described in detail below with reference to FIGS. 1-6.

[0019] The present application discloses a semiconductor device manufacturing method and a semiconductor device manufactured by the method.

[0020] Referring to FIG. 1, the method for manufacturing a semiconductor device provided in the present application comprises: S1, polishing and grinding, providing a substrate crystal bar, polishing and grinding the substrate crystal bar to obtain a bar body 1, the bar body 1 has a predetermined shape of cross section, and the surface of the bar body 1 after the grinding treatment is a smooth surface, the grinding flatness difference of each position is less than or equal to 3 nm; finally, the diameter of the obtained bar body 1 is 0.1 mm-300 mm, preferably 10-60 mm. The bar material with smaller diameter is less likely to be broken compared with the large diameter layer structure required for manufacturing a wafer, and is easier to produce, reducing the difficulty of production. In the embodiment, the provided substrate crystal bar is any one of a silicon-based crystal bar, a gallium arsenide crystal bar or a sapphire crystal bar.

[0021] In the present application, referring to FIG. 2, the grinding device comprises a workbench 7 and a plurality of grinding heads 8 fixed with the workbench 7, the plurality of grinding heads are distributed along the same circumference. The grinding head 8 is telescopic and adjustable to adapt to the grinding of substrate crystal bars with different diameters. In a possible embodiment, the grinding heads 8 can also be uniformly distributed on the same circumference. The uniform distribution of the grinding heads 8 on the circumference can provide more consistent grinding pressure and speed, avoid local over-grinding or under-grinding, and improve the grinding quality; in addition, the plurality of grinding heads can more evenly distribute the heat generated during the grinding process, which helps to prevent local overheating and protect the crystal bar material. In the present application, an ultrasonic probe 9 is also arranged on the workbench 7, and the ultrasonic probe 9 can measure the grinding accuracy of the substrate crystal bar. The substrate crystal bar can rotate around the shaft to enable the ultrasonic probe 9 to detect the grinding accuracy in real time. In actual grinding, the telescopic mechanism of the grinding head 8 and the measurement data of the ultrasonic probe 9 are integrated into a closed-loop control system, and during the grinding process, the ultrasonic probe 9 measures the grinding accuracy of the substrate crystal bar in real time and feeds back the data to the control system, and the control system automatically adjusts the pressure, speed and telescopic position of the grinding head according to the measurement results of the ultrasonic probe to achieve the best grinding effect. The telescopic mechanism of the grinding head is designed to ensure that it can accurately move according to the instructions of the control system, achieving micron-level or even nanometer-level adjustment.

[0022] In order to meet the grinding of substrate crystal bars with different cross-sectional shapes, the shape of the grinding head 8 can be adjusted according to actual needs.

[0023] In the embodiment, the provided substrate crystal bar is a semiconductor material, and before coating, ion implantation is performed on the preset position of the substrate crystal bar.

[0024] Referring to FIGS. 6(A)-6(D), in the embodiment, the cross section of the rod-shaped body 1 after grinding of the provided substrate crystal rod can be semicircular, circular, square, quasi-circular, or quasi-square. The cross section shape of the rod-shaped body 1 can be selected according to actual scenarios to achieve maximum utilization of the substrate crystal rod. For example, in FIG. 6(A), the cross section shape of the rod-shaped body 1 is circular; in FIG. 6(B), the cross section shape of the rod-shaped body is quasi-circular; in FIG. 6(C), the cross section shape of the rod-shaped body 1 is quasi-square; and in FIG. 6(D), the cross section shape of the rod-shaped body 1 is square.

[0025] Referring to FIG. 3, in the embodiment, after step S1, a self-tension support frame 5 is further provided, the self-tension support frame 5 including a base 50 and support heads 52 at opposite ends of the base 50, the substrate crystal rod is fixed to the self-tension support frame 5, and opposite ends of the substrate crystal rod are respectively clamped in the two support heads 52. The substrate crystal rod is fixed by using the self-tension support frame 5, and the substrate crystal rod can rotate relative to the self-tension support frame 5, so that the chip process of the substrate crystal rod can be performed. The self-tension support frame 5 can always keep the substrate crystal rod in a straightened state.

[0026] The self-tension support frame 5 is further provided with a position adjustment mechanism (not shown in the figure), which is configured to drive the self-tension support frame 5 to move in parallel and rotate. The position adjustment mechanism is used to rotate and translate the substrate crystal rod in each link of photolithography, film coating, and electroplating. Compared with the related art, the traditional three-dimensional position adjustment mechanism needs to control multiple axes at the same time, which requires the control system to be able to accurately synchronize and coordinate the actions of multiple motion axes. In order to achieve photolithography, the position adjustment mechanism needs to move in three-dimensional space and needs to control the motion of XYZ three dimensions; the technical solution of the present application only needs two dimensions, one is the translation dimension, and the other is the rotation dimension, the control dimension is reduced by one dimension, and the difficulty is reduced by one level. This simplification not only makes the control algorithm more intuitive and easy to implement, but also reduces the complexity of the electronic and mechanical system, thereby reducing the manufacturing cost and maintenance cost of the overall system.

[0027] Semiconductor wafers are typically available in standard wafer sizes and / or thicknesses. For example, standard wafer diameters can be 2 inches (50 mm), 4 inches (100 mm), or 6 inches (150 mm). For silicon carbide wafers, standard wafer thicknesses can be, for example, at least 0.1% or at least 0.15% of the standard wafer diameter (e.g., 350 pm for a 6-inch wafer).

[0028] In the related art, when a wafer is used to manufacture a chip, since the thickness of the wafer is small, the difference in polishing flatness of each position of the whole wafer needs to reach 3nm or below, and the control of polishing precision directly determines the quality of the chip, which makes the process of the semiconductor wafer more complex and the yield is affected. In the present embodiment, since a rod-shaped wafer is used to manufacture a chip, the shape of the polishing head required can be an arc-shaped or semicircular polishing head matching the size of the rod-shaped body 1. The arc-shaped or semicircular polishing head can completely wrap the peripheral surface of the rod-shaped body 1 for polishing, and can also be vertically polished, so that the polishing precision can be more clearly judged from the imaging mechanism, and thus the precision is higher.

[0029] S2, cleaning, removing impurities on the surface of the rod-shaped body; S3, film plating, photoetching the peripheral surface of the rod-shaped body and plating a functional film layer; the film plating method includes chemical vapor deposition and / or physical vapor deposition. Please refer to FIG. 4, in the present embodiment, the photoetching device 6 includes a laser 60, a mask plate 62 and a projection lens group 64. The mask plate 62 is arranged between the laser 60 and the projection lens group 64. In the present embodiment, the projection lens group 64 includes at least three concave mirrors. In the present embodiment, the projection lens group 64 schematically includes a first, a second and a third concave mirror along the light path. The diameters of the three concave mirrors are sequentially reduced on the light path of the laser 60. The first concave mirror converges the light beam emitted by the laser 60, and then the second and third concave mirrors gradually further converge the light beam, and finally a focus point is formed on the rod-shaped body 1 to process the rod-shaped body 1. The material of the concave mirror is silicon-molybdenum concave mirror.

[0030] The use of concave mirrors can effectively reduce diffraction when processing the rod-shaped body 1, and can improve the precision of photoetching. Because the rod-shaped body 1 is convex or convex arc, the possibility of diffraction is smaller than that of a flat wafer. This is because on the convex or arc surface, the propagation path of light is more complex than that on the flat surface, and there are usually more reflections and refractions, which make the phase distribution of light more complex and weaken the diffraction effect. In addition, for a curved surface, the incident angle of the incident light changes with the position, which causes the light at different positions to experience different optical path differences, thereby reducing the influence of the diffraction effect. Therefore, the diffraction effect on the convex or arc surface is usually smaller than that on the flat surface. Diffraction will cause the pattern to be blurred and distorted during photoetching, which limits the resolution of photoetching, so the occurrence of diffraction phenomenon should be avoided during photoetching.

[0031] The light beam emitted by the laser 60 passes through the projection lens group 64, and the lens further focuses and reduces the pattern on the light beam to form the extreme ultraviolet light, which irradiates the rod-shaped body 1, that is, the light passing through the projection lens group 64 exposes the pattern on the mask plate 62 to the rod-shaped body, and finally forms the corresponding pattern on the rod-shaped body.

[0032] The functional film layer is used to form any one or a combination of multiple of LED light-emitting chips, memory chips, sensor chips, or control chips. That is, the material or method required for film plating or the required number of layers can be selected according to the type of chip to be formed.

[0033] S4, electroplating, electroplating treatment is performed at a predetermined position of the functional film layer to form an electrode layer and a conductive circuit at a predetermined position of the rod-shaped body 1, so that each chip establishes a communication connection with the outside.

[0034] Referring to FIGS. 5 and 6(A)-6(D), the semiconductor device obtained by the scheme of the present application can form an array of chips on the circumferential surface of the rod-shaped body. In the present embodiment, the chips include a first chip 2 and a second chip 3. The first chip 2 can be soldered to the circuit board 4 in a flip-chip manner, and the second chip 3 can be mounted to the circuit board 4 in a wire-bonding manner. Since the orthographic projection of the first chip 2 can fall on the same surface as the orthographic projection of the second chip 3, the surface area occupied by the chips on the circuit board 4 can be reduced, the integration level of the chips can be improved, and the gold wire 40 can serve as a heat dissipation channel for the second chip 3. Of course, it can be understood that the first chip 2 or the second chip 3 can also be connected in series or parallel through electroplated conductive circuits or gold wires.

[0035] S5, surface treatment, stripping the impurities and photoresist remaining on the surface of the rod-shaped body 1; S6, testing, testing the multiple chips formed on the rod-shaped body 1 to determine the yield of each chip; S7, soldering, referring again to FIGS. 6(A)-6(D), providing a circuit board 4, flip-chip soldering the first chip 2 to the circuit board 4, and wire-bonding the second chip 3 to the circuit board 4 to obtain a semiconductor device having multiple first chips 2 and second chips 3 formed on the circumferential surface. This semiconductor device realizes high integration of multiple chips. In the subsequent process, the substrate crystal rod can also be cut to obtain the desired length or number of chips.

[0036] Specifically, in a specific embodiment, the substrate crystal rod is made of sapphire. The diameter of the substrate crystal rod is 10 mm. Within this diameter range, the first is to meet the demand for processing yield, and the other aspect is to further reduce the demand for space during chip production on the basis of meeting the processing yield, for example, to reduce the size of the vacuum space.

[0037] In the embodiment, the cleaning method can be reagent cleaning or ultrasonic cleaning. In the embodiment, the surface of the sapphire substrate can be cleaned by MOCVD at high temperature, and the temperature of the cavity can be increased to 1050 DEG C in a hydrogen atmosphere and held for 10 minutes, so as to obtain the semiconductor device.

[0038] In the application, a semiconductor device is also provided, which comprises a circuit board 4 and a rod-shaped body 1. The surface of the rod-shaped body 1 is formed with a plurality of chips, the chips comprising a first chip 2 and a second chip 3, the orthographic projection of the first chip 2 being capable of falling on the same surface as the orthographic projection of the second chip 3; and / or the first chip 2 and the second chip 3 are respectively arranged in an array; the first chip 2 is flip-chip mounted on the circuit board 4, and the second chip 3 is right-chip mounted on the circuit board 4 through gold wires 40.

[0039] The first chip 2 and the second chip 3 are different in type, the first chip 2 comprising a clock distributor, a power management chip and a radio frequency distributor, and the second chip 3 comprising a data processing chip and a storage chip. By using a film forming process, a plurality of chips are formed on the surface of the rod-shaped body 1, the chips are directly integrated on the circumferential surface of the rod-shaped body, the additional packaging steps and materials are reduced, the volume and weight of the device are reduced, and the device is facilitated to be integrated into a smaller equipment.

[0040] In the embodiment, the orthographic projection of the first chip 2 is capable of falling on the same surface as the orthographic projection of the second chip 3, the first chip 2 is a signal distribution center, such as a clock distribution, data buffering and the like, necessary support is provided for the right-chip mounted chip, signals are reasonably distributed to the second chip 3, signal cross interference is reduced, and the efficiency of signal processing is improved.

[0041] The cross-sectional shape of the rod-shaped body 1 can be selected according to actual scenes to achieve the maximum utilization of the substrate crystal rod. For example, in FIG. 6(A), the cross-sectional shape of the rod-shaped body 1 is circular, and an arc-shaped bearing portion is also provided on the circuit board 4, the bearing portion is formed with a solder pad, the first chip is flip-chip mounted on the bearing portion of the circuit board, the bearing portion plays a limiting role for the chip, and the rod-shaped body 1 can be stably fixed on the circuit board 4; in FIG. 6(B), the cross-sectional shape of the rod-shaped body is similar to a circle; in FIG. 6(C), the cross-sectional shape of the rod-shaped body 1 is similar to a square; and in FIG. 6(D), the cross-sectional shape of the rod-shaped body 1 is square.

[0042] In this embodiment, taking 6(C) as an example, the surface of the rod-shaped body 1 is also provided with a micro-channel 10, which is distributed along the circumference of the rod-shaped body and extends from the first chip 2 at the edge to the second chip 3 at the same edge, and the micro-channel 10 is filled with a phase change material 11, but the phase change material 11 does not fill the micro-channel 10. When the semiconductor device is heated, the phase change material 11 in the micro-channel 10 absorbs heat and begins to melt, and the phase change material 11 expands and rises along the micro-channel 10. The phase change material 11 transfers heat from the heat source area to the cooler area during the rising process. When the phase change material flows to the cooler area, it releases heat and re-solidifies, because the micro-channel 10 extends from the first chip 2 at the edge to the second chip 3 at the same edge, so that the phase change material can be heated and expanded to take away heat and can flow back under the action of gravity, and then can return to the heat source area by capillary action and gravity, the phase change material 11 circulates between solid and liquid, continuously absorbs and releases heat, and realizes the heat management of the semiconductor device.

[0043] The above are preferred embodiments of the present application, and do not limit the protection scope of the present application, therefore: any equivalent changes made on the structure, shape, principle of the present application should be covered within the protection scope of the present application.

Claims

1. A method of fabricating a semiconductor device, comprising: The method comprises the following steps: Grinding: providing a substrate crystal rod with a diameter of 0.1mm-200mm, and grinding the peripheral surface of the substrate crystal rod (1) to obtain a rod-shaped body (1) with a predetermined cross-sectional shape, and the surface of the rod-shaped body after the grinding treatment is a smooth surface; Cleaning: removing impurities on the surface of the rod-shaped body (1); Plating: photoetching the peripheral surface of the rod-shaped body (1) and plating a semiconductor functional film layer to form a chip on the peripheral surface of the rod-shaped body (1); Electroplating: performing electroplating treatment at a predetermined position of the functional film layer to form an electroplating electrode on the surface of the semiconductor functional film layer, and electroplating a conductive circuit at a predetermined position of the rod-shaped body (1) to form a plurality of chips on the peripheral surface of the rod-shaped body (1), and the conductive circuit can enable the chips to be connected in communication; Surface treatment: stripping the impurities and photoresist remaining on the peripheral surface of the rod-shaped body (1); Testing: testing the plurality of chips formed on the rod-shaped body (1); and Soldering: providing a circuit board (4), and electrically connecting the chips with the circuit board (4) to obtain a semiconductor device with a plurality of chips distributed on the periphery.

2. The method of fabricating a semiconductor device according to claim 1, wherein The chips comprise a first chip (2) and a second chip (3), and the orthographic projection of the first chip (2) can fall on the same surface as the orthographic projection of the second chip (3); and / or The first chip (2) and the second chip (3) are respectively arranged in an array; and The first chip (2) is flip-chip soldered to the circuit board (4), and the second chip (3) is wire-bonded to the circuit board (4).

3. The method of claim 1, wherein The predetermined cross-sectional shape is semicircular, circular, square, polygonal, circular-like, square-like or polygonal-like.

4. The method of claim 2, wherein After the grinding step, a self-tension support frame (5) and a position adjusting mechanism are further provided, the self-tension support frame (5) comprises a base (50) and support heads (52) located at opposite ends of the base (50), the substrate crystal rod is fixed to the self-tension support frame (5), and the opposite ends of the substrate crystal rod are respectively clamped to the two support heads (52); the position adjusting mechanism is configured to drive the self-tension support frame (5) to move in parallel along the axial direction and rotate.

5. The method of claim 4, wherein In the grinding step, a grinding device is provided, which comprises a workbench (7) and a plurality of grinding heads (8) fixed to the workbench (7), the plurality of grinding heads (8) are uniformly distributed along the same circumference, and the grinding heads (8) can be adjusted in extension and retraction by a precision mechanism.

6. The method of fabricating a semiconductor device according to claim 5, wherein The workbench (7) is further provided with an ultrasonic probe (9) and a closed-loop control system, the ultrasonic probe (9) measures the grinding precision of the substrate crystal rod in real time, and feeds back data to the closed-loop control system, and the closed-loop control system automatically adjusts the pressure, grinding speed and extension and retraction position of each grinding head (8) according to the measurement result of the ultrasonic probe (9).

7. The method according to any one of claims 1 to 6, wherein After the testing step and before the soldering step, a micro-channel (10) is provided on the surface of the rod-shaped body (1), the micro-channel (10) is distributed along the circumference of the rod-shaped body (1) and extends at least from the first chip (2) at the edge to the second chip (3) at the edge of the same side, and the micro-channel (10) is filled with a phase change material (11).

8. The method of fabricating a semiconductor device according to claim 7, wherein In the coating step, the provided photoetching equipment includes a laser (60), a mask plate (62) and a projection lens group (64), the mask plate (62) is arranged between the laser (60) and the projection lens group (64), and the projection lens group (64) includes at least three concave mirrors, the diameters of the three concave mirrors are sequentially reduced on the light path of the laser (60).

9. A semiconductor device, characterized by comprising: Comprise: a circuit board (4); and a rod-shaped body (1), the surface of the rod-shaped body (1) is formed with a plurality of chips, the chips include a first chip (2) and a second chip (3), the orthographic projection of the first chip (2) can fall on the same surface as the orthographic projection of the second chip (3); and / or the first chip (2) and the second chip (3) are respectively arranged in an array; and the first chip (2) is flip-chip soldered to the circuit board (4), and the second chip (3) is right-chip mounted to the circuit board (4) through a gold wire (40).

10. The semiconductor device of claim 9, wherein, The surface of the rod-shaped body (1) is also provided with a micro-channel (10), the micro-channel (10) is distributed along the circumference of the rod-shaped body (1) and extends at least from the first chip (2) at the edge to the second chip (3) at the edge of the same side, and the micro-channel is filled with a phase change material.

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