Preparation method for intrinsic passivation structure, and intrinsic passivation structure and cell

Abstract

Disclosed is a cell. The cell comprises an intrinsic passivation structure. The intrinsic passivation structure comprises a base layer, a first intrinsic layer, a second intrinsic layer, and a doped microcrystalline silicon layer, wherein a first interface layer is provided on a surface of the base layer; the first intrinsic layer is disposed on the first interface layer, and a second interface layer is provided on a surface of the first intrinsic layer; the second intrinsic layer is disposed on the second interface layer, and a third interface layer is provided on a surface of the second intrinsic layer; and the doped microcrystalline silicon layer is disposed on a surface of the third interface layer. Further disclosed is a preparation method for the intrinsic passivation structure.

Description

Preparation method of intrinsic passivation structure, intrinsic passivation structure and battery

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411019832.8, filed on July 26, 2024, entitled "Preparation method of intrinsic passivation structure, intrinsic passivation structure and battery", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of battery manufacturing, and more particularly, to a preparation method of intrinsic passivation structure, intrinsic passivation structure and battery. BACKGROUND

[0004] At present, the key to obtaining high performance of silicon heterojunction cells lies in that the Si-H bond of intrinsic amorphous silicon film realizes high-efficiency passivation of the dangling defects on the surface of crystalline silicon, thereby reducing the interface recombination rate and improving the open-circuit voltage of the battery. Since intrinsic amorphous silicon has poor conductivity and absorbs visible light, only a thin layer (5-10 nm) is usually deposited, and it is particularly important to control the relevant parameters in a relatively narrow process window in order to obtain the best passivation effect.

[0005] In the prior art, the intrinsic amorphous silicon is generally prepared by a laminated process. The buffer layer in contact with the crystalline silicon is deposited by silane plasma, and the content of Si-H2 and Si-H3 is high, which has a loose porous structure and can inhibit the generation of nano-rods. On this basis, the second layer is deposited by silane and hydrogen with a certain mixing ratio. Since hydrogen etching will break the weak silicon-hydrogen bond, a dense film with Si-H as the main component and low internal defect states is finally formed. However, this route still has problems to be solved, including poor interface contact between layers, serious parasitic absorption of the passivation layer, and mismatch of conductivity between the passivation layer and the doped microcrystalline silicon.

[0006] SUMMARY

[0007] An object of the present disclosure is to provide a new technical solution for a preparation method of intrinsic passivation structure, intrinsic passivation structure and battery, which can at least solve the problems of poor interface contact between layers of the silicon heterojunction cell in the prior art, serious parasitic absorption of the passivation layer, and mismatch of conductivity between the passivation layer and the doped microcrystalline silicon.

[0008] In a first aspect, the present disclosure provides an intrinsic passivation structure, comprising a base layer, a first interface layer disposed on a surface of the base layer, a first intrinsic layer disposed on the first interface layer, a second interface layer disposed on a surface of the first intrinsic layer, a second intrinsic layer disposed on the second interface layer, a third interface layer disposed on a surface of the second intrinsic layer, and a doped microcrystalline silicon layer disposed on a surface of the third interface layer.

[0009] Optionally, the first interface layer is a crystalline silicon oxide layer, the second interface layer is an amorphous silicon dense layer, and the third interface layer is a microcrystalline silicon oxide layer.

[0010] Optionally, the first intrinsic layer is an amorphous silicon thin film, and the second intrinsic layer is an amorphous silicon dense thin film.

[0011] Optionally, the first intrinsic layer has a thickness of 0.5 nm to 3 nm, the second intrinsic layer has a thickness of 2 nm to 7 nm, and the third interface layer has a thickness of 0.5 nm to 4 nm.

[0012] Optionally, the intrinsic passivation structure further comprises a conductive thin film layer disposed on a surface of the doped microcrystalline silicon layer, and an electrode disposed on the conductive thin film layer.

[0013] In a second aspect, the present disclosure provides a method for preparing an intrinsic passivation structure, for preparing the intrinsic passivation structure described in the above embodiments, the method comprising:

[0014] cleaning a silicon wafer by immersing the silicon wafer in a first solution to form a first interface layer on a surface of the silicon wafer, the first solution being an oxidizing solution;

[0015] depositing silicon on the first interface layer to form a first intrinsic layer;

[0016] performing hydrogen plasma etching on the first intrinsic layer to form a second interface layer on a surface of the first intrinsic layer;

[0017] depositing a second intrinsic layer on the second interface layer;

[0018] treating a surface of the second intrinsic layer to form a third interface layer on the surface of the second intrinsic layer; and

[0019] depositing a doped microcrystalline silicon on the third interface layer.

[0020] Optionally, the first solution is a mixed solution of hydrofluoric acid and hydrogen peroxide, and the first interface layer is an oxide layer.

[0021] Optionally, the step of depositing silicon on the first interface layer to form a first intrinsic layer comprises:

[0022] The cleaned silicon wafer is sent into a deposition device.

[0023] High-purity silane with a flow rate of 100-1200 sccm is introduced to form a hydrogen-rich amorphous silicon film on the surface of the first interface layer, and the amorphous silicon film is the first intrinsic layer.

[0024] Optionally, the step of forming a second interface layer on the surface of the first intrinsic layer by hydrogen plasma etching includes:

[0025] Plasma deposition is performed by pure hydrogen gas as hydrogen plasma in a deposition device to form the second interface layer; wherein the pure hydrogen gas has a flow rate of 500-3000 sccm of high-purity hydrogen, a reaction temperature of 170-220°C, a pressure of 0.5-1.8 mbar, a radio frequency power of 100-2000 W, and a reaction time of 10-45 s.

[0026] Optionally, the step of depositing a second intrinsic layer on the second interface layer includes:

[0027] A mixture of silane and hydrogen gas is introduced in a deposition device to form the second intrinsic layer on the second interface layer; wherein the total flow rate of the mixture of silane and hydrogen gas is 800-3000 sccm, the flow rate ratio of silane to hydrogen is between 3:1 and 1:20, the reaction temperature is 170-220°C, the pressure is 0.7-2.1 mbar, the radio frequency power is 300-1800 W, and the reaction time is 10-60 s.

[0028] Optionally, the step of forming a third interface layer on the surface of the second intrinsic layer by processing the surface of the second intrinsic layer includes:

[0029] Silane, hydrogen, and carbon dioxide are introduced in a deposition device to form a microcrystalline silicon oxide layer, and the microcrystalline silicon oxide layer is the third interface layer.

[0030] Optionally, the step of forming a microcrystalline silicon oxide layer by introducing silane, hydrogen, and carbon dioxide in a deposition device includes: the total flow rate of silane, hydrogen, and carbon dioxide is 2000-20000 sccm, the flow rate ratio of silane to hydrogen is between 1:10 and 1:200, carbon dioxide accounts for 0.1-2% of the total gas flow rate, the reaction temperature is 170-220°C, the pressure is 1.4-3.2 mbar, the radio frequency power is 500-2500 W, and the reaction time is 30-120 s.

[0031] Optionally, the method for preparing the intrinsic passivation structure further includes:

[0032] depositing a conductive thin film and an electrode on the doped microcrystalline silicon.

[0033] In a third aspect, the present disclosure provides a battery comprising the intrinsic passivation structure as described in the above embodiments.

[0034] The intrinsic passivation structure of the present disclosure effectively improves the contact between the intrinsic amorphous silicon and the crystalline silicon substrate, suppresses the generation of nanotwins, strengthens the passivation effect, and improves the minority carrier lifetime by treating the surfaces of the base layer, the first intrinsic layer, and the second intrinsic layer.

[0035] Other features of the present disclosure, and their advantages, will become apparent from the following detailed description of exemplary embodiments of the present disclosure, with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0037] FIG. 1 is a flow block diagram of a method for preparing an intrinsic passivation structure according to an embodiment of the present disclosure;

[0038] FIG. 2 is a structural schematic diagram of an intrinsic passivation structure according to an embodiment of the present disclosure;

[0039] FIG. 3 is a scanning electron microscope image of a second interface layer before modification according to an embodiment of the present disclosure;

[0040] FIG. 4 is a scanning electron microscope image of a second interface layer after modification according to an embodiment of the present disclosure;

[0041] FIG. 5 is a structural factor characterization schematic diagram of a first intrinsic layer and a second intrinsic layer according to an embodiment of the present disclosure;

[0042] FIG. 6 is a minority carrier lifetime characterization schematic diagram of an intrinsic passivation structure after interface treatment according to an embodiment of the present disclosure;

[0043] FIG. 7 is a schematic block diagram of a battery according to an embodiment of the present disclosure.

[0044] Reference signs: base layer 11; first interface layer 12; first intrinsic layer 13; second interface layer 14; second intrinsic layer 15; third interface layer 16; doped microcrystalline silicon layer 17; conductive thin film layer 18; electrode 19; intrinsic passivation structure 20; battery 30. DETAILED DESCRIPTION

[0045] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. Note that the relative arrangement, numerical expressions, and numerical values of components and steps set forth in these embodiments are not limiting to the scope of the present disclosure unless otherwise specifically stated.

[0046] The following description of at least one example embodiment is merely exemplary in nature and is in no way intended to limit the disclosure, its application, or uses.

[0047] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail herein. However, the techniques, methods, and devices are sufficiently described in the description herein, and are considered a part of the specification.

[0048] In all of the examples shown and discussed herein, any specific values should be interpreted as merely exemplary, and not a limitation. Other examples of the exemplary embodiments can have different values.

[0049] It should be noted that like reference numerals and letters in the various figures indicate similar items, and thus, once any certain item is defined in one figure, it is not necessarily discussed further in subsequent figures.

[0050] In the description of the present disclosure, the terms "first", "second", and the like, if any, can explicitly or implicitly include one or more of the features. In the description of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", in general, means that the front and rear associated objects are in an "or" relationship.

[0051] In the description of the present disclosure, it should be understood that if the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0052] In the description of the present disclosure, it should be noted that unless otherwise specified and limited, the terms "mounting", "connection", and "connection" should be understood broadly. For example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0053] The preparation method of the intrinsic passivation structure 20 according to the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings.

[0054] The intrinsic passivation structure according to the embodiments of the present disclosure is made by the preparation method of the intrinsic passivation structure in the above embodiments, as shown in FIG. 2, the intrinsic passivation structure 20 includes a base layer 11, a first intrinsic layer 13, a second intrinsic layer 15, and a doped microcrystalline silicon layer 17. The base layer 11 can be a silicon wafer, and the surface of the base layer 11 is provided with a first interface layer 12. The first intrinsic layer 13 is arranged on the first interface layer 12, and the surface of the first intrinsic layer 13 is provided with a second interface layer 14, which improves the substrate environment when the second intrinsic layer 15 is deposited. The second intrinsic layer 15 is arranged on the second interface layer 14, and the surface of the second intrinsic layer 15 is provided with a third interface layer 16. The doped microcrystalline silicon layer 17 is arranged on the surface of the third interface layer 16, which is conducive to the growth of the doped microcrystalline silicon 17 and can effectively reduce the damage to the second intrinsic layer 15 caused by the high-power and high-pressure doped microcrystalline silicon process, thereby improving the electrochemical performance of the intrinsic passivation structure 20.

[0055] Therefore, the intrinsic passivation structure 20 of the present disclosure can effectively improve the contact between the intrinsic amorphous silicon and the crystalline silicon substrate, inhibit the generation of nanotwins, strengthen the passivation effect, and improve the minority carrier lifetime by treating the surfaces of the base layer 11, the first intrinsic layer 13, and the second intrinsic layer 15.

[0056] According to one embodiment of the present disclosure, as shown in FIG. 2, the first interface layer 12 is a crystalline silicon oxide layer etched by an oxidizing solution; the second interface layer 14 is a dense amorphous silicon layer etched by hydrogen plasma; and the third interface layer 16 is a microcrystalline silicon oxide layer etched by a mixed gas of silane, hydrogen, and carbon dioxide.

[0057] Specifically, the base layer 11 can be a silicon wafer, and the surface of the silicon wafer is cleaned by a strong oxidizing mixed solution composed of hydrofluoric acid and hydrogen peroxide, which can effectively remove organic matter, dust, metal impurities, and the like remaining on the surface of the silicon wafer, improve the cleaning effect, and form a first interface layer 12 with a natural oxide layer on the surface of the silicon wafer, thereby improving the minority carrier lifetime.

[0058] The surface of the first intrinsic layer 13 is etched by hydrogen plasma to form a second interface layer 14 on the surface of the first intrinsic layer 13. Specifically, the second interface layer 14 can be formed by plasma deposition in a deposition device by using pure hydrogen gas as hydrogen plasma; wherein the flow rate of the pure hydrogen gas is 500sccm-3000sccm of high-purity hydrogen, the reaction temperature is 170°C-220°C, the pressure is 0.5mbar-1.8mbar, the radio frequency power is 100W-2000W, and the reaction time is 10s-45s. The first intrinsic layer 13 is etched by hydrogen plasma, and the weak silicon-silicon bond and the silicon-hydrogen bond are broken, so that the subsequent thin film growth is a dense layer, and the interface defect state is reduced, and the charge recombination is reduced.

[0059] The surface of the second intrinsic layer 15 forms a third interface layer 16. In the process of forming the third interface layer 16 on the surface of the second intrinsic layer 15, silane, hydrogen and carbon dioxide can be introduced into the deposition device to form a microcrystalline silicon oxide layer, and the microcrystalline silicon oxide layer is the third interface layer 16. By continuously increasing the hydrogen dilution ratio, increasing the total flow rate of the gas and introducing carbon dioxide, the deposition of the intrinsic microcrystalline silicon oxide layer can improve the conductivity of the entire passivation structure and reduce the interface contact resistance.

[0060] According to one embodiment of the present disclosure, the first intrinsic layer 13 is an amorphous silicon thin film deposited by pure silane, and the second intrinsic layer 15 is an amorphous silicon dense thin film deposited by a mixture of silane and hydrogen. Specifically, in the present disclosure, the cleaned silicon wafer can be sent into a deposition device, which can be a PECVD (plasma enhanced chemical vapor deposition) device. High-purity silane with a flow rate of 100sccm-1200sccm is introduced, the cavity temperature is set to 170°C-220°C, the pressure is controlled to 0.3mbar-1.5mbar, and the radio frequency power ranges from 100W to 2000W. The process time is 1s-60s, and the final thickness of the layer is distributed in the range of 0.5nm-3nm, so that a hydrogen-rich amorphous silicon thin film is formed on the surface of the first interface layer 12, and the hydrogen-rich amorphous silicon thin film is the first intrinsic layer 13. The pure silane is introduced to obtain a hydrogen-rich amorphous silicon thin film, which can effectively passivate the dangling bonds on the surface of the crystalline silicon and inhibit the occurrence of epitaxial growth.

[0061] The surface of the first intrinsic layer 13 is subjected to hydrogen plasma etching to form a second interface layer 14 on the surface of the first intrinsic layer 13. Specifically, the second interface layer 14 can be formed by plasma deposition of pure hydrogen gas as hydrogen plasma in a deposition device; wherein the flow rate of the pure hydrogen gas is 500-3000 sccm of high-purity hydrogen, the reaction temperature is 170-220°C, the pressure is 0.5-1.8 mbar, the radio frequency power is 100-2000 W, and the reaction time is 10-45 s. Etching the first intrinsic layer 13 by hydrogen plasma breaks the weak silicon-silicon bond and the silicon-hydrogen bond, so that the subsequent thin film growth is a dense layer, and the interface defect state is reduced, reducing charge recombination.

[0062] The second intrinsic layer 15 is deposited on the second interface layer 14. In the process of depositing the second intrinsic layer 15 on the second interface layer 14, a mixture of silane and hydrogen gas is introduced into the deposition device to form the second intrinsic layer 15 on the second interface layer 14. A large number of hydrogen atoms can effectively improve the passivation effect, and the dense thin film formed has good quality, low internal defect density, and can improve the minority carrier lifetime.

[0063] The surface of the second intrinsic layer 15 forms a third interface layer 16. In the process of treating the surface of the second intrinsic layer 15 to form the third interface layer 16 on the surface of the second intrinsic layer 15, silane, hydrogen and carbon dioxide can be introduced into the deposition device to form a microcrystalline silicon oxide layer, which is the third interface layer 16. By continuously increasing the hydrogen dilution ratio, increasing the total gas flow and introducing carbon dioxide, the intrinsic microcrystalline silicon oxide layer is deposited, which can improve the conductivity of the overall passivation structure and reduce the interface contact resistance.

[0064] In the intrinsic passivation structure 20 of the present disclosure, the effect of cleaning metal residual impurities is improved by a mixed solution of H2O2 and HF, and the minority carrier lifetime is improved by more than 200 μs. The silicon surface oxide layer and the hydrogen-rich amorphous silicon film cooperatively suppress the generation of nanometer lamellar crystals, the passivation effect is strengthened, the open circuit voltage is improved by 2 mv, and the minority carrier lifetime is improved by more than 500 μs. The intrinsic passivation structure 20 is added with hydrogen plasma treatment between layers, which improves the quality of the dense layer and further improves the minority carrier lifetime by 300 μs. The overall conductivity of the passivation layer is improved, the charge transport is improved, and a short-circuit current gain of about 0.03 A can be provided, and the final cell efficiency is improved by an average of 0.3-0.4%.

[0065] According to one embodiment of the present disclosure, the thickness of the first intrinsic layer 13 is 0.5-3 nm, the thickness of the second intrinsic layer 15 is 2-7 nm, and the thickness of the third interface layer 16 is 0.5-4 nm. By reasonably controlling the thicknesses of the first intrinsic layer 13, the second intrinsic layer 15, and the third interface layer 16, etc., the surface treatment of the first intrinsic layer 13, the second intrinsic layer 15, etc. is facilitated, the passivation effect can be improved, and the minority carrier lifetime can be improved.

[0066] According to one embodiment of the present disclosure, as shown in FIG. 2, the intrinsic passivation structure 20 further comprises: a conductive film layer 18 and an electrode 19, the conductive film layer 18 is arranged on the surface of the doped microcrystalline silicon layer 17, and the electrode 19 is arranged on the conductive film layer 18. After the interface treatment, the minority carrier lifetime is obviously improved after depositing the double-sided intrinsic amorphous silicon and the subsequent n-doped layer and p-doped layer. The double-layer structure of the first intrinsic layer 13 and the second intrinsic layer 15 significantly improves the passivation effect on the dangling bonds of the crystalline silicon surface, and successfully realizes the maximization of the passivation effect.

[0067] Of course, other structures of the intrinsic passivation structure 20 and its working principles can be understood and implemented by those skilled in the art, and will not be described in detail in the present disclosure.

[0068] According to a second aspect of the present disclosure, as shown in FIG. 1, a preparation method of an intrinsic passivation structure is provided for preparing the intrinsic passivation structure in the above embodiments, and the preparation method comprises:

[0069] S1, the silicon wafer is immersed in a first solution for cleaning to form a first interface layer 12 on the surface of the silicon wafer, and the first solution is an oxidizing solution;

[0070] S2, silicon deposition is performed on the first interface layer 12 to form a first intrinsic layer 13;

[0071] S3, hydrogen plasma etching is performed on the first intrinsic layer 13 to form a second interface layer 14 on the surface of the first intrinsic layer 13;

[0072] S4, a second intrinsic layer 15 is deposited on the second interface layer 14;

[0073] S5, the surface of the second intrinsic layer 15 is treated to form a third interface layer 16 on the surface of the second intrinsic layer 15;

[0074] S6, a doped microcrystalline silicon is deposited on the third interface layer 16.

[0075] In other words, as shown in FIG. 1, in the preparation method of the intrinsic passivation structure according to the present disclosure, first, the silicon wafer with completed etching round corners can be immersed in a first solution for cleaning, the first solution is an oxidizing solution, under the action of the oxidizing solution, the surface of the silicon wafer is eroded, so that the metal impurities and particulate matters on the surface of the silicon wafer are removed, and a natural oxide layer is formed on the surface of the silicon wafer, which serves as a first interface layer 12 and can effectively improve the lifetime of minority carriers.

[0076] Then, silicon deposition can be performed on the first interface layer 12 to form a first intrinsic layer 13; then, hydrogen plasma etching can be performed on the first intrinsic layer 13, so that the weak silicon-silicon bonds and silicon-hydrogen bonds are broken, the subsequent thin film growth is a dense layer, the interface defect state is reduced, and the charge recombination is reduced, so that a second interface layer 14 is formed on the surface of the first intrinsic layer 13.

[0077] Then, a second intrinsic layer 15 can be deposited on the second interface layer 14; the surface of the second intrinsic layer 15 is treated to form a third interface layer 16 on the surface of the second intrinsic layer 15; finally, doped microcrystalline silicon can be deposited on the third interface layer 16. By treating the surfaces of the silicon wafer, the first intrinsic layer 13 and the second intrinsic layer 15, the present disclosure can effectively improve the contact between the intrinsic amorphous silicon and the crystalline silicon substrate, inhibit the generation of nanometer twins, strengthen the passivation effect, and improve the lifetime of minority carriers.

[0078] Therefore, in the preparation method of the intrinsic passivation structure according to the present disclosure, the silicon wafer is cleaned by the first solution with oxidizing property, so that the organic matters, dust and metal impurities remaining on the surface of the silicon wafer are removed, the cleaning effect is improved, and a first interface layer 12 with a natural oxide layer is formed on the surface of the silicon wafer to improve the lifetime of minority carriers. Hydrogen plasma deposition is performed on the first intrinsic layer 13 to form a second interface layer 14 on the surface of the first intrinsic layer 13, so that the weak silicon-silicon bonds and silicon-hydrogen bonds are broken, the subsequent thin film growth is a dense layer, the interface defect state is reduced, and the charge recombination is reduced. By treating the surfaces of the silicon wafer, the first intrinsic layer 13 and the second intrinsic layer 15, the present disclosure can effectively improve the contact between the intrinsic amorphous silicon and the crystalline silicon substrate, inhibit the generation of nanometer twins, strengthen the passivation effect, and improve the lifetime of minority carriers.

[0079] According to one embodiment of the present disclosure, the first solution is a mixed solution of hydrofluoric acid and hydrogen peroxide, and the first interface layer 12 is an oxide layer. The strong oxidizing mixed solution composed of hydrofluoric acid and hydrogen peroxide can effectively remove the organic matters, dust and metal impurities remaining on the surface of the silicon wafer, improve the cleaning effect, and form a first interface layer 12 with a natural oxide layer on the surface of the silicon wafer to improve the lifetime of minority carriers.

[0080] According to one embodiment of the present disclosure, the step of performing silicon deposition on the first interface layer 12 to form the first intrinsic layer 13 includes:

[0081] The cleaned silicon wafer is sent into a deposition device;

[0082] High-purity silane with a flow rate of 100-1200 sccm is introduced to form a hydrogen-rich amorphous silicon film on the surface of the first interface layer 12; the amorphous silicon film is the first intrinsic layer 13.

[0083] That is, in the process of depositing silicon on the first interface layer 12 to form the first intrinsic layer 13, the cleaned silicon wafer can be first sent into a deposition device, which can be a PECVD (plasma-enhanced chemical vapor deposition) device. High-purity silane with a flow rate of 100-1200 sccm is introduced, the cavity temperature is set to 170-220°C, the pressure is controlled to 0.3-1.5 mbar, and the radio frequency power ranges from 100 W to 2000 W. The process time is 1-60 s, and the final thickness of the layer is distributed in the range of 0.5-3 nm, thereby forming a hydrogen-rich amorphous silicon film on the surface of the first interface layer 12, which is the first intrinsic layer 13. The introduction of pure silane results in a hydrogen-rich amorphous silicon film, which effectively passivates the dangling bonds on the surface of the crystalline silicon and suppresses the occurrence of epitaxial growth.

[0084] The coating method adopted by the present disclosure is VHF-PECVD, which can also be RF-PECVD (radio frequency plasma enhanced chemical vapor deposition) and DC-PECVD (direct current plasma enhanced chemical vapor deposition), and can also be HWCVD (hot wire chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), ECRCVD (electron cyclotron resonance chemical vapor deposition), and ETP (expanding thermal plasma deposition), etc.

[0085] According to one embodiment of the present disclosure, the step of performing hydrogen plasma etching on the first intrinsic layer 13 to form the second interface layer 14 on the surface of the first intrinsic layer 13 includes:

[0086] Plasma deposition is performed by pure hydrogen gas as hydrogen plasma in the deposition device to form the second interface layer 14; wherein the flow rate of the pure hydrogen gas is 500-3000 sccm of high-purity hydrogen, the reaction temperature is 170-220°C, the pressure is 0.5-1.8 mbar, the radio frequency power is 100-2000 W, and the reaction time is 10-45 s.

[0087] In other words, in the process of hydrogen plasma etching the first intrinsic layer 13 to form the second interface layer 14 on the surface of the first intrinsic layer 13, plasma deposition can be performed in a deposition device by using pure hydrogen gas as hydrogen plasma to form the second interface layer 14; wherein the flow rate of the pure hydrogen gas is 500sccm-3000sccm of high-purity hydrogen, the reaction temperature is 170°C-220°C, the pressure is 0.5mbar-1.8mbar, the radio frequency power is 100W-2000W, and the reaction time is 10s-45s. Etching the first intrinsic layer 13 by hydrogen plasma breaks the weak silicon-silicon bond and the silicon-hydrogen bond, so that the subsequent thin film growth is a dense layer, and the interface defect state is reduced, and the charge recombination is reduced.

[0088] According to one embodiment of the present disclosure, the step of depositing the second intrinsic layer 15 on the second interface layer 14 comprises:

[0089] In the deposition device, a mixed gas of silane and hydrogen is used to form the second intrinsic layer 15 on the second interface layer 14; wherein the total flow rate of the mixed gas of silane and hydrogen is 800sccm-3000sccm, the flow rate ratio of silane to hydrogen is between 3:1 and 1:20, the reaction temperature is 170°C-220°C, the pressure is 0.7mbar-2.1mbar, the radio frequency power is 300W-1800W, and the reaction time is 10s-60s.

[0090] That is, in the process of depositing the second intrinsic layer 15 on the second interface layer 14, a mixed gas of silane and hydrogen is used in the deposition device to form the second intrinsic layer 15 on the second interface layer 14. A large number of hydrogen atoms can effectively improve the passivation effect, and the dense thin film formed has good quality, low internal defect density, and improved minority carrier lifetime. Wherein the total flow rate of the mixed gas of silane and hydrogen is 800sccm-3000sccm, the flow rate ratio of silane to hydrogen is between 3:1 and 1:20, the reaction temperature is 170°C-220°C, the pressure is 0.7mbar-2.1mbar, the radio frequency power is 300W-1800W, the reaction time is 10s-60s, and the thickness of the second intrinsic layer 15 is 2nm-7nm.

[0091] According to one embodiment of the present disclosure, the step of treating the surface of the second intrinsic layer 15 to form the third interface layer 16 on the surface of the second intrinsic layer 15 comprises:

[0092] In the deposition device, silane, hydrogen and carbon dioxide are introduced to form a microcrystalline silicon oxide layer, which is the third interface layer 16.

[0093] That is, in the process of treating the surface of the second intrinsic layer 15 to form the third interface layer 16 on the surface of the second intrinsic layer 15, silane, hydrogen and carbon dioxide can be introduced into the deposition device to form a microcrystalline silicon oxide layer, which is the third interface layer 16. By continuously increasing the hydrogen dilution ratio, increasing the total flow rate of the gas and introducing carbon dioxide, an intrinsic microcrystalline silicon oxide layer is deposited, the conductivity of the entire passivation structure is improved, and the interface contact resistance is reduced.

[0094] Optionally, the step of introducing silane, hydrogen and carbon dioxide into the deposition device to form a microcrystalline silicon oxide layer includes: the total flow rate of silane, hydrogen and carbon dioxide is 2000sccm-20000sccm, the flow rate ratio of silane to hydrogen is between 1:10 and 1:200, carbon dioxide accounts for 0.1%-2% of the total flow rate of the gas, the reaction temperature is 170°C-220°C, the pressure is 1.4mbar-3.2mbar, the radio frequency power is 500W-2500W, the reaction time is 30s-120s, and the thickness of the third interface layer 16 is 0.5nm-4nm.

[0095] According to one embodiment of the present disclosure, the method for preparing an intrinsic passivation structure further comprises:

[0096] Depositing a conductive thin film and an electrode 19 on the doped microcrystalline silicon.

[0097] Specifically, after treating the surface of the second intrinsic layer 15 to form the third interface layer 16 on the surface of the second intrinsic layer 15, it can be transferred to another PECVD device to deposit 10nm-30nm n-type microcrystalline silicon on the front surface, and after turning over, it can be transferred to the next PECVD device to deposit 15nm-40nm p-type microcrystalline silicon on the back surface. Then, TCO thin film deposition is performed, the front surface uses an ITO target with a mass ratio of In2O3 / SnO2 of 97:3, and the back surface uses an ITO target with a mass ratio of In2O3 / SnO2 of 90:10. The cavity temperature is set to 25°C-200°C, the sputtering pressure is controlled to 0.1Pa-0.5Pa, the sputtering power ranges from 2KW to 6KW, high-purity argon and oxygen are introduced, and the oxygen accounts for 2%-8%. The pre-sputtering time is 30s, and the thickness distribution is adjusted to 70nm-150nm by adjusting the walking speed of the carrier plate.

[0098] Then, a thermal annealing process is performed, and the silicon wafer after the film deposition process is placed in an air, nitrogen or vacuum environment for annealing, and the temperature is controlled at 150°C-200°C and the time is controlled at 30min-60min. After annealing, screen printing is performed, and photovoltaic paste is printed on the surface of the TCO, and after drying and sintering, the electrode 19 of the solar cell can be formed.

[0099] Then, light injection is performed, a laser with tens of times of solar light intensity is irradiated to make weak hydrogen atoms jump or diffuse, re-activate the doping atoms, and improve the conductivity of the doping layer. Finally, test sorting is performed, an IV test system is used to measure the photoelectric conversion efficiency and electrical performance parameters, and solar cell pieces are sorted according to the test results.

[0100] The oxygen doping source adopted in the present disclosure is carbon dioxide, and can also be oxygen, ozone, dinitrogen monoxide, etc.

[0101] Since Si-H2 and Si-H have different stretching vibration absorption characteristics, this can be analyzed by infrared spectroscopy, two stretching modes at 2000 cm-1 and 2100 cm-1 are separated, and the proportions of Si-H2 and Si-H in the film layer are obtained, and then the corresponding hydrogen content and structure factor (R*) are calculated. The definition of the structure factor is:

[0102] As shown in FIG. 5, the structure factors of the modified first intrinsic layer 13 and the second intrinsic layer 15 are 0.50 and 0.27 respectively, and the Si-H2 proportion of the first layer is higher, which is conducive to forming a loose porous structure and inhibiting the generation of nanorods.

[0103] As shown in FIGS. 3 and 4, after hydrogen plasma treatment, the second intrinsic layer 15 appears a texture and the roughness increases, and the film thickness increases from 23.5 nm to 25 nm (test process). It can be considered that the film layer grows after the combination of hydrogen and dangling bonds.

[0104] As shown in FIG. 6, after the interface treatment, the minority carrier lifetime is obviously improved after the deposition of the double-sided intrinsic amorphous silicon and the subsequent n-doped layer and p-doped layer. The double-layer structure of the first intrinsic layer 13 and the second intrinsic layer 15 significantly improves the passivation effect of the dangling bonds on the crystalline silicon surface, and successfully maximizes the passivation effect. As shown in Table 1, Table 1 shows the efficiency improvement effect of the battery:

[0105] Table 1: Efficiency improvement effect of the battery piece

[0106] In the preparation method of the intrinsic passivation structure of the present disclosure, H2O2 improves the effect of cleaning metal residual impurities, and the minority carrier lifetime is improved to more than 200 μs. The crystalline silicon surface oxide layer and the hydrogen-rich amorphous silicon film cooperate to inhibit the generation of nanorods, the passivation effect is strengthened, the open circuit voltage is improved by 2 mv, and the minority carrier lifetime is improved by more than 500 μs. The hydrogen plasma treatment between the intrinsic passivation structure layers improves the quality of the dense layer, and the minority carrier lifetime is further improved by 300 μs. The overall conductivity of the passivation layer is improved, the charge transport is improved, and a short-circuit current gain of about 0.03 A is provided. The average efficiency of the final battery piece is improved by 0.3%-0.4%.

[0107] According to a third aspect of the present disclosure, a battery 30 is provided, as shown in FIG. 7, comprising the intrinsic passivation structure 20 in the above-mentioned embodiments. The carrier of the battery 30 of the present disclosure can be a plate type or a tube type. Since the intrinsic passivation structure according to the present disclosure has the above-mentioned technical effects, the battery 30 according to the embodiments of the present disclosure should also have corresponding technical effects, that is, the battery 30 of the present disclosure, by adopting the intrinsic passivation structure, ensures that the overall conductivity of the passivation layer is improved, the charge transport is improved, and a short-circuit current gain of about 0.03 A can be provided, and finally the average efficiency of the battery piece is improved by 0.3%-0.4%.

[0108] Of course, other structures of the battery 30 and their working principles are understandable and can be implemented by those skilled in the art, and will not be described in detail in the present disclosure.

[0109] Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art should understand that the above examples are only for illustration, not for limiting the scope of the present disclosure. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An intrinsically passivated structure (20) characterized in that, The application relates to a preparation method of a thin-film solar cell. The application comprises: a base layer (11) provided with a first interface layer (12) on the surface; a first intrinsic layer (13) provided on the first interface layer (12), and the surface of the first intrinsic layer (12) is provided with a second interface layer (14); a second intrinsic layer (15) provided on the second interface layer (14), and the surface of the second intrinsic layer (15) is provided with a third interface layer (16); and 2. The intrinsically passivated structure (20) according to claim 1, characterized in that a doped microcrystalline silicon layer (17) provided on the surface of the third interface layer (16).

3. The intrinsically passivated structure (20) according to claim 1 or 2, characterized in that The first interface layer (12) is a crystalline silicon oxide layer, the second interface layer (14) is an amorphous silicon dense layer, and the third interface layer (16) is a microcrystalline silicon oxide layer.

4. The intrinsic passivation structure (20) according to any one of claims 1 to 3, characterized in that The first intrinsic layer (13) is an amorphous silicon thin film, and the second intrinsic layer (15) is an amorphous silicon dense thin film.

5. The intrinsic passivation structure (20) according to any one of claims 1 to 4, characterized in that The thickness of the first intrinsic layer (13) is 0.5nm-3nm, the thickness of the second intrinsic layer (15) is 2nm-7nm, and the thickness of the third interface layer (16) is 0.5nm-4nm. The application further comprises: a conductive thin film layer (18) arranged on the surface of the doped microcrystalline silicon layer (17); and 6. A production method for producing the intrinsically passivated structure according to any one of claims 1 to 5, characterized by, an electrode (19) arranged on the conductive thin film layer (18). The preparation method comprises: cleaning a silicon wafer in a first solution to form a first interface layer on the surface of the silicon wafer, wherein the first solution is an oxidizing solution; depositing silicon on the first interface layer to form a first intrinsic layer; performing hydrogen plasma etching on the first intrinsic layer to form a second interface layer on the surface of the first intrinsic layer; depositing a second intrinsic layer on the second interface layer; processing the surface of the second intrinsic layer to form a third interface layer on the surface of the second intrinsic layer; and 7. The method for preparing the intrinsic passivation structure according to claim 6, characterized in that, depositing doped microcrystalline silicon on the third interface layer.

8. The method of producing an intrinsically passivated structure according to claim 6 or 7, characterized in that, The first solution is a mixed solution of hydrofluoric acid and hydrogen peroxide, and the first interface layer is an oxide layer. The step of depositing silicon on the first interface layer to form a first intrinsic layer comprises: feeding the cleaned silicon wafer into a deposition device; 9. The method of producing an intrinsically passivated structure according to any one of claims 6 to 8, wherein introducing high-purity silane with a flow rate of 100sccm-1200sccm to form a hydrogen-rich amorphous silicon thin film on the surface of the first interface layer, and the amorphous silicon thin film is the first intrinsic layer. The step of performing hydrogen plasma etching on the first intrinsic layer to form a second interface layer on the surface of the first intrinsic layer comprises:

10. The method of producing an intrinsically passivated structure according to any one of claims 6 to 9, wherein performing plasma deposition by using pure hydrogen as hydrogen plasma in the deposition device to form the second interface layer; wherein the pure hydrogen has a flow rate of 500sccm-3000sccm of high-purity hydrogen, a reaction temperature of 170 DEG C-220 DEG C, a pressure of 0.5mbar-1.8mbar, a radio frequency power of 100W-2000W, and a reaction time of 10s-45s. The step of depositing a second intrinsic layer on the second interface layer comprises: forming the second intrinsic layer on the second interface layer in a deposition device by a mixed gas of silane and hydrogen; wherein the total flow of the mixed gas of silane and hydrogen is 800sccm-3000sccm, the flow ratio of silane to hydrogen is between 3:1 and 1:20, the reaction temperature is 170℃-220℃, the pressure is 0.7mbar-2.1mbar, the radio frequency power is 300W-1800W, and the reaction time is 10s-60s.

11. The method of producing an intrinsically passivated structure according to any one of claims 6 to 10, wherein The step of treating the surface of the second intrinsic layer to form a third interface layer on the surface of the second intrinsic layer comprises: forming a microcrystalline silicon oxide layer as the third interface layer in a deposition device by introducing silane, hydrogen and carbon dioxide.

12. The method of claim 11, wherein the intrinsic passivation structure is prepared by a method comprising: The step of forming a microcrystalline silicon oxide layer in a deposition device by introducing silane, hydrogen and carbon dioxide comprises: The total flow of silane, hydrogen and carbon dioxide is 2000sccm-20000sccm, the flow ratio of silane to hydrogen is between 1:10 and 1:200, carbon dioxide accounts for 0.1%-2% of the total flow of the gas, the reaction temperature is 170℃-220℃, the pressure is 1.4mbar-3.2mbar, the radio frequency power is 500W-2500W, and the reaction time is 30s-120s.

13. The method of claim 6, wherein the intrinsic passivation structure is prepared by a process comprising: Further comprising: depositing a conductive thin film and an electrode on the doped microcrystalline silicon.

14. A battery (30) characterized by, The intrinsic passivation structure (20) according to any one of claims 1-5.

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