Switching one power transistor of a hybrid switching element on the basis of a control signal (target signal) and state-dependent switching of the other power transistor

Abstract

The invention relates to a method for switching a parallel circuit of power transistors (IT, MT) of different types, in which method a switching process of a first of the two power transistors (IT, MT) is carried out by changing the target level of a first switching signal (MS, IS). This switching signal directly controls this power transistor (IT, MT). The target level change is triggered by a specified control signal (PWM). A switching process of the other power transistor (MT, IT) is triggered in that an actual state signal (MM, IM; MP, IP), which characterises the actual switching state of the first power transistor, passes through a threshold value (SW). The invention further relates to a driver circuit (TS) for carrying out the method, to a correspondingly equipped power hybrid switch device, and to a correspondingly equipped vehicle traction inverter.

Description

[0001] Description

[0002] Switching one power transistor of a hybrid switching element based on a control signal (setpoint signal) and state-dependent switching of the other power transistor.

[0003] It is known to use power transistors for switching loads, especially in applications requiring a high switching frequency. For example, traction inverters in vehicles, power factor correction filters, or other active rectifiers in vehicle charging devices, or even DC-DC converters, particularly in vehicle charging devices, can be equipped with power transistors that are switched to enable current direction or current conversion.

[0004] Silicon-based switches such as IGBTs are used, particularly in vehicle traction inverters, to implement cost-effective power circuits. Other power transistors, for example MOSFETs such as SiC MOSFETs or GaN MOSFETs, offer higher slew rates than IGBTs, thus reducing switching losses, although this comes at the cost of such power transistors.

[0005] Different types of power transistors therefore have different advantages and disadvantages.

[0006] To combine their advantages, different types of power transistors are connected in parallel as a hybrid switching element (with respect to their power path). This allows, for example, combining power transistors that are advantageous during the switching process itself with power transistors that are particularly suitable for holding the current during the ON time. This enables the switching edge to be executed by the power transistor with the higher switching speed (slew rate), after which, following the switching edge, the more efficient power transistor is switched on to hold the current.

[0007] It is known to control such parallel circuits with a fixed time offset, whereby the switch with the higher switching speed is turned on first, and then the switching pulse for the other power transistor follows after a fixed time interval. When turning off, to utilize the higher switching speed, the power transistor with the higher switching speed is turned on after a fixed time interval following the turn-off of the other power transistor. This time interval must necessarily be designed such that this sequence is maintained despite variations between individual units and different operating points. Therefore, the time interval must be relatively generous, meaning that the semiconductor with the higher switching speed must also partially assume the function of holding the current. Thus, the control of switching events in hybrid semiconductor switches is, in some respects, in need of improvement.

[0008] One objective of the invention is to demonstrate an improved approach to switching hybrid switching elements.

[0009] This problem is solved by the method of claim 1. Further properties, features, embodiments and advantages are revealed by the dependent claims.

[0010] To avoid the power transistor with the higher switching speed having to carry the current alone for an unnecessarily long time due to the fixed time interval between switching events, it is proposed that the power transistor that switches downstream (i.e., after the other power transistor) in a switching event of the hybrid switch should be switched only when it is detected that the switching state of the leading power transistor has sufficiently ended. Thus, instead of switching according to a fixed timing schedule, it is proposed to detect the switching state of the power transistor that switches first (via the target control signal) and then trigger the switching operation of the other power transistor according to the detected switching state. In other words, the switching operation of the other power transistor is triggered based on the actual switching state of the first power transistor.The switching state of the first activated power transistor is determined by the level of the corresponding control signal or level change. This actual state signal reflects the current switching state of that power transistor. The actual state signal corresponds to the switching signal applied to the power transistor, to a load-side potential of the power path of the power transistor, or to a combination thereof. The hybrid switches described here are hybrid semiconductor switches. The switching state (i.e., the actual state signal) of the first activated power transistor is represented by the level of the corresponding switching signal applied to the first power transistor itself, by the level of the load-side potential of the relevant power path, or both.The current state signal can, in particular, be a gate signal, i.e., a signal that directly affects the switching state of the transistor in question. The current state signal can also be a signal from the load-side terminal (drain / collector in a collector- or drain-follower circuit, such as a low-side transistor; source / emitter in an emitter- or source-follower circuit), i.e., a signal that directly reflects the switching state of the transistor in question.

[0011] The current state signal (or its level) of the first power transistor is compared to a threshold value, and upon reaching the threshold, the switching operation of the second power transistor is triggered. When switching off, the subsequently actuated power transistor is switched in the same way, depending on the state of the first switching power transistor, with the first switching power transistor being switched off by a control signal (i.e., a target level change or a switching command). This can reduce the time elapsed between the switching operations of the two power transistors, especially compared to switching methods with a fixed time interval. This allows the current-carrying power transistor to be switched on earlier (and switched off later), so that the power transistor with the higher switching speed (the first power transistor) only has to carry the full current for a minimal time.This results in lower switching losses and also the possibility of using a fast-switching power transistor with only a low current carrying capacity, since this function can be supported by the current-carrying power transistor as soon as possible.

[0012] The invention provides for switching one of the power transistors in a parallel circuit according to a desired level change (i.e., based on a predetermined control signal). This switching process affects the power transistor that is switched first (i.e., following a predetermined control signal, such as a predetermined PWM signal). The desired level change of the switching signal of the first switching power transistor is triggered, or is the direct consequence, of a given control signal that the power transistors must convert. This control signal is a desired switching signal, which is output, for example, by a higher-level control system; if the control signal specifies a desired level change, this leads directly to the switching of the respective power transistor. The desired level change is derived directly from the control signal.A change in the level of the control signal directly leads to the desired level change in the switching signal of the relevant (first switching) power transistor. This is particularly true when the power transistors are functioning correctly or within the device in which these power transistors operate. The power transistor that switches first is therefore signal-controlled (controlled by the desired level change in the desired switching signal).

[0013] The switching operation of the second power transistor, however, is governed by the actual switching state of the first switching power transistor. In other words, the switching operation of the subsequent power transistor is state-controlled, i.e., dependent on the actual switching state of the power transistor that is switched first (by the control signal). The actual switching state of the first switched power transistor corresponds to an actual state signal that characterizes the actual switching state of the first power transistor. The switching operation of the second (subsequent) power transistor is triggered (immediately) by the actual state signal crossing a threshold value, specifically in the direction corresponding to the rising edge of the desired level change. The actual state signal is represented, in particular, by a voltage level.

[0014] The actual switching state of the first power transistor is determined by comparing its current state, or a corresponding switching state signal, with a threshold value. Switching the first switching power transistor (i.e., the signal-controlled switching power transistor) and switching the subsequent power transistor (i.e., the state-controlled switching power transistor) both involve the same switching edge of the desired control signal.

[0015] If the specified control signal specifies a change in the switching state of the parallel circuit, then one of the power transistors is switched in a signal-controlled manner (i.e., triggered by the control signal), in particular by means of a first switching signal that immediately follows the control signal (in a logical sense). To implement the change in the switching state, another of the power transistors is switched in a state-controlled manner (i.e., triggered by the state of the signal-controlled power transistor). The further power transistor is switched depending on the current switching state of the signal-controlled power transistor, in particular depending on the level of the switching signal that drives the signal-controlled power transistor, or in particular depending on a potential in the power path of the first power transistor that changes when the switching state in the power path itself changes.A load-side potential, or depending on another signal detectable at the first switched power transistor, which (possibly alongside other parameters) indicates the switching state of that power transistor (i.e., which changes itself when the switching state changes due to this change). These signals can also be used in combination to form the current state signal, or they can be evaluated (compared) as individual current state signals and then combined.The signals can be added (especially with weighting), or the signal with the strongest change (in the case of a switching state change) can be used, or individual current state signals (of different types) can be evaluated, for example by comparing them individually. The switching state change of the second (additional) power transistor is triggered when the first signal crosses the relevant threshold, or when both signals cross their respective thresholds. The load-side potential of a power path of a power transistor is the potential at the power terminal of the power transistor that is opposite to the power terminal that is permanently connected to a power potential. In particular, the load-side potential of a power path of a power transistor is the potential intended for connection to a load.If several power transistors are connected in series (e.g., as a half-bridge), the load-side potential is the potential at the junction between the power transistors (i.e., the phase connection in inverters). The load-side potential is the potential that changes during (fault-free) operation when the switching state changes.

[0016] Different switching state changes (i.e., target level changes in different directions or edges in different directions in the specified control signal) result in different power transistors being signal-controlled or state-controlled. The power transistor that switches signal-controlled (i.e., triggered by the control signal) when switching on (positive switching state change or target level change) becomes state-controlled when switching off (negative switching state change or target level change) (and therefore switches second / last when switching off). Conversely, the power transistor that switches signal-controlled (i.e., triggered by the control signal) when switching off (positive switching state change or target level change) becomes state-controlled when switching on (negative switching state change or target level change) (and therefore switches last when switching off).The power transistor that switches first upon signal activation and last upon state activation is preferably the one with the higher switching speed or steeper slew rate. This power transistor can be referred to as the first power transistor. The power transistor that switches first upon signal activation and last upon state activation is preferably the one with the higher current-carrying capacity. The roles of the different types of power transistors, or rather their control signals, are thus reversed during different switching operations (on or off).

[0017] The terms "first" and "next" in relation to the power transistors do not necessarily define the switching sequence. Rather, the first power transistor can actually be switched on first when power is turned on (signal-controlled, i.e., due to a predetermined control signal or target control signal), and this first power transistor can be switched on after the other power transistor when power is turned off (state-controlled, i.e., depending on the switching state or switching signal of the first power transistor).

[0018] A suitable method for switching a parallel circuit of power transistors of different types is proposed. The switching of the first of the two power transistors is carried out by a target level change of a first switching signal, where the target level change is triggered by a predetermined control signal, in particular by a switching edge provided therein. The first switching signal, which exhibits the target level change (triggered by the control signal), directly controls this power transistor. The target level change is the direct consequence of a level change in the predetermined control signal. This is also referred to as signal-controlled control. The first of the power transistors is thus switched by signal control.A switching operation of the second power transistor is triggered when the current state signal of the first power transistor crosses a threshold. This current state signal indicates the current switching state of the first power transistor. This switching operation of the second power transistor is corresponding to the level change in the control signal of the first power transistor; it is therefore the same switching operation of the parallel-connected power transistors. However, the switching operation of the second transistor is only indirectly dependent on the given control signal and is directly dependent on the switching signal of the first transistor.The switching operation of the other transistor is thus dependent on the state of the first transistor (represented by its switching signal, its load-side potential, or a combination thereof, particularly by representing the load-side potential as its complementary signal) and is therefore state-controlled. These (signal-controlled and state-controlled) switching operations of the two power transistors relate to the same switching edge of the given control signal. The switching operations of the two power transistors are therefore common, although not exactly synchronous, switching operations. The switching operations are executed differently (signal-controlled or state-controlled) for the transistors of different types.

[0019] The current state signal corresponds, for example, to the switching signal of the first power transistor, which is applied to this power transistor. Furthermore, the current state signal can correspond to a load-side potential of the power path of this (first) power transistor, or to a combination of these signals, whereby these signals can also be combined only after individual (logical) comparison as the results of the respective comparison.

[0020] Each power transistor of a given type can be implemented as a single transistor element or as several transistor elements of the same type connected in parallel. This allows the switching power or current-carrying capacity to be multiplied. Parallel connection of power transistors is particularly common in the switching elements of half-bridges.

[0021] To switch on power transistors of different types simultaneously, the first power transistor is switched on by a rising edge of the first switching signal, i.e., the switching signal applied to this power transistor. The desired level change of the first switching signal is a rising edge during switch-on. The first switching signal thus directly follows the specified control signal. The second transistor is switched on when the current state signal of the first power transistor exceeds a first threshold value, or when the rising edge of this current state signal exceeds the first threshold value. The complementary current state signal can be used, particularly if the load-side terminal is more positive than the other terminal of the parallel connection of the power transistors.Alternatively, the comparator can detect the crossing of a threshold value by the status signal at this point, especially if the status signal is given by the load-side potential of the power transistors.

[0022] The second transistor is thus switched on when the current state signal of the first transistor crosses the threshold value, for example, when a relevant switching signal exceeds the threshold value, or when the complementary signal of the load-side potential exceeds it, or when the load-side potential falls below the threshold value. For a better understanding of this, the complementary signal of the load-side potential is shown in Fig. 2.

[0023] When power transistors are switched off simultaneously, the roles are reversed: the power transistors are switched off together by switching off the second transistor using a rising edge as the desired level change (e.g., in a second switching signal that switches the second transistor on), where the desired level change is determined by the specified control signal. The desired level change in the switching signal applied to this power transistor is therefore determined by the specified control signal (and specifically not by the switching state of the other power transistor). The desired level change of the second switching signal (the one that controls the second transistor) is a falling edge when switching off; the specified control signal thus has a falling edge. The second switching signal is therefore directly determined by the specified control signal (or rather, by its falling edge).The first power transistor is switched off when the current state of the second power transistor exceeds a (second) threshold. A second threshold can be used for this purpose (adapted to the other transistor type), or a threshold corresponding to the first threshold can be applied. The first power transistor is thus switched off when the current state signal of the second transistor falls below the relevant threshold.

[0024] When switching off, the (first) power transistor, which is switched directly depending on the control signal when switching on, is switched by the switching state of the other (second) transistor, i.e., when the switching state of the other (second) transistor (or the corresponding current state signal that represents it) falls below the threshold value. When switching on, the (second) power transistor, which is switched directly depending on the specified control signal when switching off, is switched by the current state signal of the other (first) power transistor, i.e., when the current state signal of the other (first) transistor exceeds the threshold value.

[0025] One of the two transistors is thus switched according to a target level change in the specified switching signal. The target level change is directly dependent on the specified control signal or its level change. The specified control signal (target control signal) can, in particular, be implemented as a pulse-width modulated signal. Specifically, this signal can be received at an input of a driver circuit. The reception of the control signal (or a level change within it) thus directly triggers a switching operation in one of the transistors. Here, the power transistors are directly connected to the driver circuit. The driver circuit directly controls the power transistors. Direct control means, in particular, that no additional time delay is intentionally introduced during signal conversion; in particular, this (in the error-free case) excludes any dependence on another state or parameter.For one of the power transistors, the driver circuit directly implements the desired control signal. For the other power transistor, this is not the case (in a fault-free state); instead, it operates in a state-controlled manner (controlled by the switching state of the first power transistor). The switching of the other power transistor is therefore only indirectly triggered by the specified control signal, since the control signal first directly drives the first power transistor, whose resulting switching process (state-controlled) then triggers the switching of the other power transistor.

[0026] Preferably, the load-side potential, or a signal that reflects it, is used as the current state signal when switching on. When switching off, the switching signal applied to the power transistor, which is controlled by the specified control signal (i.e., the switching signal of the signal-controlled transistor), can be used as the current state signal.

[0027] In particular, the current state signal, i.e., the relevant switching signal or load-side potential, is fed back to a driver circuit, preferably the aforementioned driver circuit. The fed-back current state signal is compared with a relevant threshold value. The power transistor that is not directly driven by the control signal is driven by means of a current state signal from the other power transistor (such as the relevant switching signal or the load-side potential of this power transistor), in particular to change its level. The other transistor is driven by a current state signal from the first transistor to change its level when the comparison shows that the fed-back first current state signal (i.e., from the first transistor) crosses a threshold value. As mentioned, this depends in particular on the direction of the level change.The direction of the switching edge of the control signal determines which power transistor is driven by a predetermined switching signal exhibiting a target level change according to the control signal, and which power transistor is driven by an actual state signal of the other transistor, i.e., by comparing this actual state signal as a feedback signal with a threshold value, and the result driving that transistor. The designations of the transistors as first and second (other) transistor, or of the switching signals as first and second switching signal, preferably refer to different transistors or actual state signals (i.e., state signals of different transistors) in the case of opposing switching operations.

[0028] The switching operation of the first power transistor is preferably carried out by a driver controller driving a first driver output stage to generate the switching signal. In other words, it can be provided that a first driver output stage is driven according to a predetermined control signal. The execution of the corresponding switching operation of the second transistor specifically involves feeding the current state signal of the first transistor (e.g., the first switching signal, the load-side potential, or both) back to the driver controller. This signal is compared with (at least) a threshold value. Upon reaching the threshold value, a second driver output stage is driven to change the level. The comparison and driving of the driver output stage, in particular the driving according to a predetermined control signal, is performed primarily by means of the driver controller.The transistors are thus driven by means of driver output stages, which directly drive the power transistors and are controlled by a driver controller. The driver output stages and the driver controller are preferably part of the driver circuit.

[0029] A driver circuit can be used to execute the procedure described here. The driver circuit has outputs. These are configured for the (common) control of power transistors of different types. The driver circuit also has an input. This is configured to receive a predefined control signal (setpoint switching signal). The driver circuit is configured to initiate a setpoint level change in one of the outputs according to the received control signal. This serves to directly control the signal-controlled power transistor according to the predefined control signal.

[0030] The driver circuit also includes at least one comparator. This comparator is configured to compare the feedback current state signal (i.e., the first switching signal and / or the load-side potential of the first power transistor) with a threshold value. The at least one comparator is connected to another of the outputs. To control one or the other power transistor signal-controlled, depending on the direction of the switching state change, and to control the other power transistor state-controlled, the comparator can be connected upstream of both outputs (possibly via a multiplexer). This allows the comparator to be selectively connected to one or the other output, depending on the direction of the switching state change in the control signal. The comparator can be implemented as a (discrete) circuit, in which case an adjustable signal filter is provided between the comparator and the outputs.The signal switch then connects the comparator to the first output in the first direction of the switching state change in the specified control signal, and to the second output in the second direction of the switching state change in this control signal. The other output is controlled by the driver circuit or the driver controller according to the specified control signal.

[0031] To implement state-controlled operation, the driver circuit has a feedback input. This input allows the driver circuit to detect the switching signal executed according to a predefined control signal and / or the load-side potential of the relevant power transistor. A signal representing the switching state of one of the power transistors can be fed to the driver circuit via this feedback input; that is, the current state signal from the power transistor can be fed back via the feedback input. The feedback input is connected upstream of the comparator. The comparator is therefore connected downstream of the comparator to receive the first switching signal (i.e., the signal-controlled switching signal).

[0032] Embodiments of the driver circuit include a driver controller and driver output stages. The driver output stages are connected downstream of the driver controller. The driver controller is connected to the driver output stages via a control signal. The driver output stages provide the outputs of the driver circuit. Power transistors (with their control terminals) can be connected to these outputs. The driver controller is specifically configured to receive signals from the outputs of the driver output stages, for example, when a switching signal from a transistor is used as the current state signal. In this case, the driver controller preferably has a feedback input configured to receive the current state signal (switching signal and / or load-side potential of the transistor). Thus, in addition to the control connection between the driver controller and the driver output stages it controls, there is a feedback connection between the driver output stages and their outputs.The relevant load-side connection of the power transistor and the driver control, which has a corresponding input (feedback input) for this purpose. The comparator can be provided in the driver control, in particular, with the feedback input being connected upstream of the comparator.

[0033] The driver circuit is preferably configured to operate either a first output according to the predetermined control signal (signal-controlled operation), or the first output according to the output signal of the (at least one) comparator (state-controlled operation), depending on the direction of the control signal level change. In particular, the driver circuit is configured to operate a further output (e.g., the second output) according to the comparator output signal or according to the predetermined control signal (setpoint control signal), depending on the direction of the control signal level change. With a first-direction level change, the first output is operated according to the control signal, and the other, or second, output is operated according to the comparator signal.In the opposite, second direction of the level change, the first output is operated according to the comparator's output signal, and the second output is operated according to the control signal. Operation according to the comparator means state-controlled operation, and operation according to the control signal corresponds to signal-controlled operation.

[0034] A power hybrid switching device can be designed with the driver circuit according to one of the preceding claims. The switching device comprises power transistors of different types connected in parallel, which is why it can also be referred to as a hybrid switching device. The control electrodes of the different types of power transistors are connected to different outputs of the driver circuit. Transistor elements of the same type are connected to the same output, particularly if a power transistor comprises several parallel-connected transistor elements of the same type. Power transistors are defined as transistors whose continuous rated current carrying capacity is at least 10 A or at least 5 A. Power transistors preferably have a reverse voltage of more than 60 V, at least 650 V, or at least 1000 V.The load-side potentials can also be transmitted to the driver circuit via signal transmission (e.g., via a voltage divider and / or a galvanic isolation element), in particular to transmit the current state signal of the driver circuit.

[0035] A vehicle traction inverter with multiple half-bridges can be provided, wherein the switching elements of the half-bridges are each formed by means of power transistors of different types, which are preferably controlled by the driver circuit described herein or according to the method described herein. A vehicle power factor correction filter, for example, of a vehicle-mounted charger, can also be formed with multiple half-bridges, the switching elements of which are formed by power transistors of different types (connected in parallel). The hybrid switching device described herein can also be used in a chopper of a vehicle-mounted DC-DC converter. The inverter, the power factor correction filter, and / or the chopper are preferably designed for nominal power ratings of more than 10 kW, in particular more than 20 or 50 kW. A vehicle traction inverter can comprise multiple phases.Each phase is represented by a half-bridge, with each half-bridge having two power transistors connected in series, configured as a hybrid switching device.

[0036] The parallel connection of power transistors of different types is, in particular, a parallel connection of one or more SiC MOSFETs (or GaN MOSFETs) and one or more silicon-based IGBTs. The power transistors of different types can have different band gaps and / or electron mobilities. The power transistors of one type are driven synchronously. The power transistors of the other type are also driven synchronously. Parallel-connected transistor elements are controlled synchronously, for example, by means of the same switching signal. The switching signals for the power transistors of different types can have different ON levels and different OFF levels. The hybrid switches described here are hybrid semiconductor switches.

[0037] Figures 1 and 2 are symbolic representations and serve to illustrate embodiments.

[0038] Figure 1 shows a driver circuit TS, which receives a PWM control signal externally via input E. A higher-level control device MC is depicted, which generates the PWM control signal outside of the driver circuit TS and feeds it in via input E. The PWM control signal is a setpoint signal and is intended for conversion by the driver circuit. Specifically, the PWM control signal is a pulse-width modulated signal. The higher-level control device MC can, for example, include a control system or a controller, such as a field-oriented motor controller, which generates a control signal in the form of a pulse-width modulated signal (PWM) according to specifications.

[0039] The driver circuit TS has a first output AM and a second (different) output AI. In the illustrated example, the first output AM is intended for driving a power MOSFET MT, for which purpose the AM output is connected to the gate G of the MOSFET MT. The second output AI is intended for driving a power IGBT, for which purpose the AI ​​output is connected to the gate IG of the IGBT IT. This connection can be direct or can be made via a series resistor V (gate resistor). A diode DI is connected in parallel to the collector K and emitter E of transistor IT. A first driver output stage HMT, LMT is provided for generating the first switching signal and the switching signal to be output at AM, respectively.The first driver output stage comprises two series-connected driver transistors HMT and LMT, where transistor HMT (as indicated by the first letter of its reference symbol) is a high-side transistor of the output stage, and transistor LMT (as indicated by the first letter of its reference symbol) is a low-side transistor of the same output stage. The connection between the two driver transistors forms the output AM. The outer ends of the series-connected driver transistors HMT and LMT are connected (via their respective, optional series resistors R1 and R2) to two reference potentials T+ and T- of the driver circuit TS. A supply voltage exists between the reference potentials T+ and T-, provided by the voltage source UQ of the driver circuit TS. The reference potentials T+ and T- can also be referred to as supply potentials. The two transistors HMT and LMT of the first driver output stage are both MOSFETs, but with opposite polarities.The gates of the MOSFET HMT, LMT and thus the control inputs of the first driver stage are connected to the respective control outputs HMS, LMS.

[0040] The second driver output stage HIT, LIT is designed like the first driver output stage, but with a direct connection to the reference potentials T+, T- and with its own control outputs of the driver controller TC, which are connected to the control terminals (gates) of the driver transistors HIT, LIT of the driver output stage. The first and second driver output stages are thus individually connected to their respective driver transistors via two control outputs each.

[0041] Embodiments not shown provide for at least one resistor to be connected between the reference potentials and the outer ends of the series-connected driver transistors HIT, LIT. Instead of or in combination with the resistors connecting the driver transistors HIT, LIT or HMT, LMT to driver reference potentials T+, T-, other components or supply circuits can also be provided, such as current mirrors, Zener diodes, voltage converters, filter elements, filter circuits, or the like. The junction between the transistors HIT, LIT, is connected to the output AI; this connection can be direct, or, as shown, include a resistor (gate resistor) between the output AI and the junction of the driver transistors HIT, LIT. The driver output stages HMT, LMT or HIT, LIT can be configured as switchable current sources or as switchable voltage sources. In general, the driver output stages HMT, LMT or HIT, LIT form...HIT, LIT are the signal sources for the switching signals of the transistors MT, IT, wherein these signal sources are switchable and in particular are connected downstream of the driver control TC in order to be controlled by it.

[0042] If a low level (to switch off the respective power transistor MT, IT) is to be provided at output AM or AI, then the respective low-side transistor LMT or LIT receives an ON signal, while the respective high-side transistor HMT or HIT receives an OFF signal. The signals are output to the corresponding driver transistors via the LMS or LIS terminals.

[0043] If a high level (to switch on the power transistors MT and IT) is required at output AM or AI, then the respective low-side transistor LMT or LIT receives an OFF signal, while the respective high-side transistor HMT or HIT receives an ON signal. These signals are then output to the corresponding driver transistors via the LMS and LIS terminals, respectively.

[0044] The respective level at output AM or AI results from the connection of the switched-on driver transistor with the supply potential or reference potential T+, T-.

[0045] It is shown that the driver transistors HMT, LMT, HIT, LIT can be connected to the reference potentials T+, T- of the driver circuit TS via one or more resistors R1, R2. It is further shown that a driver output stage can be connected directly or via a series resistor V to the power transistors MT, IT. The driver output stage can have a resistor V located between the power transistors and the respective output AI. The resistors R1, R2, V serve to limit the current flowing or to reduce the voltage level applied to the gate IG.

[0046] To enable state-controlled operation, in one illustrated embodiment the switching signals of outputs AM and AI are fed back to the driver controller TC. This embodiment relates to the use of the switching signals as current state signals. This embodiment is described below; another variant is described subsequently. For the current state signals, the driver controller TC has an input MM and an input IM. The input MM is connected to output AM (intended for driving the MOSFET MT). This allows the first switching signal present at output AM to be fed back to the driver controller TC for evaluation. This enables the switching signal at output AM to be compared with a threshold value in order to then trigger the switching operation at the other output AI. This is the case, for example, when the device is switched on, i.e.,First, the power transistor MT is switched on, followed by the power transistor IT, which is switched on depending on the level of the first switching signal. The driver controller TC has a comparator SV that receives the signals from the inputs MM and IM. The comparator SV thus receives the control signals for the driver outputs AM and AI.

[0047] Input IM is connected to output AI (intended for driving IGBT IT). This allows the second switching signal present at output AI to be fed back to the driver controller TC for evaluation. This enables the switching signal at output AI to be compared with a threshold value in order to then trigger the switching operation at the other output AM. This is the case, for example, when switching off, i.e., when power transistor IT is switched off first, followed by power transistor MT, which is switched off depending on the level of the second switching signal.

[0048] Another option is to use the load-side potentials MP and IP as current state signals. This option is shown with dashed lines. The diagram shows that the power transistors MT and IT are connected in parallel, and that emitter E and source S are permanently connected to the negative high-voltage potential HV-. The terminal for emitter E and source S is thus permanently connected to a supply potential or reference potential. The potential there does not change with the switching state of transistors IT and MT. On the other side of transistors MT and IT, the load-side potential exists at drain D and collector K, respectively. This side is not directly connected to the positive high-voltage potential HV-, but leads to a load (such as a winding, not shown) through which transistors MT and IT are (indirectly or directly) connected to the positive high-voltage potential HV-. Therefore, the potential there indicates the switching state of transistors IT and MT.This potential is fed back as the load-side potential. Due to the parallel connection, the two load-side potentials of transistors MT and IT are identical, so only one of the load-side potentials needs to be fed back, for example, to a dedicated input of the driver controller. As mentioned, the load-side potential IP / MP can be used as the current state signal, or the previously mentioned switching signals can be used at outputs AN and AI, or a combination of both.

[0049] Upon power-up, the first switching signal is generated from the PWM control signal at input E, so that a turn-on edge at input E immediately generates a turn-on edge in the first switching signal at output AM. At the other output AI, a turn-on signal or a rising edge is generated depending on the switching state of the power transistor MT (detectable by the level at input MM or output AM, or the load-side potential IP / MP, represented for clarity as the complementary signal MP). Thus, upon power-up, the power transistor IT is switched on depending on the switching state of transistor MT. The comparator SV is used to compare the level at the respective output AM, AI, or MP (also present at inputs MM and IM) with a corresponding threshold value. The feedback loops must be taken into account.The connection between output AI and input IM provides feedback of the second switching signal, and the signal at output AM is fed back to input MM, i.e., the first switching signal is fed back to the driver control TC. The load-side potential MP or IP is also fed back to the driver control TC. During switch-off, the second switching signal is generated from the PWM control signal at input E, so that a switch-off edge at input E directly generates a switch-off edge in the second switching signal at output AI. During switch-off, a switch-off signal or a falling edge is generated at the other output AM, depending on the switching state of the power transistor IT (detectable by the level at input IM or output AI, or by the load-side potential IP or MP). Thus, during switch-off, the power transistor MT is switched depending on the switching state of the power transistor IT.

[0050] This ensures that one power transistor, MT, leads (in terms of timing) with the turn-on edge and follows the other power transistor, IT, with the turn-off edge. This means that during the switching edges, the current is carried only by power transistor MT, while after the turn-on edge ends, power transistor IT is switched on, and before the turn-off edge begins, power transistor IT is switched off. The control signals of the driver transistors HMT and MLT are inversely proportional. This also applies to the driver transistors HIT and LIT. If one of the low-side transistors is on, the associated high-side transistor is off, and vice versa. During a switching operation, the ON state of one transistor in the respective driver stage is first changed to an OFF state, whereupon the other transistor in the driver stage is switched from the OFF state to the ON state.For the sake of clarity, only the state of one transistor of a driver output stage is shown in Figure 2 to illustrate the signal waveforms, while the switching state of the other transistor of the same driver output stage results from the aforementioned behavior.

[0051] Figure 2 illustrates a switch-on process and a subsequent switch-off process using several signals. The PWM signal represents the control signal at input E, which is to be converted by the parallel-connected power transistors. The HMS signal represents the level of the control signal of transistor HMT (high-side transistor of the driver stage for MOSFET MT). The LMS signal represents the level of the control signal of transistor LMT (low-side transistor of the driver stage for MOSFET MT). The HIS signal represents the level of the control signal of transistor HIT (high-side transistor of the driver stage for IGBT IT). The LIS signal represents the level of the control signal of transistor LIT (low-side transistor of the driver stage for IGBT IT). The MP signal represents the load-side level at transistors IT and MT. The IM signal represents the level of the second switching signal.the level at output AI.

[0052] Figure 2 is not to scale; the levels shown are only varied for clarity. The amplitudes of the signals shown are arbitrary and, in particular, do not indicate the actual amplitude or the ratio of amplitudes between different signals. The PWM signal, in particular, may have a smaller amplitude than the other signals shown. The waveforms are also purely symbolic.

[0053] The turn-on process begins at time tO with a rising edge of the PWM control signal originating from the higher-level control MC. This is immediately converted (by the driver control TC) into a turn-on signal for the AM output to switch on the power transistor MT. The conversion of the PWM control signal results in a rising edge at the HMS output to switch on the high-side transistor HMT of the first driver output stage. The non-ideal behavior of the HMT transistor is symbolically represented by a finite slope of the HMS signal. Switching on the HMT transistor leads to a rising level at the first AM output. This results in the turn-on of the MT transistor, which pulls the MP signal at the load-side terminal of the transistor parallel circuit MT, IT to the HV- potential. The level of the MP signal—complementary to the MP signal in Fig. 1—thus increases.This level therefore also corresponds to the switching state of the power transistor MT.

[0054] The rising level MP at input MM (which corresponds to an increasing ON state of the power transistor MT) exceeds the (first) threshold SW at time t1, which can be monitored, for example, by the comparator SV. Exceeding the threshold SW at time t1 triggers the turn-on process of the other power transistor IT. This turn-on process of power transistor IT is carried out by increasing the level at output HIS, i.e., the turn-on level of the high-side transistor HIT of the driver stage of output AI (which is intended for power transistor IT). This then also gives output AI a high potential, thus turning on power transistor IT.

[0055] Thus, the switching signal at output AM is increased as a direct consequence of the rising edge of the PWM signal, thereby switching on the power transistor MT. The increase in signal MP, by exceeding the threshold SW, triggers the switch-on process for transistor ET. This switch-on process is carried out by switching on transistor HIT via output HIS, thereby increasing the gate voltage at gate IG of power transistor IT. A conducting power path is established between the collector K and the emitter E of power transistor IT after the switching process of power transistor T (detectable by the first switching signal, see signal MM) has sufficiently completed. The threshold SW (and the threshold SW') are preferably configured such that they represent a substantially completed ON state of the respective power transistor.

[0056] At the end of the ON level of the PWM control signal, it exhibits a falling edge, as seen at time t0'. Until this falling edge (at time t0'), the IM signal, i.e., the second switching signal fed back from output A, is at a high level. The falling edge of the PWM signal directly triggers a switch-off process for the power transistor IT. This is accomplished by switching on the transistor LIT. The transistor LIT is switched on by raising the level of output LIS as a direct consequence of the falling edge of the PWM signal. Switching on the transistor LIT (and switching off the transistor HIT) results in a falling edge at output AI, which in turn switches off the power transistor IT. Since the signal from output AI is fed back to input IM, a falling edge also occurs at input IM.

[0057] The signal at input IM or output AI falls below the threshold SW at time t1'. This triggers the turn-off of transistor MT, specifically by generating a rising signal at output LMS. The rising signal at output LMS turns on the low-side transistor LMT. Turning on LMT generates a falling switching signal at the first output AM. This turns off the connected power transistor MT. Since the falling switching signal for power transistor MT is generated on the falling edge at the second driver output AI (input IM), transistor MT is turned off only after transistor ET.

[0058] The switching on of power transistor MT and the switching off of power transistor IT are the direct consequence of the corresponding edge of the PWM control signal. This corresponds to signal-dependent control. The switching on of power transistor IT and the switching off of power transistor MT are the direct consequence of the corresponding edge of the signal at outputs AM and AI, which are fed back via IM, MM, and IP / IM and reflect the current switching state of the respective (other) power transistor. This corresponds to state-dependent control. The driver controller TC or the driver circuit TS generates corresponding signals at outputs HMS, LMS, HIS, and LIS based on the signals at inputs E, IM, and MM. These signals are then fed to the respective driver transistors HMT, LMT, LIT, and HIT for their control.The driver transistors HMT, LMT, LIT, HIT thereby generate the relevant switching signals at the driver outputs AM, AI, which are used to control the power transistors MT, IT.

[0059] The PWM signal is directly converted by the driver controller TC or the driver circuit TS into corresponding signals at the respective outputs (HMS, LMS, HIS, LIS). The signals at the driver inputs IM, MM (and thus the signals at the driver outputs AI, AM) are processed by the comparator SV, i.e., they are compared with relevant threshold values ​​in order to generate corresponding signals at the outputs HMS, LMS, HIS, LIS and thus also at the driver outputs AM, AI, based on the comparison result.

Claims

Patent claims 1. Method for switching a parallel circuit of power transistors (IT, MT) of different types, wherein a switching operation of one of the two power transistors (IT, MT) is carried out by a setpoint level change of a first switching signal (MS, IS) which directly controls this power transistor (IT, MT), wherein the setpoint level change is triggered by a predetermined control signal (PWM), and a switching operation of the other power transistor (MT, IT) is triggered by an actual state signal (MM, IM; MP, IP), which characterizes the actual switching state of the first power transistor, crossing a threshold value (SW).

2. Method according to claim 1, wherein the actual state signal (MM, IM; MP, IP) corresponds to the switching signal (IM, MM) of the first power transistor (MT, IT) which is applied to this power transistor (MT, IT), or the actual state signal (MM, IM; MP, IP) corresponds to a load-side potential (MP, IP) of the power path of this power transistor (MT, IT), or a combination thereof.

3. Method according to claim 1 or 2, wherein the power transistors (IT, MT) are switched on together by means of a switching operation of the first power transistor (MT), which is triggered by the control signal (PWM), and by means of a switching operation of the second power transistor (IT), which is triggered by the rising edge of the actual state signal exceeding a first threshold value (SW).

4. Method according to claim 1, 2 or 3, wherein the power transistors (IT, MT) are switched off together by means of a switch-off process of the second power transistor (IT), which is triggered by the control signal (PWM) and which is carried out by a target level change of a second switching signal (IM), which is provided as a falling edge and which directly controls this power transistor (IT), and by means of a switch-off process of the first power transistor (MT), which is triggered by the falling edge of the first switching signal (MM) falling below a second threshold value (SW).

5. Method according to one of the preceding claims, wherein the desired level change in the switching signal (IM, MM) is generated by triggering a level change in the predetermined control signal (PWM) received at an input (E) of a driver circuit (TS) in a first of the switching signals (MM, IM) which are directly driven by the driver circuit (TS) to the power transistors (IT, MT).

6. Method according to one of the preceding claims, wherein the actual state signal (MM, IM; MP, IP) is fed back to a driver circuit (TS) and compared with a threshold value (SW, SW), wherein the other power transistor is driven with a second switching signal (IM, MM) to change level when the comparison shows that the fed-back actual state signal (MM, IM; MP, IP) crosses a threshold value (SW, SW).

7. A method according to any of the preceding claims, wherein the switching operation of the first power transistor (IT, MT) is carried out by a driver controller (TC) driving a first driver output stage (HMT, LMT, HIT, LIT) to generate the first switching signal (MM, IM), and the execution of the switching operation of the other power transistor provides that the current state signal (MM, IM; MP, IP) is fed back to the driver controller (TC), which compares the current state signal (MM, IM; MP, IP) with a threshold value (SW, SW) and, upon reaching the threshold value (SW, SW), drives a second driver output stage (HIT, LIT, LMT, HMT) to change the level.

8. Driver circuit (TS) configured for carrying out the method according to one of the preceding claims, with outputs (AM, AI) configured for jointly controlling the power transistors (IT, MT) of different types, and with an input (E) configured for receiving an actual state signal (MM, IM; MP, IP) which causes the target level change in one of the outputs (AM, AI), as well as with a comparator configured for comparing the actual state signal (MM, IM; MP, IP) with the threshold value (SW, SW), wherein the comparator is connected to another of the outputs (AI, AM) for control.

9. Driver circuit (TS) according to claim 8, wherein the driver circuit (TS) has at least one feedback input (MM, IM) configured to receive the current state signal (MM, IM; MP, IP), wherein the comparator (SV) is connected downstream of the feedback input (MM, IM) for receiving the current state signal (MM, IM; MP, IP).

10. Driver circuit (TS) according to claim 8 or 9, comprising a driver controller (TC) and several driver output stages (HMT, LMT; HIT, LIT) downstream of the driver controller (TC), which provide the outputs (AM, AI), wherein the driver controller (TC) is configured to receive signals from the outputs of the driver output stages (HMT, LMT; HIT, LIT) and / or a load-side potential (MP, IP) of the power path of a connected power transistor (MT, IT).

11. Driver circuit according to claim 8, 9 or 10, which is configured depending on the direction of the level change of the control signal (PWM): (a) to operate one of the outputs (AM, AI) according to the control signal (PWM) and to operate the other output (AI, AM) according to the output signal of the comparator (SV), or (b) to operate the first of the outputs (AI, AM) according to the output signal of the comparator (SV), and to operate the second output (AM, AI) according to the control signal (PWM).

12. Power hybrid switching device with the driver circuit according to one of the preceding claims and with parallel-connected power transistors (IT, MT) of different types, the control electrodes of which are connected to the outputs of the driver circuit (TS).

13. Vehicle traction inverter with multiple half-bridges, each of whose switching elements is designed as a power hybrid switching device according to claim 12.

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