Digital phase shifter

Abstract

This digital phase shifter is provided with a first digital phase shift circuit group, a second digital phase shift circuit group, a digital phase shift circuit, a connection portion for connecting a digital phase shift circuit of the first digital phase shift circuit group and the digital phase shift circuit, and a connection portion for connecting a digital phase shift circuit of the second digital phase shift circuit group and the digital phase shift circuit. The digital phase shift circuit and any one of the digital phase shift circuits are configured as a relaxation circuit for reducing a discontinuity in phase shift amount. The relaxation circuit is a digital phase shift circuit having a smaller phase shift amount than that of a digital phase shift circuit other than the relaxation circuit.

Description

Digital Phase Shifter

[0001] This application claims priority from Japanese Patent Application No. 2024-120301, filed on July 25, 2024, the contents of which are incorporated herein by reference.

[0002] In recent years, digitally controlled phase shifters (digital phase shifters) for high-frequency signals such as microwaves, quasi-millimeter waves, and millimeter waves have been developed. A digital phase shifter has a configuration in which multiple digital phase shift circuits are connected in cascade as individual units. When the digital phase shifter is configured with digital phase shift circuits connected in a row, the length of the digital phase shifter becomes long.

[0003] The following Patent Document 1 discloses a digital phase shifter whose length is shortened by using a bent configuration with a connecting portion such as a bent line having a bent structure. Specifically, the following Patent Document 1 discloses a digital phase shifter having a bent configuration with a 180° bend connecting portion and a digital phase shifter having a bent configuration with a 90° bend connecting portion.

[0004] Japanese Patent No. 7076658

[0005] In the digital phase shifter disclosed in the aforementioned Patent Document 1, good impedance matching is achieved at the point where the bend-type connector and the digital phase shift circuit are connected. However, it has been found that, despite good impedance matching, a large jump in the amount of phase shift occurs before and after the bend-type connector. This large jump in the amount of phase shift reduces the controllability of the digital phase shifter, and therefore needs to be eliminated.

[0006] The present invention has been made in view of the above circumstances, and has as its object to provide a digital phase shifter that can eliminate large jumps in the amount of phase shift that occur before and after a connection portion.

[0007] In order to solve the above problems, a digital phase shifter according to a first aspect of the present invention comprises a first digital phase shift circuit group in which a plurality of digital phase shift circuits are cascaded, a second digital phase shift circuit group in which a plurality of digital phase shift circuits are cascaded, and a bend-type connection portion connecting a first digital phase shift circuit located at one end of the first digital phase shift circuit group and a second digital phase shift circuit located at one end of the second digital phase shift circuit group, wherein the digital phase shift circuit comprises a signal line, a pair of inner lines provided on both sides of the signal line, a pair of outer lines provided outside the inner lines, a first ground conductor connected to each first end of the inner line and the outer line, a second ground conductor connected to each second end of the outer lines, and a pair of electronic switches respectively provided between each second end of the inner line and the second ground conductor, a first connection line electrically connecting the signal line of the first digital phase shift circuit to the signal line of the second digital phase shift circuit; a second connection line electrically connecting each of the inner lines of the first digital phase shift circuit to each of the inner lines of the second digital phase shift circuit; and a third connection line electrically connecting each of the outer lines of the first digital phase shift circuit to each of the outer lines of the second digital phase shift circuit, wherein either the first digital phase shift circuit or the second digital phase shift circuit is a mitigation circuit that mitigates jumps in the amount of phase shift, and the mitigation circuit is the digital phase shift circuit having a smaller amount of phase shift than the digital phase shift circuits other than the mitigation circuit.

[0008] In the digital phase shifter according to the first aspect of the present invention, either the first digital phase shift circuit of the first digital phase shift circuit group or the second digital phase shift circuit of the second digital phase shift circuit group, which are connected by a connection section, is a mitigation circuit that mitigates jumps in the amount of phase shift. Here, the mitigation circuit is a digital phase shift circuit that has a smaller amount of phase shift than the digital phase shift circuits other than the mitigation circuit. This makes it possible to eliminate large jumps in the amount of phase shift that occur before and after the connection section.

[0009] A digital phase shifter according to a second aspect of the present invention may be the digital phase shifter according to the first aspect of the present invention, further comprising a third digital phase shift circuit electrically connected to the first digital phase shift circuit and the second digital phase shift circuit, wherein the connection portion has a first connection portion connecting the first digital phase shift circuit and the third digital phase shift circuit and a second connection portion connecting the second digital phase shift circuit and the third digital phase shift circuit, and the third digital phase shift circuit may be the mitigation circuit.

[0010] A digital phase shifter according to a third aspect of the present invention may be the digital phase shifter according to the first or second aspect of the present invention, wherein the digital phase shift circuit comprises a capacitor electrically connected between the signal line and at least one of the first ground conductor and the second ground conductor, and an electronic switch that switches whether or not to connect the capacitor between the signal line and at least one of the first ground conductor and the second ground conductor.

[0011] A digital phase shifter according to a fourth aspect of the present invention may be configured such that, in the digital phase shifter according to the third aspect of the present invention, the mitigation circuit satisfies at least one of the following conditions: a length thereof is shorter than that of the digital phase shift circuits other than the mitigation circuit; a distance between the signal line and the inner line is longer than that of the digital phase shift circuits other than the mitigation circuit; a distance between the signal line and the outer line is shorter than that of the digital phase shift circuits other than the mitigation circuit; the capacitor is smaller than that of the digital phase shift circuits other than the mitigation circuit; and the pair of electronic switches is smaller than that of the digital phase shift circuits other than the mitigation circuit.

[0012] A digital phase shifter according to a fifth aspect of the present invention is the digital phase shifter according to any one of the first to third aspects of the present invention, wherein the outer line of the mitigation circuit is formed in a multilayer structure.

[0013] A digital phase shifter according to a sixth aspect of the present invention may be the digital phase shifter according to any one of the first to third aspects of the present invention, wherein the mitigation circuit is the digital phase shifter in which one of the inner lines is omitted.

[0014] A digital phase shifter according to a seventh aspect of the present invention may be the digital phase shifter according to any one of the first to sixth aspects of the present invention, wherein when control is performed to switch the digital phase shift circuits sequentially from the high delay mode to the low delay mode in the order in which the digital phase shift circuits are connected, if the first digital phase shift circuit is set as the mitigation circuit, the control is performed in a direction from the first digital phase shift circuit to the second digital phase shift circuit, and if the second digital phase shift circuit is set as the mitigation circuit, the control is performed in a direction from the second digital phase shift circuit to the first digital phase shift circuit.

[0015] A digital phase shifter according to an eighth aspect of the present invention may be the digital phase shifter according to any one of the first to sixth aspects of the present invention, wherein when control is performed to switch the digital phase shift circuits sequentially from the low delay mode to the high delay mode in the order in which the digital phase shift circuits are connected, if the first digital phase shift circuit is set as the mitigation circuit, the control is performed in a direction from the second digital phase shift circuit to the first digital phase shift circuit, and if the second digital phase shift circuit is set as the mitigation circuit, the control is performed in a direction from the first digital phase shift circuit to the second digital phase shift circuit.

[0016] A digital phase shifter according to a ninth aspect of the present invention may be the digital phase shifter according to any one of the first to eighth aspects of the present invention, wherein the connection portion comprises a ground layer arranged above and / or below the first connection line and the second connection line, and a via hole connecting at least the second connection line and the ground layer.

[0017] According to the present invention, it is possible to eliminate large jumps in the amount of phase shift that occur before and after the connection portion.

[0018] 1 is a plan view showing a schematic configuration of a digital phase shifter according to a first embodiment of the present invention. FIG. 2 is a perspective view showing the configuration of a digital phase shift circuit according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a high delay mode of the digital phase shift circuit according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating a low delay mode of the digital phase shift circuit according to the first embodiment of the present invention. FIG. 5 is a diagram illustrating an example of a mitigation circuit according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating an example of a mitigation circuit according to the first embodiment of the present invention. FIG. 7 is a diagram illustrating an example of a mitigation circuit according to the first embodiment of the present invention. FIG. 8 is a perspective view illustrating another example of a mitigation circuit according to the first embodiment of the present invention. FIG. 9 is a cross-sectional view taken along line A-A in FIG. 1 . FIG. 10 is a cross-sectional view showing a modified example of a connection portion according to the first embodiment of the present invention. FIG. 11 is a diagram illustrating a first operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 12 is a diagram illustrating a first operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 13 is a diagram illustrating a first operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 1 is a diagram for explaining a first operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 2 is a diagram for explaining a first operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 3 is a diagram for explaining a first operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 4 is a diagram for explaining a first operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 5 is a diagram for explaining a first operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 6 is a diagram for explaining a first operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 7 is a diagram for explaining a first operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 8 is a diagram for explaining a second operation of the digital phase shifter according to the first embodiment of the present invention.FIG. 1 is a diagram illustrating a second operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating a second operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a second operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 4 is a diagram illustrating a second operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 5 is a diagram illustrating a second operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 6 is a diagram illustrating a second operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 7 is a diagram illustrating a second operation of the digital phase shifter according to the first embodiment of the present invention. FIG. 8 is a diagram illustrating a second operation of the digital phase shifter according to the first embodiment of the present invention. 10A and 10B are diagrams illustrating a second operation of the digital phase shifter according to the second embodiment of the present invention, and FIG. 10C are diagrams illustrating a second operation of the digital phase shifter according to the second embodiment of the present invention.

[0019] Hereinafter, digital phase shifters according to embodiments of the present invention will be described in detail with reference to the drawings.

[0020] [First Embodiment] <Digital Phase Shifter> Fig. 1 is a plan view showing a schematic configuration of a digital phase shifter according to a first embodiment of the present invention. As shown in Fig. 1, the digital phase shifter 100 of this embodiment includes a plurality of digital phase shift circuits 10, a connection portion 20a (first connection portion), and a connection portion 20b (second connection portion). The digital phase shifter 100 shifts the phase of a signal S in a predetermined frequency band using a plurality of cascade-connected digital phase shift circuits 10. The signal S is a high-frequency signal having a frequency band such as microwave, quasi-millimeter wave, or millimeter wave.

[0021] The multiple digital phase shift circuits 10 are electrically connected in cascade. In the example shown in Fig. 1, eleven digital phase shift circuits 10 are connected in cascade. However, the number of digital phase shift circuits 10 is not limited to that shown in Fig. 1, as long as it is two or more. In the example shown in Fig. 1, for convenience of explanation, the eleven cascade-connected digital phase shift circuits 10 are referred to as digital phase shift circuits 10-1, 10-2, ..., 10-11 in the order in which the signal S flows. However, the direction in which the signal S flows may be reversed.

[0022] 1 , the first to fifth cascaded digital phase shift circuits 10-1 to 10-5 constitute a first digital phase shift circuit group 30. The seventh to eleventh cascaded digital phase shift circuits 10-7 to 10-11 constitute a second digital phase shift circuit group 31. The sixth cascaded digital phase shift circuit 10-6 is electrically connected between the first digital phase shift circuit group 30 and the second digital phase shift circuit group 31.

[0023] In this embodiment, either one of the digital phase shift circuits 10-5 and 10-7 and the digital phase shift circuit 10-6 form a mitigation circuit RC. This mitigation circuit RC is a circuit that mitigates large jumps in the amount of phase shift that occur before and after the connecting portions 20a and 20b. The mitigation circuit RC is, for example, a digital phase shift circuit 10 that has a smaller amount of phase shift compared to the digital phase shift circuits 10 other than the mitigation circuit RC. The specific configurations of the digital phase shift circuit 10 and the mitigation circuit RC will be described later.

[0024] The connecting portions 20a and 20b have a 90° bend shape (bend type). The connecting portion 20a connects the digital phase shift circuit 10-5 (first digital phase shift circuit) located at one end of the first digital phase shift circuit group 30 to one end of the digital phase shift circuit 10-6 (third digital phase shift circuit). The connecting portion 20b connects the digital phase shift circuit 10-7 (second digital phase shift circuit) located at one end of the second digital phase shift circuit group 31 to the other end of the digital phase shift circuit 10-6 (third digital phase shift circuit). The specific configurations of the connecting portions 20a and 20b will be described later.

[0025] The digital phase shifter 100 does not have a structure in which a plurality of digital phase shift circuits 10 are all arranged side by side, but has a structure in which the digital phase shifter 100 is bent along the way by connecting portions 20 a and 20 b. For example, the first digital phase shift circuit group 30 and the second digital phase shift circuit group 31 are connected by connecting portions 20 a and 20 b, thereby bending the digital phase shifter 100. As a result, the first digital phase shift circuit group 30 and the second digital phase shift circuit group 31 are arranged in parallel and spaced apart by a distance H.

[0026] 2 is a perspective view showing the configuration of a digital phase shift circuit according to a first embodiment of the present invention. As shown in Fig. 2, the digital phase shift circuit 10 includes a signal line 1, a pair of inner lines 2 (a first inner line 2a and a second inner line 2b), a pair of outer lines 3 (a first outer line 3a and a second outer line 3b), a pair of ground conductors 4 (a first ground conductor 4a and a second ground conductor 4b), a capacitor 5, a plurality of connecting conductors 6, four electronic switches 7 (a first electronic switch 7a, a second electronic switch 7b, a third electronic switch 7c, and a fourth electronic switch 7d), and a switch control unit 8.

[0027] The signal line 1 is a linear strip-shaped conductor extending in a predetermined direction. That is, the signal line 1 is a long, plate-shaped conductor having a constant width W1, a constant thickness, and a predetermined length. In the example shown in Fig. 2, a signal S flows through the signal line 1 from the front side to the back side.

[0028] The first inner line 2a is a linear strip-shaped conductor. That is, the first inner line 2a is a long, plate-like conductor with a constant width, constant thickness, and predetermined length. The first inner line 2a extends in the same direction as the signal line 1. The first inner line 2a is provided in parallel to the signal line 1 and is spaced a predetermined distance M1 from one side of the signal line 1 (the right side in FIG. 1 ).

[0029] The second inner line 2b is a linear strip-shaped conductor. That is, like the first inner line 2a, the second inner line 2b is a long, plate-like conductor having a constant width, a constant thickness, and a predetermined length. The second inner line 2b extends in the same direction as the signal line 1. The second inner line 2b is provided in parallel to the signal line 1 and is spaced a predetermined distance M1 from the other side of the signal line 1 (the left side in FIG. 1 ).

[0030] The first outer line 3a is a linear strip-shaped conductor provided on one side of the signal line 1, farther from the signal line 1 than the first inner line 2a. The first outer line 3a is a long, plate-like conductor with a constant width, constant thickness, and a predetermined length. The first outer line 3a is provided parallel to and a predetermined distance from the signal line 1, with the first inner line 2a sandwiched between them. Like the first inner line 2a and the second inner line 2b, the first outer line 3a extends in the same direction as the signal line 1.

[0031] The second outer line 3b is a linear strip-shaped conductor provided on the other side of the signal line 1, farther from the signal line 1 than the second inner line 2b. Similar to the first outer line 3a, the second outer line 3b is a long, plate-like conductor having a constant width, constant thickness, and a predetermined length. The second outer line 3b is provided in parallel to the signal line 1 at a predetermined distance, with the second inner line 2b sandwiched between them. Similar to the first inner line 2a and the second inner line 2b, the second outer line 3b extends in the same direction as the signal line 1.

[0032] The first ground conductor 4a is a linear strip conductor provided at one end (first end) of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. The first ground conductor 4a is electrically connected to one end of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. The first ground conductor 4a is a long, plate-like conductor having a constant width, a constant thickness, and a predetermined length.

[0033] The first ground conductor 4a is provided so as to be perpendicular to the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b, which extend in the same direction, and is provided below and spaced a predetermined distance from the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.

[0034] The first ground conductor 4a has one end in the left-right direction (the right end in FIG. 1 ) positioned substantially flush with the right edge of the first outer line 3a, and the other end in the left-right direction (the left end in FIG. 1 ) positioned substantially flush with the left edge of the second outer line 3b.

[0035] The second ground conductor 4b is a linear strip conductor provided at the other end (second end) of each of the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. Similar to the first ground conductor 4a, the second ground conductor 4b is a long, plate-like conductor having a constant width, a constant thickness, and a predetermined length.

[0036] The second ground conductor 4b is disposed parallel to the first ground conductor 4a and, like the first ground conductor 4a, is provided so as to be perpendicular to the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b. The second ground conductor 4b is provided below and spaced a predetermined distance from the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b.

[0037] The second ground conductor 4b is positioned such that one end in the left-right direction (the right end in FIG. 1) is substantially flush with the right edge of the first outer line 3a. The other end in the left-right direction (the left end in FIG. 1) is substantially flush with the left edge of the second outer line 3b. That is, the second ground conductor 4b is positioned in the same left-right direction as the first ground conductor 4a.

[0038] The capacitor 5 is provided between the other end of the signal line 1 and the second ground conductor 4b. For example, the upper electrode of the capacitor 5 is connected to the signal line 1, and the lower electrode is electrically connected to the fourth electronic switch 7d. For example, the capacitor 5 is a thin-film capacitor with an MIM (Metal Insulator Metal) structure. The capacitor 5 has a capacitance Ca corresponding to the opposing area of ​​the parallel plates. However, instead of a parallel plate capacitor, an interdigital capacitor may be used as the capacitor 5.

[0039] The multiple connection conductors 6 include at least connection conductors 6a to 6f. The connection conductor 6a electrically and mechanically connects one end of the first inner line 2a and the first ground conductor 4a. For example, the connection conductor 6a is a conductor extending in the vertical direction, with one end (upper end) connected to the lower surface of the first inner line 2a and the other end (lower end) connected to the upper surface of the first ground conductor 4a.

[0040] The connecting conductor 6b is a conductor that electrically and mechanically connects one end of the second inner line 2b and the first ground conductor 4a. For example, the connecting conductor 6b is a conductor that extends in the vertical direction like the connecting conductor 6a, and one end (upper end) of the connecting conductor 6b is connected to the lower surface of the second inner line 2b, and the other end (lower end) is connected to the upper surface of the first ground conductor 4a.

[0041] The connecting conductor 6c electrically and mechanically connects one end of the first outer line 3a and the first ground conductor 4a. For example, the connecting conductor 6c is a conductor that extends in the vertical direction, with one end (upper end) connected to the lower surface of one end of the first outer line 3a and the other end (lower end) connected to the upper surface of the first ground conductor 4a.

[0042] The connecting conductor 6 d electrically and mechanically connects the other end of the first outer line 3 a and the second ground conductor 4 b, and for example, the connecting conductor 6 d is a conductor that extends in the vertical direction, with one end (upper end) connected to the lower surface of the other end of the first outer line 3 a and the other end (lower end) connected to the upper surface of the second ground conductor 4 b.

[0043] The connecting conductor 6 e electrically and mechanically connects one end of the second outer line 3 b and the first ground conductor 4 a, For example, the connecting conductor 6 e is a conductor extending in the vertical direction, one end (upper end) of which is connected to the lower surface of one end of the second outer line 3 b, and the other end (lower end) of which is connected to the upper surface of the first ground conductor 4 a.

[0044] The connecting conductor 6 f electrically and mechanically connects the other end of the second outer line 3 b and the second ground conductor 4 b, For example, the connecting conductor 6 f is a conductor extending in the vertical direction, with one end (upper end) connected to the lower surface of the other end of the second outer line 3 b and the other end (lower end) connected to the upper surface of the second ground conductor 4 b.

[0045] The connecting conductor 6g is a conductor that electrically and mechanically connects the other end of the signal line 1 and the upper electrode of the capacitor 5. For example, the connecting conductor 6g is a conductor that extends in the vertical direction, and one end (upper end) is connected to the underside of the other end of the signal line 1, and the other end (lower end) is connected to the upper electrode of the capacitor 5.

[0046] The first electronic switch 7 a is connected between the other end of the first inner line 2 a and the second ground conductor 4 b. The first electronic switch 7 a is, for example, a MOS type FET (field effect transistor), and has a drain terminal electrically connected to the other end of the first inner line 2 a, a source terminal electrically connected to the second ground conductor 4 b, and a gate terminal electrically connected to the switch control unit 8.

[0047] The first electronic switch 7a is controlled to a closed state or an open state based on a gate signal input to the gate terminal from the switch control unit 8. The closed state means that the drain terminal and the source terminal are conductive. The open state means that the drain terminal and the source terminal are not conductive and the electrical connection is cut off. Under the control of the switch control unit 8, the first electronic switch 7a is set to a conductive state in which the other end of the first inner line 2a and the second ground conductor 4b are electrically connected, or a cut-off state in which the electrical connection is cut off.

[0048] The second electronic switch 7b is connected between the other end of the second inner line 2b and the second ground conductor 4b. The second electronic switch 7b is, for example, a MOS type FET, and has a drain terminal connected to the other end of the second inner line 2b, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch control unit 8.

[0049] The second electronic switch 7b is controlled to a closed state or an open state based on a gate signal input to a gate terminal from the switch control unit 8. Under the control of the switch control unit 8, the second electronic switch 7b is brought into a conductive state in which the other end of the second inner line 2b and the second ground conductor 4b are electrically connected, or into a cut-off state in which the electrical connection between them is cut off.

[0050] The third electronic switch 7c is connected between the other end of the signal line 1 and the second ground conductor 4b. The third electronic switch 7c is, for example, a MOS type FET, and has a drain terminal connected to the other end of the signal line 1, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch control unit 8. In the example shown in Fig. 2, the third electronic switch 7c is provided on the other end side of the signal line 1, but this is not limitative and the third electronic switch 7c may be provided on one end side of the signal line 1. The third electronic switch 7c does not have to be used if it is not necessary.

[0051] The third electronic switch 7c is controlled to a closed state or an open state based on a gate signal input to a gate terminal from the switch control unit 8. Under the control of the switch control unit 8, the third electronic switch 7c is brought into a conductive state in which the other end of the signal line 1 and the second ground conductor 4b are electrically connected, or into a cut-off state in which the electrical connection between them is cut off.

[0052] The fourth electronic switch 7d is connected in series with the capacitor 5 between the other end of the signal line 1 and the second ground conductor 4b. The fourth electronic switch 7d is, for example, a MOS-type FET. In the example shown in Fig. 2, the fourth electronic switch 7d has a drain terminal connected to the lower electrode of the capacitor 5, a source terminal connected to the second ground conductor 4b, and a gate terminal connected to the switch control unit 8.

[0053] The fourth electronic switch 7d is controlled to a closed state or an open state based on a gate signal input to its gate terminal from the switch control unit 8. Under the control of the switch control unit 8, the fourth electronic switch 7d is set to a conductive state in which the lower electrode of the capacitor 5 and the second ground conductor 4b are electrically connected, or a cut-off state in which the electrical connection between them is cut off.

[0054] The switch control unit 8 is a control circuit that controls the first electronic switch 7a, the second electronic switch 7b, the third electronic switch 7c, and the fourth electronic switch 7d. For example, the switch control unit 8 has four output ports. The switch control unit 8 outputs individual gate signals from each output port and supplies them to the gate terminals of the electronic switches 7, thereby individually controlling each of the electronic switches 7 to an open or closed state.

[0055] FIG. 2 shows a schematic perspective view of the digital phase shift circuit 10 to make the mechanical structure of the digital phase shift circuit 10 easier to understand, but the actual digital phase shift circuit 10 is formed as a multi-layer structure using semiconductor manufacturing technology.

[0056] As an example, in the digital phase shift circuit 10, the signal line 1, the first inner line 2a, the second inner line 2b, the first outer line 3a, and the second outer line 3b are formed on a first conductive layer. The first ground conductor 4a and the second ground conductor 4b are formed on a second conductive layer facing the first conductive layer with an insulating layer sandwiched therebetween. The components formed on the first conductive layer and the components formed on the second conductive layer are connected to each other by via holes. The multiple connection conductors 6 correspond to via holes buried in the insulating layer.

[0057] Next, the operation of the digital phase shift circuit 10 in this embodiment will be described. The digital phase shift circuit 10 has a high delay mode and a low delay mode as operation modes. The digital phase shift circuit 10 operates in the high delay mode or the low delay mode.

[0058] 3 is a diagram illustrating the high delay mode of the digital phase shift circuit according to the first embodiment of the present invention. The high delay mode is a mode in which a first phase difference is generated in the signal S. In the high delay mode, as shown in FIG. 3, the first electronic switch 7a and the second electronic switch 7b are controlled to an open state, and the fourth electronic switch 7d is controlled to a closed state.

[0059] When the first electronic switch 7a is controlled to an open state, the electrical connection between the other end of the first inner line 2a and the second ground conductor 4b is interrupted. When the second electronic switch 7b is controlled to an open state, the electrical connection between the other end of the second inner line 2b and the second ground conductor 4b is interrupted. When the fourth electronic switch 7d is controlled to a closed state, the other end of the signal line 1 is connected to the second ground conductor 4b via the capacitor 5.

[0060] When a signal S propagates from the input end (the other end) to the output end (the one end) on the signal line 1, a return current R1 flows from the one end to the other end in the opposite direction to the signal S. In the high delay mode, the first electronic switch 7a and the second electronic switch 7b are open, so the return current R1 flows mainly through the first outer line 3a and the second outer line 3b, as shown in FIG.

[0061] In the high delay mode, the return current R1 flows through the first outer line 3a and the second outer line 3b, so the inductance value L is higher than in the low delay mode. A larger delay amount can be obtained in the high delay mode than in the low delay mode. Furthermore, since the other end of the signal line 1 and the second ground conductor 4b are electrically connected by the capacitor 5 when the fourth electronic switch 7d is closed, the capacitance value C of the digital phase shift circuit 10 is also higher in the high delay mode than in the low delay mode. Therefore, a larger delay amount can be obtained in the high delay mode than in the low delay mode.

[0062] <Low Delay Mode> Figure 4 is a diagram illustrating the low delay mode of the digital phase shift circuit according to the first embodiment of the present invention. The low delay mode is a mode in which a second phase difference smaller than the first phase difference is generated in the signal S. In the low delay mode, as shown in Figure 4, the first electronic switch 7a and the second electronic switch 7b are controlled to a closed state, and the fourth electronic switch 7d is controlled to an open state.

[0063] When the first electronic switch 7a is controlled to a closed state, the other end of the first inner line 2a and the second ground conductor 4b are electrically connected to each other, and when the second electronic switch 7b is controlled to a closed state, the other end of the second inner line 2b and the second ground conductor 4b are electrically connected to each other.

[0064] When a signal S propagates from the input end (the other end) to the output end (the one end) on the signal line 1, a return current R2 flows from the one end to the other end in the opposite direction to the signal S. In the low delay mode, the first electronic switch 7a and the second electronic switch 7b are closed, so that the return current R2 flows mainly through the first inner line 2a and the second inner line 2b, as shown in FIG.

[0065] In the low delay mode, the return current R2 flows through the first inner line 2a and the second inner line 2b, so the inductance value L is lower than in the high delay mode. The delay amount in the low delay mode is smaller than that in the high delay mode. Although the capacitor 5 is connected to the other end of the signal line 1, the fourth electronic switch 7d is open, so in the low delay mode, the capacitance of the capacitor 5 is not functional (it is not visible from the signal line 1), and only a parasitic capacitance that is extremely small compared to the capacitance of the capacitor 5 exists. Therefore, the delay amount in the low delay mode is smaller than that in the high delay mode.

[0066] In the low delay mode, the third electronic switch 7c is controlled to be in a closed state, thereby intentionally increasing the loss in the signal line 1. This is to make the loss of the high frequency signal in the low delay mode the same as the loss of the high frequency signal in the high delay mode.

[0067] That is, the loss of the high-frequency signal in the low-delay mode is clearly smaller than the loss of the high-frequency signal in the high-delay mode. This difference in loss causes an amplitude difference in the high-frequency signal output from the digital phase shift circuit 10 when the operating mode is switched between the low-delay mode and the high-delay mode. In response to this situation, the digital phase shift circuit 10 may eliminate the amplitude difference by controlling the third electronic switch 7c to a closed state in the low-delay mode.

[0068] 5A to 5D are diagrams illustrating an example of a mitigation circuit according to the first embodiment of the present invention. The basic configuration of the mitigation circuit RC is substantially the same as that of the digital phase shift circuit 10 (hereinafter referred to as the "standard digital phase shift circuit ST") other than the mitigation circuit RC. However, the configuration of the mitigation circuit RC is slightly different from that of the standard digital phase shift circuit ST so that the mitigation circuit RC has a smaller phase shift amount compared to the standard digital phase shift circuit ST.

[0069] For example, the mitigation circuit RC is configured to satisfy at least one of the following conditions: Condition 1: The length is shorter than that of the standard digital phase shift circuit ST; Condition 2: The distance between the signal line 1 and the inner line 2 is longer than that of the standard digital phase shift circuit ST; Condition 3: The distance between the signal line 1 and the outer line 3 is shorter than that of the standard digital phase shift circuit ST; Condition 4: The capacitor 5 is smaller than that of the standard digital phase shift circuit ST; Condition 5: The electronic switches 7a and 7b are smaller than that of the standard digital phase shift circuit ST.

[0070] 5A is a diagram showing a mitigation circuit RC that satisfies the above-mentioned "Condition 1." The mitigation circuit RC shown in FIG. 5A has a length Pa (the lengths of the signal line 1, inner line 2, outer line 3, etc.) that is shorter than the length P of the standard digital phase shift circuit ST.

[0071] 5B is a diagram showing a mitigation circuit RC that satisfies the above-mentioned "Condition 2." In the mitigation circuit RC shown in Fig. 5B, the distance Qa between the signal line 1 and the inner lines 2 (the first inner line 2a and the second inner line 2b) is longer than the distance Q between the signal line 1 and the inner lines 2 (the first inner line 2a and the second inner line 2b) in the standard digital phase shift circuit ST.

[0072] 5C is a diagram showing a mitigation circuit RC that satisfies the above-mentioned "Condition 3." In the mitigation circuit RC shown in Fig. 5C, the distance Ra between the signal line 1 and the outer lines 3 (the first outer line 3a and the second outer line 3b) is shorter than the distance R between the signal line 1 and the outer lines 3 (the first outer line 3a and the second outer line 3b) in the standard digital phase shift circuit ST.

[0073] 5D is a diagram showing a mitigation circuit RC that satisfies the above-mentioned "Condition 4." In the mitigation circuit RC shown in FIG. 5D, the size of the capacitor 5 is smaller than the size of the capacitor 5 in the standard digital phase shift circuit ST. Note that, although not shown, in the mitigation circuit RC that satisfies the above-mentioned "Condition 5," the sizes of the first electronic switch 7a and the second electronic switch 7b (see FIGS. 2 to 4) are smaller than the sizes of the first electronic switch 7a and the second electronic switch 7b in the standard digital phase shift circuit ST.

[0074] 6 and 7 are perspective views illustrating other examples of the mitigation circuit according to the first embodiment of the present invention. The mitigation circuit RC shown in FIGS. 6 and 7 has a configuration generally similar to that of the digital phase shift circuit 10 (standard digital phase shift circuit ST) shown in FIGS. 2 to 4. However, the mitigation circuit RC shown in FIG. 6 differs from the digital phase shift circuit 10 (standard digital phase shift circuit ST) shown in FIGS. 2 to 4 in that the outer lines 3 (first outer line 3a and second outer line 3b) have a multilayer structure. The mitigation circuit RC shown in FIG. 7 also differs from the digital phase shift circuit 10 (standard digital phase shift circuit ST) shown in FIGS. 2 to 4 in that one of the inner lines 2 (the second inner line 2b in the example shown in FIG. 7) is omitted.

[0075] As described above, the mitigation circuit RC has a smaller phase shift amount than the standard digital phase shift circuit ST. Therefore, by using the mitigation circuit RC instead of the standard digital phase shift circuit ST, the phase shift amount can be reduced. Therefore, the jump in the phase shift amount that occurs before and after the connecting portions 20 a and 20 b can be mitigated.

[0076] <Connection Portion> Figure 8 is a cross-sectional view taken along line A-A in Figure 1. The digital phase shifter 100 of this embodiment includes connection portions 20a and 20b, but because the connection portions 20a and 20b have the same configuration, only the connection portion 20a will be described here. As shown in Figures 1 and 8, the connection portion 20a includes a first connection line 21, a second connection line 22, a third connection line 23, a first ground layer 24, and a second ground layer 25.

[0077] The first connection line 21 is, for example, a long, plate-like conductor having a constant width W2, a constant thickness, and a predetermined length. The first connection line 21 connects the signal line 1 of the digital phase shift circuit 10-5 to the signal line 1 of the digital phase shift circuit 10-6. The signal S output from the signal line 1 of the digital phase shift circuit 10-5 is input to the signal line 1 of the digital phase shift circuit 10-6 via the first connection line 21. The width W2 of the first connection line 21 may be the same as the width W1 of the signal line 1, or may be wider than the width W1.

[0078] The second connection line 22 is a long, plate-like conductor having a constant width, a constant thickness, and a predetermined length. The second connection line 22 extends in the same direction as the extension direction of the signal line 1. The second connection line 22 is provided parallel to the first connection line 21 and is spaced a predetermined distance M2 from the first connection line 21. Specifically, the second connection line 22 is disposed on both sides of the first connection line 21 and spaced a predetermined distance M2 from the first connection line 21. In the following description, the second connection line 22 disposed on one side of the first connection line 21 may be referred to as the "second connection line 22a," and the second connection line 22 disposed on the other side of the first connection line 21 may be referred to as the "second connection line 22b."

[0079] The predetermined distance M2 may be equal to or shorter than the predetermined distance M1. For example, if the predetermined distance M1 is 10 μm, the predetermined distance M2 may be set to less than 10 μm. More preferably, the predetermined distance M2 is, for example, 2.5 μm or 2 μm or less, and it is desirable to bring the second connection line 22 as close as possible to the first connection line 21. In this embodiment, the second connection line 22 may be brought as close to the first connection line 21 as possible, at or near the manufacturing limit.

[0080] The second connecting line 22 connects the inner line 2 of the digital phase shift circuit 10-5 and the inner line 2 of the digital phase shift circuit 10-6. In the example shown in Fig. 1, one end of the second connecting line 22a is connected to the first inner line 2a of the digital phase shift circuit 10-5, and the other end is connected to the first inner line 2a of the digital phase shift circuit 10-6. The second connecting line 22b has one end connected to the second inner line 2b of the digital phase shift circuit 10-5, and the other end connected to the second inner line 2b of the digital phase shift circuit 10-6.

[0081] The third connection line 23 is a strip-shaped conductor provided on both sides of the first connection line 21 at a position farther from the first connection line 21 than the second connection line 22. The third connection line 23 is provided parallel to the first connection line 21 at a predetermined distance with the second connection line 22 sandwiched between them. In the following description, the third connection line 23 provided on one side of the first connection line 21 may be referred to as the "third connection line 23a," and the third connection line 23 provided on the other side of the first connection line 21 may be referred to as the "third connection line 23b."

[0082] The third connecting line 23 connects the outer line 3 of the digital phase shift circuit 10-5 and the outer line 3 of the digital phase shift circuit 10-6. In the example shown in Fig. 1, one end of the third connecting line 23a is connected to the first outer line 3a of the digital phase shift circuit 10-5, and the other end is connected to the first outer line 3a of the digital phase shift circuit 10-6. The third connecting line 23b has one end connected to the second outer line 3b of the digital phase shift circuit 10-5, and the other end connected to the second outer line 3b of the digital phase shift circuit 10-6.

[0083] The first ground layer 24 is provided above and spaced a predetermined distance from the first connection line 21 and the second connection line 22. It is preferable that the width of the first ground layer 24 extends at least to one side surface 220 of each second connection line 22. The side surface 220 is the side surface opposite to the side on which the first connection line 21 is arranged.

[0084] The first ground layer 24 is connected to each of the second connection line 22a and the second connection line 22b via via holes 40. As shown in FIG. 1, a plurality of via holes 40 are arranged along the second connection line 22a, and a plurality of via holes 40 are arranged along the second connection line 22b.

[0085] The second ground layer 25 is provided below and spaced a predetermined distance from the first connection line 21 and the second connection line 22. It is preferable that the width of the second ground layer 25 extends to at least one side surface 220 of each second connection line 22.

[0086] The second ground layer 25 is connected to each of the second connection line 22 a and the second connection line 22 b via via holes 42. Similar to the via holes 40, a plurality of via holes 42 are arranged along the second connection line 22 a, and a plurality of via holes 42 are arranged along the second connection line 22 b.

[0087] 9 is a cross-sectional view showing a modified example of the connection portion in the first embodiment of the present invention. As shown in Fig. 9, the connection portion 20 may be configured such that the first ground layer 24 extends above the third connection line 23 and the second ground layer 25 extends below the third connection line 23.

[0088] In this modified example, the first ground layer 24 is connected to each of the second connection lines 22a and 22b via via holes 40, and is connected to each of the third connection lines 23a and 23b via via holes 41. In the configuration illustrated in Fig. 9, a plurality of via holes 41 are arranged along the third connection line 23a, and a plurality of via holes 41 are arranged along the third connection line 23b.

[0089] The second ground layer 25 is connected to each of the second connection lines 22a and 22b via via holes 42, and is connected to each of the third connection lines 23a and 23b via via holes 43. In the configuration illustrated in Fig. 9, a plurality of via holes 43 are arranged along the third connection line 23a, as with the via holes 41, and a plurality of via holes 43 are arranged along the third connection line 23b.

[0090] 8 and 9, the connection portion 20a has the first ground layer 24 and the second ground layer 25, but is not limited to this and may include at least one of the first ground layer 24 and the second ground layer 25. In other words, it is sufficient that a ground layer is disposed above or below the first connection line 21.

[0091] <Operation of Digital Phase Shifter> The digital phase shifter 100 can achieve various delays (phase shift amounts) by setting the operation mode of each digital phase shift circuit 10 constituting the digital phase shifter 100 to a high delay mode or a low delay mode. In this embodiment, the following four operations are considered as operations of the digital phase shifter 100.

[0092] First Operation In the first operation, when all of the digital phase shift circuits 10 are in the high delay mode, the digital phase shift circuits 10 are sequentially switched to the low delay mode in the order in which they are connected, from digital phase shift circuit 10-1 to digital phase shift circuit 10-11. In the first operation, control for switching the operating mode from the high delay mode to the low delay mode starts with digital phase shift circuit 10-1 and ends with digital phase shift circuit 10-11. In other words, control is performed in a direction from digital phase shift circuit 10-5, which is the first digital phase shift circuit, to digital phase shift circuit 10-7, which is the second digital phase shift circuit. The first operation is performed when digital phase shift circuit 10-5 and digital phase shift circuit 10-6 are configured as mitigation circuits RC.

[0093] Second Operation In the second operation, when all of the digital phase shift circuits 10 are in the low-delay mode, the digital phase shift circuits 10 are sequentially switched to the high-delay mode in the order in which they are connected, from digital phase shift circuit 10-1 to digital phase shift circuit 10-11. In the second operation, the control for switching the operating mode from the low-delay mode to the high-delay mode, similar to the first operation, starts with digital phase shift circuit 10-1 and ends with digital phase shift circuit 10-11. In other words, the control is performed in a direction from digital phase shift circuit 10-5, which is the first digital phase shift circuit, to digital phase shift circuit 10-7, which is the second digital phase shift circuit. The second operation is performed when digital phase shift circuit 10-6 and digital phase shift circuit 10-7 are configured as mitigation circuits RC.

[0094] Third Operation In the third operation, when all of the digital phase shift circuits 10 are in the high-delay mode, the digital phase shift circuits 10 are sequentially switched to the low-delay mode in the order in which they are connected, starting with digital phase shift circuit 10-11 through digital phase shift circuit 10-1. In the third operation, control for switching the operating mode from the high-delay mode to the low-delay mode begins with digital phase shift circuit 10-11 and ends with digital phase shift circuit 10-1. In other words, control is performed in a direction from digital phase shift circuit 10-7, which is the second digital phase shift circuit, to digital phase shift circuit 10-5, which is the first digital phase shift circuit. The third operation is performed when digital phase shift circuit 10-6 and digital phase shift circuit 10-7 are configured as mitigation circuits RC.

[0095] Fourth Operation: In the fourth operation, when all of the digital phase shift circuits 10 are in the low-delay mode, the digital phase shift circuits 10 are sequentially switched to the high-delay mode in the order in which they are connected, from digital phase shift circuit 10-11 to digital phase shift circuit 10-1. In the fourth operation, the control for switching the operating mode from the low-delay mode to the high-delay mode, similar to the third operation, starts with digital phase shift circuit 10-11 and ends with digital phase shift circuit 10-1. In other words, the control is performed in a direction from digital phase shift circuit 10-7, which is the second digital phase shift circuit, to digital phase shift circuit 10-5, which is the first digital phase shift circuit. The fourth operation is performed when digital phase shift circuit 10-5 and digital phase shift circuit 10-6 are configured as mitigation circuits RC.

[0096] Here, the third operation has a control direction opposite to that of the first operation, and the fourth operation has a control direction opposite to that of the second operation. Therefore, the following will describe the first and second operations, and will omit a description of the third and fourth operations.

[0097] 10A to 10F and 11A to 11F are diagrams illustrating a first operation of the digital phase shifter according to the first embodiment of the present invention. The bold lines in Figures 10A to 10F and 11A to 11F indicate the main path of the return current that flows when signal S (see Figure 1) flows from digital phase shift circuit 10-1 to digital phase shift circuit 10-11. As shown in Figures 10A to 10F and 11A to 11F, the main path of the return current does not flow through the third connection line 23 (third connection line 23a) shown in Figure 1 at connection portions 20a and 20b, but rather through the second connection line 22 (second connection line 22a).

[0098] Although a pair of return currents (the pair of return currents R1 shown in FIG. 3 or the pair of return currents R2 shown in FIG. 4) flows through the digital phase shift circuit 10, only the path of one of the pair of return currents is shown in FIGS. 10A to 10F and 11A to 11F. The return current also flows through the connecting conductors 6 (connecting conductors 6a to 6f) or the electronic switches 7 (first electronic switch 7a, second electronic switch 7b) shown in FIG. 2, but for simplicity of explanation, description of the flow through these will be omitted.

[0099] In the first operation, as described above, all of the digital phase shift circuits 10 are initially set to the high delay mode. Then, the digital phase shift circuits 10-1 and 10-2 are sequentially switched to the low delay mode, and finally, control is performed to switch the digital phase shift circuit 10-11 to the low delay mode. As a result, all of the digital phase shift circuits 10 are set to the low delay mode.

[0100] Fig. 10A is a diagram showing the path of the return current when all of the digital phase shift circuits 10 are in the high delay mode. Figs. 10B to 10F are diagrams showing the path of the return current when the digital phase shift circuits 10-1 to 10-5 are sequentially switched to the low delay mode. Figs. 11A to 11F are diagrams showing the path of the return current when the digital phase shift circuits 10-6 to 10-11 are sequentially switched to the low delay mode.

[0101] The path shown in Fig. 10A and the path shown in Fig. 10B are different paths in the digital phase shift circuit 10-1. Specifically, the path shown in Fig. 10A is a path that passes through the outer line 3 in the digital phase shift circuit 10-1 and then passes through the ground conductor 4 on the side to which the signal S is input. The path shown in Fig. 10B is a path that passes through the ground conductor 4 on the digital phase shift circuit 10-2 side in the digital phase shift circuit 10-1 and then passes through the inner line 2.

[0102] 10A and 10B differ in that the return current passes through the inner line 2 or the outer line 3 in the digital phase shift circuit 10-1, resulting in a phase change. Note that both the path shown in Fig. 10A and the path shown in Fig. 10B pass through the ground conductor 4 once in the digital phase shift circuit 10-1. Although the position where the return current passes through the ground conductor 4 in Fig. 10A differs from the position where the return current passes through the ground conductor 4 in Fig. 10B, no change in phase occurs due to the difference in position.

[0103] The path shown in Fig. 10B and the path shown in Fig. 10C are different paths in the digital phase shift circuit 10-2. Specifically, the path shown in Fig. 10B is a path that passes through the outer line 3 in the digital phase shift circuit 10-2 and then passes through the ground conductor 4 on the digital phase shift circuit 10-1 side. The path shown in Fig. 10C is a path that passes through the ground conductor 4 on the digital phase shift circuit 10-3 side in the digital phase shift circuit 10-2 and then passes through the inner line 2.

[0104] 10B and 10C differ in that the return current passes through the inner line 2 or the outer line 3 in the digital phase shift circuit 10-2, resulting in a phase change. Note that both the path shown in Fig. 10B and the path shown in Fig. 10C pass through the ground conductor 4 once in the digital phase shift circuit 10-2. Although the position where the return current passes through the ground conductor 4 in Fig. 10B differs from the position where the return current passes through the ground conductor 4 in Fig. 10C, no phase change occurs due to the difference in position.

[0105] Similarly, the path shown in Figure 10C and the path shown in Figure 10D are different paths in digital phase shift circuit 10-3. The path shown in Figure 10D and the path shown in Figure 10E are different paths in digital phase shift circuit 10-4. The differences in the paths in these digital phase shift circuits 10-3 and 10-4 are similar to the differences in the paths in digital phase shift circuit 10-1 described using Figures 10A and 10B, and the differences in the paths in digital phase shift circuit 10-2 described using Figures 10B and 10C.

[0106] In this way, when the digital phase shift circuits 10-1 to 10-4 are sequentially switched from the high delay mode to the low delay mode, a similar path change occurs in each of the digital phase shift circuits 10-1 to 10-4. Therefore, when the digital phase shift circuits 10-1 to 10-4 are sequentially switched from the high delay mode to the low delay mode, no large jumps in the amount of phase shift occur.

[0107] The path shown in Fig. 10E and the path shown in Fig. 10F in the digital phase shift circuit 10-5 are significantly different. The path shown in Fig. 10E passes through the ground conductor 4 on the connection portion 20a side, then the outer line 3, and further passes through the ground conductor 4 on the digital phase shift circuit 10-4 side in the digital phase shift circuit 10-5. In contrast, the path shown in Fig. 10F passes only through the inner line 2 in the digital phase shift circuit 10-5 and never passes through the ground conductor 4.

[0108] In other words, when the digital phase shift circuits 10-1 to 10-4 are sequentially switched from high delay mode to low delay mode, the return current paths in the first digital phase shift circuit group 30 all have a convex shape extending from the inner line 2 to the outer line 3. In contrast, when the digital phase shift circuit 10-5 is switched from high delay mode to low delay mode, as shown in FIG. 10F, the return current paths in the first digital phase shift circuit group 30 become linear, resulting in a significant change in the shape of the return current paths. This significant change in the shape of the return current paths is the cause of the large jumps in the phase shift amount. For this reason, in the first operation, the digital phase shift circuit 10-5 serves as a mitigation circuit RC. In this way, large jumps in the phase shift amount are mitigated.

[0109] In the digital phase shift circuit 10, when the return current flows through the outer line 3, the inductance value L is higher than when the return current flows through the inner line 2. When the return current flows through the convex-shaped path described above, in addition to the higher inductance value L when the return current flows through the outer line 3, an inductance component due to the convex-shaped path, particularly the ground conductor 4, is added. This added inductance component causes a large jump in the amount of phase shift.

[0110] The path shown in Fig. 10F and the path shown in Fig. 11A are significantly different paths in the digital phase shift circuit 10-6. The path shown in Fig. 10F passes through the ground conductor 4 on the connection portion 20b side, then the outer line 3, and then passes through the ground conductor 4 on the connection portion 20a side in the digital phase shift circuit 10-6. In contrast, the path shown in Fig. 11A passes only through the inner line 2 in the digital phase shift circuit 10-6 and never passes through the ground conductor 4.

[0111] That is, in the state shown in FIG. 10F, the return current path in the digital phase shift circuit 10-6 has a convex shape extending from the inner line 2 to the outer line 3. In contrast, when the digital phase shift circuit 10-6 is set to the low delay mode, as shown in FIG. 11A, the return current path in the digital phase shift circuit 10-6 becomes linear, and the shape of the return current path changes significantly. This large change in the shape of the return current path is the cause of the large jump in the phase shift amount. For this reason, in the first operation, the digital phase shift circuit 10-6 is also configured as a mitigation circuit RC. In this way, the large jump in the phase shift amount is mitigated.

[0112] The path shown in Fig. 11A and the path shown in Fig. 11B are different paths in the digital phase shift circuit 10-7. Specifically, the path shown in Fig. 11A is a path that passes through the outer line 3 and then the ground conductor 4 on the connection portion 20b side in the digital phase shift circuit 10-7. The path shown in Fig. 11B is a path that passes through the ground conductor 4 on the digital phase shift circuit 10-8 side in the digital phase shift circuit 10-7 and then the inner line 2.

[0113] 11A and 11B differ in that in the digital phase shift circuit 10-7, the return current passes through the inner line 2 or the outer line 3, resulting in a phase change. Note that in the digital phase shift circuit 10-7, the position where the return current passes through the ground conductor 4 shown in FIG. 11A differs from the position where the return current passes through the ground conductor 4 shown in FIG. 11B, but no phase change occurs due to the difference in position.

[0114] Similarly, the path shown in Figure 11B and the path shown in Figure 11C are different paths in digital phase shift circuit 10-8. The path shown in Figure 11C and the path shown in Figure 11D are different paths in digital phase shift circuit 10-9. The path shown in Figure 11D and the path shown in Figure 11E are different paths in digital phase shift circuit 10-10. The differences in the paths in these digital phase shift circuits 10-8 to 10-10 are similar to the differences in the paths in digital phase shift circuit 10-7 described using Figures 11A and 11B.

[0115] The path shown in Fig. 11E and the path shown in Fig. 11F are significantly different paths in the digital phase shift circuit 10-11. The path shown in Fig. 11E passes through the ground conductor 4 on the side where the signal S is output in the digital phase shift circuit 10-11, then passes through the outer line 3, and further passes through the ground conductor 4 on the digital phase shift circuit 10-10 side. In contrast, the path shown in Fig. 11F passes only through the inner line 2 in the digital phase shift circuit 10-11, and never passes through the ground conductor 4.

[0116] In other words, when the digital phase shift circuits 10-7 through 10-10 are sequentially switched from the high-delay mode to the low-delay mode, the return current paths in the second digital phase shift circuit group 31 all have a convex shape extending from the inner line 2 to the outer line 3. This prevents large jumps in the phase shift amount. In contrast, when the digital phase shift circuit 10-11 is switched from the high-delay mode to the low-delay mode, as shown in FIG. 11F, the return current paths in the second digital phase shift circuit group 31 become linear, significantly changing the shape of the return current paths. This results in large jumps in the phase shift amount. Therefore, in the first operation, the digital phase shift circuit 10-11 may be configured as a mitigation circuit RC to mitigate large jumps in the phase shift amount.

[0117] 12A to 12F and 13A to 13F are diagrams illustrating a second operation of the digital phase shifter according to the first embodiment of the present invention. Similar to FIGS. 10A to 10F and 11A to 11F, the thick lines in FIGS. 12A to 12F and 13A to 13F indicate the main path of the return current that flows when the signal S flows from the digital phase shift circuit 10-1 to the digital phase shift circuit 10-11. In the second operation, similar to the first operation, the main path of the return current does not flow through the third connection line 23 (third connection line 23a) shown in FIG. 1 at the connection portions 20a and 20b, but rather through the second connection line 22 (second connection line 22a).

[0118] 12A to 12F and 13A to 13F, similar to Figures 10A to 10F and 11A to 11F, only the path of one of the pair of return currents is shown, and the path of the return current flowing through the connecting conductor 6 or the electronic switch 7 shown in Figure 2 is not described.

[0119] In the second operation, as described above, all of the digital phase shift circuits 10 are initially set to the low delay mode. Then, the digital phase shift circuits 10-1 and 10-2 are sequentially switched to the high delay mode, and finally, control is performed to switch the digital phase shift circuit 10-11 to the high delay mode. As a result, all of the digital phase shift circuits 10 are set to the high delay mode.

[0120] Fig. 12A is a diagram showing the path of the return current when all of the digital phase shift circuits 10 are in the low-delay mode. Figs. 12B to 12F are diagrams showing the path of the return current when the digital phase shift circuits 10-1 to 10-5 are sequentially switched to the high-delay mode. Figs. 13A to 13F are diagrams showing the path of the return current when the digital phase shift circuits 10-6 to 10-11 are sequentially switched to the high-delay mode.

[0121] The path shown in Fig. 12A and the path shown in Fig. 12B are significantly different paths in the digital phase shift circuit 10-1. Specifically, the path shown in Fig. 12A passes only through the inner line 2 in the digital phase shift circuit 10-1 and never passes through the ground conductor 4. In contrast, the path shown in Fig. 12B is a path that passes through the ground conductor 4 on the digital phase shift circuit 10-2 side, then the outer line 3, and further passes through the ground conductor 4 on the side to which the signal S is input in the digital phase shift circuit 10-1.

[0122] That is, in the state shown in Fig. 12A, the return current path in the digital phase shift circuit 10-1 was linear. In contrast, when the digital phase shift circuit 10-1 is switched from the low delay mode to the high delay mode, as shown in Fig. 12B, the return current path in the digital phase shift circuit 10-1 becomes convex from the inner line 2 to the outer line 3, and the shape of the return current path changes significantly. This causes a large jump in the phase shift amount. Therefore, in the second operation, the digital phase shift circuit 10-1 may be configured as a mitigation circuit RC to mitigate the large jump in the phase shift amount.

[0123] The path shown in Fig. 12B and the path shown in Fig. 12C are different paths in the digital phase shift circuit 10-2. Specifically, the path shown in Fig. 12B is a path that passes through the inner line 2 in the digital phase shift circuit 10-2 and then passes through the ground conductor 4 on the digital phase shift circuit 10-1 side. The path shown in Fig. 12C is a path that passes through the ground conductor 4 on the digital phase shift circuit 10-3 side in the digital phase shift circuit 10-2 and then passes through the outer line 3.

[0124] 12B and 12C differ in that in the digital phase shift circuit 10-2, the return current passes through the inner line 2 or the outer line 3, resulting in a phase change. Note that in the digital phase shift circuit 10-2, the position where the return current passes through the ground conductor 4 shown in FIG. 12B differs from the position where the return current passes through the ground conductor 4 shown in FIG. 12C, but no phase change occurs due to the difference in position.

[0125] Similarly, the path shown in Figure 12C and the path shown in Figure 12D are different paths in digital phase shift circuit 10-3. The path shown in Figure 12D and the path shown in Figure 12E are different paths in digital phase shift circuit 10-4. The path shown in Figure 12E and the path shown in Figure 12F are different paths in digital phase shift circuit 10-5. The differences in the paths in these digital phase shift circuits 10-3 to 10-5 are similar to the differences in the paths in digital phase shift circuit 10-2 described using Figures 12B and 12C.

[0126] In this way, when the digital phase shift circuits 10-2 to 10-5 are sequentially switched from the low-delay mode to the high-delay mode, a similar path change occurs in each of the digital phase shift circuits 10-2 to 10-5. Therefore, when the digital phase shift circuits 10-2 to 10-5 are sequentially switched to the low-delay mode, no large jumps in the amount of phase shift occur.

[0127] The path shown in Fig. 12F and the path shown in Fig. 13A are significantly different in the digital phase shift circuit 10-6. The path shown in Fig. 12F passes only through the inner line 2 in the digital phase shift circuit 10-6 and does not pass through the ground conductor 4 at all. The path shown in Fig. 13A is a path that passes through the ground conductor 4 on the connection portion 20b side, then the outer line 3, and further passes through the ground conductor 4 on the connection portion 20a side in the digital phase shift circuit 10-6.

[0128] That is, in the state shown in FIG. 12F, the return current path in the digital phase shift circuit 10-6 was linear. In contrast, when the digital phase shift circuit 10-6 is switched from the low delay mode to the high delay mode, as shown in FIG. 13A, the return current path in the digital phase shift circuit 10-6 becomes convex from the inner line 2 to the outer line 3, resulting in a significant change in the shape of the return current path. This significant change in the shape of the return current path is the cause of the large jump in the phase shift amount. For this reason, in the second operation, the digital phase shift circuit 10-6 is used as a mitigation circuit RC. In this way, the large jump in the phase shift amount is mitigated.

[0129] The path shown in Fig. 13A and the path shown in Fig. 13B are significantly different in the digital phase shift circuit 10-7. The path shown in Fig. 13A passes only through the inner line 2 in the digital phase shift circuit 10-7 and never passes through the ground conductor 4. The path shown in Fig. 13B is a path that passes through the ground conductor 4 on the digital phase shift circuit 10-8 side, then the outer line 3, and further passes through the ground conductor 4 on the connection portion 20b side in the digital phase shift circuit 10-7.

[0130] That is, in the state shown in FIG. 13A, the return current path in the digital phase shift circuit 10-7 was linear. In contrast, when the digital phase shift circuit 10-7 is switched from the low delay mode to the high delay mode, as shown in FIG. 13B, the return current path in the digital phase shift circuit 10-7 becomes convex from the inner line 2 to the outer line 3, resulting in a significant change in the shape of the return current path. This significant change in the shape of the return current path is the cause of the large jump in the phase shift amount. For this reason, in the second operation, the digital phase shift circuit 10-7 is also used as a mitigation circuit RC. In this way, the large jump in the phase shift amount is mitigated.

[0131] The path shown in Fig. 13B and the path shown in Fig. 13C are different paths in the digital phase shift circuit 10-8. Specifically, the path shown in Fig. 13B is a path that passes through the inner line 2 in the digital phase shift circuit 10-8 and then passes through the ground conductor 4 on the digital phase shift circuit 10-7 side. The path shown in Fig. 13C is a path that passes through the ground conductor 4 on the digital phase shift circuit 10-9 side in the digital phase shift circuit 10-8 and then passes through the outer line 3.

[0132] 13B and 13C differ in that in the digital phase shift circuit 10-8, the return current passes through the inner line 2 or the outer line 3, resulting in a phase change. Note that in the digital phase shift circuit 10-8, the position where the return current passes through the ground conductor 4 shown in FIG. 13B differs from the position where the return current passes through the ground conductor 4 shown in FIG. 13C, but no phase change occurs due to the difference in position.

[0133] Similarly, the path shown in Figure 13C and the path shown in Figure 13D are different paths in digital phase shift circuit 10-9. The path shown in Figure 13D and the path shown in Figure 13E are different paths in digital phase shift circuit 10-10. The path shown in Figure 13E and the path shown in Figure 13F are different paths in digital phase shift circuit 10-11. The differences in the paths in these digital phase shift circuits 10-9 to 10-11 are the same as the differences in the paths in digital phase shift circuit 10-8 described using Figures 13B and 13C.

[0134] In this way, when the digital phase shift circuits 10-8 to 10-11 are switched from the low delay mode to the high delay mode in sequence, a similar path change occurs in each of the digital phase shift circuits 10-8 to 10-11. Therefore, when the digital phase shift circuits 10-8 to 10-11 are switched from the low delay mode to the high delay mode in sequence, no large jumps in the amount of phase shift occur.

[0135] As described above, this embodiment includes a first digital phase shift circuit group 30, a second digital phase shift circuit group 31, a digital phase shift circuit 10-6, and connection units 20a and 20b. The first digital phase shift circuit group 30 is configured with a plurality of digital phase shift circuits 10-1 to 10-5 connected in cascade, and the second digital phase shift circuit group 31 is configured with a plurality of digital phase shift circuits 10-7 to 10-11 connected in cascade. The digital phase shift circuit 10-5 and the digital phase shift circuit 10-6 of the first digital phase shift circuit group 30 are connected by the connection unit 20a, and the digital phase shift circuit 10-7 and the digital phase shift circuit 10-6 of the second digital phase shift circuit group 31 are connected by the connection unit 20b. Either one of the digital phase shift circuits 10-5 or 10-7 and the digital phase shift circuit 10-6 form a mitigation circuit that mitigates jumps in the amount of phase shift. This makes it possible to eliminate large jumps in the amount of phase shift that occur before and after the connecting portions 20a and 20b.

[0136] Second Embodiment Digital Phase Shifter Figure 14 is a plan view showing the schematic configuration of a digital phase shifter according to a second embodiment of the present invention. In Figure 14, the same components as those shown in Figure 1 are denoted by the same reference numerals. As shown in Figure 14, a digital phase shifter 200 of this embodiment does not include the digital phase shift circuit 10-6 of the digital phase shifter 100 shown in Figure 1, and instead of the connecting sections 20a and 20b of the digital phase shifter 100 shown in Figure 1, a connecting section 20 is provided.

[0137] The connection portion 20 has a 180° bend shape. The connection portion 20 connects a digital phase shift circuit 10-5 (first digital phase shift circuit) located at one end of the first digital phase shift circuit group 30 with a digital phase shift circuit 10-7 (second digital phase shift circuit) located at one end of the second digital phase shift circuit group 31. The connection portion 20 has the same configuration as the connection portions 20a and 20b, and includes a first connection line 21, a second connection line 22, a third connection line 23, a first ground layer 24, and a second ground layer 25.

[0138] In this embodiment, either the digital phase shift circuit 10-5 or the digital phase shift circuit 10-7 is a mitigation circuit RC. This mitigation circuit RC is a circuit that mitigates large jumps in the amount of phase shift that occur before and after the connection section 20. As in the first embodiment, the mitigation circuit RC is, for example, a digital phase shift circuit 10 that has a smaller amount of phase shift compared to the digital phase shift circuits 10 other than the mitigation circuit RC.

[0139] <Operation of Digital Phase Shifter> The digital phase shifter 200 of this embodiment is capable of the above-described first, second, third, and fourth operations, similar to the digital phase shifter 100 of the first embodiment. In this embodiment, the first and fourth operations are performed when the digital phase shift circuit 10-5 is configured as the mitigation circuit RC, and the second and third operations are performed when the digital phase shift circuit 10-7 is configured as the mitigation circuit RC.

[0140] In this embodiment, the third operation is opposite in control direction to the first operation, and the fourth operation is opposite in control direction to the second operation, so the following will describe the first and second operations, and will omit a description of the third and fourth operations.

[0141] 15A to 15D are diagrams illustrating a first operation of the digital phase shifter according to the second embodiment of the present invention. Similar to FIGS. 10A to 10F and 11A to 11F, the thick lines in FIG. 15 indicate the main path of the return current that flows when the signal S flows from the digital phase shift circuit 10-1 to the digital phase shift circuit 10-11. As shown in FIG. 15, the main path of the return current does not flow through the third connection line 23 at the connection part 20, but rather through the second connection line 22.

[0142] 15A to 15D, similar to FIGS. 10A to 10F and 11A to 11F, only the path of one of the pair of return currents is shown, and the path of the return current flowing through the connecting conductor 6 or the electronic switch 7 shown in FIG. 2 is not described.

[0143] 15A is a diagram showing the path of the return current when the digital phase shift circuits 10-1 to 10-3 are switched from the high delay mode to the low delay mode, and FIGS. 15B to 15D are diagrams showing the path of the return current when the digital phase shift circuits 10-4, 10-5, and 10-7 are sequentially switched to the low delay mode, respectively.

[0144] Note that diagrams showing the paths of the return current when all of the digital phase shift circuits 10 are in the high delay mode, when the digital phase shift circuits 10-1 and 10-2 are sequentially switched to the low delay mode, and when the digital phase shift circuits 10-8 to 10-11 are sequentially switched to the low delay mode are omitted because the paths of the return current in the first digital phase shift circuit group 30 and the second digital phase shift circuit group 31 are the same as the paths shown in Figures 10A, 10B to 10C, and 11C to 11F.

[0145] The path shown in Fig. 15A and the path shown in Fig. 15B are different paths in the digital phase shift circuit 10-4. Specifically, the path shown in Fig. 15A is a path that passes through the outer line 3 in the digital phase shift circuit 10-4 and then passes through the ground conductor 4 on the digital phase shift circuit 10-3 side. The path shown in Fig. 15B is a path that passes through the inner line 2 in the digital phase shift circuit 10-4 and then passes through the ground conductor 4 on the digital phase shift circuit 10-5 side.

[0146] 15A and 15B differ in that in the digital phase shift circuit 10-4, the return current passes through the inner line 2 or the outer line 3, resulting in a phase change. Note that in the digital phase shift circuit 10-4, the position where the return current passes through the ground conductor 4 shown in Fig. 15A differs from the position where the return current passes through the ground conductor 4 shown in Fig. 15B, but no phase change occurs due to the difference in position.

[0147] The path shown in Figure 15B and the path shown in Figure 15C are significantly different paths in the digital phase shift circuit 10-5. The path shown in Figure 15B passes through the ground conductor 4 on the connection unit 20 side, then the outer line 3, and then the ground conductor 4 on the digital phase shift circuit 10-4 side in the digital phase shift circuit 10-5. In contrast, the path shown in Figure 15C passes only through the inner line 2 in the digital phase shift circuit 10-5 and never passes through the ground conductor 4. In this way, the shape of the return current path changes significantly.

[0148] Such a large change in the shape of the return current path is the cause of the large jump in the phase shift. For this reason, in the first operation, the digital phase shift circuit 10-5 is used as the mitigation circuit RC. In this way, the large jump in the phase shift is mitigated.

[0149] The path shown in Fig. 15C and the path shown in Fig. 15D are different paths in the digital phase shift circuit 10-7. Specifically, the path shown in Fig. 15C is a path that passes through the outer line 3 in the digital phase shift circuit 10-7 and then passes through the ground conductor 4 on the connection unit 20 side. The path shown in Fig. 15D is a path that passes through the ground conductor 4 on the digital phase shift circuit 10-8 side in the digital phase shift circuit 10-7 and then passes through the inner line 2.

[0150] 15C and 15D differ in that in the digital phase shift circuit 10-7, the return current passes through the inner line 2 or the outer line 3, resulting in a phase change. Note that in the digital phase shift circuit 10-7, the position where the return current passes through the ground conductor 4 shown in Fig. 15C differs from the position where the return current passes through the ground conductor 4 shown in Fig. 15D, but no phase change occurs due to the difference in position.

[0151] 16A to 16D are diagrams illustrating a second operation of the digital phase shifter according to the second embodiment of the present invention. Similar to FIGS. 12A to 12F and 13A to 13F, the thick lines in FIGS. 16A to 16D indicate the main path of the return current that flows when the signal S flows from the digital phase shift circuit 10-1 to the digital phase shift circuit 10-11. In the second operation, similar to the first operation, the main path of the return current does not flow through the third connection line 23 at the connection portion 20, but rather through the second connection line 22.

[0152] 16A to 16D, similar to Figures 12A to 12F and Figures 13A to 13F, only the path of one of the pair of return currents is shown, and the path of the return current flowing through the connecting conductor 6 or the electronic switch 7 shown in Figure 2 is not described.

[0153] 16A is a diagram showing the path of the return current when the digital phase shift circuits 10-1 to 10-4 are switched from the low delay mode to the high delay mode, and FIGS. 16B to 16D are diagrams showing the path of the return current when the digital phase shift circuits 10-5, 10-7, and 10-8 are sequentially switched to the high delay mode, respectively.

[0154] Note that diagrams showing the paths of the return current when all of the digital phase shift circuits 10 are in the low-delay mode, when the digital phase shift circuits 10-1 to 10-3 are sequentially switched to the high-delay mode, and when the digital phase shift circuits 10-9 to 10-11 are sequentially switched to the high-delay mode are omitted because the paths of the return current in the first digital phase shift circuit group 30 and the second digital phase shift circuit group 31 are the same as the paths shown in FIGS. 12A, 12B to 12D, and 13D to 13F.

[0155] The path shown in Fig. 16A and the path shown in Fig. 16B are different paths in the digital phase shift circuit 10-5. Specifically, the path shown in Fig. 16A is a path that passes through the inner line 2 and then the ground conductor 4 on the digital phase shift circuit 10-4 side in the digital phase shift circuit 10-5. The path shown in Fig. 16B is a path that passes through the ground conductor 4 on the connection unit 20 side in the digital phase shift circuit 10-5 and then the outer line 3.

[0156] 16A and 16B differ in that in the digital phase shift circuit 10-5, the return current passes through the inner line 2 or the outer line 3, resulting in a phase change. Note that in the digital phase shift circuit 10-5, the position where the return current passes through the ground conductor 4 shown in Fig. 16A differs from the position where the return current passes through the ground conductor 4 shown in Fig. 16B, but no phase change occurs due to the difference in position.

[0157] The path shown in Figure 16B and the path shown in Figure 16C are significantly different paths in the digital phase shift circuit 10-7. The path shown in Figure 16B is a path that passes only through the inner line 2 in the digital phase shift circuit 10-7 and does not pass through the ground conductor 4 even once. In contrast, the path shown in Figure 16C is a path that passes through the ground conductor 4 on the digital phase shift circuit 10-8 side, then the outer line 3, and further passes through the ground conductor 4 on the connection part 20 side in the digital phase shift circuit 10-7. In this way, the shape of the return current path changes significantly.

[0158] Such a large change in the shape of the return current path is the cause of the large jump in the phase shift. For this reason, in the second operation, the digital phase shift circuit 10-7 is used as a mitigation circuit RC. In this way, the large jump in the phase shift is mitigated.

[0159] The path shown in Fig. 16C and the path shown in Fig. 16D are different paths in the digital phase shift circuit 10-8. Specifically, the path shown in Fig. 16C is a path that passes through the inner line 2 in the digital phase shift circuit 10-8 and then passes through the ground conductor 4 on the digital phase shift circuit 10-7 side. The path shown in Fig. 16D is a path that passes through the ground conductor 4 on the digital phase shift circuit 10-9 side in the digital phase shift circuit 10-8 and then passes through the outer line 3.

[0160] 16C and 16D differ in that in the digital phase shift circuit 10-8, the return current passes through the inner line 2 or the outer line 3, resulting in a phase change. Note that in the digital phase shift circuit 10-8, the position where the return current passes through the ground conductor 4 shown in Fig. 16C differs from the position where the return current passes through the ground conductor 4 shown in Fig. 16D, but no phase change occurs due to the difference in position.

[0161] As described above, this embodiment includes a first digital phase shift circuit group 30, a second digital phase shift circuit group 31, and a connection unit 20. The first digital phase shift circuit group 30 has a configuration in which a plurality of digital phase shift circuits 10-1 to 10-5 are cascaded, and the second digital phase shift circuit group 31 has a configuration in which a plurality of digital phase shift circuits 10-7 to 10-11 are cascaded. The digital phase shift circuit 10-5 of the first digital phase shift circuit group 30 and the digital phase shift circuit 10-7 of the second digital phase shift circuit group 31 are connected by the connection unit 20. One of the digital phase shift circuits 10-5 and 10-7 serves as a mitigation circuit that mitigates jumps in the amount of phase shift. This makes it possible to eliminate large jumps in the amount of phase shift that occur before and after the connection unit 20.

[0162] Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments and can be freely modified within the scope of the present invention. For example, the connection portions 20a and 20b of the digital phase shifter 100 according to the first embodiment described above have a 90-degree bend shape, and the connection portion 20 of the digital phase shifter 200 according to the second embodiment described above has a 180-degree bend shape. However, the connection portions may have a shape other than the 90-degree bend and the 180-degree bend shape (for example, a 45-degree bend shape).

[0163] Furthermore, the digital phase shifters 100 and 200 according to the first and second embodiments described above have a U-shape in plan view. However, the digital phase shifter may have a shape other than a U-shape in plan view (e.g., a spiral shape or a meander shape). A digital phase shifter having such a shape is realized by connecting a plurality of digital phase shift circuit groups via a plurality of connection parts.

[0164] According to the present invention, it is possible to eliminate large jumps in the amount of phase shift that occur before and after the connection portion.

[0165] REFERENCE SIGNS LIST 1...signal line, 2...inner line, 3...outer line, 4a...first ground conductor, 4b...second ground conductor, 5...capacitor, 7a, 7b...electronic switch, 7d...electronic switch, 10, 10-1 to 10-11...digital phase shift circuit, 20, 20a, 20b...connection portion, 21...first connecting line, 22...second connecting line, 23...third connecting line, 24...first ground layer, 25...second ground layer, 30...first digital phase shift circuit group, 31...second digital phase shift circuit group, 40, 42...via hole, 100, 200...digital phase shifter, RC...mitigation circuit

Claims

1. A digital phase shift circuit comprising: a first group of digital phase shift circuits in which a plurality of digital phase shift circuits are cascaded; a second group of digital phase shift circuits in which a plurality of digital phase shift circuits are cascaded; and a bend-type connection section connecting a first digital phase shift circuit located at one end of the first group of digital phase shift circuits to a second digital phase shift circuit located at one end of the second group of digital phase shift circuits, wherein the digital phase shift circuits comprise a signal line, a pair of inner lines provided on both sides of the signal line, a pair of outer lines provided outside the inner lines, a first ground conductor connected to each first end of the inner line and the outer line, a second ground conductor connected to each second end of the outer lines, and a pair of electronic switches respectively provided between each second end of the inner line and the second ground conductor, and each of the digital phase shift circuits is set to a low delay mode in which a return current flows in the inner line or a high delay mode in which a return current flows in the outer line, and the connection section a first connection line electrically connecting the signal line of the first digital phase shift circuit and the signal line of the second digital phase shift circuit; a second connection line electrically connecting each of the inner lines of the first digital phase shift circuit and each of the inner lines of the second digital phase shift circuit; and a third connection line electrically connecting each of the outer lines of the first digital phase shift circuit and each of the outer lines of the second digital phase shift circuit, wherein one of the first digital phase shift circuit and the second digital phase shift circuit is a mitigation circuit that mitigates jumps in the amount of phase shift, and the mitigation circuit is the digital phase shift circuit that has a smaller amount of phase shift than the digital phase shift circuits other than the mitigation circuit.

2. A digital phase shifter as claimed in claim 1, further comprising a third digital phase shift circuit electrically connected to the first digital phase shift circuit and the second digital phase shift circuit, wherein the connection section has: a first connection section connecting the first digital phase shift circuit and the third digital phase shift circuit; and a second connection section connecting the second digital phase shift circuit and the third digital phase shift circuit, and the third digital phase shift circuit is the mitigation circuit.

3. A digital phase shifter according to claim 1 or claim 2, wherein the digital phase shift circuit comprises: a capacitor electrically connected between the signal line and at least one of the first ground conductor and the second ground conductor; and an electronic switch that switches whether or not the capacitor is connected between the signal line and at least one of the first ground conductor and the second ground conductor.

4. The digital phase shifter according to claim 3, wherein the mitigation circuit satisfies at least one of the following conditions: a length is shorter than that of the digital phase shift circuits other than the mitigation circuit; a distance between the signal line and the inner line is longer than that of the digital phase shift circuits other than the mitigation circuit; a distance between the signal line and the outer line is shorter than that of the digital phase shift circuits other than the mitigation circuit; the capacitor is smaller than that of the digital phase shift circuits other than the mitigation circuit; and the pair of electronic switches is smaller than that of the digital phase shift circuits other than the mitigation circuit.

5. The digital phase shifter according to any one of claims 1 to 3, wherein the mitigation circuit is the digital phase shift circuit in which the outer line has a multilayer structure.

6. The digital phase shifter according to any one of claims 1 to 3, wherein the mitigation circuit is the digital phase shift circuit in which one of the inner lines is omitted.

7. A digital phase shifter as claimed in any one of claims 1 to 6, wherein when control is performed to switch the digital phase shift circuits sequentially from the high delay mode to the low delay mode in the order in which the digital phase shift circuits are connected, if the first digital phase shift circuit is set as the mitigation circuit, the control is performed in a direction from the first digital phase shift circuit to the second digital phase shift circuit, and if the second digital phase shift circuit is set as the mitigation circuit, the control is performed in a direction from the second digital phase shift circuit to the first digital phase shift circuit.

8. A digital phase shifter according to any one of claims 1 to 6, wherein when control is performed to switch the digital phase shift circuits sequentially from the low delay mode to the high delay mode in the order in which the digital phase shift circuits are connected, if the first digital phase shift circuit is set as the mitigation circuit, the control is performed in a direction from the second digital phase shift circuit to the first digital phase shift circuit, and if the second digital phase shift circuit is set as the mitigation circuit, the control is performed in a direction from the first digital phase shift circuit to the second digital phase shift circuit.

9. A digital phase shifter according to any one of claims 1 to 8, wherein the connection section comprises: a ground layer disposed above and / or below the first connection line and the second connection line; and a via hole connecting at least the second connection line and the ground layer.

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