Semiconductor composite substrate, semiconductor device, and method for manufacturing semiconductor composite substrate

Abstract

This semiconductor composite substrate comprises: a substrate that contains silicon; a first buffer layer that is disposed on a main surface of the substrate and that is made of silicon nitride; and a monocrystalline layer that is disposed on the first buffer layer and that is made of a compound semiconductor.

Description

Semiconductor composite substrate, semiconductor device, and method for manufacturing semiconductor composite substrate

[0001] The present disclosure relates to a semiconductor composite substrate, a semiconductor device, and a method for manufacturing a semiconductor composite substrate.

[0002] The following techniques are known as methods for manufacturing a semiconductor composite substrate including a single crystal layer of gallium nitride (GaN) or silicon carbide (SiC).

[0003] In Patent Document 1, a stress absorption layer and a buffer layer made of gallium arsenide (GaAs) are disposed between a silicon (Si) substrate and a GaN-based compound semiconductor layer, thereby absorbing stress between the Si substrate and the compound semiconductor layer, improving the quality of the compound semiconductor layer, and preventing bending of the Si substrate.

[0004] In Patent Document 2, the surfaces of a support substrate and a single crystal layer are irradiated with an argon neutron atomic beam, thereby creating an activated state in which bonding bonds are exposed on each surface. By bringing the activated support substrate and single crystal layer into contact, the bonding bonds are bonded to each other, and the support substrate and single crystal layer are bonded together.

[0005] Patent Document 3 discloses a manufacturing method in which substrates are bonded together by island-shaped adhesive layers formed by plasma treatment.

[0006] Japanese Patent Application Laid-Open No. 09-162125 International Publication No. 2016 / 006663 Special Publication No. 2011-515825

[0007] [Summary] In Patent Document 1, stress between the substrate and the compound semiconductor layer can be alleviated, but the lattice mismatch between GaAs and GaN is large, resulting in poor crystallinity of the compound semiconductor layer. It is not possible to achieve both stress relaxation and reduction of the lattice mismatch.

[0008] In Patent Documents 2 and 3, the single crystal layer and the support substrate are bonded together, which causes bonding defects and reduces yield. Furthermore, the bonding surfaces must be polished or temporarily bonded during bonding, which increases manufacturing costs.

[0009] An object of the present disclosure is to provide a semiconductor composite substrate in which a high-quality single crystal layer with little warping, cracking, and crystal defects is formed on a substrate containing inexpensive silicon, a semiconductor device using the semiconductor composite substrate, and a method for manufacturing the semiconductor composite substrate.

[0010] The semiconductor composite substrate of the present disclosure includes a substrate containing silicon, a first buffer layer made of silicon nitride disposed on a main surface of the substrate, and a single-crystal layer made of a compound semiconductor disposed on the first buffer layer.

[0011] The semiconductor device of the present disclosure is a semiconductor device that uses a semiconductor composite substrate, and a single crystal layer of the semiconductor composite substrate serves as a drift layer.

[0012] The method for manufacturing a semiconductor composite substrate according to the present disclosure includes the steps of preparing a substrate containing silicon, forming a first buffer layer made of silicon nitride on a main surface of the substrate, and forming a single crystal layer made of a compound semiconductor on the first buffer layer.

[0013] Fig. 1 is a cross-sectional view showing the configuration of a semiconductor composite substrate 1 according to a first embodiment. Fig. 2A is a bird's-eye view showing a unit cell 39 of a silicon crystal. Fig. 2B is a plan view showing a part of the atomic arrangement when the unit cell 39 of the silicon crystal is viewed from the <111> axis direction. Fig. 3A is a cross-sectional view showing a hexagonal Si ３ N ４ 3B is a top view showing a unit cell 71 of a crystal. ３ N ４FIG. 4 is a plan view showing a portion of the atomic arrangement when a unit cell 71 of a crystal is viewed from the <0001> axis direction. FIG. 4 is a flowchart showing an example of a method for manufacturing the semiconductor composite substrate 1 of FIG. 1. FIG. 5 is a cross-sectional view (part 1) showing one of the manufacturing steps of the semiconductor composite substrate 1 of FIG. 1. FIG. 6 is a cross-sectional view (part 2) showing another of the manufacturing steps of the semiconductor composite substrate 1 of FIG. 1. FIG. 7 is a cross-sectional view showing the configuration of a semiconductor composite substrate 2 according to a second embodiment. FIG. 8 is a flowchart showing an example of a method for manufacturing the semiconductor composite substrate 2 of FIG. 7. FIG. 9 is a cross-sectional view showing one of the manufacturing steps of the semiconductor composite substrate 2 of FIG. 7. FIG. 10 is a cross-sectional view showing the configuration of a semiconductor composite substrate 3 according to a third embodiment. FIG. 11 is a flowchart showing an example of a method for manufacturing a substrate 11 included in the semiconductor composite substrate 3 of FIG. 10. FIG. 12 is a cross-sectional view showing the configuration of a semiconductor composite substrate 4 according to a fourth embodiment. FIG. 13 is a cross-sectional view showing the configuration of a semiconductor composite substrate 5 according to a fifth embodiment. 14 is a flowchart showing an example of a method for manufacturing a substrate 11 included in the semiconductor composite substrate 4 of FIG. 12 and the semiconductor composite substrate 5 of FIG. 13. FIG. 15 is a cross-sectional view showing the configuration of a semiconductor composite substrate 6 according to a sixth embodiment. FIG. 16 is a cross-sectional view showing the configuration of a semiconductor composite substrate 7 according to a seventh embodiment. FIG. 17 is a cross-sectional view showing the configuration of a semiconductor composite substrate 8 according to an eighth embodiment. FIG. 18 is a cross-sectional view showing the configuration of a semiconductor composite substrate 9 according to a ninth embodiment. FIG. 19 is a cross-sectional view showing the configuration of a Schottky barrier diode (SBD) manufactured using the semiconductor composite substrate 6 of FIG. 15. FIG. 20 is a cross-sectional view showing the configuration of a trench gate MOSFET manufactured using the semiconductor composite substrate 6 of FIG. 15. FIG. 21 is a cross-sectional view showing the configuration of a planar gate MOSFET manufactured using the semiconductor composite substrate 6 of FIG. 15.

[0014] [Detailed Description] Hereinafter, embodiments of a semiconductor composite substrate, a manufacturing method thereof, and a semiconductor device using a semiconductor composite substrate according to the present disclosure will be described in detail with reference to the drawings. The embodiments are comprehensive or specific examples. The numerical values, shapes, materials, components, and the installation positions and connection forms of the components shown in the embodiments are merely examples and are not intended to limit the scope of the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concepts will be described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. Furthermore, the following embodiments and their variations may include similar components, and similar components will be assigned common reference numerals and redundant explanations will be omitted.

[0015] 1 is a cross-sectional view showing the configuration of a semiconductor composite substrate 1 according to a first embodiment. The semiconductor composite substrate 1 includes a substrate 11 containing silicon (Si) and a silicon nitride (Si) layer disposed on a main surface 11A of the substrate 11. ３ N ４ ) and a single crystal layer 13 made of a compound semiconductor disposed on the first buffer layer 12. The semiconductor composite substrate 1 is a wafer having a diameter of 100 mm or more, more preferably a wafer having a diameter of 150 mm or more.

[0016] The substrate 11 may further contain other elements as long as it contains at least Si. In the first embodiment, as an example of the substrate 11, a single crystal silicon substrate, the entire substrate 11 being made of single crystal Si, is used.

[0017] The crystal plane exposed on the main surface 11A of the substrate 11 is not particularly limited. It may be any of the (100), (110), and (111) planes, or may be a crystal plane that is off-angled from these planes. In the first embodiment, as an example, the description will continue for the case where the silicon (111) plane is exposed on the main surface 11A of the substrate 11.

[0018] The thickness of the substrate 11 may be any thickness that allows mechanical support during handling of the semiconductor composite substrate 1. In the case of a single crystal silicon substrate, the thickness of the substrate 11 is 100 μm or more and 1000 μm or less, for example, 300 μm, 500 μm, or 725 μm.

[0019] In the first embodiment, the single crystal layer 13 is made of gallium nitride (GaN), an example of a compound semiconductor. GaN is a semiconductor known as a material for blue light-emitting diodes (blue LEDs), and in recent years, it has also been expected to be applied to power semiconductors and radar. GaN crystals belong to the hexagonal system, and the lattice constant (a-axis) of GaN is 0.318 nm. The thickness of the single crystal layer 13 is 1 μm or more and 100 μm or less, for example, 10 μm.

[0020] The Si constituting the first buffer layer 12 ３ N ４ is the atmospheric pressure phase of Si, including α and β phases. ３ N ４ Atmospheric pressure phase Si ３ N ４ has a hexagonal crystal structure, and the lattice constant (a-axis) is 0.761 nm. ３ N ４ In the first embodiment, the first buffer layer 12 is made of β-phase Si, which has low manufacturing costs. ３ N ４ The following is a description of the case where the β phase Si ３ N ４ β-Si ３ N ４ The film thickness of the first buffer layer 12 is, for example, 7 nm.

[0021] The first buffer layer 12 functions as a crystal conversion layer that converts the crystal structure (cubic system) of the substrate 11 into the crystal structure (hexagonal system) of the single crystal layer 13, and also functions as a crystallinity improving layer that improves the crystallinity of the single crystal layer 13. This will be explained in detail below.

[0022] 2A is a bird's-eye view showing a unit cell 39 of a Si crystal. As shown in FIG. 2A, the Si crystal constituting the substrate 11 has a diamond structure of the cubic crystal system. The lattice constant (a) of the Si crystal shown in FIG. 2A is 0.5431 nm.

[0023] 2B is a plan view showing a part of the arrangement of atoms 63 when the unit cell 39 of the silicon crystal in FIG. 2A is viewed from the <111> axis direction. Of the arrangement of atoms 63 when viewed from the <111> axis direction, FIG. 2B shows only six atoms 63 that are exposed in a cross section cut along the equilateral triangular (111) plane 40 shown in FIG. 2A. As shown in FIG. 2B, one atom 63 is located at each vertex and at the center of each side of the equilateral triangle. The length of one side of the equilateral triangle in FIG. 2B is 2. １／２ a = 0.7679 nm, and the lattice constant of the Si crystal on the (111) plane 40 is 2 １／２ a / 2=0.384 nm.

[0024] On the other hand, FIG. 3A shows a hexagonal Si ３ N ４ This is an overhead view of a unit cell 71 of a crystal. The unit cell 71 is made up of three crystal axes (a １ axis, a ２ axis, a ３ The three axes (c-axis) intersect at an angle of 120 degrees on the same plane, and the crystal axis (c-axis) is perpendicular to these three axes, forming the overall outer shape of a hexagonal prism. ３ N ４ The lattice constant of the crystal (a １ axis, a ２ axis, a ３ axis) is 0.761 nm.

[0025] FIG. 3B shows a hexagonal Si ３ N ４3A is a plan view showing a portion of the arrangement of atoms 73 when a unit cell 71 of a crystal is viewed from the <0001> axis (c-axis) direction. Of the arrangement of atoms 73 when viewed from the <0001> axis (c-axis) direction, Figure 3B shows only seven atoms 73 that are exposed in a cross section cut along the (0001) plane 72 of the regular hexagon shown in Figure 3A. As shown in Figure 3B, atoms 73 are located at each vertex of the regular hexagon and at the center of the regular hexagon. The regular hexagon in Figure 3B includes six equilateral triangles 74 with atoms 73 as vertices.

[0026] The length of one side of the equilateral triangular (111) face 40 in FIG. １／２ The lattice mismatch (0.9%) between the (111) plane 40 of the Si crystal (a=0.7679 nm) and the side length (0.761 nm) of the equilateral triangle 74 in FIG. 3B is small. In other words, the lattice mismatch (0.9%) between the (111) plane 40 of the Si crystal (a=0.7679 nm) and the side length (0.761 nm) of the hexagonal Si crystal ３ N ４ The degree of lattice mismatch between the lattice constant (0.761 nm) of the (0001) plane 72 of the crystal is small. ３ N ４ By using high-order epitaxy based on the least common multiple matching of Si: 0.384 nm × 2 = 2:1, the first buffer layer 12 of hexagonal crystal structure with few lattice defects such as dislocations can be epitaxially grown on the main surface 11A of the cubic crystal substrate 11. ３ N ４ : 0.761nm Si / Si ３ N ４ Lattice mismatch: 0.9%

[0027] At this time, the first buffer layer 12 undergoes crystal growth such that the (0001) plane, i.e., the c-plane, of the first buffer layer 12 is parallel to the (111) plane 40 of the substrate 11. Therefore, for example, when the silicon (111) plane is exposed on the main surface 11A of the substrate 11, the (0001) plane is exposed on the main surface 12A of the first buffer layer 12 facing the single crystal layer 13. Note that even when the crystal plane exposed on the main surface 11A is angled off-axis from the (111) plane, the parallel relationship between the (111) plane 40 of the substrate 11 and the (0001) plane of the first buffer layer 12 is maintained, and the main surface 12A of the first buffer layer 12 is also angled off-axis from the (0001) plane.

[0028] Higher order epitaxy is heteroepitaxy in which lattice mismatch is reduced by matching at a ratio of multiple:1 or multiple:multiple, with the lattice constant as a unit.

[0029] Si ３ N ４ The lattice mismatch (4.5%) between the lattice constant (a-axis) of the Si crystal and the lattice constant (a-axis) of the GaN crystal is small. ３ N ４ The first buffer layer (Si:GaN) was formed by the least common multiple matching of 2:5. ３ N ４ A single crystal layer (GaN) 13 with few lattice defects can be epitaxially grown on the Si substrate 12. ３ N ４ : 0.761nm×2=1.522nm GaN: 0.318nm×5=1.59nm Si ３ N ４ / GaN lattice mismatch: 4.5%

[0030] At this time, the first buffer layer 12 undergoes crystal growth such that the (0001) plane, i.e., the c-plane, of the single crystal layer 13 is parallel to the (0001) plane of the first buffer layer 12. Therefore, for example, when the silicon (111) plane is exposed on the main surface 12A of the first buffer layer 12, the (0001) plane is exposed on the main surface of the single crystal layer 13. When the first buffer layer 12 has an off-axis angle, the single crystal layer 13 also has an off-axis angle.

[0031] In this way, the first buffer layer 12 functions as a crystal conversion layer that converts the crystal structure from a cubic system (substrate 11) to a hexagonal system (single crystal layer 13) by being interposed between the substrate 11 and the single crystal layer 13. In addition, by high-order epitaxy using least common multiple matching, a Si layer with few lattice defects is formed on the Si. ３ N ４ It is possible to grow crystals of Si with high crystallinity. ３ N ４ High-quality GaN with fewer lattice defects can be grown on the sapphire substrate. The lattice mismatch (17%) between the lattice constant of Si crystal (0.384 nm) and the lattice constant of GaN crystal (0.318 nm) in the (111) plane is large. Therefore, the first buffer layer 12, when interposed between the substrate 11 and the single-crystal layer 13, functions as a crystallinity-improving layer that improves the crystallinity of the single-crystal layer 13. The lattice mismatch (21%) between the lattice constant of sapphire (0.238 nm) and the lattice constant of GaN crystal (0.318 nm) is even larger. Therefore, a high-quality single-crystal layer 13 (GaN) can be formed compared to GaN grown on a sapphire substrate. According to the first embodiment, the yield of the semiconductor composite substrate 1 can be improved.

[0032] An example of a method for manufacturing the semiconductor composite substrate 1 of Fig. 1 will be described with reference to Fig. 4 to Fig. 6. Fig. 4 is a flowchart showing an example of a method for manufacturing the semiconductor composite substrate 1 of Fig. 1. Figs. 5 and 6 are cross-sectional views each showing a manufacturing process of the semiconductor composite substrate 1 of Fig. 1.

[0033] First, in step S01, a substrate 11 containing silicon is prepared, as shown in Fig. 5. The crystal plane of the main surface 11A of the substrate 11 does not matter. The silicon (111) plane may be exposed on the main surface 11A. Furthermore, in order to reduce the electrical resistivity of the substrate 11, the substrate 11 may be doped in advance with impurities such as phosphorus (P), arsenic (As), boron (B), or nitrogen (N).

[0034] Proceeding to step S02, as shown in FIG. 6, Si ３ N ４Specifically, the first buffer layer 12 is grown heteroepitaxially on the primary surface 11A of the substrate 11. As described with reference to FIGS. 2A to 3B, the first buffer layer 12 is grown heteroepitaxially on the primary surface 11A of the substrate 11 by the lowest common multiple matching high-order epitaxy. ３ N ４ The highly crystalline Si is deposited on the Si crystal so that the (0001) plane of the Si is parallel to the ３ N ４ Crystals can be grown.

[0035] Nitrogen atoms react with gaseous Si to form α-phase Si ３ N ４ (α-Si ３ N ４ On the other hand, nitrogen atoms react with solid or liquid Si to form β-phase Si. ３ N ４ (β-Si ３ N ４ ) is formed. ３ N ４ Compared to β-Si ３ N ４ can be formed at low cost by a simple method.

[0036] Si ３ N ４ The thermal nitridation method can be used as a film formation method for the Si substrate. The thermal nitridation method is to heat the Si substrate to a high temperature of 1100° C. or more in a nitrogen atmosphere. ３ N ４ Since the diffusion coefficient of nitrogen in a Si substrate is small, a thin Si film with a thickness of a few nm (for example, 7 nm) is formed. ３ N ４ By slowing down the growth rate at a lower temperature, Si ３ N ４ The film can be grown epitaxially.

[0037] Si ３ N ４Other methods for forming the nitride film include plasma nitridation, low-pressure CVD (chemical vapor deposition), and plasma CVD. Plasma nitridation is a method for forming a nitride film in a low-temperature atmosphere of about 300°C using high-frequency discharge plasma in the same manner as thermal nitridation. Low-pressure CVD is a method for forming a nitride film on a Si substrate by vapor-phase reaction of Si source gas and ammonia gas at a temperature of 700°C to 800°C. ３ N ４ The plasma CVD method is a method for forming a Si film on a Si substrate in a low temperature atmosphere of 300 to 400°C by converting a Si source gas and ammonia gas into plasma. ３ N ４ This is a method for forming a film.

[0038] Proceeding to step S03, as shown in FIG. 6, a first buffer layer 12 (Si ３ N ４ A single crystal layer 13 (GaN) made of a compound semiconductor is formed on the main surface 12A of the Si substrate. ３ N ４ GaN is grown heteroepitaxially on the Si substrate. ３ N ４ The first buffer layer (Si:GaN) was formed by the least common multiple matching of 2:5. ３ N ４ A single crystal layer (GaN) 13 with few lattice defects can be epitaxially grown on the substrate 12. This allows the semiconductor composite substrate 1 shown in FIG.

[0039] Specific deposition methods include molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and laser ablation. MBE is a method of forming GaN by depositing gallium (Ga) and nitrogen (N) atoms on a substrate in an ultra-high vacuum. Growth in a high vacuum environment results in a single-crystal layer 13 with extremely high purity and crystalline quality. Low-temperature growth is possible, minimizing damage to the substrate 11. MOCVD is a method of depositing GaN by reacting an organometallic compound (e.g., trimethylgallium) with a nitrogen source (usually ammonia). Setting the growth temperature to 1100°C or higher allows for the deposition of a single-crystal layer 13 (GaN) with high crystallinity.

[0040] According to the manufacturing method described above, the semiconductor composite substrate 1 can be manufactured using the substrate 11 made of inexpensive Si, and therefore the processing and material costs can be reduced compared to the conventional bonding method and the method using a GaN substrate.

[0041] Second Embodiment The configuration of a semiconductor composite substrate 2 according to a second embodiment will be described with reference to Fig. 7. The semiconductor composite substrate 2 differs from the semiconductor composite substrate 1 of Fig. 1 in that a second buffer layer 14 made of aluminum nitride (AlN) is interposed between the single crystal layer 13 and the first buffer layer 12. The other configuration of the semiconductor composite substrate 2 is the same as that of the semiconductor composite substrate 1.

[0042] The AlN constituting the second buffer layer 14 has a hexagonal crystal structure, and the lattice constant (a-axis) of the AlN crystal is 0.3111 nm. ３ N ４ The lattice mismatch (2.2%) between the lattice constant (a-axis) of the Si crystal and the lattice constant (a-axis) of the AlN crystal is small. ３ N ４ The first buffer layer (Si:AlN=2:5) was obtained by least common multiple matching. ３ N ４A second buffer layer 14 (AlN) with few lattice defects can be epitaxially grown on the Si substrate 12. The thickness of the second buffer layer 14 is, for example, 100 nm. ３ N ４ : 0.761nm×2=1.522nm AlN: 0.3111nm×5=1.5555nm Si ３ N ４ / AlN lattice mismatch: 2.2%

[0043] The lattice mismatch (2.4%) between the lattice constant (a-axis) of the AlN crystal and the lattice constant (a-axis) of the GaN crystal is small. Therefore, a single crystal layer (GaN) 13 with few lattice defects can be epitaxially grown on the second buffer layer 14 (AlN). AlN: 0.3111 nm GaN: 0.318 nm AlN / GaN lattice mismatch: 2.4%

[0044] As explained in the first embodiment, Si ３ N ４ The lattice mismatch of Si / AlN (2.2%) and AlN / GaN (2.4%) is ３ N ４ :Si in the least common multiple matching of GaN=2:5 ３ N ４ The lattice mismatch between the single crystal layer 13 (GaN) and the first buffer layer 12 (Si ３ N ４ By interposing the second buffer layer 14 (AlN) between the first and second layers, the lattice mismatch at the bonding interface can be further reduced. Therefore, according to the semiconductor composite substrate 2 of the second embodiment, the crystallinity of the single-crystal layer 13 (GaN) finally formed can be further improved compared to the semiconductor composite substrate 1.

[0045] An example of a method for manufacturing the semiconductor composite substrate 2 of Fig. 7 will be described with reference to Fig. 8 and Fig. 9. Fig. 8 is a flowchart showing an example of a method for manufacturing the semiconductor composite substrate 2 of Fig. 7. Fig. 9 is a cross-sectional view showing a manufacturing process of the semiconductor composite substrate 2 of Fig. 7.

[0046] As shown in Fig. 8, the method for manufacturing a semiconductor composite substrate 2 differs from the flowchart in Fig. 4 in that it further includes step S04 between step S02 and step S03. Steps S01 to S03 are the same as those in the flowchart in Fig. 4, and therefore will not be described again.

[0047] In step S04, as shown in FIG. 9, a first buffer layer 12 (Si ３ N ４ A second buffer layer 14 (AlN) is formed on the main surface 12A of the Si substrate. ３ N ４ AlN is epitaxially grown on the Si substrate. ３ N ４ Since the lattice mismatch (2.4%) between the lattice constant (a-axis) of AlN and the lattice constant (a-axis) of Si is small, the first buffer layer (Si ３ N ４ A second buffer layer 14 (AlN) with few lattice defects can be epitaxially grown on the AlN layer 12. Specific methods for forming AlN include MBE and MOCVD.

[0048] Proceeding to step S03, as shown in FIG. 7, a single-crystal layer 13 (GaN) is formed on the primary surface 14A of the second buffer layer 14 (AlN). Specifically, GaN is epitaxially grown on the AlN. As described above, the lattice mismatch (2.4%) between the lattice constant (a-axis) of AlN and the lattice constant (a-axis) of GaN is small, so a single-crystal layer (GaN) 13 with few lattice defects can be epitaxially grown on the second buffer layer 14 (AlN). This allows the semiconductor composite substrate 1 shown in FIG. 7 to be manufactured.

[0049] The second buffer layer 14 (AlN) is ３ N ４ By interposing the GaN layer 12 between the GaN layer 12 and the GaN layer 13, the lattice mismatch between the layers can be further reduced. Therefore, the semiconductor composite substrate 2 can further improve the crystallinity of the GaN layer 13.

[0050] In order to eliminate the lattice mismatch between Si(111) and GaN, AlN may be grown between Si(111) and GaN. However, since it is necessary to increase the thickness of the AlN to eliminate the lattice mismatch, the AlN cracks due to thermal stress caused by the difference in the linear expansion coefficient between Si and AlN. According to the first embodiment, Si is grown on Si. ３ N ４ By growing the AlN (first buffer layer 12), the lattice mismatch is eliminated. According to the second embodiment, the lattice mismatch can be further reduced by disposing the AlN (second buffer layer 14). In this case, the thickness of the AlN (second buffer layer 14) can be made thin, which reduces the risk of cracking and warping of the substrate.

[0051] (Third Embodiment) The configuration of a semiconductor composite substrate 3 according to a third embodiment will be described with reference to Figure 10. The semiconductor composite substrate 3 differs from the semiconductor composite substrate 2 of Figure 7 in the structure of the substrate 11. That is, the substrate 11 of the semiconductor composite substrate 2 is a substrate with a single-layer structure made of single-crystal silicon. In contrast, the substrate 11 of the semiconductor composite substrate 3 has a layered structure in which multiple layers made of materials with different linear expansion coefficients or mechanical properties are stacked. The other configurations of the semiconductor composite substrate 3 are the same as those of the semiconductor composite substrate 2.

[0052] When the substrate 11 has a laminated structure, it is desirable that the substrate 11 has a single-crystal silicon layer 16 exposed on its main surface 11A. As a result, as described in the first and second embodiments, a first buffer layer 12 (Si ３ N ４ ) can be epitaxially grown. The silicon (111) plane may be exposed on the primary surface 11A of the single crystal silicon layer 16. The first buffer layer 12 and the second buffer layer 14 can be formed along the <0001> axis.

[0053] In the third embodiment, the substrate 11 further includes a support substrate 15 including polycrystalline silicon carbide (SiC) disposed on a main surface 16A of the single-crystal silicon layer 16 facing in the opposite direction to the main surface 11A of the substrate 11. The support substrate 15 only needs to have a thickness sufficient to mechanically support the semiconductor composite substrate 3 during handling. In the case of polycrystalline SiC, the thickness of the support substrate 15 is, for example, 350 μm. On the other hand, the single-crystal silicon layer 16 only needs to serve as a base for forming the first buffer layer 12, and therefore only needs to have a thickness of about several μm.

[0054] A manufacturing method of the substrate 11 shown in FIG. 10 will be described with reference to the flowchart of FIG. 11. The flowchart of FIG. 11 corresponds to the "Preparing a Substrate" step S01 shown in FIGS. 4 and 8. In step S11, a support substrate 15 made of polycrystalline SiC and a single-crystal silicon layer 16 are prepared. The surfaces of the support substrate 15 and the single-crystal silicon layer 16 are planarized by CMP. Note that the polycrystalline SiC may contain SiC crystals of various polytypes and plane orientations. Since SiC crystals of various polytypes and plane orientations can be manufactured without strict temperature control, the manufacturing cost of the support substrate 15 can be reduced. Furthermore, the support substrate 15 and the single-crystal silicon layer 16 may be doped in advance with impurities such as phosphorus (P), arsenic (As), boron (B), or nitrogen (N) to reduce electrical resistivity.

[0055] Proceeding to step S12, the planarized surfaces of the support substrate 15 and the single-crystal silicon layer 16 are bonded. For example, the method described in Patent Document 2 can be used. An argon neutron atomic beam is irradiated onto the surfaces of the support substrate 15 and the single-crystal silicon layer 16, thereby activating them so that bonding bonds are exposed on each surface. By bringing the surfaces of the activated support substrate 15 and the single-crystal silicon layer 16 into contact, the bonding bonds are bonded together, and the support substrate 15 and the single-crystal silicon layer 16 are bonded at room temperature. Subsequent heat treatment activates the doped impurities. Through these steps, a substrate 11 having the stacked structure shown in FIG. 10 can be manufactured. The method for manufacturing the semiconductor composite substrate 3 using the substrate 11 is then the same as the method for manufacturing the semiconductor composite substrate 2, and a repeated description will be omitted.

[0056] Si (111), GaN (0001), AlN (0001), Si ３ N ４ The linear expansion coefficients (x10^-6 / K) of SiC (0001) are as follows: Si(111) 2.59 GaN(0001) 5.59 AlN(0001) 6.43 Si ３ N ４ (0001) 2.6-3.5 SiC 4.4

[0057] The linear expansion coefficient of SiC is closer to that of GaN and AlN than that of Si. The difference in linear expansion coefficient is smaller. Therefore, compared to the semiconductor composite substrates 1 and 2 using the silicon substrate 11 shown in FIGS. 1 and 7, the semiconductor composite substrate 3 using the support substrate 15 made of polycrystalline SiC shown in FIG. 10 can reduce the risk of cracking and warping of the semiconductor composite substrate.

[0058] (Fourth embodiment) The configuration of a semiconductor composite substrate 4 according to a fourth embodiment will be described with reference to Fig. 12. The semiconductor composite substrate 4 has a laminated structure in which a substrate 11 is made up of multiple layers, similar to the semiconductor composite substrate 3 of Fig. 10. The configuration other than the substrate 11 is the same as that of the semiconductor composite substrate 2.

[0059] As shown in FIG. 12 , the substrate 11 has a single-crystal silicon layer 16 exposed on its main surface 11A, a W bonding layer 18 containing tungsten (W) disposed on the main surface 16A of the single-crystal silicon layer 16 facing in the opposite direction to the main surface 11A of the substrate 11, and a support substrate 17 containing Si disposed on the main surface 18A of the W bonding layer 18.

[0060] The thickness of the support substrate 17 may be any thickness that allows it to mechanically support the semiconductor composite substrate 4 during handling. The support substrate 17 may be made of either polycrystalline Si or single-crystalline Si.

[0061] The W bonding layer 18 functions as an adhesive layer that bonds the support substrate 17 and the single-crystal silicon layer 16. The W bonding layer 18 contains tungsten silicide (WSi ２ ) may contain Si in addition to W.

[0062] A method for manufacturing the substrate 11 shown in Fig. 12 will be described with reference to the flowchart of Fig. 14. The flowchart of Fig. 14 corresponds to "preparing the substrate" step S01 shown in Fig. 4 and Fig. 8. The flowchart of Fig. 14 also includes step S13 instead of step S12 in the flowchart of Fig. 11.

[0063] In step S11, a support substrate 17 containing Si and a single-crystal silicon layer 16 are prepared. The surfaces of the support substrate 17 and the single-crystal silicon layer 16 are planarized by CMP. To reduce electrical resistance, the support substrate 17 and the single-crystal silicon layer 16 may be doped in advance with impurities such as phosphorus (P), arsenic (As), boron (B), or nitrogen (N).

[0064] Proceeding to step S13, the planarized surfaces of the support substrate 17 and the single-crystal silicon layer 16 are bonded using a W bonding layer 18. First, a thin film of W is formed on at least one surface of the support substrate 17 and the single-crystal silicon layer 16 using physical vapor deposition (PVD) such as sputtering or electron beam evaporation (EB evaporation). The thickness of the W may be approximately several nm to several μm. The surfaces of the support substrate 17 and the single-crystal silicon layer 16 are superimposed with the W bonding layer 18 interposed therebetween and heated. The heating temperature may be approximately 400°C to 700°C. Bonding is formed by the interaction between Si and W. Through the above steps, a substrate 11 having the stacked structure shown in FIG. 12 can be manufactured. The method for manufacturing the semiconductor composite substrate 4 using the substrate 11 is then the same as the method for manufacturing the semiconductor composite substrate 2, and will not be described again.

[0065] The Young's modulus of the W bonding layer 18 containing W is smaller than those of the support substrate 17 containing Si and the single-crystal layer 13 made of GaN. In other words, the W bonding layer 18 is a layer that is softer than the support substrate 17 and the single-crystal layer 13. By disposing the W bonding layer 18 between the support substrate 17 and the first buffer layer 12, the second buffer layer 14, and the single-crystal layer 13, the W bonding layer 18 can alleviate the difference in linear expansion coefficients, thereby reducing the risk of cracking and warping of the substrate.

[0066] 10, the support substrate 17 is made of Si, which is an inexpensive material. According to the semiconductor composite substrate 4, a high-quality single-crystal layer 13 can be formed using the support substrate 17 made of inexpensive silicon.

[0067] Fifth Embodiment The configuration of a semiconductor composite substrate 5 according to a fifth embodiment will be described with reference to Fig. 13. The semiconductor composite substrate 5 differs from the semiconductor composite substrate 4 of Fig. 12 in that the support substrate contains polycrystalline SiC. The other configurations of the semiconductor composite substrate 5 are the same as those of the semiconductor composite substrate 4, and a repeated description will be omitted.

[0068] 13 , the substrate 11 includes a single-crystal silicon layer 16 exposed on its main surface 11A, a W-bonding layer 18 containing tungsten (W) disposed on the main surface 16A of the single-crystal silicon layer 16 facing in the opposite direction to the main surface 11A of the substrate 11, and a support substrate 15 containing SiC disposed on the main surface 18A of the W-bonding layer 18. The linear expansion coefficient of SiC (4.4) is closer to the linear expansion coefficients of GaN and AlN than the linear expansion coefficient of Si (2.59). Therefore, the semiconductor composite substrate 5 can further reduce the risk of substrate cracking and warping compared to the semiconductor composite substrate 4 of FIG. 12 .

[0069] Sixth Embodiment The configuration of a semiconductor composite substrate 6 according to a sixth embodiment will be described with reference to Fig. 15. The semiconductor composite substrate 6 differs from the semiconductor composite substrate 1 of Fig. 1 in that the single crystal layer 19 is made of silicon carbide (SiC). The other configurations of the semiconductor composite substrate 6 are the same as those of the semiconductor composite substrate 1 of Fig. 1, and therefore will not be described again.

[0070] SiC has attracted attention in the field of power electronics as a semiconductor device material suitable for use in high-frequency, high-voltage, and high-temperature environments, particularly as powertrain components for electric vehicles (EVs). SiC crystals have many crystal polytypes, such as hexagonal 4H-SiC and 6H-SiC, and cubic 3C-SiC, but any of these crystal polytypes may be used in the sixth embodiment. The lattice constants (a-axis) of SiC are 0.30730 nm for 4H-SiC, 0.30806 nm for 6H-SiC, and 0.43596 nm for 3C-SiC. The film thickness of the single crystal layer 19 is 1 μm or more and 100 μm or less, for example, 10 μm.

[0071] Even when the single crystal layer 19 is made of SiC, the first buffer layer 12 functions as a crystal conversion layer that converts the crystal structure (cubic system) of the substrate 11 into the crystal structure (hexagonal system) of the single crystal layer 19, and also functions as a crystal improvement layer that improves the crystallinity of the single crystal layer 19. ３ N ４ The lattice mismatch that occurs when the single crystal layer 19 (SiC) is epitaxially grown on the Si substrate will now be described in detail.

[0072] Taking 4H—SiC as an example, we will explain hexagonal SiC. ３ N ４ The lattice mismatch (1.0%) between the lattice constant (a-axis) of the 4H-SiC crystal is small, and the lattice constant (a-axis) of the 4H-SiC crystal is small. ３ N ４ The lattice mismatch between Si and ３ N ４ : 0.761nm×2=1.522nm 4H-SiC: 0.30730nm×5=1.5365nm Si ３ N ４ / 4H—SiC lattice mismatch: 1.0%

[0073] Therefore, Si ３ N ４ The first buffer layer 12 (Si:4H-SiC) was grown by high-order epitaxy using the least common multiple matching of 4H-SiC=2:5. ３ N ４On the main surface 12A of the silicon substrate 12, a hexagonal single crystal layer 19 (4H--SiC) having few lattice defects such as dislocations can be epitaxially grown.

[0074] Cubic SiC will be explained using 3C-SiC as an example. 3C-SiC, like Si, has the diamond structure shown in FIG. 2A. The lattice constant (a-axis) of 3C-SiC is 0.43596 nm. Therefore, the lattice constant of 3C-SiC on the (111) plane 40 is 2 １／２ a / 2=0.30827 nm.

[0075] Si ３ N ４ The lattice mismatch (1.3%) between twice the lattice constant (a-axis) of the crystal and five times the lattice constant of 3C-SiC on the (111) plane 40 is small.

[0076] Si ３ N ４ : 0.761nm×2=1.522nm 3C-SiC: 0.30827nm×5=1.541nm Si ３ N ４ / 3C-SiC lattice mismatch: 1.3%. Therefore, Si ３ N ４ The first buffer layer 12 (Si:3C-SiC=2:5) was grown by high-order epitaxy using the least common multiple matching. ３ N ４ On the main surface 12A of the silicon nitride film, a cubic single crystal layer 19 (3C-SiC) with few lattice defects such as dislocations can be epitaxially grown.

[0077] In this way, the first buffer layer 12 functions as a crystal conversion layer that converts the crystal structure from a cubic system (substrate 11) to a hexagonal system (single crystal layer 19) by being interposed between the substrate 11 and the single crystal layer 19. In addition, by high-order epitaxy using least common multiple matching, a Si layer with few lattice defects on the Si substrate is formed. ３ N ４ It is possible to grow crystals of Si with high crystallinity. ３ N ４It is possible to grow high-quality SiC crystals with fewer lattice defects on the substrate 11. There is a large lattice mismatch between the lattice constant of Si crystal (0.384 nm) and the lattice constants of SiC crystal (0.30806 nm, 0.30730 nm, 0.43596 nm) on the (111) plane. Furthermore, 4H-SiC requires step-flow growth, making it difficult to grow on Si. Therefore, the first buffer layer 12, interposed between the substrate 11 and the single-crystal layer 19, functions as a crystallinity-improving layer that improves the crystallinity of the single-crystal layer 19.

[0078] A specific example of a method for epitaxially growing the single crystal layer 19 (SiC) will be described. CVD or MBE can be used as a method for forming the single crystal layer 19 (SiC). In CVD, silane or other Si precursor and propane or other carbon (C) precursor are introduced into a reaction chamber, and these precursor gases react on a substrate heated to 1200°C to 1600°C to grow SiC. In MBE, atomic beams of Si and C are irradiated onto a substrate in an ultra-high vacuum, and these atoms grow into crystals on the substrate surface.

[0079] Seventh Embodiment Fig. 16 is a cross-sectional view showing the configuration of a semiconductor composite substrate 7 according to a seventh embodiment. The semiconductor composite substrate 7 differs from the semiconductor composite substrate 6 of Fig. 15 in that a third buffer layer 28 containing platinum (Pt) is interposed between the first buffer layer 12 and the substrate 11. The film thickness of the third buffer layer 28 is, for example, 100 nm.

[0080] Pt crystals have a face-centered cubic lattice structure. Therefore, the third buffer layer 28 can be grown on the substrate 11 along the Si(111) plane. Then, by high-order epitaxy using least common multiple matching, the first buffer layer 12, which is a hexagonal crystal with few lattice defects such as dislocations, can be epitaxially grown on the third buffer layer 28.

[0081] Specific methods for forming a Pt film include MBE and CVD. In CVD, platinum acetylacetonate can be used as a platinum precursor gas.

[0082] The Young's modulus of the third buffer layer 28 containing platinum (Pt) is smaller than those of the substrate 11 containing Si and the single-crystal layer 19 made of SiC. In other words, the third buffer layer 28 is a layer softer than those of the substrate 11 and the single-crystal layer 19. By disposing the third buffer layer 28 between the substrate 11 and the first buffer layer 12 and the single-crystal layer 19, the third buffer layer 28 can relieve thermal stress and reduce the risk of cracking and warping of the substrate.

[0083] Eighth Embodiment Fig. 17 is a cross-sectional view showing the configuration of a semiconductor composite substrate 8 according to an eighth embodiment. The semiconductor composite substrate 8 differs from the semiconductor composite substrate 6 of Fig. 15 in that hafnia (hafnium dioxide: HfO ２ ) and zirconia (zirconium dioxide: ZrO ２ ) is interposed therebetween. The thickness of the fourth buffer layer 29 is, for example, 30 nm. The fourth buffer layer 29 is made of HfO ２ and ZrO ２ Mixed crystal of Hf ｘ Zr １－ｘ O ２ ) or HfO ２ layer and ZrO ２ It may have a multi-layer structure.

[0084] HfO ２ and ZrO ２ (Hereafter, “Hf-ZrO ２ ") undergoes a phase transformation from orthorhombic to tetragonal to cubic as the temperature rises from room temperature. This improves the symmetry of the crystal structure, expands the lattice, and reduces the density. Hf-ZrO ２ When compressive stress is applied to Hf—ZrO, the compressive stress is relieved by transformation to the orthorhombic side. ２ When tensile stress is applied to Hf—ZrO, the tensile stress is alleviated by transforming to the cubic side. ２The fourth buffer layer 29 including the above-mentioned compound is disposed between the first buffer layer 12 and the substrate 11, thereby making it possible to utilize phase transformation to relieve thermal stress, thereby reducing the risk of cracking and warping of the semiconductor composite substrate 8.

[0085] Hf—ZrO on the substrate 11 (Si) ２ By growing Hf-ZrO with a changed lattice constant, ２ is formed, and Hf—ZrO ２ The lattice constant of the Hf—ZrO grown on the substrate 11 (Si) can be made closer to that of the single crystal layer 19 (SiC). ２ The lattice constant of Hf—ZrO changes during crystal growth of the single crystal layer 19. ２ In this way, the fourth buffer layer 29 can reduce the difference in lattice constant between the substrate 11 (Si) and the single-crystal layer 19 (SiC), allowing the growth of a high-quality single-crystal layer 19.

[0086] Hf-ZrO ２ Since the lattice mismatch between Hf—ZrO and Si (substrate 11) is large, ２ There are many lattice defects in the grown film. As the film is grown, the above-mentioned phase transformation occurs and the film changes to its original crystal structure. During the initial unstable growth, the substrate 11 and the grown film (Hf-ZrO ２ Phase transformations can be used to improve lattice matching of the

[0087] 18 is a cross-sectional view showing the configuration of a semiconductor composite substrate 9 according to a ninth embodiment. The semiconductor composite substrate 9 has both the third buffer layer 28 and the fourth buffer layer 29 described in the seventh and eighth embodiments. In detail, the fourth buffer layer 29 (Hf—ZrO ２ ) is formed on the semiconductor composite substrate 9, and a third buffer layer 28 (Pt) is formed on the fourth buffer layer 29. By providing both the third buffer layer 28 and the fourth buffer layer 29, stress due to differences in lattice constants and linear expansion coefficients can be further alleviated. This further reduces the risk of cracking and warping of the semiconductor composite substrate 9, allowing a high-quality single-crystal layer 19 to be grown.

[0088] Tenth Embodiment Next, an embodiment of a semiconductor device using the semiconductor composite substrates 1 to 9 will be described. The semiconductor device according to the embodiment includes any of the semiconductor composite substrates 1 to 9, with the single crystal layer 19 of the semiconductor composite substrates 1 to 9 serving as a drift layer, and the other layers of the semiconductor composite substrates 1 to 9 excluding the single crystal layer 19 serving as substrate layers. As an embodiment of a semiconductor device manufactured using any of the semiconductor composite substrates 1 to 9, a Schottky barrier diode (SiC-SBD), a SiC trench gate metal-oxide-semiconductor field-effect transistor (MOSFET), and a SiC planar gate MOSFET will be described. Of the semiconductor composite substrates 1 to 9, the semiconductor composite substrate 6 having the single crystal layer 19 made of SiC will be used for the description.

[0089] 19 is a cross-sectional view of a SiC-SBD 20. The SiC-SBD 20 was fabricated using the semiconductor composite substrate 6 shown in FIG. 15. The substrate 11 and the first buffer layer 12 were 5×10 １８ / cm ３ From 2 x 10 ２２ / cm ３ The single crystal layer 19 is doped to a high concentration of n+ type in the range of 5×10 １４ / cm ３ From 2 x 10 １７ / cm ３ The substrate 11 is doped with a low concentration of n-type in the range of 1 to 1000 to form a drift layer. The bottom surface of the substrate 11 is covered with a cathode electrode 21, which is connected to a cathode terminal K.

[0090] The main surface 19A of the single crystal layer 19 is provided with a contact hole 23 that exposes a part of the single crystal layer 19 as a body region 22, and a field insulating film 25 is formed in a field region 24 surrounding the body region 22. The field insulating film 25 is made of SiO ２ (silicon oxide), but silicon nitride (Si ２ N ３The field insulating film 25 may be made of other insulating materials such as SiO 2 , SiO 2 , or the like. An anode electrode 26 is formed on the field insulating film 25 and is connected to an anode terminal A.

[0091] A p-type JTE (junction termination extension) structure 27 is formed in the vicinity of the main surface 19A (surface layer portion) of the single crystal layer 19 so as to contact the anode electrode 26. The JTE structure 27 is formed along the contour of the contact hole 23 in the field insulating film 25 so as to straddle the inside and outside of the contact hole 23.

[0092] 20 is a cross-sectional view of a SiC trench gate MOSFET 30. The SiC trench gate MOSFET 30 is fabricated using the semiconductor composite substrate 6 shown in FIG. 15. The substrate 11 and the first buffer layer 12 are 5×10 １８ / cm ３ From 2 x 10 ２２ / cm ３ High concentration of n in the range ＋ The single crystal layer 19 is doped to form a substrate layer. １４ / cm ３ From 2 x 10 １７ / cm ３ Low concentration n in the range － The bottom surface of the substrate 11 is covered with a drain electrode 31, which is connected to a drain terminal D.

[0093] A p-type body region 32 is formed on a main surface 19A of the single crystal layer 19. In the single crystal layer 19, the portion on the substrate 11 side relative to the body region 32 is a lightly doped n-type layer that is maintained in the state of the single crystal layer 19. - The single crystal layer 19 has a gate trench 34 formed therein. The gate trench 34 penetrates the body region 32 from the main surface 19A of the single crystal layer 19, and its deepest portion reaches the drain region 33.

[0094] A gate insulating film 35 is formed on the inner surface of the gate trench 34 and on the main surface 19A of the single-crystal layer 19 so as to cover the entire inner surface of the gate trench 34. The inside of the gate insulating film 35 is filled with, for example, polysilicon, thereby embedding a gate electrode 36 in the gate trench 34. A gate terminal G is connected to the gate electrode 36.

[0095] The surface layer of the body region 32 is formed with a highly doped n-type impurity dopant (nPt) that forms part of the side surface of the gate trench 34. + The single-crystal layer 19 has a source region 37 formed therein. The single-crystal layer 19 also has a highly doped p + A mold body contact region 38 is formed.

[0096] An interlayer insulating film 41 made of SiO2 is formed on the single crystal layer 19. A source electrode 43 is connected to the source region 37 and the body contact region 38 via a contact hole 42 formed in the interlayer insulating film 41. A source terminal S is connected to the source electrode 43.

[0097] By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 36 while a predetermined potential difference is generated between the source electrode 43 and the drain electrode 31 (between the source and drain), a channel can be formed in the body region 32 near the interface with the gate insulating film 35 due to the electric field from the gate electrode 36. This allows a current to flow between the source electrode 43 and the drain electrode 31, turning on the SiC trench-gate MOSFET 30.

[0098] 21 is a cross-sectional view of a SiC planar gate MOSFET 50. The SiC planar gate MOSFET 50 is fabricated using the semiconductor composite substrate 6 shown in FIG. 15. The substrate 11 and the first buffer layer 12 are 5×10 １８ / cm ３ From 2 x 10 ２２ / cm ３ High concentration of n in the range ＋The single crystal layer 19 is doped to form a substrate layer. １４ / cm ３ From 2 x 10 １７ / cm ３ Low concentration n in the range － The bottom surface of the substrate 11 is covered with a drain electrode 51, which is connected to a drain terminal D.

[0099] A p-type body region 52 is formed in a well shape on a main surface 19A of the single crystal layer 19. In the single crystal layer 19, the portion on the substrate 11 side relative to the body region 52 is a lightly doped n-type layer in which the state of the single crystal layer 19 is maintained as it is. - The surface layer of the body region 52 is a heavily doped n + A source region 54 of the type is formed at a distance from the periphery of the body region 52. Inside the source region 54, a heavily doped p + A body contact region 55 is formed on the source region 54. The body contact region 55 penetrates the source region 54 in the depth direction and is connected to the body region 52.

[0100] A gate insulating film 56 is formed on the main surface 19A of the single crystal layer 19. The gate insulating film 56 covers a portion of the body region 52 surrounding the source region 54 (the peripheral portion of the body region 52) and the outer periphery of the source region 54. A gate electrode 57 made of, for example, polysilicon is formed on the gate insulating film 56. The gate electrode 57 faces the peripheral portion of the body region 52 with the gate insulating film 56 interposed therebetween. A gate terminal G is connected to the gate electrode 57.

[0101] An interlayer insulating film 58 made of SiO2 is formed on the single crystal layer 19. A source electrode 62 is connected to the source region 54 and the body contact region 55 via a contact hole 61 formed in the interlayer insulating film 58. A source terminal S is connected to the source electrode 62.

[0102] By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 57 while a predetermined potential difference is generated between the source electrode 62 and the drain electrode 51 (between the source and drain), a channel can be formed in the body region 52 near the interface with the gate insulating film 56 due to the electric field from the gate electrode 57. This allows a current to flow between the source electrode 62 and the drain electrode 51, turning on the SiC planar gate MOSFET 50.

[0103] Although not shown, in the SiC planar gate MOSFET 50 of FIG. 21, the conductivity type of the substrate layer is set to a different conductivity type (p ＋ The semiconductor composite substrate 6 can be used to manufacture an insulated-gate bipolar transistor (IGBT).

[0104] In the semiconductor devices (20, 30, 50) described above, by using the single crystal layer 19 with good crystallinity as the drift layer, leakage current and the like can be suppressed, and the reliability of the semiconductor device can be improved.

[0105] The substrate layer corresponds to the layers of the semiconductor composite substrate 6 excluding the single crystal layer 19, i.e., the substrate 11 and the first buffer layer 12. Therefore, for example, in the case of the semiconductor composite substrate 9 shown in Fig. 18, the substrate layer corresponds to the substrate 11, the fourth buffer layer 29, the third buffer layer 28, and the first buffer layer 12. In order to reduce the on-resistance of the semiconductor device, the substrate 11 may be thinned by grinding from the bottom surface.

[0106] The semiconductor composite substrates 1 to 9 according to the embodiments may be used to manufacture devices such as MEMS (Micro Electro Mechanical Systems), high electron mobility transistors (HEMTs), light emitting diodes (LEDs), laser diodes (LDs), and the like, in addition to the semiconductor devices described above.

[0107] Although the present disclosure has been described in detail above, it will be apparent to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure, as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and explanatory, and is not intended to be limiting of the present disclosure.

[0108] When the crystal plane exposed on the main surface 11A of the substrate 11 is a crystal plane different from the silicon (100) plane, for example, the (111) plane and the (100) plane, or when an off angle is formed from these crystal planes, an off angle is also formed on the surfaces of the layers growing as crystals on the substrate 11, for example, the first buffer layer 12 and the single crystal layer 13 of the semiconductor composite substrate 1 in Fig. 1. In terms of the characteristics of semiconductor devices, it is desirable that the surface of the single crystal layer 13 does not have an off angle, so it is desirable that the silicon (100) plane is exposed on the main surface 11A of the substrate 11.

[0109] In the first to fifth embodiments, the single crystal layer 13 is made of GaN, but the single crystal layer 13 may be made of SiC. A semiconductor composite substrate having a single crystal layer 13 made of SiC with good crystallinity can be manufactured at low cost and with a high yield.

[0110] In the sixth to ninth embodiments, the single crystal layer 19 is made of SiC, but the single crystal layer 19 may be made of GaN. A semiconductor composite substrate having a single crystal layer 19 made of GaN with good crystallinity can be manufactured at low cost and with a high yield.

[0111] The second buffer layer 14 and the substrate 11 having the laminated structure shown in the second to fifth embodiments may be applied to the semiconductor composite substrates 6 to 9 shown in the sixth to ninth embodiments.

[0112] The third buffer layer 28 and the fourth buffer layer 29 shown in the seventh to ninth embodiments may be applied to the semiconductor composite substrates 1 to 5 shown in the first to fifth embodiments.

[0113] (Note 1) The semiconductor composite substrates 1 to 9 each include a substrate 11 containing silicon and a silicon nitride (Si ３ N ４ The semiconductor device has a first buffer layer 12 made of silicon nitride (Si), and single crystal layers 13 and 19 made of compound semiconductors disposed on the first buffer layer 12. A silicon nitride (Si ３ N ４ By disposing the first buffer layer 12 made of silicon dioxide, the first buffer layer 12 can reduce the differences in lattice constant, thermal expansion coefficient, and mechanical properties between the silicon contained in the substrate 11 and the single-crystal layers 13 and 19. Therefore, it is possible to provide a semiconductor composite substrate in which a high-quality single-crystal layer with little warping, cracking, or crystal defects is formed on an inexpensive silicon-containing substrate.

[0114] (Supplementary Note 2) In the semiconductor composite substrates 1 to 9 described in Supplementary Note 1, the silicon (111) plane may be exposed on the main surface 11A of the substrate 11.

[0115] (Supplementary Note 3) In the semiconductor composite substrates 1 to 9 described in Supplementary Note 1 or 2, the first buffer layer 12 may be made of hexagonal silicon nitride.

[0116] (Supplementary Note 4) In the semiconductor composite substrates 1 to 9 according to any one of Supplementary Notes 1 to 3, the first buffer layer 12 may be made of β-phase silicon nitride.

[0117] (Supplementary Note 5) In the semiconductor composite substrates 1 to 9 according to any one of Supplementary Notes 1 to 4, the (0001) plane may be exposed on the main surface of the first buffer layer 12 facing the single crystal layers 13 and 19 .

[0118] (Supplementary Note 6) In the semiconductor composite substrates 1 to 5 according to any one of Supplementary Notes 1 to 5, the single crystal layer 13 may be made of gallium nitride (GaN).

[0119] (Appendix 7) In the semiconductor composite substrates 2 to 5 described in any of Appendices 1 to 6, a second buffer layer 14 made of aluminum nitride (AlN) may be interposed between the single crystal layer 13 and the first buffer layer 12. By interposing the second buffer layer 14, the lattice mismatch between the substrate 11 and the single crystal layer 13 can be further reduced.

[0120] (Appendix 8) In the semiconductor composite substrates 2 to 5 described in appendix 7, the (0001) plane may be exposed on the main surface 14A of the second buffer layer 14 facing the single crystal layer 13.

[0121] (Appendix 9) In the semiconductor composite substrates 3 to 5 described in any one of Appendices 1 to 8, the substrate 11 may have a single-crystal silicon layer 16 exposed on the main surface 11A of the substrate 11. A first buffer layer 12 having high crystallinity can be formed on the single-crystal silicon layer 16.

[0122] (Supplementary Note 10) In the semiconductor composite substrate 3 described in Supplementary Note 9, the substrate 11 may further include a support substrate 15 including polycrystalline silicon carbide (SiC) arranged on a main surface 16A of the single-crystal silicon layer 16 facing in the opposite direction to the main surface 11A of the substrate 11. Compared to the substrate 11 made of silicon, this can reduce the risk of cracking and warping of the semiconductor composite substrate.

[0123] (Supplementary Note 11) In the semiconductor composite substrate 4 described in Supplementary Note 9, the substrate 11 may further include a W bonding layer 18 containing tungsten (W) and disposed on a main surface 16A of the single-crystal silicon layer 16 facing in the opposite direction to the main surface 11A of the substrate 11, and a support substrate 17 containing silicon and disposed on the main surface 18A of the W bonding layer 18. The W bonding layer 18 can reduce the difference in linear expansion coefficient between the support substrate 17 and the single-crystal layer 13, thereby reducing the risk of cracking and warping of the substrate.

[0124] (Appendix 12) In the semiconductor composite substrate 5 described in Appendix 9, the substrate 11 may further include a W bonding layer 18 containing tungsten (W) and disposed on a main surface 16A of the single-crystal silicon layer 16 facing in the opposite direction to the main surface 11A of the substrate 11, and a support substrate 15 containing polycrystalline SiC and disposed on the main surface 18A of the W bonding layer 18.

[0125] (Supplementary Note 13) In the semiconductor composite substrates 6 to 9 according to any one of Supplementary Notes 1 to 5, the single crystal layer 19 may be made of silicon carbide (SiC).

[0126] (Appendix 14) In the semiconductor composite substrates 6 to 9 described in Appendix 13, the single crystal layer 19 may be made of hexagonal silicon carbide (SiC), and the (0001) plane may be exposed on the main surface 19A of the single crystal layer 19.

[0127] (Appendix 15) In the semiconductor composite substrates 6 to 9 described in Appendix 13, the single crystal layer 19 may be made of cubic silicon carbide (SiC), and the (111) plane may be exposed on the main surface 19A of the single crystal layer 19.

[0128] (Appendix 16) In the semiconductor composite substrate 7 or 9 according to any one of Appendices 13 to 15, a third buffer layer 28 containing platinum (Pt) may be interposed between the first buffer layer 12 and the substrate 11. The third buffer layer 28 can relieve thermal stress and reduce the risk of cracking and warping of the semiconductor composite substrate.

[0129] (Appendix 17) In the semiconductor composite substrate 8 or 9 described in any one of Appendices 13 to 15, a fourth buffer layer 29 containing at least one of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2) may be interposed between the first buffer layer 12 and the substrate 11. Thermal stress can be alleviated by utilizing phase transformation, thereby reducing the risk of cracking and warping of the semiconductor composite substrate.

[0130] (Supplementary Note 18) In the semiconductor composite substrates 1 to 9 described in any one of Supplementary Notes 1 to 17, the lattice mismatch between the substrate 11 and the first buffer layer 12 due to least common multiple matching may be smaller than the lattice mismatch between the substrate 11 and the single-crystal layers 13 and 19. Silicon nitride (Si ３ N ４ By providing the first buffer layer 12 made of silicon carbide, the first buffer layer 12 can reduce the lattice mismatch between the silicon contained in the substrate 11 and the single crystal layers 13 and 19 .

[0131] (Supplementary Note 19) Semiconductor devices 20, 30, and 50 are semiconductor devices using the semiconductor composite substrates 1 to 9 according to any one of Supplementary Notes 1 to 18, and the single crystal layers 13 and 19 of the semiconductor composite substrates 1 to 9 serve as drift layers. By using the single crystal layers 13 and 19 with good crystallinity as drift layers, it is possible to suppress leakage current and improve the reliability of the semiconductor device.

[0132] (Supplementary Note 20) The semiconductor device according to Supplementary Note 19 may constitute at least one of a Schottky barrier diode, a MOS field effect transistor, and a planar MOSFET.

[0133] (Note 21) The method for manufacturing the semiconductor composite substrates 1 to 9 includes the steps of: preparing a substrate 11 containing silicon; depositing silicon nitride (Si ３ N ４ The method includes a step S02 of forming a first buffer layer 12 made of a compound semiconductor, and a step S03 of forming single crystal layers 13, 19 made of a compound semiconductor on the first buffer layer 12. The first buffer layer 12 can reduce the differences in lattice constant, thermal expansion coefficient, and mechanical properties between the silicon contained in the substrate 11 and the single crystal layers 13, 19. Therefore, a high-quality single crystal layer with little warping, cracking, or crystal defects can be formed on a substrate containing inexpensive silicon.

[0134] (Appendix 22) In the method for manufacturing the semiconductor composite substrates 1 to 9 described in appendix 21, the first buffer layer 12 may be epitaxially grown using a thermal nitridation method.

[0135] (Appendix 23) In the method for manufacturing semiconductor composite substrates 1 to 9 described in appendix 21, a first buffer layer may be epitaxially grown on the main surface 11A of the substrate 11.

[0136] (Appendix 24) In the method for manufacturing the semiconductor composite substrate 1 to 9 according to any one of Appendices 21 to 23, the single crystal layer 13 may be epitaxially grown on the first buffer layer 12.

[0137] (Appendix 25) In the method for manufacturing semiconductor composite substrates 1 to 9 described in any one of Appendices 21 to 24, step S01 of preparing a silicon-containing substrate 11 may include step S11 of preparing a support substrate 15 and a single-crystal silicon layer 16 containing polycrystalline SiC, and step S12 of bonding the support substrate 15 and the single-crystal silicon layer 16 by room-temperature bonding.

[0138] (Appendix 26) In the method for manufacturing semiconductor composite substrates 1 to 9 according to any one of Appendices 21 to 24, step S01 of preparing a silicon-containing substrate 11 may include step S11 of preparing support substrates 15, 17 and a single-crystal silicon layer 16, and step S13 of bonding the support substrates 15, 17 and the single-crystal silicon layer 16 together using a W bonding layer 18 containing tungsten (W).

[0139] 1 to 9...Semiconductor composite substrate, 11...Substrate, 12...First buffer layer, 13, 19...Single crystal layer, 14...Second buffer layer, 15, 17...Support substrate, 16...Single crystal silicon layer, 17...Support substrate, 18...W junction layer, 20...SiC-SBD (semiconductor device), 28...Third buffer layer, 29...Fourth buffer layer, 30...SiC trench gate type MOSFET (semiconductor device), 50...SiC planar gate type MOSFET (semiconductor device)

Claims

1. A semiconductor composite substrate comprising: a substrate containing silicon; a first buffer layer made of silicon nitride disposed on a principal surface of the substrate; and a single crystal layer made of a compound semiconductor disposed on the first buffer layer.

2. The semiconductor composite substrate according to claim 1, wherein the silicon (111) plane is exposed on the main surface of said substrate.

3. The semiconductor composite substrate according to claim 1 or 2, wherein said first buffer layer is made of hexagonal silicon nitride.

4. The semiconductor composite substrate according to any one of claims 1 to 3, wherein the first buffer layer is made of β-phase silicon nitride.

5. The semiconductor composite substrate according to any one of claims 1 to 4, wherein the (0001) plane is exposed on the main surface of said first buffer layer facing said single crystal layer.

6. The semiconductor composite substrate according to any one of claims 1 to 5, wherein said single crystal layer is made of gallium nitride.

7. The semiconductor composite substrate according to any one of claims 1 to 6, wherein a second buffer layer made of aluminum nitride is interposed between said single crystal layer and said first buffer layer.

8. The semiconductor composite substrate according to claim 7, wherein the (0001) plane is exposed on the main surface of said second buffer layer facing said single crystal layer.

9. The semiconductor composite substrate according to any one of claims 1 to 8, wherein the substrate comprises: a single crystal silicon layer exposed on a main surface of the substrate; 10. The semiconductor composite substrate according to claim 9, wherein the substrate further comprises: a support substrate including polycrystalline silicon carbide disposed on a main surface of the single crystal silicon layer facing in a direction opposite to the main surface of the substrate.

11. The semiconductor composite substrate according to claim 9, wherein the substrate further comprises: a W bonding layer containing tungsten disposed on a main surface of the single-crystal silicon layer facing in a direction opposite to the main surface of the substrate; and a support substrate containing silicon disposed on the main surface of the W bonding layer.

12. The semiconductor composite substrate according to claim 9, wherein the substrate further comprises: a W bonding layer containing tungsten disposed on a main surface of the single-crystal silicon layer facing in a direction opposite to the main surface of the substrate; and a support substrate containing polycrystalline SiC disposed on the main surface of the W bonding layer.

13. The semiconductor composite substrate according to any one of claims 1 to 5, wherein the single crystal layer is made of silicon carbide.

14. The semiconductor composite substrate according to claim 13, wherein the single crystal layer is made of hexagonal silicon carbide, and the (0001) plane is exposed on the main surface of the single crystal layer.

15. The semiconductor composite substrate according to claim 13, wherein the single crystal layer is made of cubic silicon carbide, and the (111) plane is exposed on the main surface of the single crystal layer.

16. The semiconductor composite substrate according to any one of claims 13 to 15, wherein a third buffer layer containing platinum is interposed between the first buffer layer and the substrate.

17. The semiconductor composite substrate according to any one of claims 13 to 16, wherein a fourth buffer layer containing at least one of hafnium dioxide and zirconium dioxide is interposed between the first buffer layer and the substrate.

18. A semiconductor device using the semiconductor composite substrate according to any one of claims 1 to 17, wherein the single crystal layer serves as a drift layer.

19. The semiconductor device according to claim 18, which constitutes at least one of a Schottky barrier diode, a MOS field effect transistor, and a planar MOSFET.

20. A method for manufacturing a semiconductor composite substrate, comprising: a step of preparing a substrate containing silicon; a step of forming a first buffer layer made of silicon nitride on a main surface of the substrate; and a step of forming a single crystal layer made of a compound semiconductor on the first buffer layer.

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