Processed wafer and method for manufacturing semiconductor device

Abstract

The present invention comprises: forming an alignment mark (110) and a base insulating film (120) on a dicing line (DL); disposing an interlayer insulating film (22) and a resist (130); forming an opening portion (131) for a contact hole in the resist (130), and forming an opening portion (132) for position measurement in a portion located on the base insulating film (120); determining processing accuracy on the basis of the alignment mark (110) and the opening portion (132) for position measurement; forming a contact hole (23) in the interlayer insulating film (22); forming a metal film (310) so as to form a metal silicide layer (31), and disposing an electrode (30) on the metal silicide layer (31); and patterning the electrode (30) that is disposed in a device formation region (1a) while removing the electrode (30) that is disposed on the dicing line (DL).

Description

Processed wafer and semiconductor device manufacturing method CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2024-118770, filed on July 24, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a processed wafer and a method for manufacturing a semiconductor device.

[0003] Conventionally, a semiconductor device manufacturing method has been proposed in which a semiconductor wafer having multiple device formation regions defined by dicing lines is prepared, desired semiconductor elements are formed in the device formation regions to form a processed wafer, and then the processed wafer is divided along the dicing lines to manufacture multiple semiconductor devices (see, for example, Patent Document 1). Specifically, in this semiconductor device manufacturing method, a silicon-containing semiconductor wafer is prepared. Then, in this semiconductor device manufacturing method, after the semiconductor elements are formed in the device formation regions, an interlayer insulating film is disposed on one side of the semiconductor wafer, and contact holes are formed in the interlayer insulating film to expose predetermined portions of the semiconductor elements. The contact holes are formed by disposing a resist, patterning the resist using photolithography, and then performing etching or the like using the resist as a mask to form the contact holes.

[0004] Next, in this semiconductor device manufacturing method, a metal film is disposed on the portion exposed through the contact hole, and the metal film is subjected to a silicidation reaction with the semiconductor wafer to form a metal silicide layer. After that, in this semiconductor device manufacturing method, the unreacted metal film that did not undergo the silicidation reaction is removed, and an electrode is formed on the metal silicide layer to form a processed wafer.

[0005] In addition, in this semiconductor device manufacturing method, an insulating film is disposed on the dicing line before disposing a metal film for forming the metal silicide layer, so that a metal silicide layer is less likely to form on the dicing line. As a result, when unreacted metal film that has not undergone the silicide reaction is removed, the metal film on the dicing line is also removed at the same time, preventing the metal film from remaining on one side of the dicing line. Therefore, when a dicing blade or the like is used to divide the device formation region from one side of the processed wafer along the dicing line, it is possible to prevent the generation of metal chips and the generation of cracks originating from the metal.

[0006] Japanese Patent Application Laid-Open No. 2018-6443

[0007] The present inventors have been studying how to determine the processing accuracy of photolithography so as to suppress variations in characteristics. Even when determining the processing accuracy of photolithography in this way, it is desirable to be able to suppress the metal film from remaining on the dicing line on one side of the processed wafer, thereby suppressing the generation of metal debris during dicing and the generation of cracks originating from the metal film.

[0008] An object of the present disclosure is to provide a processed wafer and a method for manufacturing a semiconductor device that can suppress the generation of metal debris during dicing and the occurrence of cracks originating from the metal film.

[0009] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device includes: preparing a semiconductor wafer having one surface and including silicon, in which a plurality of device formation regions are partitioned by dicing lines; forming alignment marks on one surface side of the dicing lines; forming an underlying insulating film on one surface side of the dicing lines after forming the alignment marks; forming an interlayer insulating film in the device formation regions and the dicing lines after forming the underlying insulating film; disposing a resist on the interlayer insulating film; performing photolithography on the resist to form openings for contact holes in portions located in the device formation regions and to form openings for position measurement in portions located on the dicing lines that are located on the underlying insulating film; The photolithography processing accuracy is determined based on the position measurement opening, and after it is determined that the photolithography processing accuracy is normal, a resist is used as a mask to expose a part of the semiconductor wafer in a portion of the interlayer insulating film located in the device formation region, and a contact hole connecting to the contact hole opening is formed. After removing the resist, a metal film is formed on the semiconductor wafer exposed from the interlayer insulating film, a heat treatment is performed to cause a silicidation reaction of the metal film to form a metal silicide layer, the unreacted metal film is removed, electrodes are arranged on the metal silicide layer, the electrodes arranged on the device formation region are patterned while removing the electrodes arranged on the dicing lines, and division is performed along the dicing lines.

[0010] According to this method, since the processing accuracy is determined, variations in the characteristics of the manufactured semiconductor device can be suppressed. Furthermore, the position measurement opening used when determining the processing accuracy is formed in a portion located on the underlying insulating film. Therefore, even if the portion of the interlayer insulating film exposed through the position measurement opening is dug down when forming a contact hole, the underlying insulating film can prevent the semiconductor wafer from being exposed. Therefore, when forming a metal silicide layer, the metal silicide layer can be prevented from being formed on the dicing line, and the metal film can be prevented from remaining on the dicing line. This prevents the generation of metal debris during dicing and the generation of cracks originating from the metal film.

[0011] According to another aspect of the present disclosure, a processed wafer comprises: a semiconductor wafer having one surface and containing silicon, wherein a plurality of device formation regions are partitioned by dicing lines; alignment marks formed on one side of the dicing lines; an underlying insulating film formed on one side of the dicing lines; an interlayer insulating film formed in the device formation regions and the dicing lines, the interlayer insulating film having contact holes formed therein to expose the semiconductor wafer in the portions located in the device formation regions and the dicing lines, and having openings formed therein that expose the underlying insulating film in the portions located in the dicing lines and have bottoms made of the underlying insulating film; a metal silicide layer formed in the portions of the semiconductor wafer exposed from the interlayer insulating film; and an electrode arranged on the metal silicide layer, wherein the metal silicide layer and the electrode are arranged only in the device formation regions.

[0012] According to this, since the metal silicide layer and the electrodes are disposed only in the device formation region, it is possible to suppress the generation of metal chips during dicing and the occurrence of cracks originating from the metal film.

[0013] 5A is a plan view of a semiconductor device in a first embodiment. FIG. 5B is a cross-sectional view of the semiconductor device taken along line III-III in FIG. 1. FIG. 5C is a cross-sectional view of the semiconductor device taken along line III-III in FIG. 5I. FIG. 5D is a cross-sectional view of the semiconductor device taken along line II-II in FIG. 5A. FIG. 5B is a cross-sectional view of the semiconductor device taken along line III-III in FIG. 5C. FIG. 5D is a cross-sectional view of the semiconductor device taken along line III-III in FIG. 5E. FIG. 5F is a cross-sectional view of the semiconductor device taken along line III-III in FIG. 5G. FIG. 5H is a cross-sectional view of the semiconductor device taken along line III-III in FIG. 5I. FIG. 5A is a plan view of the dicing line of FIG. 5B. FIG. 5D is a cross-sectional view of the dicing line of FIG. 5D.

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0015] First Embodiment A first embodiment will be described with reference to the drawings. First, the configuration of a semiconductor device 1 obtained by a manufacturing method of the semiconductor device 1 according to the present embodiment will be described. Note that the following description will be given taking as an example a semiconductor device 1 in which a MOSFET with a trench gate structure is formed. MOSFET is an abbreviation for metal oxide semiconductor field effect transistor.

[0016] 1, the semiconductor device 1 has a rectangular planar shape and includes a cell region Ra including an inner edge region in the center and an outer peripheral region Rb surrounding the cell region Ra. Pad portions 2 and the like connected to gate electrodes 16 and the like, which will be described later, are arranged in the outer peripheral region Rb.

[0017] 2 and 3, the semiconductor device 1 has one surface 10a and another surface 10b, and is configured using a semiconductor substrate 10 such as a silicon substrate containing silicon or a silicon carbide substrate. ＋ a n-type drain region 11 and a n-type impurity region 12 disposed on the drain region 11 and having a lower impurity concentration than the drain region 11; － In the cell region Ra, the semiconductor substrate 10 has a p-type drift layer 12. In addition, the semiconductor substrate 10 has a p-type base layer 13 arranged in a surface layer portion of the drift layer 12. The base layer 13 is also formed in the outer peripheral region Rb.

[0018] In the cell region Ra of the semiconductor substrate 10, trenches 14 are formed so as to penetrate the base layer 13 from the one surface 10a side to reach the drift layer 12, and the base layer 13 is separated into a plurality of parts by these trenches 14. Note that although only one trench 14 is shown in FIG. 2, in reality, a plurality of trenches 14 are formed in the cell region Ra.

[0019] Each trench 14 is filled with a gate insulating film 15 formed to cover the wall surface of the trench 14, and a gate electrode 16 made of polysilicon or the like formed on the gate insulating film 15. This forms a trench gate structure.

[0020] In the surface layer portion of the base layer 13, in the cell region Ra, ＋ A p-type source region 17 and a p-type source region 17 sandwiched between the source regions 17 ＋ The source region 17 has a higher impurity concentration than the drift layer 12, terminates in the base layer 13 formed in the cell region Ra, and is formed to contact the side surface of the trench 14. The contact region 18 has a higher impurity concentration than the base layer 13, and, like the source region 17, is formed to terminate in the base layer 13 formed in the cell region Ra.

[0021] More specifically, the source region 17 is structured to extend in a rod shape in the region between the trenches 14 along the longitudinal direction of the trench 14 so as to contact the side surface of the trench 14, and to terminate inside the tip of the trench 14. The contact region 18 is sandwiched between the two source regions 17 and extends in a rod shape along the longitudinal direction of the trench 14 (i.e., the longitudinal direction of the source region 17).

[0022] As shown in FIG. 3 , the trench 14 (i.e., the trench gate structure) of this embodiment is formed so as to extend from the cell region Ra to the peripheral region Rb. The source region 17 is formed so as to contact the side surface of the trench 14, but as described above, it is formed only in the cell region Ra and not in the peripheral region Rb. A field insulating film 21 is formed on one surface 10a of the semiconductor substrate 10 (i.e., on the surface of the base layer 13) at the longitudinal end of the trench 14 located in the peripheral region Rb. The field insulating film 21 is thicker than the gate insulating film 15 so as to be less susceptible to breakdown even when a high voltage is applied. The field insulating film 21 is made of a different material from the interlayer insulating film 22 (described later), e.g., an oxide film.

[0023] The gate insulating film 15 formed in the trench 14 is also extended to the outside of the trench 14 and is also formed on the field insulating film 21. Similarly, the gate electrode 16 is also extended to the outside of the trench 14 and is disposed on the field insulating film 21 with the gate insulating film 15 interposed therebetween. Although not described in detail, the gate electrode 16 extended to the outside of the trench 14 is used as a gate liner, and a portion of it is exposed from the interlayer insulating film 22 described later and is connected to a wiring portion disposed on the interlayer insulating film 22.

[0024] An interlayer insulating film 22 is formed on one surface 10a of the semiconductor substrate 10. Contact holes 23 are formed in the interlayer insulating film 22 to expose the source region 17 and the contact region 18. Although not shown, the interlayer insulating film 22 also has a contact hole formed therein to expose a portion of the gate electrode 16 extended to the outside of the trench 14 in a cross section different from that in FIG. 3 . The interlayer insulating film 22 in this embodiment is formed by stacking a first interlayer insulating film 22a made of NSG (abbreviation for non-doped silicate glass) or the like and a second interlayer insulating film 22b made of BPSG (abbreviation for borophosphosilicate glass) or the like.

[0025] An upper electrode 30 is formed on the interlayer insulating film 22 in the cell region Ra, and is electrically connected to the source region 17 and the contact region 18 through the contact hole 23. In this embodiment, the upper electrode 30 can also be referred to as a first electrode.

[0026] Specifically, a metal silicide layer 31 containing a metal such as Ni (nickel) is formed on the source region 17 and the contact region 18 in the portions exposed from the contact hole 23. The metal silicide layer 31 serves to reduce the contact resistance between the source region 17 and the contact region 18 and the upper electrode 30. The metal silicide layer is not limited to one containing Ni, and may be one containing a metal such as Ti.

[0027] The upper electrode 30 is connected to the source region 17 and the contact region 18 via a metal silicide layer 31. In this embodiment, the upper electrode 30 has a barrier metal 30a formed by stacking Ti (titanium) and TiN (titanium nitride), and a main portion 30b disposed on the barrier metal 30a and made of Al-Si or the like containing Al (aluminum) as a main component. The barrier metal 30a is also formed on the wall surface of the contact hole 23 and on the surface of the interlayer insulating film 22. The barrier metal 30a prevents Al constituting the upper electrode 30 from diffusing toward the semiconductor substrate 10 or the interlayer insulating film 22, and prevents Ni constituting the metal silicide layer 31 from diffusing toward the upper electrode 30.

[0028] 3, a wiring portion is also formed on the interlayer insulating film 22. The wiring portion is connected to the gate electrode 16 extended to the outside of the trench 14. Similar to the upper electrode 30, the wiring portion has a main portion 30b disposed on a barrier metal 30a. A metal silicide layer containing a metal such as Ti is formed between the barrier metal 30a and the gate electrode 16.

[0029] A lower electrode 32 electrically connected to the drain region 11 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 32 can also be called a second electrode.

[0030] A protective film 40 made of polyimide or the like is formed in the peripheral region Rb on the one surface 10a side of the semiconductor substrate 10. An opening 41 exposing the upper electrode 30 is formed in the protective film 40.

[0031] In the semiconductor device 1 of this embodiment, an n-channel inversion trench gate MOSFET is configured with this structure. Note that in this embodiment, the n-type can also be referred to as the first conductivity type, and the p-type can also be referred to as the second conductivity type.

[0032] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figure 4, Figures 5A to 5J, and Figures 6A to 6C. Note that the cross-sectional views of the device formation region 1a in Figures 5A to 5J correspond to Figure 2.

[0033] First, as shown in FIG. 4 , a semiconductor wafer 100 is prepared, in which multiple device formation regions 1a are partitioned by dicing lines DL. The device formation regions 1a are portions that are divided along the dicing lines DL to form the semiconductor substrate 10 and the semiconductor device 1. Although not specifically shown, fine alignment marks (i.e., AA marks) and pre-alignment marks (i.e., PA marks) are appropriately formed on the semiconductor wafer 100. The fine alignment marks are marks used in wafer auto-alignment, which aligns the center position and orientation of the orientation flat of the semiconductor wafer 100 in an exposure apparatus. The pre-alignment marks are marks used for pre-alignment in an exposure apparatus. Pre-alignment refers to calculating the feed offset of the semiconductor wafer 100 so that the fine alignment marks of the semiconductor wafer 100 fall within the supplementary range of the wafer auto-alignment of the exposure apparatus. Then, when performing the processes described below, the fine alignment marks and pre-alignment marks are appropriately used as needed.

[0034] Next, as shown in FIG. 5A, a recess 110 serving as an alignment mark is formed on the dicing line DL of the semiconductor wafer 100 from the one surface 100a side of the semiconductor wafer 100. In this embodiment, as shown in FIG. 6A, a flat frame-shaped recess 110 is formed on the dicing line DL as an alignment mark. For example, in this embodiment, if one direction in the surface direction of the semiconductor wafer 100 is defined as the X-axis direction, one direction in the surface direction that is perpendicular to the X-axis direction is defined as the Y-axis direction, and a direction perpendicular to the X-axis and Y-axis directions is defined as the Z-axis direction, recess 110 having lengths in the X-axis direction and the Y-axis direction of approximately 20 to 40 μm is formed. However, the size of recess 110 is not particularly limited as long as it is a size that can be recognized when determining the processing accuracy, which will be described later. Note that, for example, in FIG. 6A, the left-right direction on the paper surface is defined as the X-axis direction, and the up-down direction on the paper surface is defined as the Y-axis direction. The recess 110 is formed as a mark separate from the above-mentioned fine alignment mark and pre-alignment mark.

[0035] Next, as shown in FIG. 5B , the recess 110 is used as a reference for alignment as needed to form the base layer 13, source region 17, contact region 18, trench 14, etc. (details omitted). If the base layer 13, etc. is formed using an epitaxial layer, the base layer 13, etc. may be formed before forming the recess 110. Next, the trench 14 is used as a reference for alignment to form the base insulating film 120 along the dicing line DL. Specifically, an insulating film is deposited on the semiconductor wafer 100 by a CVD (short for Chemical Vapor Deposition) method or the like, and then patterned by wet etching or the like to form the base insulating film 120. Note that the insulating film constituting the base insulating film 120 is also disposed within the trench 14 and recess 110, but the insulating film disposed within the trench 14 and recess 110 is removed when the insulating film is patterned to form the base insulating film 120.

[0036] 6B , the base insulating film 120 has a rectangular planar shape and is disposed within the frame-shaped recess 110 in the normal direction to the surface 100 a. In this embodiment, the base insulating film 120 is formed so that the center of its planar shape coincides with the center of the frame-shaped recess 110. The base insulating film 120 is made of a material different from that of the interlayer insulating film 22. The base insulating film 120 is used as an etching stopper to prevent an opening 24 (described later) from reaching the semiconductor wafer 100 when dry etching is performed to form a contact hole 23 (described later), and has a thickness that prevents the opening 24 from reaching the semiconductor wafer 100.

[0037] The base insulating film 120 may be disposed within the recess 110 and may also be disposed from within the recess 110 to a portion outside the recess 110. In this embodiment, when the base insulating film 120 is formed, the field insulating film 21 disposed in the outer periphery region Rb is also formed at the same time in a cross section different from that in FIG. 5B . That is, in this embodiment, when the field insulating film 21 disposed in the outer periphery region Rb is formed, the base insulating film 120 is also formed in the dicing line DL.

[0038] 5C , using the trench 14 as a reference for alignment, the gate insulating film 15 and the gate electrode 16 are sequentially formed by CVD, patterning, or the like. Subsequently, the first interlayer insulating film 22a and the second interlayer insulating film 22b are sequentially disposed by CVD or the like to form the interlayer insulating film 22, and then a resist 130 is disposed on the interlayer insulating film 22. The thickness of the interlayer insulating film 22 is arbitrary, but it is preferable that the length h between the upper surface of the portion disposed on the base insulating film 120 and the lower surface located closest to the semiconductor wafer 100 (i.e., the height along the Z-axis) be 20 μm or less to prevent difficulty in achieving focus when determining the processing accuracy described below.

[0039] 5D , photolithography using an exposure device is performed to pattern the resist 130, forming contact hole openings 131 in the device formation region 1a and position measurement openings 132 in the dicing line DL. The contact hole openings 131 are for forming contact holes 23 that expose the source region 17 and the contact region 18. The position measurement openings 132 are for determining the processing accuracy of the photolithography. Although not specifically shown, an opening is also formed for forming a contact hole that exposes the gate electrode 16 extended outside the trench 14.

[0040] In this embodiment, the contact hole opening 131 and the position measurement opening 132 are formed in the same process. Furthermore, the position measurement opening 132 is formed on the underlying insulating film 120 at the dicing line DL, as shown in FIGS. 5D and 6C . For example, the position measurement opening 132 is formed with the center of the frame-shaped recess 110 (i.e., the center of the underlying insulating film 120) as its target position. After the position measurement opening 132 is formed, the position measurement opening 132 may be used as a new fine alignment mark or a new pre-alignment mark.

[0041] Thereafter, the processing accuracy of the photolithography is determined. In this embodiment, an overlay accuracy measuring device is used to determine the positions of the recess 110 and the position measurement opening 132, and the processing accuracy of the photolithography is determined. Specifically, first, the positions of the recess 110 and the position measurement opening 132 are determined using the overlay accuracy measuring device. Then, in the length in the X-axis direction between the side surface of the position measurement opening 132 and the inner surface of the recess 110, the length extending from the position measurement opening 132 in one direction in the X-axis direction is defined as a first X-axis length A, and the length extending from the position measurement opening 132 in the other direction in the X-axis direction is defined as a second X-axis length B, and the amount of positional deviation in the X-axis direction is calculated by (B - A) / 2. Furthermore, in the length in the Y-axis direction between the side surface of the position measurement opening 132 and the inner surface of the recess 110, the length extending from the position measurement opening 132 in one direction in the Y-axis direction is defined as the first Y-axis length C, and the length extending from the position measurement opening 132 in the other direction in the Y-axis direction is defined as the second Y-axis length D, and the positional deviation in the Y-axis direction is calculated as (D-C) / 2.

[0042] The calculated amount of misalignment in the X-axis direction is then compared with a predetermined X-axis threshold range, and if the amount of misalignment in the X-axis direction is within the X-axis threshold range, it is determined that the photolithography was performed normally. On the other hand, if the amount of misalignment in the X-axis direction is not within the X-axis threshold range, it is determined that the photolithography was not performed normally. In other words, if the amount of misalignment in the X-axis direction is not within the X-axis threshold range, it is determined that the misalignment in the photolithography was large and that the photolithography was not performed appropriately.

[0043] Similarly, the calculated misalignment amount in the Y-axis direction is compared with a predetermined Y-axis threshold range, and if the misalignment amount in the Y-axis direction is within the Y-axis threshold range, it is determined that the photolithography was performed normally. On the other hand, if the misalignment amount in the Y-axis direction is not within the Y-axis threshold range, it is determined that the photolithography was not performed normally. In other words, if the misalignment amount in the Y-axis direction is not within the Y-axis threshold range, it is determined that the misalignment in the photolithography was large and the photolithography was not performed appropriately.

[0044] If the amount of misalignment in the X-axis direction is not within the X-axis threshold range or if the amount of misalignment in the Y-axis direction is not within the Y-axis threshold range, continuing the manufacturing process as is is likely to result in manufacturing semiconductor devices 1 with large variations in characteristics. For this reason, in this embodiment, the resist 130 is stripped by chemical cleaning or the like, new resist 130 is placed, and the process of FIG. 5D is performed again.

[0045] On the other hand, if it is determined that the misalignment amount in the X-axis direction is within the X-axis threshold range and that the misalignment amount in the Y-axis direction is within the Y-axis threshold range, dry etching is performed using resist 130 as a mask to form contact holes 23 in the device formation region 1a, exposing source regions 17 and contact regions 18, as shown in FIG. 5E . At this time, the dicing line DL is also similarly etched to form openings 24 in the interlayer insulating film 22 that are exposed through the position measurement openings 132. However, because the position measurement openings 132 are formed on the underlying insulating film 120, the underlying insulating film 120 acts as an etching stopper, preventing the openings 24 from being dug down to the first surface 100a of the semiconductor wafer 100. In other words, the bottom surface of the openings 24 is formed by the underlying insulating film 120. Therefore, the dicing line DL prevents the first surface 100a of the semiconductor wafer 100 from being exposed through the openings 24. In addition, since the base insulating film 120 serves as an etching stopper for the opening 24 , it can be said that it is made of a material that is more difficult to etch than the interlayer insulating film 22 when forming the contact hole 23 .

[0046] 5F , after the resist 130 is removed by chemical cleaning or the like, a metal film 310 for forming a metal silicide layer 31 is disposed on the semiconductor wafer 100 exposed from the contact holes 23. In this embodiment, the metal film 310 made of Ni is disposed by, for example, sputtering. Note that, since the metal film 310 is disposed by sputtering, it is formed not only on the semiconductor wafer 100 exposed from the contact holes 23 but also on the interlayer insulating film 22. Furthermore, the metal film 310 is formed on the dicing line DL as well as on the device formation region 1 a.

[0047] 5G, a heat treatment is performed at about 600 to 800° C. to cause a silicidation reaction between the metal (i.e., Ni) of the metal film 310 and the silicon of the semiconductor wafer 100, thereby forming a metal silicide layer 31 in the device formation region 1a. Specifically, the metal silicide layer 31 is formed in the portions of the source region 17 and the contact region 18 that are exposed from the interlayer insulating film 22.

[0048] At this time, the metal film 310 is also disposed within the openings 24 in the dicing lines DL, but the openings 24 do not reach the one surface 100a of the semiconductor wafer 100. Therefore, in the dicing lines DL, the entire metal film 310 is out of contact with the semiconductor wafer 100, making it difficult to form the metal silicide layer 31. In other words, in this embodiment, the metal silicide layer 31 can be formed in the device formation region 1a in a self-aligned manner.

[0049] 5H, unreacted portions of the metal film 310 that have not undergone the silicidation reaction are removed by chemical cleaning or wet etching, thereby removing the entire metal film 310 above the dicing line DL.

[0050] 5I, a Ti film and a TiN film are sequentially formed on the metal silicide layer 31 by sputtering or the like to form a barrier metal 30a. In this process, the barrier metal 30a is formed not only on the metal silicide layer 31 but also on the interlayer insulating film 22. The barrier metal 30a is also formed on the dicing line DL in addition to the device formation region 1a.

[0051] Next, a heat treatment is performed to densify the barrier metal 30a. As a result, although not shown, a metal silicide layer is formed in the portion in contact with the gate electrode 16 drawn out of the trench 14 by reacting Ti with silicon contained in the gate electrode 16. Next, a main portion 30b made of AlSi or the like is formed on the barrier metal 30a by a method such as sputtering.

[0052] 5J, the main portion 30b and the barrier metal 30a are patterned by wet etching, dry etching, or the like using a mask (not shown) to form the upper electrode 30, thereby constructing the processed wafer 200. In this embodiment, the main portion 30b is patterned by wet etching, and the barrier metal 30a is patterned by dry etching. Note that the barrier metal 30a and the main portion 30b arranged on the dicing line DL are arranged on the interlayer insulating film 22, which makes it difficult for a metal silicide layer to form thereon, and therefore are simultaneously removed by the etching that forms the upper electrode 30.

[0053] Thereafter, although not shown, lower electrodes 32 and the like are formed on the other surface of the processed wafer 200 opposite the first surface 100a, and the device formation regions 1a are divided along the dicing lines DL from the first surface 100a of the processed wafer 200, thereby manufacturing the above-mentioned semiconductor device 1. At this time, in this embodiment, no metal film is disposed along the dicing lines DL on the first surface 100a of the processed wafer 200. This prevents metal chips from being generated during dicing and prevents cracks from occurring starting from the metal film.

[0054] According to the embodiment described above, since processing accuracy is determined, variations in the characteristics of the manufactured semiconductor device 1 can be suppressed. Furthermore, the position measurement opening 132 used when determining processing accuracy is formed in a portion located above the underlying insulating film 120. Therefore, even if the portion of the interlayer insulating film 22 exposed through the position measurement opening 132 is dug down during the formation of the contact hole 23, the underlying insulating film 120 can prevent the semiconductor wafer 100 from being exposed. Therefore, during the formation of the metal silicide layer 31, the formation of the metal silicide layer on the dicing line DL can be suppressed, and the metal film can be prevented from remaining on the dicing line. This suppresses the generation of metal debris during dicing and the generation of cracks originating from the metal film.

[0055] (1) In this embodiment, a frame-shaped recess 110 is formed as an alignment mark, and the base insulating film 120 is formed so as to be located inside the recess 110. Therefore, compared to when the base insulating film 120 is formed outside the recess 110, alignment can be easily performed when forming the base insulating film 120.

[0056] (2) In this embodiment, when the base insulating film 120 is formed on the dicing line DL, the base insulating film 120 is formed simultaneously with the field insulating film 21 configured in the semiconductor device 1. This eliminates the need for a process for forming only the base insulating film 120, thereby preventing an increase in the number of manufacturing processes.

[0057] (3) In this embodiment, after the position-measuring opening 132 is formed, the position-measuring opening 132 can be used as a new fine alignment mark or pre-alignment mark. When the position-measuring opening 132 is used as a fine alignment mark or pre-alignment mark, the position-measuring opening 132 is formed on the underlying insulating film 120, and therefore less material is placed on the mark than when the fine alignment mark or pre-alignment mark is first formed on the semiconductor wafer 100. Therefore, when the position-measuring opening 132 is used as a fine alignment mark or pre-alignment mark, the visibility of the mark is improved compared to when the fine alignment mark or pre-alignment mark is first formed on the semiconductor wafer 100, which makes it easier to simplify the manufacturing process and reduce manufacturing errors.

[0058] (Other Embodiments) While the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0059] For example, in the first embodiment, a method for manufacturing a semiconductor device 1 having a trench gate structure has been described. However, the method for manufacturing a semiconductor device 1 in the first embodiment can also be applied to a method for manufacturing a semiconductor device 1 having a planar gate structure. Furthermore, the semiconductor element formed in the semiconductor device 1 may be a diode element or the like.

[0060] In the first embodiment, the recess 110 serving as the alignment mark may be annular or polygonal rather than frame-shaped. The recess 110 may also be linear rather than frame-shaped. Furthermore, instead of the recess 110, a protrusion may be formed as the alignment mark.

[0061] Furthermore, in the first embodiment, the upper electrode 30 may not include the barrier metal 30a and may be composed of only the main portion 30b.

Claims

1. A method for manufacturing a semiconductor device, comprising: preparing a semiconductor wafer (100) having one surface (100a) and including silicon, with a plurality of device formation regions (1a) partitioned by dicing lines (DL); forming an alignment mark (110) on one surface of the dicing line; after forming the alignment mark, forming an underlying insulating film (120) on one surface of the dicing line; after forming the underlying insulating film, forming an interlayer insulating film (22) in the device formation region and the dicing line; arranging a resist (130) on the interlayer insulating film; performing photolithography on the resist to form a contact hole opening (131) in a portion located in the device formation region and to form a position measurement opening (132) in a portion located on the dicing line and on the underlying insulating film; determining the processing accuracy of the photolithography based on the alignment mark and the position measurement opening; a contact hole (23) connected to the contact hole opening, using the resist as a mask to expose a portion of the semiconductor wafer in a portion of the interlayer insulating film located in the device formation region after it has been determined that the photolithography processing accuracy is normal; removing the resist and then forming a metal film (310) on the semiconductor wafer exposed from the interlayer insulating film; performing a heat treatment to cause a silicidation reaction of the metal film to form a metal silicide layer (31); removing unreacted metal film; arranging electrodes (30) on the metal silicide layer; patterning the electrodes located in the device formation region while removing the electrodes located on the dicing lines; and dividing the semiconductor wafer along the dicing lines.

2. A method for manufacturing a semiconductor device as described in claim 1, wherein forming the alignment mark forms a frame-shaped alignment mark, and forming the base insulating film forms the base insulating film inside the alignment mark in the normal direction to the one surface.

3. A method for manufacturing a semiconductor device according to claim 1 or 2, wherein the formation of the base insulating film is carried out simultaneously with the formation of a field insulating film (21) in the device formation region of one surface of the semiconductor wafer.

4. A processed wafer comprising: a semiconductor wafer (100) having one surface (100a) and containing silicon, with a plurality of device formation regions (1a) partitioned by dicing lines; alignment marks (110) formed on one surface of the dicing lines; an underlying insulating film (120) formed on one surface of the dicing lines; an interlayer insulating film (22) formed in the device formation regions and the dicing lines, with contact holes (23) formed to expose the semiconductor wafer in the portions located in the device formation regions, and with openings (24) formed with the underlying insulating film at the portions located in the dicing lines, the openings having a bottom surface made of the underlying insulating film; a metal silicide layer (31) formed in the semiconductor wafer in the portions exposed from the interlayer insulating film; and an electrode (30) arranged on the metal silicide layer, wherein the metal silicide layer and the electrode are arranged only in the device formation regions.

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