Verification method of an integrated circuit

Abstract

A method and apparatus for verification of an integrated circuit are provided. The method comprises obtaining simulation results of a first netlist and a layout-extracted netlist comprising parasitic elements. These elements may include parasitic resistors, capacitors, lateral bipolar transistors, field-effect transistors, substrate or well resistances, thermal models, and mechanical stress distributions. Parasitic elements are selectively included in a second netlist based on estimated electrical disturbances derived from simulation data and on contextual factors such as node impedance, node sensitivity, circuit hierarchy, and mode of operation. The method further includes checking whether parasitic elements exceed maximum electrical ratings and enables selective extraction to reduce simulation complexity. The apparatus comprises systems and executable instructions for implementing the method, including parasitic selection, extraction, and rating verification.

Description

[0001] Verification Method of an Integrated Circuit

[0002] TECHNICAL FIELD

[0003] This disclosure presents a method for verifying an integrated circuit.

[0004] BACKGROUND ART

[0005] The problem this disclosure solves is how to effectively verify the impact of parasitic elements in an integrated circuit. By the term "integrated circuit," we understand an entire semiconductor chip, or a block of a semiconductor chip. Nowadays, a typical integrated circuit might contain thousands, millions, or even billions of elements sharing the same piece of semiconductor material and containing even a higher number of parasitic elements. These parasitic elements are not intentionally added by the designer but appear as side effects of the physical layout and manufacturing process. They include not only parasitic wiring capacitances and resistances but also complex effects such as parasitic bipolar transistors, parasitic field-effect transistors, substrate or well resistances, as well as thermally and mechanically induced parasitics.

[0006] The sheer number and diversity of these parasitic elements make top-level verification of an integrated circuit highly complex and expensive in terms of human labor and computational resources. At the same time, there is growing pressure on design teams to deliver first-time-right silicon under tight schedules, without costly redesign iterations. This results in a dramatic trade-off between verification cost and the level of coverage and assurance.

[0007] PRIOR ART AND NOVELTY

[0008] Parasitic extraction for IC layouts is a known practice. For example, US 7669152 Bl discloses efficient 3D Monte Carlo-based hierarchical extraction of resistive / capacitive parasitics, and US 2002013688 Al describes rule-based or field-solver approaches for layout parasitic modeling. Other works such as US 20190034574 Al focus on partitioning and fast post-layout simulation flows.

[0009] However, these approaches stop at generating a full parasitic netlist and do not incorporate simulation-driven selection of only performance-relevant parasitics. They also lack subsequent verification steps, such as checking maximum voltag e / curr ent ratings of parasitics. Moreover, none address dynamic sub-block operating modes, substrate / well modeling as linear interaction matrices, or stress effects extracted from layout or package.

[0010] In contrast, the present disclosure provides a coherent, feedback-driven verification method: beginning with schematic simulation, followed by layout-extracted parasitics, algorithmic selection of impactful elements (including bipolar FETs, substrate resistances, thermal and mechanical stress), and automatic rating checks. The method goes significantly beyond prior art by enabling mode-aware parasitic selection, matrix-based substrate modeling, and inclusion of mechanical stress in the netlist, all within an integrated flow optimized for accuracy and efficiency.

[0011] DISCLOSURE OF THE INVENTION

[0012] To tackle this challenge, this disclosure proposes a unified verification method that combines simulation results, layout-extracted parasitics, selection of critical parasitic elements, and maximum ratings checking into a single, coherent flow. Rather than treating these steps as isolated tasks, the method leverages their interplay to improve verification efficiency and quality.

[0013] The method begins by generating simulation results of the integrated circuit without parasitics. These results are then combined with a layout-extracted netlist comprising parasitic elements. The method evaluates which parasitics are likely to affect performance — based on voltage or current disturbances, node impedance, sensitivity, or hierarchy — and selects only those for inclusion in a second round of simulation.

[0014] Additionally, the method takes into account the mode of operation of sub-blocks within the integrated circuit. For example, if a sub-block is in power-down or sleep mode, the influence of parasitic elements connected to it may be negligible. Conversely, if the sub-block is in an active mode, such as turn-on or high-gain mode, the same parasitic elements may become highly relevant. By identifying the operating mode of each sub-block from the first simulation, the method can refine the parasitic selection process and further reduce unnecessary simulation effort.

[0015] This process also allows for automatic checking of maximum allowable ratings (e.g., voltage or current) for parasitic elements and guides the selective extraction of parasitic lateral bipolar and field-effect transistors.

[0016] Furthermore, thermal and mechanical parasitics may also be incorporated. Athermal model may be extracted to estimate temperature distributions across the integrated circuit, either in steady-state (based on power dissipation) or transient conditions (based on short-term heat impulses). Similarly, mechanical stress distributions may be extracted and included in the netlist to enable verification of stress-related circuit degradation. Such mechanical stress models may be derived from layout and / or package-level simulations, and the resulting information can be used to affect the content of the second netlist, ensuring that stress-sensitive effects are included in the verification.

[0017] In addition, substrate or well resistance may be modeled as a linear relationship between currents and voltages at various contact terminals. Since the substrate or well behaves as a 2D or 3D conductive medium, the relationship between the current injected into each terminal and the resulting voltage can be expressed as a linear system defined by a matrix of resistive interactions. When relevant, such a model can be extracted based on layout geometry and material parameters and included in the circuit simulation. This enables better understanding and prediction of substrate coupling effects.

[0018] By integrating simulation, extraction, selection, and maximum ratings verification into one feedback loop, the method enables accurate and scalable parasitic-aware verification of complex integrated circuits.

[0019] The invention is defined by the appended claims, which form an integral part of this disclosure.

[0020] Advantages of the Proposed Solution

[0021] • Automation: The method can be largely automated and leverages simulation setups that are already available.

[0022] • Reduced Simulation Effort: Only a small subset of parasitics is retained, minimizing simulation overhead.

[0023] • Broad Coverage: Different types of parasitic effects (electrical, thermal, mechanical) are considered together, improving verification quality.

[0024] • Scalability: The method is applicable at top-level or sub-block level, and accommodates hierarchical circuit design.

[0025] • Debugging Simplicity: In case of failure, fewer parasitic elements in the second simulation simplify root-cause analysis.

[0026] Industrial Applicability

[0027] The invention is applicable to the design and verification of analog and mixed-signal integrated circuits in industrial semiconductor flows.

[0028] BRIEF DESCRIPTION OF THE DRAWINGS

[0029] A further understanding of various aspects of the invention may be obtained by reference to the following detailed description in conjunction with the associated drawing, which is described briefly below.

[0030] Fig. 1 outlines a use-case of the verification method of an integrated circuit.

[0031] Fig. 2 outlines an embodiment of a method of extraction of parasitic elements from an integrated circuit.

[0032] Fig. 3 presents extraction of parasitic lateral bipolar transistors.

[0033] Fig. 4 presents a fragment of a schematic of an integrated circuit to illustrate the concept of selection of parasitic resistors.

[0034] Fig. 5 presents a fragment of a schematic of an integrated circuit to illustrate the concept of estimating effective node impedance.

[0035] Fig. 6 illustrates a concept of extraction of a parasitic field-effect transistor. DETAILED DESCRIPTION OF THE INVENTION

[0036] Fig. 1 outlines a use-case of the verification method of an integrated circuit. Databases are represented as ovals and information processing units are represented as rectangles. The database of the integrated circuit comprises a representation of the hierarchy of the integrated circuit comprising top-level blocks, their sub-blocks and elements such as transistors, capacitors, resistors, etc. Elements and blocks are connected by nodes. Different blocks might be represented by different views, like a schematic that presents the topology of the integrated circuit, a layout that presents physical implementation, or a functional representation in hardware description language. The netlister tool obtains the database of the integrated circuit, or part of the database of the integrated circuit and creates a netlist. Similarly, the layout extraction tool can also produce a netlist. The netlist comprises information about elements and nodes. The layout extraction tool is capable of extracting parasitic elements from the layout representation. The parasitic elements typically are: parasitic capacitors, parasitic resistors, parasitic field-effect transistors, or parasitic lateral bipolar transistors, or others. Normally, parasitic elements are unintentional elements and they result from physical implementation of the integrated circuit, like wiring of nodes, or sharing the same substrate by different diffusions, etc. Their impact must be taken into account to prevent malfunction of the integrated circuit. The first netlist might be generated based on a schematic view of the integrated circuit, or its sub-blocks, by the netlister tool. It can also be generated based on the layout view by the layout extraction tool. It can also be generated based on hardware description language, or a combination of schematic / layout / hardware description language. The first netlist comprises elements connected by nodes and typically doesn't include parasitic elements. The first netlist also includes information about stimuli to simulate specific scenarios and verify functionality. The circuit simulator obtains the first netlist and provides simulation results, typically comprising voltage waveforms of nodes and current waveforms of terminals of elements or blocks. The post-processing obtains simulation results, processes them, and verifies whether the integrated circuit meets its specifications. Traditionally, post-processing used to be performed by humans, but for complex integrated circuits and a higher number of iterations, it makes sense to automate the process and let the computer apply pass / fail criteria. The databases and information processing tools described so far are standard in any integrated circuit verification flow. The subject matter of this disclosure includes information processing tools such as selection of parasitic elements and checking maximum ratings of parasitic elements. The function of the tool for selection of parasitic elements is to short-list the parasitic elements from the layout-extracted netlist based on their relevance for circuit performance. It obtains the simulation results of the first netlist and the layout-extracted netlist with a set of parasitic elements and, based on that, estimates current or voltage disturbances caused by those parasitic elements. Only those parasitic elements whose impact on circuit performance seems significant are selected and added to a second netlist. The selection of parasitic elements is based on the estimation of voltage or current disturbance introduced by the parasitic element as well as the impedance of nodes to which the parasitic element is connected, sensitivity of the involved nodes, or whether a node is part of a top-level hierarchy. Finally, the second netlist is simulated by the circuit simulator and results are post-processed to check if the integrated circuit including parasitic elements still meets the required performance. The function of the tool for checking maximum ratings of parasitic elements is to make sure that parts of the integrated circuit represented by parasitic elements will not break down, get destroyed, or be overstressed during operation. Specifically, voltage ratings of closely spaced metal tracks, represented by parasitic capacitors, or closely spaced diffusions represented by parasitic lateral bipolar transistors can be verified, as well as current densities through parasitic wiring resistors.

[0037] Fig. 2 outlines an embodiment of a method for extracting parasitic elements from an integrated circuit. Data is represented as arrows, and information-processing units are represented as ovals. The database comprising the physical design of the integrated circuit contains the layout of the integrated circuit. This layout may be flat or may include a hierarchy of sub-blocks. The extraction of parasitic elements obtains information about the physical design from the database.

[0038] The extraction process includes units specialized in extracting different types of parasitic elements: parasitic wiring capacitors, parasitic wiring resistors, parasitic bipolar transistors, parasitic field-effect transistors, substrate / well resistances, a thermal model, and a mechanical stress model. Extraction of a particular type of parasitic element typically involves obtaining geometric information about physical structures and their position on the silicon chip, and based on that, calculating parameters for the respective parasitic element.

[0039] The result of extraction may be a list of parasitic elements to be added to the netlist or, in the case of the thermal or mechanical models, additional transient signals or modified properties of intended elements in the netlist. Parasitic wiring capacitors result from the physical implementation of nodes using polysilicon or metal layers. These nodes are separated by dielectric materials and thus form parasitic capacitors. Parasitic wiring resistors also arise from the physical implementation of nodes and represent the effective resistance of the poly or metal layers used.

[0040] Parasitic substrate / well resistance is the effective resistance between different terminals of the substrate or of p-type or n-type wells, which typically implement MOS transistor bulks. Often, such resistance cannot be modeled with a single resistor but must be represented as a 2D distributed resistance network. Normally, ICs are designed to minimize significant current flow through these substrate / well resistances. However, in some cases, these may share current paths with parasitic wiring resistors of supply nodes, making a combined model necessary to accurately capture circuit behavior.

[0041] Parasitic bipolar transistors of the npn or pnp type occur wherever two diffusions of the same type (n- or p-type) are placed within another diffusion of the opposite type. This structure forms a bipolar transistor. In a typical integrated circuit, many such parasitic transistors exist, but most are inactive because their base-emitter junctions are not forward-biased. However, forward-biasing can activate multiple parasitic B JTs, and the goal of this method is to identify and extract only those transistors whose effects may significantly impact circuit performance. To avoid extracting all possible combinations of diffusion pairs — which would lead to an overwhelming number of elements — simulation results are used to narrow down candidates. Only those diffusions where simulation data indicates a forward-biased base-emitter junction are considered for extraction.

[0042] Sometimes, a wire in the layout crosses npn or pnp regions, potentially forming a parasitic field-effect transistor. This is especially likely if the wire is in a lower metal layer, such as poly or metal 1, and the node it connects to is at a high voltage relative to the underlying regions (e.g., in power-management ICs). If sufficient gate-to- source or gate-to-bulk voltage is present, these parasitic transistors may conduct unwanted current.

[0043] The thermal model is generated using data from the physical design and packaging. It is used to predict effective temperatures of circuit elements, given the ambient temperature and power dissipation of the IC’s components. Similarly, the mechanical stress distribution is estimated using layout and packaging information. Mechanical stress can alter the parameters of IC elements subjected to such stress.

[0044] After extraction, respective selection units for parasitic wiring capacitors, wiring resistors, bipolar transistors, field-effect transistors, and substrate / well resistances decide which parasitics to include in the final netlist based on simulation results. These results — such as node voltages or terminal currents — can be used to estimate disturbances introduced by each parasitic element, in terms of voltage or current, and assess whether they are likely to affect circuit performance.

[0045] Typically, in an IC with at least thousands of elements, there is a comparable number of parasitic elements. In a well-designed circuit, only a few dozen parasitics may cause malfunction.

[0046] Therefore, if the selection process reduces the number of parasitics to a few hundred, it ensures that all relevant ones are included while keeping simulation effort manageable.

[0047] Some critical parasitic phenomena result from the combined effects of multiple types of parasitic elements. For example, supply coupling may arise from both parasitic wiring resistance and coupling capacitance. Another case is when a large current through parasitic substrate / well resistance induces a voltage drop that activates parasitic BJTs. To account for such cases, the method can be iterated: the parasitic selection may be based not on the original simulation of the schematic-only netlist, but on a netlist that already includes parasitic elements.

[0048] Fig. 3 presents a part of a layout of an integrated circuit comprising n-type diffusion regions (22), (23), (24), and (25) in a p-substrate (20). These diffusions may be n+ diffusions, n-wells, or deep-n-wells. This structure results in multiple parasitic lateral bipolar transistors of the npn type. In real ICs, the number of such diffusions can be very large, making the total number of possible npn or pnp parasitic transistors extremely high. On the other hand, it is not uncommon for such parasitic lateral bipolar transistors to unexpectedly affect IC performance. The strategy disclosed here is to extract only those parasitic lateral bipolar transistors that matter for performance. To achieve this, simulation results are used to identify which diodes become forward-biased during the first netlist simulation. For example, if the diode formed by diffusion (21) and the p-substrate (20) becomes forward-biased, the layout extraction tool will extract only those npn parasitic lateral bipolar transistors whose emitter is diffusion (21) and whose base is the p-substrate (20).

[0049] For each extracted parasitic bipolar transistor (25), (26), and (27), the tool assigns a beta parameter estimating how much of the emitter current reaches the collector. Transistor (25) represents a case where the emitter and collector face each other. In contrast, transistor (27) represents a case where the n-diffusions are spatially separated, and emitter-collector interaction is weaker. For lateral bipolar transistors where the emitter and collector face each other, the layout tool may also provide a pinch-off voltage rating, which can be checked by the maximum rating verification tool during simulation.

[0050] There are two types of parasitic lateral bipolar transistors: npn and pnp. Fig. 3 shows an npn example; the pnp case is analogous — for instance, p+ diffusions within an n-well can form parasitic pnp transistors.

[0051] Fig. 4 presents a fragment of a schematic of an integrated circuit in which elements (31), (32), and (33) are connected to the same node (30), which is physically realized using metallization. The associated parasitic resistors (34), (35), (36), and (37) represent the resistance of the metal implementation.

[0052] If the current waveforms at the terminals of elements (31), (32), and (33) are available from simulation results, this information — combined with the topology and values of parasitic resistors — can be used to estimate voltage differences between the terminals. Based on these estimates, the tool for parasitic selection may discard those resistors that do not significantly contribute to voltage differences at node (30).

[0053] Additionally, information about current density through each parasitic resistor can be used by the maximum rating checker to verify that current magnitudes are within safe limits for each resistor.

[0054] Fig. 5 presents a fragment of a schematic of an integrated circuit to illustrate the concept of estimating effective node impedance. Each element (41), (42), (43), or (44) can be represented by its effective impedance: Zl, Z2, Z3, and Z4. The effective impedance may be constant, as in the case of a resistor, or dependent on simulation results, as in the case of a transistor.

[0055] By representing the circuit as a graph of nodes connected by these impedances, the effective impedance of any node to ground can be estimated. For node (45), its impedance to ground is defined as the voltage change (AV) in response to the injection of an additional current (Al) by an ideal current source (46). This metric is useful in evaluating how sensitive a node is to disturbances caused by parasitics.

[0056] Fig. 6 illustrates a parasitic field-effect transistor. If wire (53) crosses two different n-doped regions (51) and (52), such a transistor can form, particularly if the wire is implemented using a poly-silicon or metal 1 layer that lies close to the silicon surface. The n-doped regions may be n-wells or n-diffusions.

[0057] In this structure, the n-doped regions (51) and (52) serve as the drain and source of the parasitic field-effect transistor (54), the wire (53) functions as the gate, and the p-doped region (50) acts as the bulk. The layout extraction tool can identify such structures and extract all relevant parasitic FETs.

[0058] The parasitic selection tool can then determine which of these extracted transistors have the potential to conduct significant current during circuit operation and therefore warrant inclusion in the verification netlist due to their potential performance impact.

Claims

1. Method of selection of parasitic elements for verification of an integrated circuit, the method comprising: obtaining simulation results of a first netlist of the integrated circuit, the simulation results comprising voltage waveforms of a plurality of nodes of the integrated circuit; obtaining a layout-extracted netlist, the layout-extracted netlist comprising a plurality of parasitic elements of the integrated circuit; for at least one of the parasitic elements, estimating currents at terminals of the parasitic element based on voltage waveforms of nodes connected to the terminals; determining whether the parasitic element will be included in a second netlist based on the magnitude of the estimated currents; and providing the second netlist of the integrated circuit, comprising the selected parasitic elements.

2. The method of Claim 1, further comprising: for a plurality of nodes, estimating impedances based on operating points of elements whose terminals are connected to the nodes; estimating voltage disturbance caused by at least one parasitic element by multiplying the estimated current at a terminal by the impedance of a node connected to the terminal; and determining whether the parasitic element will be included in the second netlist based on the magnitude of the estimated voltage disturbance.

3. Method of selection of parasitic elements for verification of an integrated circuit, the method comprising: obtaining simulation results of a first netlist of the integrated circuit, the simulation results comprising current waveforms at a plurality of terminals of elements of the integrated circuit; obtaining a layout-extracted netlist comprising a plurality of parasitic elements of the integrated circuit; for at least one node, estimating voltage differences between terminals of elements connected to the node based on the simulated current waveforms; determining whether a parasitic resistor connected to the node will be included in the second netlist based on the magnitude of the estimated voltage differences; and providing the second netlist comprising selected parasitic resistors.

4. The method of any one of Claims 1 to 3, further comprising: determining whether at least one node is a sensitive node based on the name of the node and names of blocks and terminals connected to the node; and determining whether a parasitic element connected to the sensitive node will be included in the second netlist based on node sensitivity.

5. The method of any one of Claims 1 to 4, further comprising: determining whether a node is a top-level node in the hierarchy of the integrated circuit; and determining whether a parasitic element connected to such a node will be included in the second netlist based on node hierarchy.

6. The method of any one of Claims 1 to 5, further comprising: obtaining mode-of-operation data for at least one sub-block from simulation of the first netlist; and selecting parasitic elements based on whether their terminals are connected to the sub-block and based on the mode of operation of that sub-block.

7. The method of any one of Claims 1 to 6, wherein the parasitic element is a parasitic capacitor.

8. The method of any one of Claims 1 to 6, wherein the parasitic element is a parasitic field-effect transistor.

9. The method of any one of Claims 1 to 6, wherein the parasitic element is a parasitic lateral bipolar transistor.

10. Method for extracting parasitic lateral bipolar transistors in an integrated circuit, the method comprising: obtaining simulation results of a first netlist comprising at least one current waveform of a diode element; obtaining a layout of the integrated circuit; for at least one diode element that is forward-biased during simulation, extracting at least one parasitic lateral bipolar transistor comprising emitter, base, and collector, wherein the emitter and base correspond to the terminals of the diode; and providing an extracted netlist comprising the parasitic lateral bipolar transistor.

11. The method of Claim 10, further comprising modeling a current gain (beta) of the parasitic lateral bipolar transistor based on the layout of the integrated circuit, wherein the beta is determined as a function of geometric proximity, orientation, or facing of the emitter and collector regions in the layout.

12. The method of Claim 10, further comprising modeling a pinch-off voltage of the extracted parasitic lateral bipolar transistor based on the layout of the integrated circuit.

13. The method of Claim 9, wherein at least one parasitic lateral bipolar transistor is extracted according to Claim 10, 11, or 12.

14. Method for extracting parasitic field-effect transistors in an integrated circuit, the method comprising: obtaining a layout of the integrated circuit; identifying wires that cross at least two n-doped regions separated by a p-doped region, wherein the n-doped regions belong to different nodes; extracting a parasitic field-effect transistor comprising a source (first n-doped region), a drain (second n-doped region), a gate (wire), and a bulk (p-doped region); and providing an extracted netlist including the parasitic field-effect transistor.

15. Method for extracting parasitic field-effect transistors in an integrated circuit, the method comprising:obtaining a layout of the integrated circuit; identifying wires that cross at least two p-doped regions separated by an n-doped region, wherein the p-doped regions belong to different nodes; extracting a parasitic field-effect transistor comprising a source (first p-doped region), a drain (second p-doped region), a gate (wire), and a bulk (n-doped region); and providing an extracted netlist including the parasitic field-effect transistor.

16. The method of any one of the previous Claims, further comprising modeling the substrate or well resistance as a linear relationship between currents and voltage differences across connected terminals.

17. The method of any one of the previous Claims, further comprising extracting a thermal model of the integrated circuit and providing an extracted netlist including the thermal model.

18. The method of Claim 17, wherein the thermal model comprises a steady-state mapping between power dissipation of at least one element of the integrated circuit and the temperature of a plurality of elements of the integrated circuit.

19. The method of Claim 17, wherein the thermal model comprises a transient mapping between a Dirac-impulse of thermal power dissipation of at least one element of the integrated circuit and temperature transients of a plurality of elements of the integrated circuit.

20. The method of any one of the previous Claims, further comprising extracting the mechanical stress distribution of the integrated circuit and including it in the extracted netlist.

21. Method of checking maximum ratings of parasitic elements, the method comprising: obtaining simulation results comprising voltage waveforms at multiple nodes; obtaining a layout-extracted netlist with parasitic elements; obtaining maximum allowed voltage differences for at least one parasitic element; verifying whether the simulated voltages exceed the maximum allowed limits; and providing information about violating parasitic elements.

22. The method of Claim 21, wherein the parasitic element is a capacitor.

23. The method of Claim 21, wherein the parasitic element is a lateral bipolar transistor.

24. The method of Claim 23, wherein the lateral bipolar transistor is extracted according to Claim 10, 11, or 12.

25. Method of checking maximum ratings of parasitic resistors, the method comprising: obtaining current waveforms from simulation; obtaining a layout-extracted netlist comprising a set of parasitic resistors of the integrated circuit; obtaining maximum allowed current for at least one parasitic resistor; estimating the current through the parasitic resistor; verifying whether the estimated current exceeds the limit; and providing information about violating resistors.

26. The method of any one of Claims 1 to 6, further comprising obtaining at least one parasitic thermal model as defined in any one of Claims 17, 18, or 19; estimating the temperature of at least one element of the integrated circuit based on simulation results and the parasitic thermal model; and determining whether the parasitic thermal model will be included in the second netlist based on the estimated temperature.

27. The method of any one of Claims 1 to 6, further comprising including mechanical stress distribution as defined in Claim 20 in the second netlist.

28. System comprising at least one processor and a storage medium storing instructions for implementing the method according to any one of Claims 1 to 27.

29. Executable instructions implementing the method according to any one of Claims 1 to 27.

30. The method of any one of Claims 1 to 9, further comprising: simulating the second netlist to verify the performance or safe operation of the integrated circuit including the selected parasitic elements.

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