Semiconductor device and manufacturing method therefor

Abstract

Disclosed in the present invention are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate and a laterally double-diffused metal oxide semiconductor transistor; the laterally double-diffused metal oxide semiconductor transistor comprises a drift region, and a source region, a gate region and a drain region that are sequentially arranged in the horizontal direction; the laterally double-diffused metal oxide semiconductor transistor further comprises a body region; the gate region comprises a gate oxide layer and a gate conductor located in channels in the drift region, the gate oxide layer surrounding the gate conductor, so that the gate conductor is insulated from the source region, the drain region, the body region and the drift region separately; the gate oxide layer comprises a first oxide structure located between the gate conductor and the drain region; in the arrangement direction of the gate region and the drain region, the width of the first oxide structure at a first depth is a first width, and the width of the first oxide structure at a second depth is a second width, the first depth being greater than the second depth, and the first width being less than the second width. The above technical solution can reduce on-resistance while increasing breakdown voltage.

Description

Semiconductor device and manufacturing method thereof

[0001] The present application claims priority to the Chinese patent application No. 202411057464.6, filed on August 2, 2024, and entitled "Semiconductor device and manufacturing method thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0003] Lateral double-diffused metal oxide semiconductor field effect transistors are widely used in the field of integrated circuits due to their advantages in gain, linearity, switching performance, heat dissipation performance, etc.

[0004] The on-resistance and the breakdown voltage of a lateral double-diffused metal oxide semiconductor transistor are its two main parameters, and there is a mutual restrictive relationship between the two. If the withstand voltage value is increased, the on-resistance will also be increased, which is not conducive to the flow of current, and if the on-resistance is reduced, it is not conducive to the withstand voltage of the semiconductor device, and the semiconductor device is easy to burn out. SUMMARY

[0005] The present application provides a semiconductor device and a manufacturing method thereof to improve the withstand voltage value of a lateral double-diffused metal oxide semiconductor transistor and reduce the on-resistance.

[0006] According to an aspect of the present application, a semiconductor device is provided, comprising: a semiconductor substrate, and a lateral double-diffused metal oxide semiconductor transistor located on one side of the semiconductor substrate.

[0007] The lateral double-diffused metal oxide semiconductor transistor comprises a drift region, and a source region, a gate region and a drain region arranged in sequence in a horizontal direction above the drift region.

[0008] The lateral double-diffused metal oxide semiconductor transistor further comprises a body region; the body region is located in the drift region and adjacent to the source region.

[0009] The gate region comprises a gate oxide layer and a gate conductor located in a groove in the drift region; the gate oxide layer surrounds the gate conductor, so that the gate conductor is insulated from the source region, the drain region, the body region and the drift region, respectively.

[0010] The gate oxide layer comprises a first oxide structure between the gate conductor and the drain region; along the arrangement direction of the gate region and the drain region, the first oxide structure has a first width at a first depth, and the first oxide structure has a second width at a second depth; the first depth is greater than the second depth, and the first width is less than the second width.

[0011] Optionally, the first oxide structure comprises a slope surface.

[0012] At the first depth, the slope surface is at a first distance from the drain region; at the second depth, the slope surface is at a second distance from the drain region.

[0013] The first distance is greater than the second distance.

[0014] Optionally, along the arrangement direction of the gate region and the drain region, the maximum width of the first oxide structure is greater than or equal to the maximum width of the gate conductor along the arrangement direction of the gate region and the drain region.

[0015] Optionally, the lateral double-diffusion metal-oxide-semiconductor transistor further comprises a field plate gate.

[0016] The field plate gate is above the first oxide structure.

[0017] Optionally, the gate oxide layer further comprises a second oxide structure below the gate conductor.

[0018] Along the arrangement direction of the gate region and the drain region, the minimum width of the first oxide structure is greater than or equal to the maximum width of the second oxide structure along the vertical direction.

[0019] Optionally, along the vertical direction, the maximum depth of the first oxide structure is less than the maximum depth of the gate conductor.

[0020] Optionally, the maximum depth of the first oxide structure is greater than or equal to the maximum depth of the drain region.

[0021] Optionally, the body region comprises a body heavily doped region and a body lightly doped region.

[0022] The body heavily doped region is arranged along the horizontal direction with the source region, and the body heavily doped region is located on the side of the source region away from the gate region; the body lightly doped region is located below the source region and above the drift region.

[0023] The body region further comprises a heavily doped extension region; the heavily doped extension region is located below the body heavily doped region and above the drift region, and the body heavily doped region is in contact with the body heavily doped region and the body lightly doped region, respectively.

[0024] Optionally, the lateral double-diffused metal oxide semiconductor transistor comprises a first transistor and a second transistor; the first transistor and the second transistor are oppositely arranged;

[0025] The body heavily doped region of the first transistor is multiplexed as the body heavily doped region of the second transistor;

[0026] The heavily doped extension region of the first transistor is multiplexed as the heavily doped extension region of the second transistor.

[0027] According to another aspect of the present application, a preparation method of the above semiconductor device is provided, comprising:

[0028] A semiconductor substrate is provided, and ion implantation and diffusion are performed above the semiconductor substrate to form the drift region of the lateral double-diffused metal oxide semiconductor transistor;

[0029] Etching is performed on the surface of the drift region to form a first trench;

[0030] A local oxidation process is adopted to locally oxidize the sidewall of a partial region of the first trench, so that the sidewall of the partial region of the first trench forms a slope;

[0031] After the slope is formed, oxidation deposition is performed on the first trench to fill the first trench with an oxidation material, and the oxidation material constitutes the first oxidation structure;

[0032] A photolithography and etching process is adopted to form a second trench on the sidewall of the trench away from the slope side, and to expose the sidewall of the first oxidation structure;

[0033] An oxide layer is formed on the inner wall of the second trench, and the oxide layer and the first oxidation structure constitute the gate oxide layer;

[0034] A gate conductor is formed in the oxide layer, and then the source region, the drain region and the body region of the lateral double-diffused metal oxide semiconductor transistor are formed.

[0035] Optionally, etching is performed on the surface of the drift region to form a first trench, comprising:

[0036] A first oxide layer and a first silicon nitride layer are sequentially formed on the surface of the drift region, and a photolithography and etching process is adopted to form a first trench on the drift region;

[0037] A local oxidation process is adopted to locally oxidize the sidewall of a partial region of the first trench,

[0038] Before the sidewall of the partial region of the first trench forms a slope, further comprising:

[0039] forming a second oxide layer, a second silicon nitride layer in sequence after forming the first trench;

[0040] adopting photoetching and etching process to remove the first oxide layer, the first silicon nitride layer, the second oxide layer and the second silicon nitride layer in the preset area, so as to expose the sidewall of the partial area of the first trench;

[0041] after forming the slope, performing oxidation deposition on the first trench, and filling the oxidation material in the first trench, the oxidation material constitutes the first oxide structure, including:

[0042] after forming the slope, removing the second silicon nitride layer, and performing oxidation deposition on the first trench;

[0043] after filling the oxidation material in the first trench, adopting chemical mechanical polishing process to remove the oxidation material outside the first trench, and then removing the first silicon nitride layer, the oxidation material inside the first trench constitutes the first oxide structure.

[0044] Optionally, before adopting local oxidation process to locally oxidize the sidewall of the partial area of the first trench to form the slope of the sidewall of the partial area of the first trench, the method further comprises:

[0045] isotropically etching the sidewall.

[0046] Optionally, after adopting local oxidation process to locally oxidize the sidewall of the partial area of the first trench to form the slope of the sidewall of the partial area of the first trench, the method further comprises:

[0047] growing a wet oxygen sacrificial oxide layer and removing it.

[0048] The technical scheme of the present application can increase the width of the first oxide structure locally, and the second width of the first oxide structure is larger at the second depth with a shallower depth, and the first width of the first oxide structure is smaller at the first depth with a deeper depth, so that the distance between the gate conductor and the drain region can be increased while the resistance of current flow is reduced, which is beneficial to increase the withstand voltage of the lateral double diffused metal oxide semiconductor transistor while reducing its on-resistance.

[0049] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to make the technical solutions in the embodiments of the present application clearer, the accompanying drawings needed in the embodiments will be briefly introduced. Obviously, the accompanying drawings in the following description only show some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0051] Fig. 1 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0052] Fig. 2 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0053] Fig. 3 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0054] Fig. 4 is a flow chart of a preparation method of a semiconductor device provided by an embodiment of the present application;

[0055] Fig. 5 is a structural schematic diagram of a preparation process of a first oxide structure provided by an embodiment of the present application;

[0056] Fig. 6 is a structural schematic diagram of a preparation process of a lateral double-diffusion metal oxide semiconductor transistor provided by an embodiment of the present application;

[0057] Fig. 7 is a flow chart of a preparation method of another semiconductor device provided by an embodiment of the present application;

[0058] Fig. 8 is a structural schematic diagram of a preparation process of another first oxide structure provided by an embodiment of the present application;

[0059] In the drawings:

[0060] 01-semiconductor substrate, 02-lateral double-diffusion metal oxide semiconductor transistor, 10-drift region, 20-source region, 30-gate region, 31-gate oxide layer, 301-first oxide structure, 302-second oxide structure, 303-third oxide structure, 32-gate conductor, 40-drain region, 50-body region, 51-body heavily doped region, 52-body lightly doped region, 53-heavily doped extension region, 60-field plate gate, 71-first oxide layer, 72-second oxide layer, 73-third oxide layer, 81-first silicon nitride layer, 82-second silicon nitride layer, SP-ramp surface, h01-first trench, h02-second trench. DETAILED DESCRIPTION

[0061] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely in combination with the accompanying drawings in the embodiments of the present application, so that those skilled in the art can better understand the technical solutions of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work should belong to the protection scope of the present application.

[0062] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units need not be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0063] Fig. 1 is a structural schematic diagram of a semiconductor device according to an embodiment of the present application. Referring to Fig. 1, the semiconductor device comprises a semiconductor substrate 01 and a lateral double-diffused metal oxide semiconductor transistor 02 located on one side of the semiconductor substrate 01. The lateral double-diffused metal oxide semiconductor transistor 02 comprises a drift region 10, a source region 20, a gate region 30 and a drain region 40 arranged in sequence in a horizontal direction above the drift region 10, and a body region 50. The body region 50 is located in the drift region 10 and adjacent to the source region 20. The gate region 30 comprises a gate oxide layer 31 and a gate conductor 32 located in a trench in the drift region 10. The gate oxide layer 31 surrounds the gate conductor 32 so as to insulate the gate conductor 32 from the source region 20, the drain region 40, the body region 50 and the drift region 10, respectively. The gate oxide layer 31 comprises a first oxide structure 301 between the gate conductor 32 and the drain region 40. In the arrangement direction of the gate region 30 and the drain region 40, the first oxide structure 301 has a first width T1 at a first depth D1 and a second width T2 at a second depth D2. The first depth D1 is greater than the second depth D2, and the first width T1 is less than the second width T2. Above the drift region 10 means a direction away from the side of the semiconductor substrate 01 in a vertical direction. The vertical direction means a direction perpendicular to the plane of the semiconductor substrate 01. The horizontal direction means a direction parallel to the plane of the semiconductor substrate 01. The depth means a distance extending in the vertical direction from the surface of the semiconductor device to the semiconductor substrate 01. The width means a distance of a structure or a region in a certain direction (which can be the horizontal direction or the vertical direction).

[0064] Specifically, the lateral double-diffused metal oxide semiconductor transistor 02 further comprises a source electrode S02, a gate electrode G02 and a drain electrode D02 located on the surface of the semiconductor device. The source electrode S02 is located on the surface of the source region 20, the gate electrode G02 is located on the surface of the gate region 30, and the drain electrode D02 is located on the surface of the drain region 40. When a positive voltage or a negative voltage is applied between the gate electrode G02 and the source electrode S02, charges can be generated between the gate electrode G02 and the source electrode S02, and minority carriers can be accumulated. If a positive voltage or a negative voltage is also applied between the drain electrode D02 and the source electrode S02, a channel of minority carriers can be formed in the body region 50, and current can be conducted. When the absolute value of the voltage between the gate electrode G02 and the source electrode S02 is greater than the absolute value of the threshold voltage, and a corresponding voltage is also applied between the drain electrode D02 and the source electrode S02, current can flow in the horizontal direction from the drain region 40 to the source region 20 or from the source region 20 to the drain region 40 through the drift region 10.

[0065] It should be noted that the source electrode S02 is only exemplarily shown as being located on the surface of the source region 20 and on the surface of the body region 50. In other alternative embodiments, the source electrode S02 can be replaced by two independent electrodes located on the surface of the source region 20 and on the surface of the body region 50, respectively.

[0066] Continuing to refer to FIG. 1, the gate region 20 includes a gate oxide layer 31 and a gate conductor 32 located in the trench of the drift region 10, the gate conductor 32 is arranged between the source region 20 and the drain region 40 in the horizontal direction, and the gate oxide layer 31 and the gate conductor 32 constitute a vertical gate structure, which is conducive to increasing the withstand voltage of the lateral double diffused metal oxide semiconductor transistor 02, so that the breakdown voltage is large and it is not easy to be damaged. Among them, in the vertical direction, the maximum depth of the trench where the gate oxide layer 31 and the gate conductor 32 are located can be set according to actual needs, and the embodiment of the present application does not limit this.

[0067] The gate oxide layer 31 can insulate the gate conductor 32 from other regions in the semiconductor device, and the thickness of the gate oxide layer 31 (i.e. the distance of the gate oxide layer 31 between the gate conductor 32 and other regions in the semiconductor device) will also affect the characteristics of the lateral double diffused metal oxide semiconductor transistor 02. The first oxide structure 301 of the gate oxide layer 31 is located between the gate conductor 32 and the drain region 40, and the width of the first oxide structure 301 in the arrangement direction of the gate region 30 and the drain region 40 is the distance of the gate oxide layer 31 insulated by the gate conductor 32 and the drain region 40. The width of the first oxide structure 301 in the arrangement direction of the gate region 30 and the drain region 40 is positively correlated with the gate-drain breakdown voltage of the lateral double diffused metal oxide semiconductor transistor 02. The wider the width of the first oxide structure 301 in the arrangement direction of the gate region 30 and the drain region 40, the greater the gate-drain breakdown voltage of the lateral double diffused metal oxide semiconductor transistor 02, but at the same time, the on-resistance will also increase. By locally increasing the width of the first oxide structure 301 in the arrangement direction of the gate region 30 and the drain region 40, that is, the width of the first oxide structure 301 gradually decreases in the arrangement direction of the gate region 30 and the drain region 40 as the depth increases, the resistance of the current flow between the drain region 40 and the source region 20 can be reduced, thereby increasing the breakdown voltage while reducing the on-resistance, which is conducive to balancing the withstand voltage and on-resistance of the lateral double diffused metal oxide semiconductor transistor 02.

[0068] For example, taking the NMOS transistor as an example. The semiconductor substrate 01 can be a P-type substrate P-sub, the drift region 10 can be an N-type drift region N-drift, the source region 20 and the drain region 40 can each include an N-type heavily doped region N+, and the body region 50 can include a P-type heavily doped region P+ and a P-type lightly doped region PB. When a positive voltage is applied between the drain D02 and the source S02, and the voltage between the gate G02 and the source S02 is greater than the threshold voltage, an N-type channel is formed between the drain region 40 and the source region 20 and is turned on, and the current flows from the drain region 40 to the source region 20.

[0069] It can be understood that the lateral double-diffusion metal-oxide semiconductor transistor can also be a PMOS transistor, in which case the semiconductor substrate can be an N-type substrate, the drift region can be a P-type drift region, the source region and the drain region can each include a P-type heavily doped region, and the body region can include an N-type heavily doped region and an N-type lightly doped region. When a positive voltage is applied between the source and the drain, and the voltage between the gate and the source is less than the threshold voltage, a P-type channel is formed between the source region and the drain region and is turned on, and current flows from the source region to the drain region.

[0070] In the embodiment of the present application, by locally increasing the width of the first oxide structure, and by making the second width of the first oxide structure larger at the second depth which is shallower, and the first width of the first oxide structure smaller at the first depth which is deeper, the distance between the gate conductor and the drain region can be increased while the resistance of current flow is reduced, which is conducive to increasing the withstand voltage of the lateral double-diffusion metal-oxide semiconductor transistor while reducing the on-resistance thereof.

[0071] Optionally, with continued reference to FIG. 1, the first oxide structure 301 includes a slope surface SP; at the first depth D1, the distance between the slope surface SP and the drain region 40 is a first distance L1; at the second depth D2, the distance between the slope surface SP and the drain region 40 is a second distance L2; the first distance L1 is greater than the second distance L2.

[0072] Specifically, as the depth increases, the width of the first oxide structure 301 gradually decreases along the arrangement direction of the gate region 30 and the drain region 40, and at the same time, as the depth increases, the first oxide structure 301 gradually moves away from the drain region 40, which can shorten the transmission path of the carriers in the channel formed between the source region 20 and the drain region 40, and is conducive to reducing the on-resistance and improving the performance of the semiconductor device, so as to avoid that a large corner exists below the side of the first oxide structure 301 close to the drain region 40, which hinders the current flow, increases the on-resistance, and is not conducive to the withstand voltage and current flow, and burns the device; the width of the slope surface SP along the arrangement direction of the gate region 30 and the drain region 40 and / or the depth along the vertical direction can be adjusted according to actual needs, so as to flexibly adjust and optimize the breakdown voltage and the on-resistance. In addition, the slope surface SP of the first oxide structure 301 is also conducive to uniformizing the electric field intensity near the drain region 40, and avoiding the formation of an electric field peak near the drain region 40, which affects the withstand voltage of the lateral double-diffusion metal-oxide semiconductor transistor 02.

[0073] Optionally, FIG. 2 is a structural schematic diagram of another semiconductor device provided by the embodiment of the present application, and with reference to FIG. 2, the maximum width T301 of the first oxide structure 301 along the arrangement direction of the gate region 30 and the drain region 40 is greater than or equal to the maximum width T32 of the gate conductor 32 along the arrangement direction of the gate region 30 and the drain region 40. By setting the maximum width T301 of the first oxide structure 301 to be relatively wide, the distance between the gate conductor 32 and the drain region 40 can be increased, so as to increase the withstand voltage of the transistor.

[0074] On the basis of the above-mentioned embodiments, the lateral double-diffused metal oxide semiconductor transistor 02 further comprises a field plate gate 60; the field plate gate 60 is located above the first oxide structure 301.

[0075] Specifically, below the first oxide structure 301, and the edge of the drain region 40 close to the gate conductor 32 can gather a large number of electric field lines, forming a high electric field peak, when the voltage difference between the gate conductor 32 and the drain region 40 increases, the electric field will increase rapidly, the high electric field in the local area is easy to cause the device to occur avalanche breakdown and failure, by setting the field plate gate 60 can reduce the strong electric field near the gate conductor 32, improve the breakdown voltage, thereby improving the performance of the semiconductor device. Among them, the potential of the field plate gate 60 can be set according to actual needs, for example, the field plate gate 60 can be provided with a fixed potential, connected to the source region 20, the gate conductor 32 or the drain region 40, the embodiments of the present application do not make limitation.

[0076] In an optional embodiment, the potential of the field plate gate 60 can be consistent with the potential of the source region 20.

[0077] Optionally, continuing to refer to FIG. 2, the gate oxide layer 31 further comprises a second oxide structure 302 located below the gate conductor 32; along the arrangement direction of the gate region 30 and the drain region 40, the minimum width T301' of the first oxide structure 301 is greater than or equal to the maximum width T302 of the second oxide structure 302 along the vertical direction. By setting the minimum width T301' of the first oxide structure 301 to be greater than or equal to the maximum width T302 of the second oxide structure 302, it is beneficial to increase the maximum width T301 of the first oxide structure 301, thereby increasing the withstand voltage value of the transistor.

[0078] Optionally, continuing to refer to FIG. 2, the gate oxide layer 31 further comprises a third oxide structure 303 located between the gate conductor 32 and the source region 20; along the arrangement direction of the gate region 30 and the source region 20, the maximum width T303 of the third oxide structure 303 is less than or equal to the maximum width T302 of the second oxide structure 302 along the vertical direction. In this way, it is beneficial to reduce the threshold voltage and on-resistance of the transistor.

[0079] Optionally, continuing to refer to FIG. 2, along the vertical direction, the maximum depth D301 of the first oxide structure 301 is less than the maximum depth D32 of the gate conductor 32.

[0080] For example, only part of the gate oxide layer 31 on the side of the gate conductor 32 close to the drain region 40 is the first oxide structure 301, which is locally thickened. The part of the gate oxide layer 31 on the side of the gate conductor 32 close to the drain region 40, with a depth of D301-D32, is not thickened, the part with a depth of 0-D301 is locally thickened, and the width gradually increases as the depth decreases, which is beneficial to increase the withstand voltage of the lateral double diffused metal oxide semiconductor transistor while reducing the on-resistance.

[0081] Optionally, continuing to refer to FIG. 2, the maximum depth D301 of the first oxide structure 31 is greater than or equal to the maximum depth D40 of the drain region 40, that is, the depth (the maximum depth D301) at which the minimum width of the first oxide structure 31 is located is greater than or equal to the maximum depth D40 of the drain region 40 along the arrangement direction of the gate region 30 and the drain region 40, so that the gate oxide layer 31 (the part with a depth of 0-D40) between the gate conductor 32 and the drain region 40 is the first oxide structure 31, which can effectively increase the withstand voltage of the lateral double diffused metal oxide semiconductor transistor.

[0082] Optionally, continuing to refer to FIG. 2, the body region 50 includes a body heavily doped region 51 and a body lightly doped region 52; the body heavily doped region 51 is arranged in a horizontal direction along the source region 20, and the body heavily doped region 51 is located on the side of the source region 20 away from the gate region; the body lightly doped region 52 is located below the source region 20 and above the drift region 10; the body region 50 further includes a heavily doped extension region 53; the heavily doped extension region 53 is located below the body heavily doped region 51 and above the drift region 10, and the body heavily doped region 53 is in contact with the body heavily doped region 51 and the body lightly doped region 52, respectively.

[0083] For example, taking the lateral double diffused metal oxide semiconductor transistor 02 as an NMOS transistor as an example, the body heavily doped region 51 includes a P-type heavily doped region P+, the body lightly doped region 52 includes a P-type lightly doped region PB, and the heavily doped extension region 53 includes a P-type heavily doped region Extra-P+. The heavily doped extension region 53 can be an extension region of the body heavily doped region 51, which is equivalent to the body heavily doped region 51. By providing the heavily doped extension region 53, it is beneficial to increase the contact area of the body heavily doped region 51 and the body lightly doped region 52, and to increase the depth of the body heavily doped region 51 (i.e., to reduce the height of the body heavily doped region 51), so that the contact surface position of the body heavily doped region 51 and the body lightly doped region 52 is lower.

[0084] Thus, the contact resistance between the body heavy doped region 51 and the body light doped region 52 can be reduced, and when the semiconductor device is subjected to radiation, such as space radiation, the holes in the body light doped region 52 can be quickly led out of the device by the body heavy doped region 51, avoiding the holes in the body light doped region 52 being transmitted to the source region 20, and a large base current of the parasitic NPN formed by the source region 20, the body light doped region 52 and the drift region 10, the conduction of the parasitic NPN, the large current of the parasitic NPN and the latch-up effect of the device. When the lateral double diffused metal oxide semiconductor transistor 02 is an NMOS transistor, the electrons will flow to the high potential drain region 40, i.e. to the collector of the parasitic NPN formed by the source region 20, the body light doped region 52 and the drift region 10, and the parasitic NPN will not be conducted to form a large current.

[0085] Optionally, FIG. 3 is a structural schematic diagram of another semiconductor device according to an embodiment of the present application. Referring to FIG. 3, the lateral double diffused metal oxide semiconductor transistor 02 includes a first transistor and a second transistor; the first transistor and the second transistor are oppositely arranged; the body heavy doped region 51 of the first transistor is reused as the body heavy doped region 51 of the second transistor; and the heavy doped extension region 53 of the first transistor is reused as the heavy doped extension region 53 of the second transistor.

[0086] For example, in the horizontal direction (from left to right or from right to left in the figure), the drain region 40, the gate region 30, the source region 20, the body heavy doped region 51 of the first transistor, and the body heavy doped region 51, the source region 20, the gate region 30 and the drain region 40 of the second transistor are arranged in sequence, and the partial regions of the body regions 50 adjacent to the first transistor and the second transistor are reused, so that the size of the lateral double diffused metal oxide semiconductor transistor 02 in the horizontal direction can be reduced, and the integration of the semiconductor device is facilitated.

[0087] Based on the same inventive concept, the present application also provides a preparation method of a semiconductor device. FIG. 4 is a flow chart of a preparation method of a semiconductor device according to an embodiment of the present application. FIG. 5 is a structural schematic diagram of a preparation process of a first oxide structure according to an embodiment of the present application. FIG. 6 is a structural schematic diagram of a preparation process of a lateral double diffused metal oxide semiconductor transistor according to an embodiment of the present application. Referring to FIGS. 4-6, the preparation method includes the following steps.

[0088] S1001, providing a semiconductor substrate, and performing ion implantation and diffusion above the semiconductor substrate to form a drift region of a lateral double diffused metal oxide semiconductor transistor.

[0089] The semiconductor substrate 01 includes but is not limited to a silicon substrate.

[0090] For example, referring to FIG. 5, taking the NMOS transistor as an example, the semiconductor substrate 01 can be a P-type substrate P-sub, and the drift region 10 can be an N-type drift region N-drift.

[0091] S1002, etching the surface of the drift region to form a first trench.

[0092] For example, referring to FIG. 5, a mask layer (not shown in the figure) can be formed on the surface of the drift region 10 first, and the mask layer is patterned to expose the region of the surface of the drift region 10 where the first trench h01 is to be formed. The exposed surface of the drift region 10 is etched to form the first trench h01. The process of forming the first trench h01 is not limited in the embodiment of the present application, and the depth of the first trench h01 can be set according to actual needs, which is not limited in the embodiment of the present application.

[0093] S1003, using a local oxidation process to locally oxidize the sidewall of a part of the first trench to form a slope on the sidewall of the part of the first trench.

[0094] For example, referring to FIG. 5, a silicon nitride layer (not shown in the figure) can be formed near the sidewall of the part of the first trench before the slope is formed, which acts as a local hard mask. The silicon nitride covers the region where oxidation should not occur, and the oxide is only grown on the bare silicon. Because silicon and silicon nitride have different thermal expansion coefficients, a thin oxide layer (not shown in the figure) can be deposited between the silicon and the silicon nitride to prevent strain caused by temperature changes.

[0095] Using the local oxidation process and the different oxidation rates of silicon and silicon nitride, when the bare silicon is oxidized, the thin oxide layer causes the lateral diffusion of the oxide under the silicon nitride, so that the oxide at the edge of the nitride mask also grows, and the extended part has a shape like a beak, which is also called beak effect. Using the beak effect of the local oxidation process, the sidewall of the part of the first trench h01 can form a slope.

[0096] S1004, after the slope is formed, the first trench is oxidized and deposited to fill the first trench with an oxide material, and the oxide material constitutes a first oxide structure.

[0097] Specifically, referring to FIG. 5, the oxide material in the first trench h01 constitutes a first oxide structure 301, and the width of the first oxide structure 301 gradually decreases along the horizontal direction as the depth increases. In an optional embodiment, the semiconductor substrate 01 includes a silicon substrate, and the oxide material includes silicon dioxide.

[0098] S1005, forming a second trench on the sidewall of the trench far from the slope by using photolithography and etching process, and exposing the sidewall of the first oxidation structure.

[0099] For example, referring to FIG. 6, a mask layer (not shown in the figure) can be formed on the surface first, and the mask layer is patterned to expose the area of the surface where the second trench h02 is to be formed. The exposed surface is etched to form the second trench h02. The second trench h02 is located on the side of the first oxidation structure 301 far from the slope.

[0100] S1006, forming an oxidation layer on the inner wall of the second trench, and the oxidation layer and the first oxidation structure constitute a gate oxide layer.

[0101] For example, referring to FIG. 6, the gate oxide layer 31 includes the first oxidation structure 301, the second oxidation structure 302 located on the inner wall of the bottom of the second trench h02, and the third oxidation structure 303 located on the inner wall of the side of the second trench h02 far from the first oxidation structure 301.

[0102] S1007, forming a gate conductor in the oxidation layer, and then forming a source region, a drain region and a body region of a lateral double-diffusion metal oxide semiconductor transistor.

[0103] In the embodiment of the present application, by forming a slope on the sidewall of the partial area of the first trench after forming the first trench, the first oxidation structure formed in the first trench is partially thickened. The width of the first oxidation structure is larger at a position with a shallower depth, and the width of the first oxidation structure is smaller at a position with a deeper depth. The distance between the gate conductor and the drain region can be increased while the resistance of current flow is reduced, which is beneficial to increasing the withstand voltage of the lateral double-diffusion metal oxide semiconductor transistor while reducing the on-resistance thereof.

[0104] In an optional embodiment, before the partial oxidation process is used to partially oxidize the sidewall of the partial area of the first trench to form a slope on the sidewall of the partial area of the first trench, the method further includes: isotropically etching the sidewall.

[0105] Specifically, by isotropically etching the sidewall of the partial area of the first trench before the partial oxidation process is used to form the slope, the sidewall can be formed with a certain slope first, and then the partial oxidation process is performed, which is beneficial to adjusting the slope of the slope.

[0106] In yet another optional embodiment, after the partial oxidation process is used to partially oxidize the sidewall of the partial area of the first trench to form a slope on the sidewall of the partial area of the first trench, the method further includes: growing a wet oxygen sacrificial oxidation layer and removing it to obtain a smooth slope, so as to eliminate the chamfer formed in the partial oxidation process.

[0107] Optionally, FIG. 7 is a flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present application, and FIG. 8 is a structural schematic diagram of a process for manufacturing a first oxide structure according to an embodiment of the present application. Referring to FIGS. 6-8, the method comprises the following steps:

[0108] S2001, providing a semiconductor substrate, and performing ion implantation and diffusion above the semiconductor substrate to form a drift region of a lateral double-diffusion metal-oxide-semiconductor transistor.

[0109] S2002, sequentially forming a first oxide layer and a first silicon nitride layer on the surface of the drift region, and forming a first trench in the drift region by using a photolithography and etching process.

[0110] For example, referring to FIG. 8, before forming the first trench h01, a first oxide layer 71 can be formed on the surface by thermal oxidation, and then a first silicon nitride layer 81 can be formed on the surface of the first oxide layer 71 by using a chemical vapor deposition process. The first silicon nitride layer 81 can be used as a stop layer for a chemical mechanical polishing process when the oxide material outside the first trench h01 is removed, and the first oxide layer 71 can alleviate the stress damage to the semiconductor substrate 01 and the drift region 10 caused by forming the first silicon nitride layer 81.

[0111] In an optional embodiment, the semiconductor substrate 01 comprises a silicon substrate, and the first oxide layer 71 comprises silicon dioxide.

[0112] S2003, sequentially forming a second oxide layer and a second silicon nitride layer after forming the first trench.

[0113] For example, after forming the first trench h01, a second oxide layer 72 and a second silicon nitride layer 82 can be formed in sequence to cover the inner wall surface of the first trench h01 with the second oxide layer 72 and the second silicon nitride layer 82. The second silicon nitride layer 82 can be used as a local hard mask in a subsequent local oxidation process, and the second oxide layer 72 can prevent strain caused by temperature changes.

[0114] In an optional embodiment, a third oxide layer 73 can be formed after forming the second silicon nitride layer 82 to planarize the surface, which is beneficial to subsequent processing.

[0115] S2004, removing the first oxide layer, the first silicon nitride layer, the second oxide layer, and the second silicon nitride layer in a preset region by using a photolithography and etching process to expose the sidewall of a partial region of the first trench.

[0116] The preset region refers to a position above a region where a slope needs to be formed.

[0117] Specifically, the second oxide layer 72 and the second silicon nitride layer 82 in the preset region are removed to expose the region where the slope is to be formed, so that the region can be processed to form the slope in the subsequent process.

[0118] S2005, a local oxidation process is used to locally oxidize the sidewall of the partial region of the first trench, so that the sidewall of the partial region of the first trench forms a slope.

[0119] S2006, after the slope is formed, the second silicon nitride layer is removed, and the first trench is oxidized and deposited.

[0120] Specifically, after the slope is formed, the second silicon nitride layer 82 used as a mask in the first trench h01 and the second silicon nitride layer 82 outside the first trench h01 are removed. If the subsequent oxide material filled in the first trench h01 is the same as the material of the second oxide layer 72, the second oxide layer 72 can be removed in this step; if the subsequent oxide material filled in the first trench h01 is different from the material of the second oxide layer 72, the second oxide layer 72 needs to be removed in this step.

[0121] S2007, after the first trench is filled with the oxide material, a chemical mechanical polishing process is used to remove the oxide material outside the first trench, and then the first silicon nitride layer is removed, and the oxide material inside the first trench constitutes the first oxide structure.

[0122] For example, the chemical mechanical polishing process can be used to remove the oxide material above the surface of the first silicon nitride layer 81, then hydrofluoric acid is used to remove the oxide material above the surface of the first oxide layer 71, and finally the first silicon nitride layer 81 is removed.

[0123] In an optional embodiment, after the first silicon nitride layer is removed, the first oxide layer outside the first trench can also be removed by lithography and etching, and only the oxide material inside the first trench is reserved to form the first oxide structure.

[0124] S2008, a second trench is formed on the sidewall of the trench away from the slope by using a lithography and etching process, and the sidewall of the first oxide structure is exposed.

[0125] S2009, an oxide layer is formed on the inner wall of the second trench, and the oxide layer and the first oxide structure constitute a gate oxide layer.

[0126] S2010, a gate conductor is formed in the oxide layer, and then a source region, a drain region and a body region of a lateral double diffused metal oxide semiconductor transistor are formed.

[0127] As needed to be supplemented in the above two preparation method embodiments, after the device preparation is completed by the above preparation method, to ensure normal use of the semiconductor device, the device needs to be connected with the outside, that is, the metal electrodes need to be connected, such as the source S02, the gate G02 and the drain D02 shown in FIG. 1, therefore, after S1007 or S2010, the following steps are added: performing a back-end process to form a plurality of contact holes, and connecting each pole of the device with the corresponding metal layer through the contact holes.

[0128] The preparation method of the semiconductor device provided by the embodiments of the present application is used to prepare the semiconductor device provided by any of the embodiments of the present application, has the technical features and beneficial effects of the semiconductor device, and the content not described in detail in the embodiments of the preparation method of the semiconductor device can be referred to the description of the semiconductor device above, which will not be described here again. Similarly, the semiconductor device of the embodiments of the present application also has the functional modules and beneficial effects of being able to perform the preparation method of the semiconductor device provided by the embodiments of the present application, and the content not described in detail in the embodiments of the semiconductor device can be referred to the description of the preparation method of the semiconductor device above, which will not be described here again.

[0129] It should be noted that the above are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments herein, and those skilled in the art can make various obvious changes, re-adjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate, and a laterally double-diffused metal-oxide-semiconductor transistor located on one side of the semiconductor substrate; The lateral double-diffused metal-oxide-semiconductor transistor includes a drift region and a source region, a gate region, and a drain region arranged sequentially in a horizontal direction above the drift region. The lateral double-diffused metal-oxide-semiconductor transistor further includes a body region; the body region is located in the drift region and is adjacent to the source region; The gate region includes a gate oxide layer and a gate conductor located within the trench of the drift region. The gate oxide layer surrounds the gate conductor so that the gate conductor is insulated from the source region, the drain region, the body region, and the drift region, respectively. The gate oxide layer includes a first oxide structure located between the gate conductor and the drain region; along the arrangement direction of the gate region and the drain region, the width of the first oxide structure at a first depth is a first width, and the width of the first oxide structure at a second depth is a second width; the first depth is greater than the second depth, and the first width is less than the second width.

2. The semiconductor device according to claim 1, characterized in that, The first oxide structure includes a sloping surface; At the first depth, the distance between the slope and the leaking area is a first distance; at the second depth, the distance between the slope and the leaking area is a second distance. The first distance is greater than the second distance.

3. The semiconductor device according to claim 1, characterized in that, Along the arrangement direction of the gate region and the drain region, the maximum width of the first oxide structure is greater than or equal to the maximum width of the gate conductor along the arrangement direction of the gate region and the drain region.

4. The semiconductor device according to claim 3, characterized in that, The laterally double-diffused metal-oxide-semiconductor transistor further includes a field gate; The field plate grid is located above the first oxide structure.

5. The semiconductor device according to claim 1, characterized in that, The gate oxide layer further includes a second oxide structure located below the gate conductor; Along the arrangement direction of the gate region and the drain region, the minimum width of the first oxide structure is greater than or equal to the maximum width of the second oxide structure in the vertical direction.

6. The semiconductor device according to claim 1, characterized in that, Along the vertical direction, the The maximum depth of the first oxide structure is less than the maximum depth of the gate conductor.

7. The semiconductor device according to claim 1, characterized in that, The maximum depth of the first oxide structure is greater than or equal to the maximum depth of the leak region.

8. The semiconductor device according to claim 1, characterized in that, The bulk region includes a bulk heavy-doped region and a bulk light-doped region; The bulk doped region is arranged horizontally with the source region, and the bulk doped region is located on the side of the source region away from the gate region; the bulk light doped region is located below the source region and above the drift region; The bulk region further includes a heavily doped extension region; the heavily doped extension region is located below the heavy doped region and above the drift region, and the heavy doped region is in contact with and connected to the heavy doped region and the lightly doped bulk region, respectively.

9. The semiconductor device according to claim 8, characterized in that, The laterally double-diffused metal-oxide-semiconductor transistor includes a first transistor and a second transistor; the first transistor and the second transistor are disposed opposite to each other; The weight doped region of the first transistor is reused as the weight doped region of the second transistor; The heavily doped extended region of the first transistor is reused as the heavily doped extended region of the second transistor.

10. A method for fabricating a semiconductor device as described in any one of claims 1-9, characterized in that, include: A semiconductor substrate is provided, and ion implantation and diffusion are performed over the semiconductor substrate to form the drift region of the lateral double-diffused metal-oxide-semiconductor transistor; The surface of the drift region is etched to form a first trench; A localized oxidation process is used to locally oxidize a portion of the sidewalls of the first trench, thereby creating a slope on the sidewalls of that portion of the first trench. After the slope is formed, the first trench is subjected to oxidative deposition, and the first trench is filled with an oxidative material, which constitutes the first oxidative structure; A second trench is formed on the sidewall of the trench on the side away from the slope using photolithography and etching processes, exposing the sidewall of the first oxide structure. An oxide layer is formed on the inner wall of the second trench, and the oxide layer and the first oxide structure constitute the gate oxide layer; A gate conductor is formed within the oxide layer, and then the source region, drain region, and body region of the lateral double-diffused metal-oxide-semiconductor transistor are formed.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, Etching is performed on the surface of the drift region to form a first trench, including: A first oxide layer and a first silicon nitride layer are sequentially formed on the surface of the drift region, and a first trench is formed in the drift region using photolithography and etching processes; Before forming a slope on the sidewalls of a portion of the first trench using a localized oxidation process, the process further includes: After the first trench is formed, a second oxide layer and a second silicon nitride layer are formed sequentially. Photolithography and etching processes are used to remove the first oxide layer, the first silicon nitride layer, the second oxide layer, and the second silicon nitride layer in the preset area to expose the sidewalls of a portion of the first trench. After the slope is formed, the first trench is subjected to oxidative deposition, and an oxidative material is filled into the first trench, the oxidative material constituting the first oxidative structure, including: After the slope is formed, the second silicon nitride layer is removed, and the first trench is oxidized and deposited. After the first trench is filled with the oxide material, the oxide material located outside the first trench is removed by chemical mechanical polishing, and then the first silicon nitride layer is removed. The oxide material located inside the first trench constitutes the first oxide structure.

12. The method for fabricating a semiconductor device according to claim 10, characterized in that, Before employing a localized oxidation process to locally oxidize the sidewalls of a portion of the first trench, thereby forming a slope on the sidewalls of that portion of the first trench, the process further includes: The sidewalls are etched isotropically.

13. The method for fabricating a semiconductor device according to claim 10, characterized in that, After employing a localized oxidation process to locally oxidize a portion of the sidewalls of the first trench, thereby creating a slope on the sidewalls of that portion of the first trench, the process includes: A wet oxygen sacrificial oxide layer is grown and then removed.

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