Package structure integrating MEMS and ASIC, and manufacturing method therefor

Abstract

The present application belongs to the technical field of resonator manufacturing, and relates to a package structure integrating an MEMS and an ASIC, and a manufacturing method therefor. The package structure comprises an SOI wafer, wherein a first region and a second region are arranged on a top silicon surface of the SOI wafer, an ASIC driving circuit unit is arranged in the first region, and an MEMS resonator unit is arranged in the second region; and a metal connection layer is arranged on the surface of the SOI wafer, the ASIC driving circuit unit and the MEMS resonator unit are connected by means of the metal connection layer, and the ASIC driving circuit unit is used for exciting the vibration of the MEMS resonator unit and processing an output signal of the MEMS resonator unit. By arranging an MEMS resonator unit and an ASIC driving circuit unit on the same SOI wafer, there is no need to stack and thin the MEMS resonator unit and the ASIC driving circuit unit, such that the volume of a package housing can be made smaller, thereby enabling a higher degree of integration between the MEMS resonator unit and the ASIC driving circuit unit.

Description

Packaging structure integrating MEMS and ASIC and manufacturing method thereof

[0001] The present application claims priority to the Chinese patent application No. 202411023320.9, filed on July 29, 2024, and entitled "Packaging structure integrating MEMS and ASIC and manufacturing method thereof", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application belongs to the technical field of resonator manufacturing, and specifically relates to a packaging structure integrating MEMS and ASIC and a manufacturing method thereof. BACKGROUND

[0003] Traditional clock devices are usually based on the piezoelectric effect of quartz crystals to generate high-precision oscillation frequencies. Quartz crystal oscillators are widely used in electronic devices for time and frequency control and stabilization, but have poor compatibility with CMOS processes and cannot meet the demand for high integration. Therefore, with the development of technology, MEMS (Micro-Electro-Mechanical System) clock devices with better compatibility with CMOS processes have gradually become substitutes for quartz crystal oscillators.

[0004] The packaging inside the MEMS clock device in the prior art is mainly divided into a MEMS resonator part and a CMOS driving circuit part, and mainly adopts packaging forms such as QFN, SOT, LCC, and CSP to integrate the MEMS Die and the CMOS Die in a top-and-bottom stacking manner.

[0005] However, in the process of packaging the MEMS Die and the CMOS Die, in order to meet the requirements of the packaging size, the MEMS Die and the CMOS Die need to be thinned, resulting in a complex packaging method. SUMMARY

[0006] The embodiments of the present application provide a packaging structure integrating MEMS and ASIC and a manufacturing method thereof, which are used to solve the problem that, in the process of packaging the MEMS Die and the CMOS Die in the prior art, in order to meet the requirements of the packaging size, the MEMS Die and the CMOS Die need to be thinned, resulting in a complex packaging method.

[0007] In a first aspect, the embodiments of the present application provide a packaging structure integrating MEMS and ASIC, comprising an SOI wafer, a top surface of the SOI wafer is provided with a first area and a second area, an ASIC driving circuit unit is arranged in the first area, and a MEMS resonator unit is arranged in the second area.

[0008] The SOI wafer is provided with a metal connecting layer, the ASIC driving circuit unit and the MEMS resonator unit are connected through the metal connecting layer, the ASIC driving circuit unit is used for exciting vibration of the MEMS resonator unit, and an output signal of the MEMS resonator unit is processed.

[0009] In the embodiment of the application, the ASIC driving circuit unit is provided with a passivation layer on the surface, and the passivation layer is used for isolating the ASIC driving circuit unit from external air.

[0010] In the embodiment of the application, the SOI wafer is provided with a groove, and the MEMS resonator unit is provided with a cantilever beam, and the cantilever beam is located above the groove.

[0011] The second aspect further provides a packaging structure manufacturing method of integrated MEMS and ASIC, providing an SOI wafer, and dividing a top silicon surface of the SOI wafer into a first region and a second region;

[0012] An ASIC driving circuit unit is manufactured in the first region;

[0013] A MEMS resonator unit is manufactured in the second region, and is connected with the ASIC driving circuit unit through a metal connecting layer.

[0014] In the embodiment of the application, the substrate silicon in the SOI wafer has a thickness of 300-800 microns, the buried oxygen layer has a thickness of 1-5 microns, and the top silicon has a thickness of 2-20 microns.

[0015] In the embodiment of the application, the ASIC driving circuit unit is manufactured in the first region, and the specific method is as follows,

[0016] The ASIC driving circuit unit is manufactured in the first region on the top silicon by using a CMOS process with a process of 40-80 nanometers.

[0017] In the embodiment of the application, after the ASIC driving circuit unit is manufactured in the first region, a passivation material is used to perform passivation treatment on the ASIC driving circuit unit, so as to form a passivation layer on the surface of the ASIC driving circuit unit, and the passivation layer on the PAD electrode in the ASIC driving circuit unit is removed through a photoetching and etching process.

[0018] In the embodiment of the application, the MEMS resonator unit is manufactured in the second region, and is connected with the ASIC driving circuit unit through a metal connecting layer, and the specific method is as follows,

[0019] A bottom electrode metal layer is deposited on the top silicon surface by using a deposition process, and the bottom electrode metal layer in the second region is subjected to a patterning treatment;

[0020] depositing a piezoelectric layer metal layer on top of the bottom electrode metal layer by using a deposition process;

[0021] depositing a top electrode metal layer on top of the piezoelectric layer metal layer by using a deposition process, and performing a patterning process on the top electrode metal layer in the second region;

[0022] The bottom electrode metal layer, the piezoelectric layer metal layer and the top electrode metal layer form a metal connection layer, and the metal connection layer in the second region is removed by using a photolithography and etching process to remove the excess metal layer and release the cantilever beam, thereby obtaining the MEMS resonator unit;

[0023] The metal connection layer in the first region is removed by using a photolithography and etching process to remove the excess metal connection layer, and only the metal connection layer for connecting the PAD electrode in the ASIC driving circuit and the MEMS resonator unit is reserved, so that the MEMS resonator unit is connected with the ASIC driving circuit.

[0024] In the embodiments of the present application, the metal connection layer in the second region is removed by using a photolithography and etching process to remove the excess metal connection layer and release the cantilever beam, thereby obtaining the MEMS resonator unit, specifically,

[0025] After the metal connection layer in the second region is removed by using a photolithography and etching process to remove the excess metal connection layer, the top layer silicon and the buried oxygen layer of the SOI wafer are etched by using an etching process to obtain a groove, thereby releasing the cantilever beam and obtaining the MEMS resonator unit.

[0026] In the embodiments of the present application, the material of the bottom electrode metal layer is molybdenum, the material of the piezoelectric layer metal layer is aluminum nitride, and the material of the top electrode metal layer is molybdenum.

[0027] The packaging structure integrating the MEMS and the ASIC and the manufacturing method thereof provided in the embodiments of the present application include an SOI wafer, and a first region and a second region are arranged on the top layer silicon surface of the SOI wafer. The ASIC driving circuit unit is arranged in the first region, and the MEMS resonator unit is arranged in the second region. A metal connection layer is arranged on the surface of the SOI wafer, and the ASIC driving circuit unit and the MEMS resonator unit are connected through the metal connection layer. The ASIC driving circuit unit is used to excite the vibration of the MEMS resonator unit and process the output signal of the MEMS resonator unit. By arranging the MEMS resonator unit and the ASIC driving circuit unit on the same SOI wafer, the stacking and thinning of the MEMS resonator unit and the ASIC driving circuit unit are not needed, so that the volume of the packaging shell can be smaller, and the integration degree between the MEMS resonator unit and the ASIC driving circuit unit is higher. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.

[0029] Fig. 1 is a top view of a package structure integrating MEMS and ASIC provided by the present application;

[0030] Fig. 2 is a flow chart of a manufacturing method of the package structure integrating MEMS and ASIC provided by the present application;

[0031] Fig. 3 is a structure diagram of the package structure integrating MEMS and ASIC provided by the present application without metal deposition;

[0032] Fig. 4 is a structure diagram of the package structure integrating MEMS and ASIC provided by the present application after deposition of three metal layers;

[0033] Fig. 5 is a structure diagram of Fig. 4 after removal of the top electrode metal layer;

[0034] Fig. 6 is a structure diagram of Fig. 5 after removal of the piezoelectric layer metal layer;

[0035] Fig. 7 is a structure diagram of Fig. 6 after removal of the bottom electrode metal layer;

[0036] Fig. 8 is a structure diagram of Fig. 7 after removal of part of the top silicon layer;

[0037] Fig. 9 is a structure diagram of Fig. 8 after formation of a groove by removal of part of the buried oxygen layer.

[0038] Reference signs:

[0039] 100 - SOI wafer; 110 - substrate silicon; 120 - buried oxygen layer; 130 - top silicon layer; 140 - groove;

[0040] 200 - ASIC driving circuit unit; 210 - PAD electrode;

[0041] 300 - MEMS resonator unit; 310 - cantilever beam;

[0042] 400 - metal connection layer; 410 - bottom electrode metal layer; 420 - piezoelectric layer metal layer; 430 - top electrode metal layer;

[0043] 500 - passivation layer.

[0044] The above-described drawings show specific embodiments of the present application, which will be described in more detail hereinafter. These drawings and the written description are not intended to restrict the scope of the present application in any way, but are merely meant to illustrate the principles of the application by reference to specific embodiments DETAILED DESCRIPTION

[0045] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are only a part of embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0046] The terms "first", "second", "third", "fourth" and the like (if any) in the description, claims and drawings of the present application are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in other than the order illustrated or described herein.

[0047] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean example, illustration, or description. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or having greater advantages than other embodiments or design solutions. Rather, the use of "exemplary" or "for example" is intended to present the relevant concept in a particular manner.

[0048] In the description of the embodiments of the present application, it should be understood that the terms "inner", "outer", "upper", "bottom", "front", "back" and the like indicate the orientation or positional relationship (if any) shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be understood as limiting the present application.

[0049] Noun explanation: MEMS (Micro-Electro-Mechanical Systems) is a micro system integrating microelectronic technology, micro mechanical technology and micro sensing technology. MEMS Die is a microelectromechanical system system die. MEMS resonator is a micro resonator manufactured by microelectromechanical system technology. ASIC driving circuit is an integrated circuit designed and optimized for a specific application, used to control and drive other electronic elements or systems, used in the present application to drive MEMS resonator. CMOS process is a complementary metal oxide semiconductor process, which is the current mainstream integrated circuit manufacturing technology, with the advantages of low power consumption, high speed and high density.

[0050] The packaging of the prior art MEMS clock device is mainly divided into a MEMS resonator part and a CMOS driving circuit part, and mainly adopts QFN, SOT, LCC, CSP and other packaging forms to integrate the MEMS Die and the CMOS Die in a stacked manner.

[0051] However, in the packaging process of the MEMS Die and the CMOS Die, in order to meet the requirement of the packaging size, the MEMS Die and the CMOS Die need to be thinned, which leads to a complex packaging mode.

[0052] Therefore, the embodiment of the present application provides a packaging structure integrating MEMS and ASIC and a manufacturing method thereof. The MEMS resonator unit and the ASIC driving circuit unit are arranged on the same SOI wafer, and the stacking of the MEMS resonator unit and the ASIC driving circuit unit is not needed, so that the integration degree between the MEMS resonator unit and the ASIC driving circuit unit is higher. The present application will be described below with reference to the drawings.

[0053] Among them, Fig. 1 is a top view of the packaging structure integrating MEMS and ASIC provided by the present application. Fig. 2 is a structure diagram of the packaging structure integrating MEMS and ASIC provided by the present application without depositing metal. Fig. 3 is a structure diagram of the packaging structure integrating MEMS and ASIC provided by the present application after depositing three metal layers. Fig. 4 is a structure diagram of the packaging structure integrating MEMS and ASIC provided by the present application after removing the top electrode metal layer. Fig. 5 is a structure diagram of the packaging structure integrating MEMS and ASIC provided by the present application after removing the piezoelectric layer metal layer. Fig. 6 is a structure diagram of the packaging structure integrating MEMS and ASIC provided by the present application after removing the bottom electrode metal layer. Fig. 7 is a structure diagram of the packaging structure integrating MEMS and ASIC provided by the present application after removing part of the top silicon layer. Fig. 8 is a structure diagram of the packaging structure integrating MEMS and ASIC provided by the present application after removing part of the buried oxygen layer to form a groove.

[0054] As shown in Fig. 1, the embodiment of the present application provides a packaging structure integrating MEMS and ASIC, which comprises an SOI wafer 100, and the top surface of the SOI wafer 100 is provided with a first area and a second area. The first area is provided with an ASIC driving circuit unit 200, and the second area is provided with a MEMS resonator unit 300.

[0055] The surface of the SOI wafer 100 is provided with a metal connection layer 400, and the ASIC driving circuit unit 200 and the MEMS resonator unit 300 are connected through the metal connection layer 400. The ASIC driving circuit unit 200 is used to excite the vibration of the MEMS resonator unit 300 and process the output signal of the MEMS resonator unit 300.

[0056] The SOI wafer 100 can adopt a wafer with a diameter of 10 cm, 15 cm and 20 cm. The SOI wafer 100 is divided into two parts, wherein the right side is the first area and the left side is the second area.

[0057] By setting the MEMS resonator unit 300 and the ASIC driving circuit unit 200 on the same SOI wafer 100 and connecting through the metal connecting layer 400, the stacking and thinning of the MEMS resonator unit 300 and the ASIC driving circuit unit 200 are not required, so the volume of the packaging shell can be made smaller, and the degree of integration between the MEMS resonator unit 300 and the ASIC driving circuit unit 200 is higher.

[0058] Meanwhile, the MEMS resonator unit 300 and the ASIC driving circuit unit 200 are set on the same SOI wafer 100 and connected through the metal connecting layer 400, without the need for additional connection lines, reducing the inter-chip electrical interconnection and reducing power consumption and noise.

[0059] In the embodiment of the present application, the ASIC driving circuit unit 200 is provided with a passivation layer 500 on the surface, which is used to isolate the ASIC driving circuit unit 200 from the external air.

[0060] The passivation layer 500 is set on the surface of the ASIC driving circuit unit 200 by a chemical vapor deposition (CVD) or physical vapor deposition (PVD) method, wherein the material of the passivation layer 500 is silicon oxide, silicon nitride or polyimide. And one or more passivation layers 500 can be set according to actual needs. The main function of the passivation layer 500 is to protect the circuit and prevent the influence of the external environment (such as moisture and pollutants in the air) on the circuit, thereby improving the reliability and life of the circuit

[0061] In the embodiment of the present application, a groove 140 is provided on the SOI wafer 100, and a cantilever beam 310 is provided on the MEMS resonator unit 300, and the cantilever beam 310 is located above the groove 140.

[0062] The cantilever beam 310 is used to realize high-precision and high-stability resonance function, and is a main component for the MEMS resonator unit 300 to generate a resonance signal.

[0063] In the embodiment of the present application, a double-cantilever beam 310 structure is adopted, and two cantilever beams 310 are located on opposite sides of the MEMS resonator unit 300. The length of each cantilever beam 310 is 150 microns, the width is 15 microns, and the thickness is 3 microns.

[0064] As shown in FIG. 2, for the above-mentioned integrated MEMS and ASIC packaging structure, the present application further provides a packaging structure manufacturing method for integrating MEMS and ASIC, comprising:

[0065] S100, providing an SOI wafer 100, and dividing a top layer silicon 130 surface of the SOI wafer 100 into a first region and a second region;

[0066] S200, manufacturing an ASIC driving circuit unit 200 in the first region;

[0067] S300, manufacturing a MEMS resonator unit 300 in the second region, and connecting the MEMS resonator unit 300 with the ASIC driving circuit unit 200 through a metal connecting layer 400.

[0068] In the embodiment of the present application, the thickness of the substrate silicon 110 in the SOI wafer is 300-800 microns, the thickness of the buried oxygen layer 120 is 1-5 microns, and the thickness of the top layer silicon 130 is 2-20 microns.

[0069] In the embodiment of the present application, the ASIC driving circuit unit 200 is manufactured in the first region, and the specific method is as follows,

[0070] In the first region on the top layer silicon 130, the ASIC driving circuit unit 200 is manufactured by using a 40-80 nanometer process CMOS technology.

[0071] Specifically, the ASIC driving circuit unit 200 is manufactured in the first region on the top layer silicon 130 by using an 80 nanometer process CMOS technology. The ASIC driving circuit unit 200 includes an input interface, a signal processing unit, a power amplifier, and an output interface. By means of steps such as photoetching, ion implantation, thin film deposition, and etching, a low-power-consumption and high-speed integrated circuit is formed.

[0072] As shown in FIG. 3, in the embodiment of the present application, after the ASIC driving circuit unit 200 is manufactured in the first region, a passivation material is used to perform passivation treatment on the ASIC driving circuit unit 200, so as to form a passivation layer 500 on the surface of the ASIC driving circuit unit 200, and the passivation layer 500 on the PAD electrode 210 in the ASIC driving circuit unit 200 is removed through a photoetching and etching process.

[0073] The PAD electrode 210 after the passivation layer 500 is removed is used to connect with the MEMS resonator unit 300 and connect with an external circuit or a pin.

[0074] In combination with FIGS. 4-9, in the embodiment of the present application, the MEMS resonator unit 300 is manufactured in the second region, and the MEMS resonator unit 300 is connected with the ASIC driving circuit unit 200 through the metal connecting layer 400, and the specific method is as follows,

[0075] A bottom electrode metal layer 410 is deposited on the surface of the top layer silicon 130 by using a deposition process, and the bottom electrode metal layer 410 in the second region is subjected to a patterning treatment;

[0076] A piezoelectric layer metal layer 420 is deposited on the bottom electrode metal layer 410 by a deposition process;

[0077] A top electrode metal layer 430 is deposited on the piezoelectric layer metal layer 420 by a deposition process, and the top electrode metal layer 430 in the second region is patterned;

[0078] The bottom electrode metal layer 410, the piezoelectric layer metal layer 420 and the top electrode metal layer 430 form a metal connection layer 400, and the metal connection layer 400 in the second region is removed by a lithography and etching process to release the cantilever beam 310, thereby obtaining the MEMS resonator unit 300;

[0079] The metal connection layer 400 in the first region is removed by a lithography and etching process to only retain the metal connection layer 400 for connecting the PAD electrode 210 in the ASIC driving circuit and the MEMS resonator unit 300, so that the MEMS resonator unit 300 is connected to the ASIC driving circuit.

[0080] In the embodiment, the bottom electrode metal layer 410, the piezoelectric layer metal layer 420 and the top electrode metal layer 430 are deposited on the top surface of the top layer silicon 130 by a deposition process, which can be a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) method.

[0081] In the embodiment, the metal connection layer 400 in the second region is removed by a lithography and etching process to release the cantilever beam 310, thereby obtaining the MEMS resonator unit 300, which specifically comprises the following steps:

[0082] After the metal connection layer 400 in the second region is removed by a lithography and etching process, the top layer silicon 130 and the buried oxide layer 120 of the SOI wafer 100 are etched by an etching process to obtain a groove 140, thereby releasing the cantilever beam 310 and obtaining the MEMS resonator unit 300.

[0083] In the embodiment, the bottom electrode metal layer 410, the piezoelectric layer metal layer 420 and the top electrode metal layer 430 are deposited on the top surface of the top layer silicon 130 by a deposition process, which can be a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) method.

[0084] In the embodiment, the bottom electrode metal layer 410 is made of metal molybdenum, gold or platinum, with a thickness of 20-100 nm, the piezoelectric layer metal layer 420 is made of aluminum nitride, lead zirconate titanate or zinc oxide, with a deposition thickness of 500-2000 nm, and the top electrode metal layer 430 is made of molybdenum, gold or platinum, with a thickness of 20-100 nm.

[0085] The present application sets the MEMS resonator unit 300 and the ASIC driving circuit unit 200 on the same SOI wafer 100, and does not need to perform the stacking and thinning of the MEMS resonator unit 300 and the ASIC driving circuit unit 200, so that the volume of the package shell can be made smaller, and the degree of integration between the MEMS resonator unit 300 and the ASIC driving circuit unit 200 is higher.

[0086] So far, the technical solutions of the present application have been described in combination with the preferred embodiments shown in the drawings, but those skilled in the art can easily understand that the protection scope of the present application is obviously not limited to these specific embodiments, and the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application

[0087] In general, terms should be understood in the context of their usage, for example, the term "one or more" as used herein, can be used to describe any feature, structure, or characteristic in the singular or in the plural, depending on the context in which it is used. Similarly, terms such as "a", "an", or "the" can be understood to convey a singular usage, or a plural usage, depending on the context in which it is used.

[0088] It should be readily understood that "on", "above", and "over" in the present disclosure should be interpreted in the broadest manner, such that "on" means not only "directly on", but also includes the meaning of "on" with intermediate features or layers therebetween, and "above" or "over" includes not only the meaning of "above" or "over", but also the meaning of "above" or "over" without intermediate features or layers therebetween (i.e., directly on).

Claims

1. An integrated MEMS and ASIC package structure, characterized by, The SOI wafer (100) is provided with a first area and a second area on the surface of the top layer silicon (130), the ASIC driving circuit unit (200) is arranged in the first area, and the MEMS resonator unit (300) is arranged in the second area; The SOI wafer (100) is provided with a metal connecting layer (400), the ASIC driving circuit unit (200) and the MEMS resonator unit (300) are connected through the metal connecting layer (400), the ASIC driving circuit unit (200) is used for exciting the vibration of the MEMS resonator unit (300), and the output signal of the MEMS resonator unit (300) is processed.

2. The integrated MEMS and ASIC package structure of claim 1, wherein, The ASIC driving circuit unit (200) is provided with a passivation layer (500) on the surface, and the passivation layer (500) is used for isolating the ASIC driving circuit unit (200) from the contact with external air.

3. The integrated MEMS and ASIC package structure of claim 2, wherein, The SOI wafer (100) is provided with a groove (140), and the MEMS resonator unit (300) is provided with a cantilever beam (310) located above the groove (140).

4. A method of fabricating a package structure integrating a MEMS and an ASIC, the method comprising: The method comprises: An SOI wafer (100) is provided, and the surface of the top layer silicon (130) of the SOI wafer (100) is divided into a first area and a second area; An ASIC driving circuit unit (200) is made in the first area; A MEMS resonator unit (300) is made in the second area and connected with the ASIC driving circuit unit (200) through a metal connecting layer (400).

5. The method of claim 4, wherein: The thickness of the substrate silicon (110) in the SOI wafer is 300-800 microns, the thickness of the buried oxygen layer (120) is 1-5 microns, and the thickness of the top layer silicon (130) is 2-20 microns.

6. The method of claim 5, wherein: The ASIC driving circuit unit (200) is made in the first area on the top layer silicon (130) by using a 40-80 nanometer process CMOS process. After the ASIC driving circuit unit (200) is made in the first area, a passivation material is used for passivation treatment of the ASIC driving circuit unit (200) to form a passivation layer (500) on the surface of the ASIC driving circuit unit (200), and the passivation layer (500) on the PAD electrode (210) in the ASIC driving circuit unit (200) is removed through a photoetching and etching process.

7. The method of claim 6, wherein: The ASIC driving circuit unit (200) is made in the first area, and the ASIC driving circuit unit (200) is made in the first area.

8. The method of claim 7, wherein: A bottom electrode metal layer (410) is deposited on the surface of the top layer silicon (130) by using a deposition process, and the bottom electrode metal layer (410) in the second area is subjected to a patterning treatment; A piezoelectric layer metal layer (420) is deposited on the top of the bottom electrode metal layer (410) by using a deposition process; ​ A top electrode metal layer (430) is deposited on top of the piezoelectric layer metal layer (420) by a deposition process, and the top electrode metal layer (430) in the second region is patterned; The metal connection layer (400) includes a bottom electrode metal layer (410), a piezoelectric layer metal layer (420), and a top electrode metal layer (430), and the metal connection layer (400) in the second region is removed by a photolithography and etching process to release the cantilever beam (310) and obtain the MEMS resonator unit (300). The metal connection layer (400) in the first region is removed by a photolithography and etching process to only retain the metal connection layer (400) for connecting the PAD electrode (210) in the ASIC driving circuit and the MEMS resonator unit (300), so that the MEMS resonator unit (300) is connected to the ASIC driving circuit.

9. The method of claim 8, wherein: The metal connection layer (400) in the second region is removed by a photolithography and etching process to release the cantilever beam (310) and obtain the MEMS resonator unit (300), specifically, After the metal connection layer (400) in the second region is removed by a photolithography and etching process, the top layer silicon (130) and the buried oxide layer (120) of the SOI wafer (100) are etched by an etching process to obtain a groove (140), thereby releasing the cantilever beam (310) and obtaining the MEMS resonator unit (300).

10. The method of claim 9, wherein: The bottom electrode metal layer (410) is made of molybdenum, the piezoelectric layer metal layer (420) is made of aluminum nitride, and the top electrode metal layer (430) is made of molybdenum.

Images