Optoelectronic chip and manufacturing method therefor

Abstract

An optoelectronic chip and a manufacturing method therefor. The optoelectronic chip comprises: a substrate (10); a plurality of light-emitting units (20), which are linearly arranged and formed on a first surface (10a) of the substrate (10), each light-emitting unit (20) comprising a first reflective layer (21), an active layer (22), a confinement layer (23) and a second reflective layer (24); a first electrode (30), which is electrically connected to the second reflective layers (24) of the plurality of light-emitting units (20), the first electrode (30) comprising a bonding electrode region (30a); an isolation layer (40), which is formed on a second surface (10b) of the substrate (10), the isolation layer being provided with a window (41) which penetrates therethrough so as to expose the substrate (10); and a second electrode (50), which is formed on the surface of the isolation layer (40) and which is in ohmic contact connection with the substrate (10) via the window (41). In the arrangement direction of the plurality of light-emitting units (20), the ohmic contact area between the second electrode (50) and the substrate (10) tends to increase in a direction away from the bonding electrode region (30a).

Description

Optoelectronic chip and method for manufacturing the same

[0001] Related applications

[0002] The present application claims priority to the Chinese patent application No. 202411026104.X, filed on July 30, 2024, and entitled "Optoelectronic chip and method for manufacturing the same", the content of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present application belongs to the technical field of semiconductor devices, and specifically relates to an optoelectronic chip and a method for manufacturing the same. BACKGROUND

[0004] Vertical cavity surface emitting lasers (VCSEL) are used in optical communications, optical parallel processing, optical connection, 3D face recognition, automotive radar, etc. Laser diodes used in communication modules are designed to operate at low current. However, when such VCSEL lasers are applied to 3D face recognition, structured light, LIDAR sensors, a larger device area and a higher operating current are required to achieve a greater optical output power. This also causes problems of reduced conversion efficiency and increased threshold current.

[0005] In the prior art, attempts have been made to change VCSEL from a single array lighting to a one-dimensional addressable control device by row and column by using partitioning technology, etc. In this way, the advantages of addressability can be utilized to achieve individual capture and analysis of information in each region. The following advantages are achieved:

[0006] - System power consumption can be saved by effectively controlling the light-emitting area;

[0007] - Better heat dissipation performance and better light-emitting efficiency;

[0008] - Reducing unnecessary object glare;

[0009] - Through appropriate system design, system-level anti-interference capability can be achieved, and the spatial resolution of ToF / LIDAR is improved, etc.

[0010] However, for the one-dimensional addressable control device in the prior art, when using a line-shaped partition, especially a long line-shaped partition, the metal electrode needs to diffuse the current to a very long distance. Due to the impedance of the electrode itself, the current density received by the emission holes close to the bonding pad and the emission holes far away from the bonding pad will be different. On the other hand, all the emission holes are designed to have the same size, so under the same driving condition, the light emitted by the emission holes at the near end and the far end will be different, affecting the uniformity of the light emitted by the device.

[0011] The information disclosed in this Background section is only for the purpose of increasing an understanding of the general background of the present application and should not be taken as an acknowledgement or any form of suggestion that this information forms the general knowledge of those skilled in the art before the present application was made. SUMMARY

[0012] The present application aims to provide an optoelectronic chip and a preparation method thereof, which can solve the problem of uneven light emission of a device caused by uneven current density of each emission hole due to different current transmission distances (different first current spreading resistances) of the first electrode (metal electrode in the background section).

[0013] To achieve the above-mentioned purpose, one embodiment of the present application provides an optoelectronic chip, comprising: a substrate having a first surface and a second surface arranged oppositely; a plurality of light emitting units arranged in a line on the first surface of the substrate, each of the light emitting units comprising, in sequence in a direction away from the substrate, a first reflective layer, an active layer, a confinement layer having an emission hole, and a second reflective layer; a first electrode electrically connected to the second reflective layer of the plurality of light emitting units, the first electrode comprising a bonding electrode region located at one end or both ends of the plurality of light emitting units; an isolation layer formed on the second surface of the substrate, the isolation layer having one or more windows formed therethrough to expose the substrate; and a second electrode formed on the surface of the isolation layer and in ohmic contact with the substrate through the windows; wherein, in the arrangement direction of the plurality of light emitting units, the ohmic contact area between the second electrode and the substrate increases in a direction away from the bonding electrode region.

[0014] In one or more embodiments of the present application, the isolation layer has one window formed thereon; the shape of the window is arranged such that, in the arrangement direction of the plurality of light emitting units, the size of the substrate exposed by the window increases in a stepped, linear, or irregular manner in a direction away from the bonding electrode region.

[0015] In one or more embodiments of the present application, the isolation layer has a plurality of windows formed thereon; in the arrangement direction of the plurality of light emitting units, the size of the plurality of windows increases in a stepped, linear, or irregular manner in a direction away from the bonding electrode region.

[0016] In one or more embodiments of the present application, the isolation layer has a plurality of windows formed thereon; in the arrangement direction of the plurality of light emitting units, the distribution density of the plurality of windows increases in a stepped, linear, or irregular manner in a direction away from the bonding electrode region.

[0017] In one or more embodiments of the present application, the sizes of the plurality of windows are the same; or the sizes of the plurality of windows increase in a stepwise manner or linearly or irregularly in a direction away from the bonding electrode region.

[0018] In one or more embodiments of the present application, the sizes of the plurality of windows are the same; or the sizes of the plurality of windows increase in a stepwise manner or linearly or irregularly in a direction away from the bonding electrode region.

[0019] In one or more embodiments of the present application, the sizes of the plurality of windows are the same; or the sizes of the plurality of windows increase in a stepwise manner or linearly or irregularly in a direction away from the bonding electrode region.

[0020] In one or more embodiments of the present application, the sizes of the plurality of windows are the same; or the sizes of the plurality of windows increase in a stepwise manner or linearly or irregularly in a direction away from the bonding electrode region.

[0021] In one or more embodiments of the present application, the sizes of the plurality of windows are the same; or the sizes of the plurality of windows increase in a stepwise manner or linearly or irregularly in a direction away from the bonding electrode region.

[0022] In one or more embodiments of the present application, the sizes of the plurality of windows are the same; or the sizes of the plurality of windows increase in a stepwise manner or linearly or irregularly in a direction away from the bonding electrode region.

[0023] Yet another specific embodiment of the present application provides a preparation method of the photoelectric chip, comprising: providing a substrate, the substrate having a first surface and a second surface arranged oppositely; forming an epitaxial structure on the first surface of the substrate, the epitaxial structure comprising a first reflective layer, an active layer, a confinement layer and a second reflective layer in sequence; etching the epitaxial structure to the second reflective layer to form a plurality of mesa structures; oxidizing the mesa structures to form emission holes in the confinement layer; forming an insulating layer on the surface of the mesa structure, the insulating layer exposing the emission holes; forming a first electrode on the surface of the insulating layer, the first electrode extending in a first direction and being electrically connected to the second reflective layer of a plurality of light emitting units, the first electrode comprising a bonding electrode region; forming a separation layer on the second surface of the substrate, and forming one or more windows penetrating through the separation layer and exposing the substrate, the one or more windows being arranged such that, in the extending direction of the first electrode, the exposed area of the substrate shows an increasing trend in the direction away from the bonding electrode region; and forming a second electrode on the surface of the separation layer, the second electrode being in ohmic contact with the substrate through the window.

[0024] Compared with the prior art, the photoelectric chip and the preparation method thereof provided by the embodiments of the present application compensate for the problem of uneven current density of each emission hole caused by different current transmission distances (different first current spreading resistances) of the first electrode by designing the position and area size of the ohmic contact region between the second electrode and the substrate, thereby avoiding the problem of uneven light emission of the device.

[0025] The photoelectric chip and the preparation method thereof provided by the embodiments of the present application purposefully change the position and area size of the ohmic contact region of the second electrode. At one end close to the bonding electrode region, the ohmic contact area is small or there is no ohmic contact, and in the direction gradually away from the bonding electrode region, the ohmic contact area gradually increases, so as to adjust the second current spreading resistance and the ohmic contact resistance of the substrate on the back side (the side where the second electrode is located), balance the problem of uneven current caused by different current transmission distances (different first current spreading resistances) of the first electrode, and make the light emission of all emission holes of the entire device more uniform.

[0026] The photoelectric chip and the preparation method thereof provided by the embodiments of the present application are also designed to have a smaller ohmic contact area or no ohmic contact close to the bonding electrode region and a gradually increasing ohmic contact area towards the center of the bonding electrode region for the structure in which the bonding electrode region is arranged at both ends, and can also adjust the second current spreading resistance and the ohmic contact resistance of the substrate on the back side (the side where the second electrode is located), so as to make the light emission of all emission holes of the entire device more uniform. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to make the technical solutions in the application or the prior art clearer, the accompanying drawings needed in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments described in the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0028] Fig. 1 is a top view of an optoelectronic chip according to an embodiment of the application;

[0029] Fig. 2 is a partial cross-sectional view of an optoelectronic chip according to an embodiment of the application;

[0030] Figs. 3a-3f are schematic views of different isolation layer structures of an optoelectronic chip (with a bonding electrode region at one end) according to an embodiment of the application;

[0031] Figs. 4a-4f are schematic views of different isolation layer structures of an optoelectronic chip (with a bonding electrode region at both ends) according to an embodiment of the application;

[0032] Fig. 5 is a top view of an optoelectronic chip according to another embodiment of the application;

[0033] Fig. 6 is a schematic view of different isolation layer structures of an optoelectronic chip (with a bonding electrode region at one end) according to another embodiment of the application;

[0034] Fig. 7 is a schematic view of different isolation layer structures of an optoelectronic chip (with a bonding electrode region at both ends) according to an embodiment of the application. DETAILED DESCRIPTION

[0035] In order to make those skilled in the art better understand the technical solutions in the application, the technical solutions in the embodiments of the application will be described clearly and completely with reference to the accompanying drawings of the embodiments of the application. Obviously, the described embodiments are only some embodiments of the application, but not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor should fall within the scope of protection of the application.

[0036] First, some professional terms possibly involved in the application will be explained:

[0037] Addressable: the array of emission holes on the entire device is divided into several regions (rows or columns), each region can be individually or simultaneously individually lit.

[0038] As described in the background, for the one-dimensional addressable control device in the prior art, when using a linear partition, especially a long linear partition, the metal electrode needs to spread the current to a very long distance. Due to the impedance of the electrode itself, the current density received by the emission hole close to the bonding pad and the emission hole far away from the bonding pad will be different. On the other hand, all the emission holes are designed to have the same size, so under the same driving condition, the light emitted by the near-end and far-end emission holes will be different, affecting the uniformity of the light emitted by the device.

[0039] The solution to this technical problem in the prior art is to arrange the bonding pads at both ends of the same row or column. However, this solution still has the following shortcomings: 1) The additional bonding pads need to occupy additional device area, reducing the number of chips that can be produced from each wafer, indirectly increasing production costs; 2) For a longer linear partition, although the bonding pads are arranged at both ends, the current still encounters the above-mentioned problem when transmitted to the middle of the region.

[0040] Based on this, the present application provides an optoelectronic chip and a preparation method thereof. By designing the size and area of the ohmic contact region between the second electrode and the substrate, the position and area of the ohmic contact region of the second electrode are purposefully set to change. At one end close to the bonding pad region, the ohmic contact area is small or there is no ohmic contact, and in the direction gradually away from the bonding pad region, the ohmic contact area gradually increases, thereby adjusting the second current spreading resistance and ohmic contact resistance of the back surface (the side where the second electrode is located) substrate, compensating for the problem of uneven current density of each emission hole caused by different current transmission distances (different first current spreading resistances) on the first electrode, and making the light emitted by all the emission holes of the entire device more uniform.

[0041] Referring to FIGS. 1 and 2, an embodiment of the present application provides an optoelectronic chip, which includes a substrate 10, a plurality of light emitting units 20 arranged in a line, a first electrode 30, a separation layer 40, and a second electrode 50.

[0042] The substrate 10 has a first surface 10a and a second surface 10b arranged opposite to each other. The substrate 10 can be made of any conductive semiconductor material, such as GaAs, etc.

[0043] The plurality of light emitting units 20 arranged in a line are formed on the first surface 10a of the substrate 10, and the plurality of light emitting units 20 arranged in a line constitute a partition (which can be a row or a column) in the addressable device. Each light emitting unit 20 includes, in sequence in the direction away from the substrate 10, a first reflective layer 21, an active layer 22, a confinement layer 23 having an emission hole, and a second reflective layer 24.

[0044] The first reflective layer 21 of all the light emitting units 20 and the substrate 10 are connected to make the plurality of light emitting units 20 integrally connected. The second reflective layer 24, the confinement layer 23 with the emission hole and the active layer 22 of each light emitting unit 20 are etched into a mesa structure (exposing the first reflective layer 21, and the emission hole is formed by oxidizing the confinement layer 23 after etching).

[0045] The above description is only one specific embodiment of the light emitting unit 20 of the present application, but the present application does not limit the light emitting unit 20 to only the structure described above, as long as the structure of the light emitting unit 20 containing the structure described above and having the light emitting function is within the protection scope of the present application.

[0046] The first electrode 30 is electrically connected to the second reflective layer 24 of the plurality of light emitting units 20. The first electrode 30 extends from the surface of the second reflective layer 24 to the surface of the first reflective layer 21 from the side of the mesa structure. The first electrode 30 is electrically isolated from the side of the mesa structure and the surface of the first reflective layer 21 by the insulating layer 60.

[0047] All the light emitting units 20 share one first electrode 30. The first electrode 30 includes a bonding electrode area 30a located at one end or both ends of the partition formed by the plurality of light emitting units 20. The bonding electrode area 30a is used for subsequent electrical connection with the outside during the packaging of the optoelectronic chip, that is, the bonding electrode area 30a is the injection point of the external current.

[0048] The isolation layer 40 is formed on the second surface 10b of the substrate 10. The material of the isolation layer 40 can be selected from insulating materials such as SiO2 or SiN. One or more windows 41 are formed on the isolation layer 40 to expose the substrate 10, as shown in FIGS. 3a-3f and 4a-4f.

[0049] The second electrode 50 is formed on the surface of the isolation layer 40 and is electrically connected between the substrate 10 through the window 41. In the arrangement direction of the plurality of light emitting units 20, the ohmic contact area between the second electrode 50 and the substrate 10 increases in the direction away from the bonding electrode area 30a. Optionally, the second electrode 50 and the substrate 10 do not have ohmic contact at the position corresponding to the bonding electrode area 30a, and more preferably, the second electrode 50 and the substrate 10 do not have ohmic contact within a certain range close to the bonding electrode area 30a. The certain range can be obtained according to the specific device structure required and the corresponding data calculation.

[0050] In a specific embodiment, only one window 41 is formed on the isolation layer 40. In order to realize the increasing trend of the ohmic contact area between the second electrode 50 and the substrate 10 in the direction away from the bonding electrode area 30a, the shape of the window 41 is set as: in the arrangement direction of the plurality of light emitting units 20, the size of the substrate 10 exposed by the window 41 increases in a stepped manner or a linear manner or an irregular form in the direction away from the bonding electrode area 30a.

[0051] For example, referring to FIGS. 3a and 4a, the shape of the window 41 is triangular, and the tip direction of the window 41 is toward the direction where the bonding electrode area 30a is located, so that the window 41 presents a state of large opening area in the area far away from the bonding electrode area 30a, and small opening area or no opening in the area close to the bonding electrode area 30a (linear increase).

[0052] For another example, referring to FIGS. 3b and 4b, the shape of the window 41 is a double-sided stepped structure with a stepped increase in pitch, and the side with smaller pitch of the window 41 is toward the direction where the bonding electrode area 30a is located, so that the window 41 presents a state of large opening area in the area far away from the bonding electrode area 30a, and small opening area or no opening in the area close to the bonding electrode area 30a (stepped increase).

[0053] For yet another example, referring to FIGS. 3c and 4c, the shape of the window 41 is a double-sided stepped structure with an irregular increase in pitch, and the side with smaller pitch of the window 41 is toward the direction where the bonding electrode area 30a is located, so that the window 41 presents a state of large opening area in the area far away from the bonding electrode area 30a, and small opening area or no opening in the area close to the bonding electrode area 30a (irregular form increase).

[0054] In yet another specific embodiment, a plurality of windows 41 are formed on the isolation layer 40. In order to realize the increasing trend of the ohmic contact area between the second electrode 50 and the substrate 10 in the direction away from the bonding electrode area 30a, the shape of the window 41 is set as: in the arrangement direction of the plurality of light emitting units 20, the size of the plurality of windows 41 increases in a stepped manner or a linear manner or an irregular form in the direction away from the bonding electrode area 30a.

[0055] For example, referring to FIGS. 3d and 4d, the shapes of the plurality of windows 41 are all circular but with different diameters. In the area close to the bonding electrode area 30a, the diameters of the windows 41 are small, and in the direction away from the bonding electrode area 30a, the diameters of the windows 41 become larger and larger. So that the window 41 presents a state of large opening area in the area far away from the bonding electrode area 30a, and small opening area or no opening in the area close to the bonding electrode area 30a.

[0056] For example, referring to Figs. 3e and 4e, the plurality of windows 41 have different shapes and sizes. In the region close to the bonding electrode region 30a, the area of the windows 41 is small, and the area of the windows 41 increases in the direction away from the bonding electrode region 30a. Thus, the windows 41 have a large opening area in the region far from the bonding electrode region 30a, and a small opening area or no opening in the region close to the bonding electrode region 30a.

[0057] In another embodiment, the isolation layer 40 also has a plurality of windows 41. In order to increase the ohmic contact area between the second electrode 50 and the substrate 10 in the direction away from the bonding electrode region 30a, the windows 41 are arranged in a stepped, linear or irregular manner in the direction away from the bonding electrode region 30a.

[0058] Optionally, the plurality of windows 41 have the same size, or the size of the plurality of windows 41 increases in a stepped, linear or irregular manner in the direction away from the bonding electrode region 30a.

[0059] For example, referring to Figs. 3f and 4f, the windows 41 include a square window and a plurality of circular windows, and the plurality of circular windows include a first circular window having a large area and a second circular window having a small area. The square window is arranged in the region farthest from the bonding electrode region 30a, the plurality of first circular windows are arranged in the middle region, and the plurality of second circular windows are arranged in the region close to the bonding electrode region 30a.

[0060] It can be understood that the factors affecting the luminous intensity of the light emitting unit of the optoelectronic chip include the resistance of the current path from the front side (the side of the first electrode) to the emission hole (hereinafter referred to as the first current spreading resistance), the internal resistance of the light emitting unit, the resistance of the current path from the emission hole to the second electrode on the back side (hereinafter referred to as the second current spreading resistance), and the ohmic contact resistance between the substrate and the second electrode on the back side. Of course, the current on the back side (the side of the second electrode) also has a resistance when transmitted in the second electrode, but the resistance of the second electrode is negligible because the second electrode is a relatively ideal conductor.

[0061] Since the size of the light emitting units is the same, the internal resistance of each light emitting unit is the same for all the light emitting units 20 on the substrate, but the size of the current spreading resistance (including the first current spreading resistance and the second current spreading resistance) is related to the transmission path of the current, so for the first current spreading resistance on the side of the first electrode, the first current spreading resistance of the light emitting unit closer to the bonding electrode area 30a (the injection point of the external current) is smaller, and the first current spreading resistance of the light emitting unit farther from the bonding electrode area 30a (the injection point of the external current) is larger.

[0062] The arrangement position of the light emitting units in the same sub-area (a row or a column) is fixed, so the first current spreading resistance corresponding to each light emitting unit 30 on the first electrode is determined, that is, the farther from the bonding electrode area 30a (the injection point of the external current), the larger the first current spreading resistance.

[0063] Since the voltage applied between the first electrode 30 and the second electrode 50 is the same, the current of the light emitting unit with a larger first current spreading resistance is smaller, so the luminance of the emission hole of the light emitting unit is lower.

[0064] In order to keep the luminance of the multiple light emitting units consistent and improve the light emission uniformity of the whole device, the present application changes the size of the second current spreading resistance and the ohmic contact resistance formed on the substrate after the current passing through each light emitting unit 30 according to the size of the first spreading resistance corresponding to each light emitting unit 30, and designs the position (which affects the transmission distance of the current in the substrate - the size of the second current spreading resistance) and the area size (which affects the ohmic contact resistance) of the ohmic contact area between the second electrode and the substrate, so as to change the second current spreading resistance and the ohmic contact resistance, balance the first current spreading resistance, and compensate for the current density unevenness problem of each emission hole caused by the different current transmission distances (different first current spreading resistances) on the first electrode, thereby avoiding the problem of uneven light emission of the device.

[0065] The present application changes the ohmic contact position and area between the second electrode and the substrate through the isolation layer and the window thereon, so that the current can only flow out from the second electrode at the window after flowing through the substrate, and the position of the window and the size of the window can affect the transmission path of the current in the substrate, thereby balancing the current distribution unevenness problem caused by the first current spreading resistance by adjusting the flow path of the current passing through the light emitting unit 30 close to the bonding electrode area in the substrate when flowing to the second electrode.

[0066] As shown in FIG. 5 and FIG. 2, the present application provides a photoelectric chip, which comprises a substrate 10, a plurality of light emitting units 20 arranged in an array, a plurality of first electrodes 30, an isolation layer 40 and a second electrode 50. The plurality of first electrodes 30 respectively extend in the first direction or the second direction (in a row or in a column) and are electrically connected to the second reflective layer 24 of the plurality of light emitting units 20 to form a plurality of light emitting unit groups in series. One light emitting unit group has only one first electrode 30.

[0067] The substrate 10 has a first surface 10a and a second surface 10b arranged oppositely. The material of the substrate 10 can be any conductive semiconductor material, such as GaAs, etc.

[0068] The plurality of light emitting units 20 arranged in an array are formed on the first surface 10a of the substrate 10. The plurality of light emitting units 20 arranged in an array can be divided into several rows or columns in the first direction or the second direction, and each row or column can be individually or simultaneously individually lighted. Each light emitting unit 20 sequentially has a first reflective layer 21, an active layer 22, a confinement layer 23 with an emission hole and a second reflective layer 24 in the direction away from the substrate 10.

[0069] The first reflective layer 21 of all the light emitting units 20 is connected to the substrate 10 to make the plurality of light emitting units 20 integrally connected. The second reflective layer 24, the confinement layer 23 with an emission hole and the active layer 22 of each light emitting unit 20 are etched into a mesa structure (exposing the first reflective layer 21, and the emission hole is formed by oxidizing the confinement layer 230 after etching).

[0070] The above description is only one specific embodiment of the light emitting unit 20 of the present application, but the present application does not limit the light emitting unit 20 to only the structure described above. As long as the structure of the light emitting unit 20 contains the structure described above and has the light emitting function, it is within the protection scope of the present application.

[0071] Each first electrode 30 extends in the first direction (in a row) and is electrically connected to the second reflective layer 24 of the plurality of light emitting units 20 to form a light emitting unit group in series. The first electrode 30 extends from the surface of the second reflective layer 24 of the light emitting unit 20 in the light emitting unit group to the surface of the first reflective layer 21 from the side of the mesa structure. The first electrodes 30 of the plurality of light emitting unit groups are electrically isolated. In each light emitting unit group, the first electrode 30 is electrically isolated from the side of the mesa structure and the surface of the first reflective layer 21 by the insulating layer 60.

[0072] All the light emitting units 20 in each group of light emitting units (a row or a column) share one first electrode 30. Each first electrode 30 includes a bonding electrode area 30a at one or both ends of the group of light emitting units; the bonding electrode area 30a is used for electrical connection with the outside during subsequent photoelectric chip packaging, i.e., the bonding electrode area 30a is the injection point of external current.

[0073] An isolation layer 40 is formed on the second surface 10b of the substrate 10, and the material of the isolation layer 40 can be an insulating material such as SiO2 or SiN. In each group of light emitting units (a row or a column), one or more windows 41 are formed in the isolation layer 40 to expose the substrate 10, as shown in FIGS. 6 and 7.

[0074] A second electrode 50 is formed on the surface of the isolation layer 40 and is electrically connected between the substrate 10 through the window 41; in each group of light emitting units, the area of ohmic contact between the second electrode 50 and the substrate 10 increases in the direction away from the bonding electrode area 30a. Optionally, the second electrode 50 and the substrate 10 do not have ohmic contact at the position corresponding to the bonding electrode area 30a, or more preferably, the second electrode 50 and the substrate 10 do not have ohmic contact within a certain range close to the bonding electrode area 30a. The certain range can be obtained according to the specific device structure and corresponding data calculation.

[0075] In a specific embodiment, in each group of light emitting units (a row or a column), only one window 41 is formed in the isolation layer 40. In order to achieve the increasing trend of the area of ohmic contact between the second electrode 50 and the substrate 10 in the direction away from the bonding electrode area 30a, the shape of the window 41 is set as follows: in each group of light emitting units (a row or a column), the size of the substrate 10 exposed by the window 41 increases in a stepped, linear, or irregular manner in the direction away from the bonding electrode area 30a.

[0076] For example, referring to FIGS. 6 and 7, the shape of the window 41 is a triangle, and the tip of the window 41 is directed toward the direction of the bonding electrode area 30a, so that the window 41 has a large opening area in the area far from the bonding electrode area 30a and a small opening area or no opening in the area close to the bonding electrode area 30a (linear increase).

[0077] For another example, the shape of the window 41 is a double-sided stepped structure with a gradually increasing interval, and the side with a smaller interval of the window 41 is directed toward the direction of the bonding electrode area 30a, so that the window 41 has a large opening area in the area far from the bonding electrode area 30a and a small opening area or no opening in the area close to the bonding electrode area 30a (stepped increase), as shown in FIGS. 3b and 4b.

[0078] For example, the shape of the window 41 is a double-sided stepped structure with irregularly increasing intervals, the side with smaller intervals of the window 41 is directed towards the direction of the bonding electrode area 30a, so that the window 41 presents a state of larger opening area in the area far from the bonding electrode area 30a and smaller opening area or no opening in the area close to the bonding electrode area 30a (irregularly increasing), as shown in FIGS. 3c and 4c.

[0079] In yet another embodiment, a plurality of windows 41 are formed on the isolation layer 40 within each group of light emitting unit groups (a row or a column). In order to achieve the increasing trend of the ohmic contact area between the second electrode 50 and the substrate 10 in the direction away from the bonding electrode area 30a, the shape of the window 41 is set as: within each group of light emitting unit groups (a row or a column), the size of the plurality of windows 41 increases in a stepped manner or linearly or irregularly in the direction away from the bonding electrode area 30a.

[0080] For example, the shape of the plurality of windows 41 is circular but with different diameters. In the area close to the bonding electrode area 30a, the diameter of the window 41 is small, and in the direction away from the bonding electrode area 30a, the diameter of the window 41 becomes larger and larger. So that the window 41 presents a state of larger opening area in the area far from the bonding electrode area 30a and smaller opening area or no opening in the area close to the bonding electrode area 30a, as shown in FIGS. 3d and 4d.

[0081] For example, the shape of the plurality of windows 41 is circular but with different diameters. In the area close to the bonding electrode area 30a, the diameter of the window 41 is small, and in the direction away from the bonding electrode area 30a, the diameter of the window 41 becomes larger and larger. So that the window 41 presents a state of larger opening area in the area far from the bonding electrode area 30a and smaller opening area or no opening in the area close to the bonding electrode area 30a, as shown in FIGS. 3d and 4d.

[0082] In yet another embodiment, a plurality of windows 41 are formed on the isolation layer 40 within each group of light emitting unit groups (a row or a column). In order to achieve the increasing trend of the ohmic contact area between the second electrode 50 and the substrate 10 in the direction away from the bonding electrode area 30a, the shape of the window 41 is set as: within each group of light emitting unit groups (a row or a column), the size of the plurality of windows 41 increases in a stepped manner or linearly or irregularly in the direction away from the bonding electrode area 30a.

[0083] Optionally, the size of the plurality of windows 41 is the same; or, the size of the plurality of windows 41 also increases in a stepped manner or linearly or irregularly in the direction away from the bonding electrode area 30a.

[0084] For example, the window 41 includes a square window and a plurality of circular windows, the plurality of circular windows are divided into a first circular window with a larger area and a second circular window with a smaller area. The square window is arranged in the area farthest from the bonding electrode area 30a, the plurality of first circular windows are arranged in the middle area, and the plurality of second circular windows are arranged in the area close to the bonding electrode area 30a. Please refer to FIGS. 3f and 4f.

[0085] The present application also provides an optoelectronic chip. The difference between the present embodiment and the above-mentioned embodiments shown in FIG. 5 or FIG. 1 is that, in the present embodiment, the second electrode 50 does not completely cover the surface of the insulating layer 40, but only covers the window 41 of the insulating layer 40. For example, when the number of windows 41 is one, please refer to FIGS. 3a-3c, 4a-4c, the shape of the second electrode 50 is basically consistent or completely consistent with the shape of the window 41; when the number of windows 41 is multiple, the second electrodes 50 covering each window 41 are in contact to achieve electrical communication.

[0086] The present application also provides a preparation method of the above-mentioned optoelectronic chip, specifically including the following steps:

[0087] providing a substrate, the substrate having a first surface and a second surface arranged oppositely;

[0088] forming an epitaxial structure on the first surface of the substrate, the epitaxial structure including a first reflective layer, an active layer, a confinement layer and a second reflective layer in sequence;

[0089] etching the epitaxial structure to the second reflective layer to form a plurality of mesa structures;

[0090] oxidizing the mesa structure to form an emission hole in the confinement layer;

[0091] forming an insulating layer on the surface of the mesa structure, the insulating layer exposing the emission hole;

[0092] forming a first electrode on the surface of the insulating layer, the first electrode extending in a first direction and electrically connecting the second reflective layer of a plurality of light emitting units, the first electrode including a bonding electrode area;

[0093] forming an isolation layer on the second surface of the substrate, and forming one or more windows penetrating through the isolation layer and exposing the substrate, the one or more windows being arranged such that, in the extension direction of the first electrode, the area of the substrate exposed increases in the direction away from the bonding electrode area;

[0094] forming a second electrode on the surface of the isolation layer, the second electrode being electrically connected to the substrate through the window.

[0095] Compared with the prior art, the photoelectric chip and the preparation method thereof provided by the embodiment of the present application compensate for the problem of uneven current density of each emission hole caused by different current transmission distances (different first current spreading resistances) on the first electrode by designing the ohmic contact area and the size of the second electrode and the substrate, thereby avoiding the problem of uneven light emission of the device.

[0096] The photoelectric chip and the preparation method thereof provided by the embodiment of the present application purposefully change the position and the size of the ohmic contact area of the second electrode, that is, the ohmic contact area is small or there is no ohmic contact near one end of the bonding electrode area, and the ohmic contact area gradually increases in the direction away from the bonding electrode area, thereby adjusting the second current spreading resistance and the ohmic contact resistance of the substrate on the back side (the side where the second electrode is located), balancing the problem of uneven current caused by different current transmission distances (different first current spreading resistances) on the first electrode, and making the light emission of all emission holes of the entire device more uniform.

[0097] The photoelectric chip and the preparation method thereof provided by the embodiment of the present application are also designed to have a small ohmic contact area or no ohmic contact near the bonding electrode area and a gradually increasing ohmic contact area in the direction from the two ends to the center of the bonding electrode area for the structure in which the bonding electrode area is arranged at both ends, thereby also adjusting the second current spreading resistance and the ohmic contact resistance of the substrate on the back side (the side where the second electrode is located), and making the light emission of all emission holes of the entire device more uniform.

[0098] It is apparent for those skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, and the present application can be implemented in other concrete forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all aspects as illustrative and not restrictive, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended to encompass all changes falling within the meaning and range of equivalents of the elements of the claims. Any reference signs in the claims should not be considered as limiting the claims involved.

[0099] In addition, it should be understood that, although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the specification is described in this way only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. An optoelectronic chip, comprising: a substrate having a first surface and a second surface oppositely arranged; a plurality of light emitting units arranged in a line on the first surface of the substrate, each of the light emitting units comprising, in sequence along a direction away from the substrate, a first reflective layer, an active layer, a confinement layer having an emission aperture, and a second reflective layer; a first electrode electrically connected to the second reflective layers of the plurality of light emitting units, the first electrode comprising a bonding electrode region located at one or both ends of the plurality of light emitting units; an isolation layer formed on the second surface of the substrate, the isolation layer having one or more windows formed therethrough to expose the substrate; and a second electrode formed on a surface of the isolation layer and in ohmic contact with the substrate through the windows; wherein, in a direction of arrangement of the plurality of light emitting units, an area of ohmic contact between the second electrode and the substrate has a tendency to increase in a direction away from the bonding electrode region. one of the windows is formed on the isolation layer; a shape of the window is configured such that, in the direction of arrangement of the plurality of light emitting units, a size of the substrate exposed by the window has a tendency to increase in a stepped, linear, or irregular manner in the direction away from the bonding electrode region. a plurality of the windows are formed on the isolation layer; in the direction of arrangement of the plurality of light emitting units, sizes of the plurality of the windows have a tendency to increase in a stepped, linear, or irregular manner in the direction away from the bonding electrode region. a plurality of the windows are formed on the isolation layer; in the direction of arrangement of the plurality of light emitting units, a distribution density of the plurality of the windows has a tendency to increase in a stepped, linear, or irregular manner in the direction away from the bonding electrode region.

2. The optoelectronic chip of claim 1, wherein, the sizes of the plurality of the windows are the same; or the sizes of the plurality of the windows have a tendency to increase in a stepped, linear, or irregular manner in the direction away from the bonding electrode region.

3. The optoelectronic chip of claim 1, wherein, 6.An optoelectronic chip, comprising: a substrate having a first surface and a second surface oppositely arranged; a plurality of light emitting units arranged in an array on the first surface of the substrate, each of the light emitting units comprising, in sequence along a direction away from the substrate, a first reflective layer, an active layer, a confinement layer having an emission aperture, and a second reflective layer; a plurality of first electrodes each extending in a first direction and electrically connected to the second reflective layers of a plurality of the light emitting units to form a group of light emitting units in series, each of the first electrodes comprising a bonding electrode region located at one or both ends of the group of light emitting units; an isolation layer formed on the second surface of the substrate, the isolation layer having one or more windows formed therethrough to expose the substrate within each of the groups of light emitting units; and a second electrode formed on a surface of the isolation layer and in ohmic contact with the substrate through the windows; wherein, in each of the groups of light emitting units, an area of ohmic contact between the second electrode and the substrate has a tendency to increase in a direction away from the bonding electrode region. one of the windows is formed on the isolation layer within each of the groups of light emitting units.

4. The optoelectronic chip of claim 1, wherein, ​ ​ 5. The optoelectronic chip of claim 4, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ 7. The optoelectronic chip of claim 6, wherein, ​ The shape of the window is set to: in each group of the light emitting unit group, the size of the substrate exposed by the window increases in a stepwise manner or linearly or irregularly in the direction away from the bonding electrode area.

8. The optoelectronic chip of claim 6, wherein, In each group of the light emitting unit group, a plurality of the windows are formed on the isolation layer; In each group of the light emitting unit group, the size of the plurality of the windows increases in a stepwise manner or linearly or irregularly in the direction away from the bonding electrode area.

9. The optoelectronic chip of claim 6, wherein, In each group of the light emitting unit group, a plurality of the windows are formed on the isolation layer; In each group of the light emitting unit group, the distribution density of the plurality of the windows increases in a stepwise manner or linearly or irregularly in the direction away from the bonding electrode area.

10. The optoelectronic chip of claim 9, wherein, In each group of the light emitting unit group, the size of the plurality of the windows is the same; or, The size of the plurality of the windows increases in a stepwise manner or linearly or irregularly in the direction away from the bonding electrode area.

11. A method for manufacturing the optoelectronic chip according to any one of claims 1-5 or claims 6-10, comprising: providing a substrate, the substrate having oppositely arranged first and second surfaces; forming an epitaxial structure on the first surface of the substrate, the epitaxial structure comprising in order a first reflective layer, an active layer, a confinement layer, and a second reflective layer; etching the epitaxial structure to the second reflective layer to form a plurality of mesa structures; oxidizing the mesa structures to form emission holes in the confinement layer; forming an insulating layer on the surface of the mesa structure, the insulating layer exposing the emission holes; forming a first electrode on the surface of the insulating layer, the first electrode extending in a first direction and electrically connecting the second reflective layer of a plurality of the light emitting units, the first electrode comprising a bonding electrode area; forming an isolation layer on the second surface of the substrate, and forming one or more windows through the isolation layer and exposing the substrate, the one or more windows being arranged such that, in the extending direction of the first electrode, the area of the substrate exposed increases in the direction away from the bonding electrode area; forming a second electrode on the surface of the isolation layer, the second electrode being in ohmic contact with the substrate through the window.

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