CMOS image sensor and imaging device

Abstract

The embodiments of the present application relate to the technical field of image sensors. Provided are a CMOS image sensor and an imaging device, which are used to mitigate the problem of optical crosstalk. The CMOS image sensor comprises a semiconductor substrate, a metal wiring layer and an embedded structure, wherein the semiconductor substrate comprises a first surface and a second surface that are opposite to each other in a first direction, and photodiodes are formed in the semiconductor substrate; and the metal wiring layer is arranged on the outer side of the first surface of the semiconductor substrate. In a region directly facing the photodiodes, the embedded structure is embedded into the semiconductor substrate by means of the first surface; and the embedded structure is made of a non-metallic material, the refractive index of which is lower than that of a semiconductor material of the semiconductor substrate. The CMOS image sensor can be applied to an imaging device.

Description

CMOS image sensor and imaging device

[0001] The present application claims priority to the Chinese patent application No. 202411049617.2, filed on July 31, 2024, entitled "CMOS image sensor and imaging device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of image sensors, in particular to a CMOS image sensor and an imaging device. BACKGROUND

[0003] A CMOS image sensor (CIS) refers to a solid-state imaging chip made of a complementary metal oxide semiconductor (CMOS) process. Compared with a charge coupled device (CCD) image sensor, the CIS has the advantages of low power consumption, easy integration with other devices, fast readout speed, small size, and low cost.

[0004] In a CMOS image sensor, a pixel array formed by a plurality of pixel units is included. The pixel units in the pixel array are used to convert optical signals into electrical signals, thereby realizing the function of imaging. However, when the CMOS image sensor is working, the incident light irradiated to a certain pixel unit may be incident into other pixel units in the transmission process due to reasons such as incident angle, reflection, diffraction, and scattering, and the photoelectric conversion is completed in the other pixel units, thereby generating optical crosstalk. The problem of optical crosstalk between pixel units will cause the image obtained by the CMOS image sensor to have abnormal phenomena such as a decrease in clarity, color cast, color noise, and a checkerboard pattern, thereby affecting the imaging quality. In particular, with the development of semiconductor process technology, CMOS image sensors are gradually evolving towards higher resolution and smaller size. Higher resolution and smaller size of the CMOS image sensor will reduce the distance between adjacent pixel units, thereby further exacerbating the problem of optical crosstalk. SUMMARY

[0005] The present application provides a CMOS image sensor and an imaging device for improving the problem of optical crosstalk.

[0006] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, the embodiments of the present application provide a CMOS image sensor, comprising a semiconductor substrate, a metal circuit layer and an embedded structure, wherein the semiconductor substrate comprises a first surface and a second surface opposite to each other in a first direction, and a photodiode is formed in the semiconductor substrate; the metal circuit layer is arranged outside the first surface of the semiconductor substrate.

[0008] In the region opposite to the photodiode, the embedded structure is embedded into the semiconductor substrate through the first surface; the material of the embedded structure is a non-metal material, and the refractive index is less than the refractive index of the semiconductor material in the semiconductor substrate.

[0009] In the CMOS image sensor provided by the embodiments of the present application, the embedded structure is arranged; due to the material difference between the embedded structure and the semiconductor substrate, the refractive index on both sides of the interface between the embedded structure and the semiconductor substrate has a small-large relationship. Such design can fully reflect the unabsorbed light (light not absorbed by the photodiode in the first pass) transmitted to the embedded structure, so as to limit the unabsorbed light in the semiconductor substrate and improve the problem of light crosstalk caused by the unabsorbed light passing through the metal circuit layer to other pixel units.

[0010] In some embodiments, the embedded structure comprises a plurality of embedded parts arranged in the region opposite to the photodiode. Such design can make the interface between the embedded structure and the semiconductor substrate have an extension feature with high and low relief relative to the second surface, in which case, on the one hand, it is beneficial to increase the number of full reflections of the unabsorbed light, and on the other hand, it is beneficial to fully reflect the unabsorbed light at different positions and different incident angles, so as to more effectively limit the unabsorbed light in the semiconductor substrate and further improve the problem of light crosstalk caused by the unabsorbed light passing through the metal circuit layer to other pixel units.

[0011] In some embodiments, the shape of the plurality of embedded parts in the embedded structure comprises at least one of a hemisphere, a cone, a circular truncated cone, a cylinder, a prism, a pyramid and a truncated pyramid. In the CMOS image sensor provided by the embodiments of the present application, the embedded structure can adopt embedded parts with different structures, which can adapt to different molding processes and application scenarios.

[0012] In some embodiments, the plurality of embedded parts in the embedded structure are the same in structure and size, and are arrayed in the region opposite to the photodiode. Such design facilitates the processing and molding of the embedded structure, and reduces the processing difficulty of the embedded structure.

[0013] In some embodiments, the cross-sectional shape of the embedded portion gradually decreases in a direction away from the first surface along the first direction; wherein the cross-sectional shape is a shape of the embedded portion in a cross section perpendicular to the first direction. In this way, the interface between the embedded structure and the semiconductor substrate can include an inclined surface inclined with respect to the first direction, thereby facilitating total reflection of the unabsorbed light at different positions and different incident angles, and more facilitating the limitation of the unabsorbed light in the semiconductor substrate, and further improving the problem of light crosstalk caused by the unabsorbed light through the metal wiring layer to other pixel units.

[0014] In some embodiments, among the plurality of embedded portions in the embedded structure, the embedded portions are arranged without spacing with at least one adjacent embedded portion. In this way, by reducing the spacing between the embedded portions, the interface between the embedded structure and the semiconductor substrate can cover more of the target area (the area directly opposite the photodiode), thereby facilitating total reflection of the unabsorbed light at more positions, and more facilitating the limitation of more or even all of the unabsorbed light in the semiconductor substrate, and improving the problem of light crosstalk caused by the unabsorbed light through the metal wiring layer to other pixel units.

[0015] In some embodiments, in a projection along the first direction to the second surface, the plurality of embedded portions in the embedded structure cover the area directly opposite the photodiode without spacing. In this way, the interface between the embedded structure and the semiconductor substrate can completely cover the target area (the area directly opposite the photodiode), thereby facilitating total reflection of the unabsorbed light at more positions, and more facilitating the limitation of all of the unabsorbed light in the semiconductor substrate, and improving the problem of light crosstalk caused by the unabsorbed light through the metal wiring layer to other pixel units.

[0016] In some embodiments, the embedded structure further includes a base layer, and the plurality of embedded portions in the embedded structure are arranged on a side of the base layer close to the second surface. In this way, on the one hand, the plurality of embedded portions in the embedded structure can be deeper into the semiconductor substrate, thereby facilitating total reflection of the unabsorbed light at deeper positions, and more facilitating the limitation of more or even all of the unabsorbed light in the semiconductor substrate. On the other hand, when the embedded structure has a plurality of embedded portions arranged without spacing, the processing difficulty of the embedded structure can be reduced.

[0017] In some embodiments, the embedded structure has a surface flush with the first surface. In this way, the influence of the embedded structure on the first surface of the semiconductor substrate can be reduced, and it is beneficial to fabricate other structures outside the first surface of the semiconductor substrate.

[0018] In some embodiments, the semiconductor material in the semiconductor substrate comprises one or a combination of silicon, germanium, carbon, tin, indium, gallium, nitrogen, phosphorus and arsenic; and the material of the embedded structure comprises at least one of silicon oxide, hafnium oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, terbium sesquioxide and ytterbium oxide. The scheme provided by the embodiments of the present application can be applied to CMOS image sensors of different semiconductor materials.

[0019] In some embodiments, the CMOS image sensor comprises a plurality of pixel units arranged in an array, each pixel unit comprising a photodiode and a pixel circuit, the pixel circuit comprising a transistor and a floating diffusion capacitor.

[0020] The first isolation structure is arranged on the semiconductor substrate corresponding to the pixel unit, and the first isolation structure surrounds a pixel active region, the pixel active region comprising a light sensing region and a circuit region. In the light sensing region, the semiconductor substrate comprises a doped region for forming the photodiode; and in the circuit region, the semiconductor substrate comprises a doped region for forming the transistor and the floating diffusion capacitor.

[0021] The first isolation structure penetrates the semiconductor substrate along a first direction; and the embedded structure is embedded in the light sensing region.

[0022] In this way, the area of the first isolation structure reflecting the incident light can be expanded, so that the transmission of the incident light into the adjacent pixel unit during the transmission of the semiconductor substrate can be better avoided.

[0023] In some embodiments, the photodiode is a PN photodiode or a PIN photodiode. The scheme provided by the embodiments of the present application can be applied to CMOS image sensors of different types of photodiodes.

[0024] In some embodiments, the CMOS image sensor further comprises a color filter array layer and a microlens array layer.

[0025] The color filter array layer and the microlens array layer are both arranged on the side of the metal line layer away from the semiconductor substrate; or the color filter array layer and the microlens array layer are both arranged outside the second surface of the semiconductor substrate. The scheme provided by the embodiments of the present application can be applied to back-illuminated and front-illuminated CMOS image sensors.

[0026] In some embodiments, the color filter array comprises a color filter arranged corresponding to the photodiode, and further comprises a second isolation structure arranged between adjacent color filters. In this way, the reflection of light by the second isolation structure can improve the problem of light crosstalk during the transmission of the incident light in the color filter array layer.

[0027] In a second aspect, the embodiments of the present application also provide an imaging device, which comprises a lens, the CMOS image sensor as described in the first aspect, and an image processor; wherein the lens is configured to focus light onto the CMOS image sensor, the CMOS image sensor is configured to convert the light into raw image data, and the image processor is electrically connected to the CMOS image sensor and configured to process the raw image data.

[0028] The imaging device provided by the embodiments of the present application can achieve the same technical effects as the CMOS image sensor in any of the above embodiments, and thus the details are not repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0029] FIG. 1 is a structural schematic diagram of a CMOS image sensor provided by the embodiments of the present application;

[0030] FIG. 2 is a circuit diagram of a pixel unit in FIG. 1;

[0031] FIG. 3 is a sectional view of a CMOS image sensor provided by the embodiments of the present application along A-A' in FIG. 1;

[0032] FIG. 4 is a top view of a semiconductor substrate corresponding to one pixel unit in FIG. 3;

[0033] FIG. 5 is a schematic diagram of the arrangement of a color filter unit 40 in a color filter array layer provided by the embodiments of the present application;

[0034] FIG. 6 is a sectional view of another CMOS image sensor provided by the embodiments of the present application along A-A' in FIG. 1;

[0035] FIG. 7 is a schematic diagram of light crosstalk of the back-illuminated CMOS image sensor in FIG. 3;

[0036] FIG. 8 is a schematic diagram of light crosstalk of the front-illuminated CMOS image sensor in FIG. 6;

[0037] FIG. 9 is a sectional view of another CMOS image sensor provided by the embodiments of the present application along A-A' in FIG. 1;

[0038] FIG. 10 is a structural schematic diagram of an embedded structure in FIG. 9;

[0039] FIG. 11 is a schematic diagram of the arrangement of multiple embedded parts in the embedded structure in FIG. 10;

[0040] FIG. 12 is a de-crosstalk principle diagram of the embedded structure in FIG. 9;

[0041] FIG. 13 is a structural schematic diagram of another embodiment of the embedded structure in FIG. 9;

[0042] Fig. 14 is a sectional view of another CMOS image sensor along A-A' in Fig. 1 according to an embodiment of the present application;

[0043] Fig. 15 is a schematic diagram of a de-aliasing principle of the embedded structure in Fig. 14;

[0044] Fig. 16 is a schematic diagram of an imaging device according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments.

[0046] Hereinafter, in the embodiments of the present application, the terms "first", "second", and the like are only used for description convenience, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0047] In the embodiments of the present application, "up", "down", "left", and "right" are not limited to be defined according to the relative positions of the components shown in the drawings, and it should be understood that these directional terms are relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the changes of the positions of the components shown in the drawings.

[0048] In the embodiments of the present application, unless the context requires otherwise, in the entire specification and claims, the term "comprising" is interpreted to mean "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplary", or "some examples" are intended to mean that the specific features, structures, materials, or characteristics related to that embodiment or example include in at least one embodiment or example of the present application. The exemplary representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0049] As used herein, "about", "approximately", or "around" includes the stated value and the average value within an acceptable range of deviation from the specific value, wherein the acceptable range of deviation is determined by considering the measurement being discussed and the error related to the measurement of the specific quantity (i.e., the limitations of the measurement system) by a person of ordinary skill in the art.

[0050] As used herein, “parallel,” “perpendicular,” “equal” include the recited condition and conditions that are approximately the recited condition, the range of which is within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “parallel” includes absolute parallel and approximately parallel, where the acceptable deviation range for approximately parallel can be, for example, within 5°; “perpendicular” includes absolute perpendicular and approximately perpendicular, where the acceptable deviation range for approximately perpendicular can also be, for example, within 5°. “Equal” includes absolute equality and approximate equality, where the acceptable deviation range for approximately equal can be, for example, a difference between the two that is less than or equal to 5% of either.

[0051] It should be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0052] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations and / or equivalent circuit diagrams that are depicted as idealized examples. In the interest of clarity, not all of the individual parts of the devices are shown in the figures nor is every instance of composition of matter A thickness of layers and regions are exaggerated in the drawings for clarity. It will be appreciated that variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments are not to be construed as limited to the precise shapes illustrated. For example, an etched region illustrated as a rectangle will generally have rounded features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0053] Embodiments of the present application provide a CMOS image sensor (CIS), which refers to a solid-state imaging chip made by a complementary metal oxide semiconductor (CMOS) process. Compared with a charge coupled device (CCD) image sensor, the CIS has the advantages of low power consumption, easy integration with other devices, fast readout speed, small size, light weight, and low cost.

[0054] As shown in Figure 1, the CMOS image sensor 100 includes a pixel array 110 and peripheral circuitry 120. The pixel array 110 comprises multiple pixel units 1 arranged in an array, for example, multiple pixel units 1 arranged in multiple rows and columns along two perpendicular directions. The pixel units 1 in the pixel array 110 are used to convert optical signals into electrical signals. The peripheral circuitry 120 is coupled to the pixel units 1 in the pixel array 110 and is used to read out the electrical signals generated by the pixel units 1 in the pixel array 110 sequentially. The peripheral circuitry 120 may include timing control circuitry, addressing circuitry, and analog-to-digital conversion circuitry, etc.

[0055] As shown in Figures 1 and 2, in the CMOS image sensor 100 provided in this embodiment, the pixel unit 1 in the pixel array 110 is an active pixel, including a photodiode PD and a pixel circuit. Under incident light, the photodiode PD generates photogenerated carriers, i.e., an electrical signal, proportional to the intensity of the incident light, based on the photoelectric effect, thus completing photoelectric conversion. The pixel circuit is coupled to the photodiode PD and is used to convert the photogenerated carriers generated by the photodiode PD into a voltage signal, and amplify and output the voltage signal. The pixel circuit includes transistors and a floating diffusion capacitor FD. Depending on the pixel circuit, the number of transistors can be 3, 4, or other numbers. The type of pixel unit 1 is usually indicated by the number of transistors in the pixel circuit. For example, a 3T pixel unit means that the pixel circuit of pixel unit 1 has 3 transistors, and a 4T pixel unit means that the pixel circuit of pixel unit 1 has 4 transistors.

[0056] For example, as shown in Figure 2, pixel unit 1 in this embodiment is a 4T pixel unit. The four transistors in the pixel circuit are a reset transistor M2, a source-follower transistor M3, a transfer transistor M1, and a select transistor M4. Each transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated using CMOS technology, and each includes a gate, a first electrode, and a second electrode. The first electrode is one of the source and drain, and the second electrode is the other of the source and drain.

[0057] In the pixel circuit, the first and second terminals of the transfer transistor M1 are electrically connected to the photodiode PD and the floating diffusion capacitor FD, respectively. The floating diffusion capacitor FD is also electrically connected to the first terminal of the reset transistor M2 and the gate of the source follower transistor M3. The first terminal of the source follower transistor M3 and the second terminal of the reset transistor M2 are both electrically connected to the high-level voltage source VDD. The second terminal of the source follower transistor M3 is electrically connected to the first terminal of the selection transistor M4.

[0058] The working process of pixel unit 1 shown in Figure 2 is as follows:

[0059] Before receiving light, reset transistor M2 and transfer transistor M1 are turned on, while other transistors are turned off, resetting the floating diffusion capacitor FD and photodiode PD. Then, all transistors are turned off, and photodiode PD receives light and performs photoelectric conversion to generate photogenerated carriers. Next, transfer transistor M1 is turned on, and other transistors are turned off. The photogenerated carriers transfer from photodiode PD to the floating diffusion capacitor FD via transfer transistor M1. Then, the photogenerated carriers in the floating diffusion capacitor FD are input to source follower transistor M3. Source follower transistor M3 is turned on and converts the photogenerated carrier signal into a voltage signal, which is then amplified and output through its second terminal to the first terminal of select transistor M4. Under the control of the selection signal, select transistor M4 outputs the electrical signal from its first terminal through its second terminal, completing one optical signal acquisition and transmission cycle.

[0060] Figure 3 is a cross-sectional view of a CMOS image sensor provided in an embodiment of this application along line A-A' in Figure 1. As shown in Figure 3, the CMOS image sensor includes a metal line layer 3, a gate structure 6, a semiconductor substrate 2, a color filter array (CFA) layer 4, and a microlens (ML) array layer 5 stacked in a first direction.

[0061] The semiconductor substrate 2 is a substrate structure formed of semiconductor material. The thickness direction of the substrate structure is parallel to the first direction, and the surface of the structure includes a first surface 210 and a second surface 220 opposite to each other in the first direction. The semiconductor substrate 2 can be a substrate, an epitaxial wafer (including a substrate and an epitaxial layer formed on the substrate), or an epitaxial layer after removing the substrate; the first surface 210 and the second surface 220 can be the front and back sides of the substrate, the epitaxial wafer, or the epitaxial layer, respectively.

[0062] The semiconductor material in the semiconductor substrate 2 may include one or a combination of group III, IV, and V materials such as silicon (Si), germanium (Ge), carbon (C), tin (Sn), indium (In), gallium (Ga), nitrogen (N), phosphorus (P), and arsenic (As), for example, silicon-germanium (GeSi), silicon carbide (SiC), or gallium arsenide (GaAs); the semiconductor material is also doped with impurity elements. Doping of the semiconductor material can be divided into N-type doping and P-type doping. In N-type doping, the doping impurity element can be a group V element such as phosphorus (P), arsenic (As), antimony (Sb), or bismuth (Bi). These impurity elements can provide additional electrons, making electrons the majority carriers in the semiconductor material. In P-type doping, the doping impurity element can be a group III element such as boron (B), gallium (Ga), or indium (In). These impurity elements can provide additional holes, making holes the majority carriers in the semiconductor material.

[0063] The doping method for the semiconductor substrate 2 can be in-situ doping, ion implantation, or impurity diffusion. In the CMOS image sensor provided in this application embodiment, the doping type, doping region, and doping concentration of the semiconductor substrate 2 can be determined based on factors such as the semiconductor material in the semiconductor substrate 2, the type of photodiode 21, and the pixel circuit.

[0064] Referring to Figures 3 and 4, the semiconductor substrate 2 includes a first isolation structure 23. The first isolation structure 23 surrounds and defines the active pixel region 24 corresponding to the pixel unit 1 on the semiconductor substrate 2. Adjacent pixel units 1 are isolated on the semiconductor substrate 2 through the first isolation structure 23 to reduce crosstalk between pixel units 1. The first isolation structure 23 can be a deep trench isolation (DTI) structure, which extends a certain distance from the first surface 210 along a first direction toward the depth of the semiconductor substrate 2.

[0065] As shown in Figure 4, the active pixel region 24 in the semiconductor substrate 2 includes a photosensitive region 241 and a circuit region 242. The photosensitive region 241 includes doped regions of different doping types, which form a photodiode 21. The photodiode 21 can be a PN-type photodiode or a PIN-type photodiode. In this paper, a PN-type photodiode is used as an example to illustrate the scheme.

[0066] In a CMOS image sensor, photodiode 21 operates under reverse bias. When light shines on the PN junction of photodiode 21, electrons in the semiconductor valence band absorb photon energy and then jump to the conduction band, thereby generating electron-hole pairs, i.e., photogenerated carriers; thus realizing photoelectric conversion.

[0067] The circuit region 242 in the active region 24 of the pixel includes multiple doped regions, including doped regions used to form transistors (e.g., M1 to M4 in FIG2) in the pixel circuit, such as doped regions used to form the channel region, source region and drain region in the transistor; it also includes a doped region used to form a floating diffusion capacitor (FD in FIG2), which is also referred to as floating diffusion region 22.

[0068] Referring again to Figure 3, the gate structure 6 is disposed on the first surface 210 of the semiconductor substrate 2, and is located in the first surface 210 opposite to the circuit region 242. The gate structure 6 includes a gate electrode and a gate dielectric layer. The gate dielectric layer is in contact with the semiconductor substrate 2, and the gate electrode is disposed on the side of the gate dielectric layer away from the semiconductor substrate 2. The gate structure 6 and the doped region of the semiconductor substrate 2 in the circuit region 242 form transistors (e.g., M1 to M4 in Figure 2) in the pixel circuit.

[0069] As shown in Figure 3, the metal line layer 3 is disposed on the side of the semiconductor substrate 2 with the gate structure 6, that is, on the outer side of the first surface 210 of the semiconductor substrate 2. The metal line layer 3 covers the gate structure 6 and the semiconductor substrate 2, and includes multiple interlayer dielectric (ILD) layers stacked in a first direction and metal line structures 31 disposed in the interlayer dielectric layers. The metal line structures 31 include metal traces disposed on the surface of the interlayer dielectric layers and metal conductive pillars penetrating the interlayer dielectric layers. The metal line structures 31 in the metal line layer 3 are in contact with the gate structure 6 and the circuit region 242 in the semiconductor substrate 2, connecting the transistor and the floating diffusion region 22 (i.e., the floating diffusion capacitor FD) to form a pixel circuit. The metal line structures 31 in the metal line layer 3 are also used for connection with peripheral circuits to achieve the purpose of electrically connecting the pixel unit 1 and the peripheral circuits.

[0070] The CMOS image sensor provided in this embodiment further includes a color filter array layer 4 and a microlens array layer 5, as shown in FIG3. The color filter array layer 4 is disposed on the side of the semiconductor substrate 2 away from the metal circuit layer 3, that is, on the outer side of the second surface 220 in the semiconductor substrate 2. The color filter array layer 4 includes a plurality of color filters 41 corresponding to a plurality of pixel units 1 in the pixel array, and the color filters 41 correspond one-to-one with the pixel units. The color filters 41 only allow light of a specific wavelength to pass through, while blocking other light. For example, the red filter only allows red light to pass through, while blocking light of other colors; thereby realizing the function of color filtering.

[0071] In the color filter array layer 4, color filters 41 of different colors are arranged according to a spectral dispersion rule to form a color filter unit. For example, as shown in parts (a) to (d) of FIG5, the arrangement rule of the color filters 41 in the color filter unit 40 can be RGGB (red, green, green, and blue), RGBW (red, green, blue, and white), RGBIR (red, green, blue, and infrared), and CMYK (cyan, magenta, yellow, and black). It should be noted that the color filter unit 40 in this embodiment is not limited to the above-described arrangement rule of the color filters 41.

[0072] The color filter array layer 4 includes multiple color filter units 40 arranged in an array.

[0073] When incident light irradiates the color filter array layer 4 with the above structure, the color filter unit 40 can split the incident light into different color channels. For example, when incident light irradiates the RGGB color filter unit 40, the RGGB color filter unit 40 will split the incident light into different color channels according to red, green, green and blue, and then irradiate the corresponding pixel unit through the different color channels, and the photoelectric conversion is completed in the photodiode 21 of the pixel unit.

[0074] Based on the above description of photodiode 21, it can be seen that the photogenerated carriers generated by photodiode 21 are proportional to the intensity of the incident light. The intensity of the incident light affects the electrical signal generated by photodiode 21. Therefore, photodiode 21 only acquires the intensity information of the incident light and cannot obtain color information. By setting the color filter array layer 4, the CMOS image sensor can obtain color information related to the incident light, thereby achieving the effect of color imaging.

[0075] Referring to Figure 3, the color filter array layer 4 also includes a second isolation structure 42 located between adjacent color filters 41. The second isolation structure 42 is used to isolate the color filters 41 and prevent incident light transmitted to the color filters 41 from entering the adjacent color filters 41 and causing crosstalk. The second isolation structure 42 can be a metal grid made of metal material or a dielectric structure made of dielectric material.

[0076] The microlens array layer 5 is disposed on the side of the color filter array layer 4 away from the semiconductor substrate 2, and includes multiple microlenses 51 disposed in the corresponding pixel unit 1. The microlenses 51 are used to focus external light into the photodiode 21 of the corresponding pixel unit to improve the light collection capability of the photodiode 21.

[0077] In a CMOS image sensor, the first surface 210 on the semiconductor substrate 2 where the gate structure 6 is disposed is typically referred to as the front side, and the second surface 220 opposite to the first surface 210 is referred to as the back side. The metal circuit layer 3 is disposed on the front side of the semiconductor substrate 2. As can be seen from the above description, in the CMOS image sensor provided in the above embodiment, the microlens array layer 5 and the color filter array layer 4 are disposed on the back side of the semiconductor substrate 2. During operation, incident light passes through the microlens array layer 5 and the color filter array layer 4 and enters the semiconductor substrate 2 on the back side (second surface 220). Therefore, the above-described CMOS image sensor is also called a back-side illuminated (BSI) CMOS image sensor.

[0078] The CMOS image sensor provided in this application embodiment can also be a front-side illuminated (FSI) CMOS image sensor, as shown in FIG6. The front-side illuminated CMOS image sensor includes a substrate 7, a semiconductor substrate 2, a gate structure 6, a metal circuit layer 3, a color filter array layer 4, and a microlens array layer 5 stacked in a first direction. The microlens array layer 5 and the color filter array layer 4 are disposed on the side of the metal circuit layer 3 away from the semiconductor substrate 2. That is, the microlens array layer 5, the color filter array 41, and the metal circuit layer 3 are all disposed on the front side of the semiconductor substrate 2. During operation, incident light passes through the microlens array layer 5, the color filter array layer 4, and the metal circuit layer 3, and then enters the semiconductor substrate 2 on the front side (first surface 210).

[0079] In addition, the front-illuminated CMOS image sensor may also include a substrate 7, which is disposed on the side of the semiconductor substrate 2 away from the gate structure 6. The semiconductor substrate 2 may be an epitaxial layer disposed on the substrate 7.

[0080] The CMOS image sensors provided in the above embodiments, whether front-illuminated or back-illuminated, suffer from optical crosstalk between pixel units during operation.

[0081] Optical crosstalk refers to the phenomenon where incident light illuminating a pixel unit, due to factors such as incident angle, reflection, diffraction, and scattering, enters other pixel units during transmission and completes photoelectric conversion in those units. Optical crosstalk can occur at any time and any transmission position during the process from when the incident light enters the pixel unit until it is completely absorbed by the photodiode 21 and converted into photogenerated carriers. For example, in a back-illuminated CMOS image sensor, incident light may enter other pixel units while propagating in the color filter array layer 4, or it may enter other pixel units while propagating in the semiconductor substrate 2, thus causing optical crosstalk. Similarly, in a front-illuminated CMOS image sensor, incident light may enter other pixel units while propagating in the color filter array layer 4 and the metal circuit layer 3, or it may enter other pixel units while propagating in the semiconductor substrate 2, thus causing optical crosstalk.

[0082] Optical crosstalk between pixel units can cause anomalies such as decreased sharpness, color cast, color noise, and grid patterns in images acquired by CMOS image sensors, affecting image quality. Furthermore, with the development of semiconductor process technology, CMOS image sensors are gradually evolving towards higher resolution and smaller size. Higher resolution and smaller size CMOS image sensors reduce the spacing between adjacent pixel units, further exacerbating the optical crosstalk problem.

[0083] To mitigate optical crosstalk between pixel units, as shown in Figures 7 and 8, the CMOS image sensor provided in the above embodiments of this application is provided with a first isolation structure 23 and a second isolation structure 42. The first isolation structure 23 can mitigate optical crosstalk during the transmission of incident light in the semiconductor substrate 2 by reflecting light. The second isolation structure 42 can mitigate optical crosstalk during the transmission of incident light in the color filter array layer 4 by reflecting light.

[0084] However, during the process of the incident light transmitted to the semiconductor substrate 2 passing through the photodiode 21, it is difficult for it to be completely absorbed by the semiconductor material in the photodiode 21 and converted into an electrical signal. In this paper, the part of the incident light that is not absorbed and converted into an electrical signal during the process of passing through the photodiode 21 is called unabsorbed light (dashed arrow in the figure). Unabsorbed light (dashed arrow in the figure) will continue to be transmitted in the semiconductor substrate 2 after passing through the photodiode 21.

[0085] As shown in Figure 7, in a back-illuminated CMOS image sensor, unabsorbed light (dashed arrow in the figure) may be transmitted to the first surface 210 (front side) of the semiconductor substrate 2 and enter the metal circuit layer 3 through the first surface 210. As shown in Figure 8, in a front-illuminated CMOS image sensor, unabsorbed light (dashed arrow in the figure) may be transmitted to the second surface 220 (back side) of the semiconductor substrate 2, reflected by the second surface 220, and transmitted in the opposite direction, then transmitted to the first surface 210 (front side) of the semiconductor substrate 2 and enter the metal circuit layer 3 through the first surface 210.

[0086] When unabsorbed light (dashed arrow in the figure) enters the metal circuit layer 3, the metal circuit structure 31 in the metal circuit layer 3 changes the transmission direction of the unabsorbed light (dashed arrow in the figure) through scattering, reflection, or diffraction. This may cause the unabsorbed light (dashed arrow in the figure) to propagate laterally in the metal circuit layer 3 and enter other pixel units, thus generating optical crosstalk. This part of optical crosstalk is difficult to optimize and remove through algorithms and processes, which seriously affects the imaging quality of CMOS image sensors.

[0087] Since the light absorption efficiency of the semiconductor material in photodiode 21 decreases with increasing wavelength, the unabsorbed light passing through photodiode 21 is typically long-wavelength light, such as near-infrared light (near-infrared light lies between visible and mid-infrared light, generally referring to the wavelength range between 750nm and 1.4μm). In other words, near-infrared light more easily enters the metal circuit layer 3, causing optical crosstalk. This phenomenon severely affects the performance of CMOS image sensors that require near-infrared light to improve low-light imaging capabilities.

[0088] Based on this, embodiments of this application provide another CMOS image sensor to improve the above-mentioned problems. This CMOS image sensor can be either back-illuminated or front-illuminated.

[0089] Taking a back-illuminated CMOS image sensor as an example, as shown in Figure 9, the CMOS image sensor includes a metal line layer 3, a gate structure 6, a semiconductor substrate 2, a color filter array layer 4, and a microlens array layer 5 stacked in a first direction; the description of the metal line layer 3, the gate structure 6, the color filter array layer 4, and the microlens array layer 5 can be found above, and will not be repeated here.

[0090] As shown in Figure 9, the first isolation structure 23 in the semiconductor substrate 2 penetrates the semiconductor substrate 2 along the first direction. This design can expand the area where the first isolation structure 23 reflects incident light, thereby better preventing incident light from entering adjacent pixel units during transmission in the semiconductor substrate 2.

[0091] In some embodiments, the CMOS image sensor may further include an anti-reflection layer and an intermediate dielectric layer. The anti-reflection layer may be disposed on the outer side of the second surface 220 of the color filter array layer 4 in the semiconductor substrate 2, that is, on the outer side of the light-gathering surface of the semiconductor substrate 2, to reduce the reflection of incident light by the semiconductor substrate 2 and improve quantum efficiency. The intermediate dielectric layer may be disposed between the anti-reflection layer and the color filter array layer 4 to isolate the anti-reflection layer and the color filter array layer 4, and to provide a structural basis for the fabrication of the color filter array layer 4.

[0092] Referring to Figure 9, the CMOS image sensor also includes an embedding structure 8 corresponding to the pixel unit. In the region directly opposite the photodiode 21 in the pixel unit, the embedding structure 8 is embedded into the semiconductor substrate 2 via the first surface 210. In this text, the region directly opposite the photodiode 21 refers to the region where the projection onto a reference plane perpendicular to the first direction (such as the second surface 220) coincides with the projection of the photodiode 21. It can be seen that the region directly opposite the photodiode 21 is a three-dimensional region with the photodiode 21 as a reference, and the photodiode 21 and some structures in the semiconductor substrate 2 are located in this region; all other structures in this region, except for the photodiode 21, are directly opposite the photodiode 21 in the first direction. For ease of description, the region directly opposite the photodiode 21 will be referred to as the target region below. In the target region, the embedding structure 8 is embedded into the semiconductor substrate 2 via the first surface 210, that is, embedded into the photosensitive area 241 of the semiconductor substrate 2 via the first surface 210.

[0093] Please refer to Figures 10 and 11 simultaneously. The embedded structure 8 includes multiple embedded parts 81 of the same shape and size. The multiple embedded parts 81 are arranged in an array in the target area, for example, arranged in multiple rows and columns along the second direction and the third direction. The first direction, the second direction and the third direction are perpendicular to each other, and the second direction and the third direction are parallel to the first surface 210 and the second surface 220.

[0094] Furthermore, as shown in parts (a), (b), and (c) of Figure 10, the multiple embedding portions 81 in the embedding structure 8 all have a "larger at the top and smaller at the bottom" structure, meaning that the cross-sectional shape of the embedding portion 81 gradually decreases as it moves away from the first surface 210 along the first direction; here, the cross-sectional shape refers to the shape of the embedding portion 81 in a section perpendicular to the first direction. When the embedding portion 81 has a "larger at the top and smaller at the bottom" structure, the structural surface of the embedding portion 81 includes an inclined surface relative to the first direction. Here, the inclined surface relative to the first direction refers to a surface that is neither parallel nor perpendicular to the first direction, and can be either a plane or a curved surface.

[0095] For example, the embedded part 81 can be a conical structure, a pyramidal structure, a frustum structure, a truncated cone structure, or a hemispherical structure, etc.

[0096] The material of the embedded structure 8 is a non-metallic dielectric material with a refractive index lower than that of the semiconductor material in the semiconductor substrate 2. For example, silicon oxide (SiO2), hafnium oxide (HfO2), silicon nitride (Si3N4), and silicon oxynitride (SiO2) can be selected. x N y The embedded structure 8 is formed by first etching the semiconductor substrate 2 to form a substrate groove 25, and then filling the substrate groove 25 with material. Therefore, the shape of the embedded structure 8 can be controlled by controlling the shape of the substrate groove 25.

[0097] The embedded structure 8 may have a surface that is flush with the first surface 210 on the side away from the second surface 220. This design can reduce the impact of the embedded structure 8 on the first surface 210 in the semiconductor substrate 2, and facilitate the fabrication of other structures on the outside of the first surface 210 of the semiconductor substrate 2.

[0098] The embedded structure 8 with the above design has the following advantages: First, due to the material difference between the embedded structure 8 and the semiconductor substrate 2, there is a relationship of one side having a smaller refractive index and the other side having a larger refractive index at the interface between the embedded structure 8 and the semiconductor substrate 2. Second, due to the shape, size, and arrangement characteristics of the multiple embedded portions 81 in the embedded structure 8, the interface between the embedded structure 8 and the semiconductor substrate 2 exhibits an extension feature with varying heights relative to the second surface 220 in the target area. Furthermore, the undulating interface includes multiple inclined surfaces relative to the first direction, where the inclined surfaces in the interface are formed by the inclined surfaces of the structural surfaces in the embedded portions 81.

[0099] In this case, when light is incident from the semiconductor substrate 2 (the part with a higher refractive index) to the embedded structure 8 (the part with a lower refractive index), total internal reflection will occur at the interface. Furthermore, due to the aforementioned extended characteristics of the interface between the embedded structure 8 and the semiconductor substrate 2, total internal reflection can be achieved for light with different incident angles, and the number of reflections of light will be increased, thereby helping to confine the light to the semiconductor substrate 2.

[0100] When light travels from the embedded structure 8 (the part with a lower refractive index) to the semiconductor substrate 2 (the part with a higher refractive index), the light can enter the semiconductor substrate 2 through the interface between the embedded structure 8 and the semiconductor substrate 2.

[0101] The operation of the back-illuminated CMOS image sensor with the above-mentioned embedded structure 8 is as follows:

[0102] As shown in Figure 12, the incident light passes through the microlens array layer 5, the color filter array layer 4, the intermediate dielectric layer, and the anti-reflection layer, and then enters the semiconductor substrate 2 on the back side (second surface 220). The photodiode 21 in the semiconductor substrate 2 absorbs the incident light and converts the optical signal into an electrical signal, which is then output to the peripheral circuit through the pixel circuit.

[0103] In the presence of unabsorbed light (dashed arrow in the figure), the unabsorbed light is transmitted in the semiconductor substrate 2 to the location of the embedded structure 8. Under the action of the embedded structure 8 and the semiconductor substrate 2, the propagation direction of the unabsorbed light is changed, and the unabsorbed light is confined in the semiconductor substrate 2 to prevent the unabsorbed light from entering the metal circuit layer 3 and causing optical crosstalk.

[0104] This demonstrates that in a back-illuminated CMOS image sensor, the embedded structure 8 can mitigate the optical crosstalk problem caused by incident light entering the metal circuit layer 3 from the semiconductor substrate 2 and then propagating to other pixel units within the metal circuit layer 3. This crosstalk reduction effectively improves the imaging quality of the back-illuminated CMOS image sensor. This effect is particularly pronounced for back-illuminated CMOS image sensors that require near-infrared light to enhance low-light imaging capabilities.

[0105] In some embodiments, the plurality of embedded portions 81 in the embedded structure 8 are arranged without spacing, where "without spacing" means that the minimum distance between an embedded portion 81 and at least one adjacent embedded portion 81 is zero. From another perspective, in the projection along the first direction onto the second surface 220, the embedded portion 81 contacts or overlaps with at least one adjacent embedded portion 81, that is, the minimum distance between them is zero.

[0106] For example, the embedded part 81 is a hemispherical structure, a conical structure, or a frustum-shaped structure; in the projection along the first direction onto the second surface 220, the projected shape of the embedded part 81 is circular, and the circular projections of the embedded part 81 are tangentially contacted with those of the adjacent embedded parts 81; or by overlapping projections, the projections of multiple embedded parts 81 in the embedded structure 8 can completely cover the target area.

[0107] In another example, the embedded part 81 is a quadrangular pyramidal structure or a quadrangular frustum structure; in the projection along the first direction onto the second surface 220, the projection shape of the embedded part 81 is a quadrilateral, and the projections of multiple embedded parts 81 are spliced ​​together to completely cover the target area.

[0108] The embedded structure 8 with the above design can reduce the spacing between the embedded parts 81, so that the interface between the embedded structure 8 and the semiconductor substrate 2, especially the inclined surface in the interface, can cover more of the target area (the area facing the photodiode 21). This allows for total internal reflection of unabsorbed light at more locations, which is beneficial for confining more or even all of the unabsorbed light in the semiconductor substrate 2.

[0109] In some embodiments, as shown in FIG13, the embedded structure 8 further includes a base layer 82, which is a layered structure parallel to the first surface 210, and a plurality of embedded portions 81 are disposed on the side of the base layer 82 near the second surface 220. This design allows the plurality of embedded portions 81 in the embedded structure 8 to penetrate deeper into the semiconductor substrate 2, thereby enabling total internal reflection of unabsorbed light at a deeper location, which is beneficial for confining more or even all of the unabsorbed light within the semiconductor substrate 2.

[0110] On the other hand, as described above, the embedded structure 8 can be formed by first etching substrate grooves 25 on the semiconductor substrate 2, and then filling the substrate grooves 25 with material; the shape of the embedded structure 8 can be controlled by controlling the shape of the substrate grooves 25. Therefore, when forming multiple embedded portions 81 arranged without spacing in the absence of a base layer 82, it is necessary to first form substrate grooves 25 arranged without spacing on the semiconductor substrate 2, and then fill the substrate grooves 25 with material. This process requires high processing precision, making the formation of the embedded structure 8 more difficult. When forming multiple embedded portions 81 arranged without spacing in the presence of a base layer 82, multiple substrate grooves 25 arranged with spacing can be formed first, then the spacing between the substrate grooves 25 can be thinned, and then the substrate grooves 25 can be filled with material. Thus, it can be seen that when the embedded structure 8 has a base layer 82, the requirements for processing precision can be reduced, thereby reducing the difficulty of forming the embedded structure 8.

[0111] In some embodiments, the outer peripheral surface of the substrate 82 surrounding the first direction is inclined. This design can improve the total internal reflection capability of the embedded structure 8 and the semiconductor substrate 2 for unabsorbed light, thereby helping to confine more or even all of the unabsorbed light in the semiconductor substrate 2.

[0112] In the CMOS image sensor provided in the embodiments of this application, the extension features of the interface between the embedded structure 8 and the semiconductor substrate 2 can be modified by changing the size, number, shape and combination rules of the multiple embedded parts 81 in the embedded structure 8.

[0113] For example, in some embodiments, the multiple embedded portions 81 in the embedded structure 8 have different shapes, or the same shape but different sizes. This design allows for a more disordered extension of the interface formed between the embedded structure 8 and the semiconductor substrate 2, thereby improving the ability to confine unabsorbed light.

[0114] For example, in other embodiments, the multiple embedded portions 81 in the embedded structure 8 can adopt a structure other than "larger at the top and smaller at the bottom", such as a cylindrical structure or a prism structure. In this case, there is a certain interval between adjacent multiple embedded portions 81. The embedded structure 8 with the above design can still form an interface with the semiconductor substrate 2 with varying heights relative to the second surface 220, which is beneficial to improving the optical crosstalk problem caused by unabsorbed light.

[0115] For example, in some other embodiments, the number of embedding parts 81 in the embedding structure 8 can be one or two. This design helps to simplify the embedding structure 8 and reduce the difficulty of processing.

[0116] The embedded structure 8 designed above can also be applied to front-illuminated CMOS image sensors, where it can also play a role in de-crosstalk.

[0117] As exemplarily shown in FIG14, the front-illuminated CMOS image sensor includes a substrate 7, a semiconductor substrate 2, a gate structure 6, a metal line layer 3, a color filter array layer 4, and a microlens array layer 5 stacked in a first direction, wherein an embedded structure 8 is disposed on the side of the semiconductor substrate 2 near the metal line layer 3. A description of the embedded structure 8, the substrate 7, the gate structure 6, the metal line layer 3, the color filter array layer 4, and the microlens array layer 5 can be found above and will not be repeated here.

[0118] The operation of the front-illuminated CMOS image sensor with the above-mentioned embedded structure 8 is as follows:

[0119] As shown in Figure 15, after the incident light passes through the microlens array layer 5, the color filter array layer 4, and the metal circuit layer 3, it illuminates the first surface 210 (front side) of the semiconductor substrate 2, which is the location of the embedded structure 8. Since the embedded structure 8 does not affect the incident light entering the semiconductor substrate 2 from the outside, the incident light can be transmitted through the embedded structure 8 to the location of the photodiode 21. The photodiode 21 in the semiconductor substrate 2 absorbs the incident light and converts the optical signal into an electrical signal, which is then output through the pixel circuit.

[0120] In the presence of unabsorbed light (dashed arrow in the figure), the unabsorbed light continues to propagate in the semiconductor substrate 2. After reaching the second surface 220 (back side) of the semiconductor substrate 2, it is reflected back into the semiconductor substrate 2 by the substrate 7 and propagates towards the embedded structure 8 in the semiconductor substrate 2. When the unabsorbed light propagates to the embedded structure 8, the embedded structure 8 and the semiconductor substrate 2 change the propagation direction of the unabsorbed light to confine the unabsorbed light in the semiconductor substrate 2, so as to avoid the unabsorbed light from entering the metal circuit layer 3 and causing optical crosstalk.

[0121] This demonstrates that in a front-illuminated CMOS image sensor, the embedded structure 8 can mitigate the optical crosstalk problem caused by incident light entering the metal circuit layer 3 from the semiconductor substrate 2 and then propagating to other pixel units within the metal circuit layer 3. This crosstalk reduction effectively improves the imaging quality of the CMOS image sensor. The effect of crosstalk reduction and the improvement in imaging quality are particularly significant for CMOS image sensors that require near-infrared light to enhance low-light imaging capabilities.

[0122] This application also provides an imaging device with the above-mentioned CMOS sensor. The imaging device can be a camera module, or a device dedicated to shooting, such as a camera, camcorder, vehicle camera, industrial camera, and security camera. It can also be an electronic device with shooting function, such as a mobile phone, tablet computer, laptop computer, smart wearable device, and smart home device.

[0123] As exemplarily shown in FIG16, the imaging device 1000 includes a lens 200, a CMOS image sensor 100, and an image signal processor (ISP) 300. The lens 200 focuses light from the imaging area onto the CMOS image sensor 100, which converts the focused light into electrical signals to generate raw image data. The image processor 300 is electrically connected to the CMOS image sensor 100 and processes the raw image data generated by the CMOS image sensor 100, such as performing color correction, image enhancement, and noise reduction, to improve the imaging quality of the imaging device 1000.

[0124] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A CMOS image sensor, characterized by, The CMOS image sensor comprises a semiconductor substrate, a metal circuit layer and an embedded structure, wherein the semiconductor substrate comprises a first surface and a second surface opposite to each other in a first direction, and a photodiode is formed in the semiconductor substrate; the metal circuit layer is arranged outside the first surface of the semiconductor substrate; In a region opposite to the photodiode, the embedded structure is embedded into the semiconductor substrate through the first surface; the material of the embedded structure is a non-metal material, and the refractive index is less than the refractive index of the semiconductor material in the semiconductor substrate.

2. The CMOS image sensor according to claim 1, characterized by The embedded structure comprises a plurality of embedded parts arranged in the region opposite to the photodiode.

3. The CMOS image sensor according to claim 2, characterized by The shape of the plurality of embedded parts in the embedded structure comprises at least one of a hemisphere, a cone, a circular truncated cone, a cylinder, a prism, a pyramid and a truncated pyramid.

4. The CMOS image sensor according to claim 2 or 3, characterized by, The structure and size of the plurality of embedded parts in the embedded structure are the same, and the plurality of embedded parts are arrayed in the region opposite to the photodiode.

5. The CMOS image sensor according to any one of claims 2 to 4, characterized by, In the process of moving away from the first surface along the first direction, the cross-sectional shape of the embedded part gradually becomes smaller; The cross-sectional shape is the shape of the embedded part in a cross section perpendicular to the first direction.

6. The CMOS image sensor according to any one of claims 2 to 5, characterized by, In the plurality of embedded parts in the embedded structure, the embedded part is arranged without spacing with at least one adjacent embedded part.

7. The CMOS image sensor according to any one of claims 2 to 6, characterized by, In the projection of the embedded structure along the first direction to the second surface, the plurality of embedded parts in the embedded structure cover the region opposite to the photodiode without spacing.

8. The CMOS image sensor according to any one of claims 2 to 7, characterized by, The embedded structure further comprises a base layer, and the plurality of embedded parts in the embedded structure are arranged on one side of the base layer close to the second surface.

9. The CMOS image sensor according to any one of claims 1 to 8, characterized by, The embedded structure has a surface flush with the first surface.

10. The CMOS image sensor according to any one of claims 1 to 9, characterized by, The semiconductor material in the semiconductor substrate comprises one or a combination of silicon, germanium, carbon, tin, indium, gallium, nitrogen, phosphorus and arsenic; The material of the embedded structure comprises at least one of silicon oxide, hafnium oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, terbium sesquioxide and ytterbium oxide.

11. The CMOS image sensor according to any one of claims 1 to 10, characterized by, The CMOS image sensor comprises a plurality of pixel units arranged in an array, and each pixel unit comprises the photodiode and a pixel circuit, and the pixel circuit comprises a transistor and a floating diffusion capacitor; A first isolation structure is arranged on the semiconductor substrate and corresponds to the pixel unit, the first isolation structure surrounds and limits a pixel active area, and the pixel active area comprises a light sensing area and a circuit area; in the light sensing area, the semiconductor substrate comprises a doped area for forming the photodiode; in the circuit area, the semiconductor substrate comprises a doped area for forming the transistor and the floating diffusion capacitor; The first isolation structure penetrates through the semiconductor substrate along the first direction; The embedded structure is embedded in the light sensing area.

12. The CMOS image sensor according to any one of claims 1 to 11, characterized by, The photodiode is a PN photodiode or a PIN photodiode.

13. The CMOS image sensor according to any one of claims 1 to 12, characterized by, The CMOS image sensor further comprises a color filter array layer and a microlens array layer; The color filter array layer and the microlens array layer are arranged on a side of the metal circuit layer away from the semiconductor substrate; Alternatively, the color filter array layer and the microlens array layer are both disposed outside the second surface in the semiconductor substrate.

14. The CMOS image sensor according to claim 13, characterized by The color filter array includes color filters disposed corresponding to the photodiodes, and further includes second isolation structures disposed between adjacent color filters.

15. An imaging device, characterized by The imaging device includes a lens, the CMOS image sensor according to any one of claims 1 to 14, and an image processor; wherein the lens is configured to focus light onto the CMOS image sensor, the CMOS image sensor is configured to perform photoelectric conversion to form raw image data; and the image processor is electrically connected to the CMOS image sensor and configured to process the raw image data.

Images