Memory array, memory and electronic device

Abstract

The embodiments of the present application relate to the technical field of electronic devices. Provided are a memory array, a memory and an electronic device. The memory array comprises a substrate, a plurality of memory matrices, bit lines, word lines and a plurality of first external connection structures. Each memory matrix comprises N submatrices. The bit lines are electrically connected to the N submatrices, word lines are electrically connected to one submatrix, and each submatrix is correspondingly electrically connected to a plurality of word lines arranged at intervals in a first direction; and the distance between two adjacently arranged word lines respectively electrically connected to two adjacently arranged submatrices in the first direction is greater than the distance between two adjacently arranged word lines electrically connected to the same submatrix. First connection points of some of the first external connection structures are located between at least one pair of adjacently arranged submatrices, and first connection points of some of the first external connection structures are located between at least one pair of adjacently arranged memory matrices. The structural design can reduce the parasitic capacitance generated in the memory array, thereby improving the electrical performance of the memory array.

Description

Storage array, memory and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411028711X, filed on July 29, 2024, and entitled “Storage array, memory and electronic device”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of electronic devices, and in particular to a storage array, a memory and an electronic device. BACKGROUND

[0003] Memories, such as Dynamic Random Access Memory (DRAM), are widely used in various electronic devices, and people have increasingly high demands for the capacity of memories. From the perspective of cost competitiveness, memory suppliers need to continuously improve the integration density (the number of memory cells per unit area) of memories, and the micro-fabrication of traditional two-dimensional memories approaches the physical limit, so three-dimensional memories, such as heterogeneous stacked three-dimensional DRAM solutions, become an important option for further improving the integration density.

[0004] In some memories, a storage array and a peripheral circuit (including amplifiers, drivers and other logic circuits) or other storage arrays are respectively formed on different wafers and can be stacked and interconnected together through hybrid bonding to realize a three-dimensional structure design. While realizing hybrid bonding, it is necessary to ensure that the storage array has good electrical performance. However, the current three-dimensional memory has a large parasitic capacitance, which affects the electrical performance of the memory. SUMMARY

[0005] Embodiments of the present application provide a storage array, a memory and an electronic device, which aims to reduce the parasitic capacitance of the storage array caused by three-dimensional interconnection through structural design, thereby improving the electrical performance of the storage array.

[0006] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a storage array is provided, which includes a substrate, a plurality of storage matrices, a plurality of bit lines, a plurality of word lines and a plurality of first external connection structures.

[0008] The plurality of storage matrices are arranged on the substrate, and the plurality of storage matrices are arranged in an array along a first direction and a second direction; each storage matrix comprises N sub-matrices arranged in an interval along the first direction, and each sub-matrix comprises a plurality of storage units arranged in an array along the first direction and the second direction; the first direction and the second direction are parallel to the substrate and intersect with each other; N is a positive integer, and N≥2.

[0009] The plurality of bit lines and the plurality of word lines are arranged in an array along the first direction and the second direction, and the bit lines extend along the first direction and the word lines extend along the second direction; the word lines intersect with the bit lines, and the intersection positions of the two are the arrangement positions of the storage units; each bit line is electrically connected with a plurality of storage units in N sub-matrices, and each word line is electrically connected with a plurality of storage units in one storage matrix; the interval between two word lines arranged in an interval along the first direction and electrically connected with two adjacent sub-matrices is greater than the interval between two word lines arranged in an interval and electrically connected with the same sub-matrix.

[0010] The plurality of first external connection structures are arranged on a side of the substrate away from the plurality of storage matrices, or arranged on a side of the plurality of storage matrices away from the substrate; each first external connection structure is electrically connected with one bit line; in the plurality of first external connection structures, first contact points of a part of the first external connection structures are located between at least one pair of sub-matrices belonging to the same storage matrix and arranged in an interval, and first contact points of another part of the first external connection structures are located between at least one pair of storage matrices arranged in an interval along the first direction; the first contact point is a part of the first external connection structure for electrical connection with the bit line.

[0011] In related embodiments, all the first external connection structures in the storage array are arranged between adjacent storage matrices, resulting in that the plurality of first external connection structures are arranged too concentratedly, and a large parasitic capacitance is generated, which affects the electrical performance of the storage array.

[0012] In the storage array provided by the embodiments of the present application, the storage matrix is divided into N sub-matrices, so that a large design space is spaced between adjacent sub-matrices and between adjacent storage matrices, for example, the interval between adjacent sub-matrices in the first direction and the interval between adjacent storage matrices in the first direction are both larger than the interval between two adjacent word lines in the same sub-matrix, thereby increasing the area available for the arrangement of the first external connection structures, so that part of the first external connection structures can be arranged between adjacent storage matrices, and the remaining part of the first external connection structures can be arranged between adjacent sub-matrices, thereby realizing the dispersed arrangement of the plurality of first external connection structures, avoiding the concentrated arrangement of the plurality of first external connection structures between adjacent storage matrices, thereby reducing the parasitic capacitance generated between two adjacent first external connection structures and the parasitic capacitance generated between adjacent connection columns for connecting the first external connection structures and the bit lines, and thereby improving the electrical performance of the storage array.

[0013] In a possible implementation of the first aspect, the storage array includes N groups of bit lines, each row of the storage matrix is provided with a corresponding group of bit lines along a first direction, the N groups of bit lines are arranged along a second direction, each group of bit lines includes a plurality of rows of bit lines arranged along the second direction, each row of bit lines includes a plurality of bit lines arranged along the first direction, in the N groups of bit lines, each bit line in the first group of bit lines is electrically connected to a plurality of storage units in one storage matrix, in the N groups of bit lines, each bit line in the M+1th group of bit lines is electrically connected to a plurality of storage units in the M+1th to Nth sub-matrices of one storage matrix and the first to Mth sub-matrices of an adjacent storage matrix, where M is a positive integer and M+1≤N.

[0014] By dividing the storage matrix into N sub-matrices and correspondingly dividing the plurality of bit lines into N groups of bit lines and designing the arrangement positions of the N groups of bit lines according to the foregoing rule, the bit lines in different groups of bit lines span at least one different sub-matrix, so that the arrangement positions of the first external connection structures are designed correspondingly according to the arrangement rule of the bit lines, for example, the first external connection structures are electrically connected to the end portions of the bit lines, and then the end portions of the bit lines in different groups of bit lines are regularly located between different sub-matrices, so that the plurality of first external connection structures are regularly distributed between different sub-matrices, facilitating the uniform distribution of the plurality of first external connection structures, so that the parasitic capacitances at different positions of the storage array are substantially the same, and the consistency of the electrical performance of the storage units at different positions of the storage array is improved.

[0015] In a possible implementation of the first aspect, the plurality of rows of bit lines in the first group of bit lines to the plurality of rows of bit lines in the Nth group of bit lines are arranged in turn along the second direction.

[0016] In a possible implementation of the first aspect, N=2, the first group of bit lines includes odd-numbered rows of bit lines in the plurality of rows of bit lines arranged along the second direction, and the second group of bit lines includes even-numbered rows of bit lines in the plurality of rows of bit lines arranged along the second direction.

[0017] By arranging the plurality of rows of bit lines in the first group of bit lines to the plurality of rows of bit lines in the Nth group of bit lines in turn along the second direction, different first external connection structures belonging to different groups of bit lines can be located between different sub-matrices according to the arrangement positions of the groups of bit lines, so that the different first external connection structures are staggered with each other in the second direction, reducing the parasitic capacitance, and the first external connection structures electrically connected by different rows of bit lines in the same group of bit lines can also be spaced apart, which also reduces the parasitic capacitance.

[0018] In a possible implementation of the first aspect, the first group of bit line groups to the Nth group of bit line groups are sequentially arranged along the second direction.

[0019] In a possible implementation of the first aspect, N=2, each row of the storage matrix is divided into a first part and a second part, and the first part and the second part are arranged along the second direction. The first group of bit line groups is arranged in the region where the first part is located, and the second group of bit line groups is arranged in the region where the second part is located.

[0020] By arranging the first group of bit line groups A1 to the Nth group of bit line groups A N are sequentially arranged along the second direction Y, and the different first external connection structures belonging to different bit line groups are located between different sub-matrices, so that the different first external connection structures are staggered in the second direction, thereby reducing the parasitic capacitance.

[0021] In a possible implementation of the first aspect, among the plurality of first external connection structures, at least one pair of first external connection structures is arranged in a central symmetry, and the first contact points of the two first external connection structures arranged in a central symmetry are located on the same straight line extending along the second direction. The two first external connection structures extend along the first direction and extend in opposite directions from the first contact points thereof, respectively, which can reduce the directly facing area of the pair of first external connection structures in the second direction, thereby further reducing the parasitic capacitance between the at least one pair of adjacent first external connection structures, and further optimizing the electrical performance of the storage array 10.

[0022] In a possible implementation of the first aspect, among the plurality of first external connection structures, at least one pair of first external connection structures is arranged in an axial symmetry, and the axis of symmetry extends along the second direction. The first contact points of the two first external connection structures arranged in an axial symmetry are electrically connected to the opposite two end portions of the two adjacent bit lines, respectively. The two first external connection structures extend along the first direction and extend in opposite directions from the first contact points thereof, respectively, which can make the pair of first external connection structures close to each other in the first direction, thereby facilitating the pair of first external connection structures to be electrically connected to the same sensitive amplifier in the peripheral circuit.

[0023] In a possible implementation of the first aspect, the first contact points of the two first external connection structures arranged adjacent to each other along the second direction are spaced apart by at least one row of bit lines, thereby further reducing the parasitic capacitance between the two first external connection structures M1 arranged adjacent to each other along the second direction Y.

[0024] In a possible implementation of the first aspect, the storage array further includes a plurality of second external connection structures, the plurality of second external connection structures are arranged on two sides of the substrate separately from the plurality of first external connection structures, and each second external connection structure is electrically connected with a bit line. In the plurality of second external connection structures, second contact points of a part of the second external connection structures are located between at least one pair of sub-matrices that belong to a same storage matrix and are arranged adjacently, and second contact points of another part of the second external connection structures are located between at least one pair of storage matrices arranged adjacently along the first direction; the second contact point is a part of the second external connection structure for electrical connection with the bit line.

[0025] The first external connection structure is used to externally connect the bit line to one side of the substrate, and the second external connection structure is used to externally connect the bit line to the other side of the substrate, so that both sides of the storage array can be electrically connected with other structures. The second external connection structure is arranged in a similar manner to the first external connection structure, so as to ensure that the side where the second external connection structure of the storage array is located also has a small parasitic capacitance.

[0026] In a possible implementation of the first aspect, the storage array further includes a plurality of first transfer parts, the plurality of first transfer parts are arranged between a layer where the first external connection structure is located and a layer where the plurality of bit lines are located, and the first external connection structure is electrically connected with the bit line through the first transfer part, so as to avoid deep hole digging in the process of electrical connection between the first external connection structure and the bit line, and reduce the preparation difficulty of the storage array.

[0027] In a possible implementation of the first aspect, the storage array further includes a plurality of third external connection structures.

[0028] In the plurality of third external connection structures, two adjacent word lines arranged along the second direction are electrically connected in pairs, and the connection positions are located between two storage matrices; in the plurality of columns of word lines arranged along the first direction, the connection positions of each pair of word lines in the odd-numbered column of word lines and the connection positions of each pair of word lines in the even-numbered column of word lines are staggered with each other in the first direction.

[0029] The plurality of third external connection structures are arranged on the same side of the substrate as the plurality of first external connection structures and are arranged at intervals from the plurality of first external connection structures; each third external connection structure is electrically connected with a pair of electrically connected word lines; a projection of a third contact point of the third external connection structure on the substrate overlaps a projection of a connection position of the pair of electrically connected word lines on the substrate; the third contact point is a part of the third external connection structure for electrical connection with the pair of electrically connected word lines.

[0030] The connection positions of each pair of word lines in the odd-numbered column of word lines and the connection positions of each pair of word lines in the even-numbered column of word lines are staggered with each other in the first direction, so that the third contact points of the third external connection structures in the odd-numbered column and the third contact points of the third external connection structures in the even-numbered column are also staggered with each other, thereby avoiding the problem of high parasitic capacitance caused by the distance between two adjacent third external connection structures in the first direction being too close, and also optimizing the electrical performance of the storage array.

[0031] In a possible implementation of the first aspect, in the plurality of third external connection structures, at least one pair of third external connection structures is arranged in a central symmetry, and the third contact points of the two third external connection structures arranged in the central symmetry are located on the same straight line extending in the first direction, the two third external connection structures extend in the second direction and extend in opposite directions respectively from the third contact points thereof, so that the facing area of the pair of third external connection structures in the first direction can be reduced, the parasitic capacitance generated between the at least one pair of adjacent third external connection structures can be reduced, and the electrical performance of the memory array is further optimized.

[0032] In a possible implementation of the first aspect, the plurality of pairs of third external connection structures arranged in the central symmetry are arranged in an array along the first direction and the second direction, and at least part of the first external connection structure is arranged between the two third external connection structures arranged adjacent to each other in the first direction. Thus, the first external connection structure and the third external connection structure arranged adjacent to each other are substantially arranged in a windmill manner, and the facing area with a long distance in the same direction between any conductive structures (the first external connection structure or the third external connection structure) is avoided, so that the parasitic capacitance is reduced.

[0033] In a possible implementation of the first aspect, in the plurality of pairs of third external connection structures arranged in the central symmetry, the two pairs of third external connection structures arranged adjacent to each other in the first direction are arranged in an axial symmetry, and the axis of symmetry extends in the second direction; and at least part of the first external connection structure is arranged between the two third external connection structures with a larger spacing in the first direction in the two pairs of third external connection structures arranged in the axial symmetry. Thus, in the case that at least one pair of first external connection structures is arranged in the axial symmetry in the plurality of first external connection structures, the first external connection structure and the third external connection structure arranged adjacent to each other can still be substantially arranged in a windmill manner, and the facing area with a long distance in the same direction between the conductive structures is also avoided, so that the parasitic capacitance is reduced.

[0034] In a second aspect, a memory is provided, which includes a peripheral circuit and the memory array provided in any one of the embodiments of the first aspect.

[0035] In the memory provided in the second aspect,

[0036] The technical effects brought by the memory provided in the second aspect can refer to the technical effects brought by the design of the memory array in the first aspect, which will not be described herein again.

[0037] In a possible implementation of the second aspect, the peripheral circuit includes a plurality of sensitive amplifiers and a plurality of sub-word line driving circuits, and the storage array includes a plurality of first external connection structures and a plurality of third external connection structures. At least one pair of first external connection structures adjacent in the first direction is electrically connected to the same sensitive amplifier, and the sub-word line driving circuit is electrically connected to the third external connection structure. Thus, the sensitive amplifier can amplify the subtle voltage difference between the two bit lines connected by the pair of first external connection structures, realize the selection of a certain bit line, and the sub-word line driving circuit can drive the transistor corresponding to the word line connected by the third external connection structure, so as to realize the selection of the storage unit through the selected bit line and the opened transistor.

[0038] In a third aspect, an electronic device is provided, which includes a bus and the memory provided in any one of the embodiments of the second aspect. The middle wire is electrically connected to the memory.

[0039] The technical effects brought by the electronic device in the third aspect can refer to the technical effects brought by the design of the storage array in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0040] FIG. 1 is a structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0041] FIG. 2 is a structural schematic diagram of a memory provided in an embodiment of the present application;

[0042] FIG. 3 is a structural schematic diagram of a storage wafer provided in an embodiment of the present application;

[0043] FIG. 4 is a top view of a memory provided in an embodiment of the present application;

[0044] FIG. 5 is a top view of a storage array provided in an embodiment of the present application;

[0045] FIG. 6 is a sectional view of a storage array provided in an embodiment of the present application;

[0046] FIG. 7 is an equivalent circuit diagram of a storage unit provided in an embodiment of the present application;

[0047] FIG. 8 is a partial enlarged view of a top view of a storage array provided in an embodiment of the present application;

[0048] FIG. 9 is another top view of a storage array provided in an embodiment of the present application;

[0049] FIG. 10 is another top view of a storage array provided in an embodiment of the present application;

[0050] FIG. 11 is another top view of a storage array provided in an embodiment of the present application;

[0051] FIG. 12 is another top view of a storage array, according to embodiments of the application;

[0052] FIG. 13 is another top view of a storage array, according to embodiments of the application;

[0053] FIG. 14 is another top view of a storage array, according to embodiments of the application;

[0054] FIG. 15 is another cross-sectional view of a storage array, according to embodiments of the application. DETAILED DESCRIPTION

[0055] The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments provided by the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0056] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0057] Unless otherwise required by the context, the term "comprises" is to be interpreted as an open, inclusive meaning, i.e. "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "exemplarily" or "some examples" and the like are intended to mean that a particular feature, structure, material or characteristic included in at least one embodiment or example of the present application. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, a particular feature, structure, material or characteristic can be included in any one or more embodiments or examples in any appropriate manner.

[0058] Hereinafter, the terms "first", "second", and the like are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0059] Connect / connected: can refer to a mechanical connection relationship or a physical connection relationship, that is, A and B are connected or A and B are connected can mean that there is a fastening component (such as a screw, a bolt, a rivet, etc.) between A and B, or A and B are in contact with each other and A and B are difficult to be separated, wherein A and B can be fixedly connected, or can be detachably connected, or can be integrated; can be directly connected, or can be indirectly connected through an intermediate medium.

[0060] Coupling: can be understood as direct coupling and / or indirect coupling, and "coupling connection" can be understood as direct coupling connection and / or indirect coupling connection. Direct coupling can also be referred to as "electrical connection", which is understood as that the components are in direct or indirect physical contact and are electrically conductive, for example, in the form of connection between different components in a circuit structure through an entity line such as a copper foil or a wire of a printed circuit board (PCB) that can transmit an electrical signal; "indirect coupling" can be understood as that two conductors are electrically conductive in a spaced / untouched manner. In an embodiment, indirect coupling can also be referred to as capacitive coupling, for example, signal transmission is realized by forming an equivalent capacitor through coupling between the gap between two conductive parts.

[0061] "A, B and C at least one of them" and "A, B or C at least one of them" have the same meaning, and include the following combinations of A, B and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B and C.

[0062] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0063] As used herein, "parallel", "perpendicular", "equal" include the stated case and the approximate case of the stated case, and the approximate case is within an acceptable deviation range, wherein the acceptable deviation range is determined by considering the measurement being discussed and the error related to the measurement of a specific quantity (i.e., the limitation of the measurement system) by a person of ordinary skill in the art. For example, "parallel" includes absolute parallel and approximate parallel, wherein the acceptable deviation range of approximate parallel can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicular and approximate perpendicular, wherein the acceptable deviation range of approximate perpendicular can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equalities is less than or equal to 5% of either one.

[0064] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic and many are shown exaggerated in number and / or size for clarity. The same reference numbers in different drawings represent the same or similar elements.

[0065] In addition, the scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, with the appearance of new scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0066] The electronic device provided by the embodiments of the present application may, for example, be a mobile phone, a tablet computer, a personal digital assistant, a television, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality terminal device, an augmented reality terminal device, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), a drone, a radar, an aerospace device, a vehicle-mounted device, a vehicle, or a terminal device of different types of user equipment. The electronic device may, for example, also be a network device such as a base station. The embodiments of the present application do not specially limit the specific form of the electronic device.

[0067] FIG. 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application.

[0068] Exemplarily, as shown in FIG. 1, the electronic device 1000 may, for example, include a bus 205 and a system on chip (SoC) 210 connected with the bus 205.

[0069] The system on chip 210 may, for example, be used for processing data, such as processing data of an application program, processing image data, and buffering temporary data.

[0070] Exemplarily, the system on chip 210 can include an application processor (AP) 211 for processing application programs, a graphics processing unit (GPU) 212 for processing image data, and an on-chip memory 213 for caching high-speed data.

[0071] Exemplarily, the on-chip memory 213 can be a static random access memory (SRAM) or an embedded flash (eflash), etc.

[0072] Exemplarily, the application processor 211, the graphics processing unit 212, and the on-chip memory 213 can be integrated in one die, or can be respectively arranged in multiple dies.

[0073] Exemplarily, as shown in FIG. 1, the electronic device 1000 can further include an off-chip memory 220 connected to the system on chip 210 through the bus 205.

[0074] Exemplarily, the off-chip memory 220 can be a dynamic random access memory (DRAM). The off-chip memory 220 can be used to save volatile data, such as temporary data generated by the system on chip 210. The storage capacity of the off-chip memory 220 is usually larger than that of the on-chip memory 213, but the reading speed is usually slower than that of the on-chip memory 213.

[0075] Exemplarily, the system on chip 210 and the off-chip memory 220 can be packaged in one packaging structure, such as a 2.5D (dimension) or 3D packaging, etc., to obtain a faster inter-chip data transmission rate.

[0076] Exemplarily, as shown in FIG. 1, the electronic device 1000 can further include a communication chip 230 and a power management chip 240 connected to the system on chip 210 through the bus 205.

[0077] The communication chip 230 can be used for processing of a protocol stack, or amplifying, filtering, etc. of analog radio frequency signals, or both. The power management chip 240 can be used for power supply of other chips.

[0078] It can be understood that the structure of the electronic device 1000 shown in FIG. 1 does not constitute a specific limitation on the electronic device 1000, and the electronic device 1000 can include more or fewer components than those shown in FIG. 1, or can combine certain components shown in FIG. 1, or can be arranged differently from the components shown in FIG. 1.

[0079] Embodiments of the present application also provide a memory 100, which can be applied in the electronic device 1000 described above, for example, the memory 100 can be the on-chip memory 213 shown in FIG. 1, or the memory 100 can also be the off-chip memory 220 shown in FIG. 1. Embodiments of the present application do not limit the specific application scenarios of the memory 100.

[0080] FIG. 2 is a structural schematic diagram of the memory 100 provided by embodiments of the present application. As shown in FIG. 2, the memory 100 includes a storage array 10 and a peripheral circuit 20.

[0081] For example, referring to FIG. 2, the storage array 10 and the peripheral circuit 20 can be formed on different wafers, for example, referring to FIG. 2, the storage array 10 can be formed on a storage wafer 10A, and the peripheral circuit 20 can be formed on a logic wafer 20A.

[0082] For example, referring to FIG. 2, the memory 100 can include at least one storage array 10 stacked, for example, referring to FIG. 2, the memory 100 can include two layers of storage wafers 10A stacked, and each layer of storage wafers 10A forms a storage array 10 thereon.

[0083] Referring to FIG. 2, the peripheral circuit 20 is stacked on one side of the storage array 10 and electrically connected to the storage array 10.

[0084] For example, the adjacent two layers of wafers are mixedly bonded, for example, the logic wafer 20A and the storage wafer 10A are mixedly bonded, so as to realize the electrical connection between the storage array 10 and the peripheral circuit 20. Or for example, the adjacent two layers of stacked storage wafers 10A can also be mixedly bonded.

[0085] FIG. 3 is a structural schematic diagram of a storage wafer 10A provided by embodiments of the present application, in which the storage array 10 is formed on the storage wafer 10A.

[0086] As shown in FIG. 3, a plurality of memory arrays 10 can be formed on a memory wafer 10A in an array manner, each memory array 10 can be divided into a plurality of memory matrices 2 in an array manner, each memory matrix 2 can include a plurality of word lines WL and a plurality of bit lines BL, the word lines WL and the bit lines BL cross each other, and a memory cell G is arranged at a position where the word lines WL and the bit lines BL cross each other, the memory cell G is used to store an electrical signal, for example, an electrical signal "1" or an electrical signal "0", and each memory matrix 2 can include a plurality of memory cells G arranged in an array manner.

[0087] FIG. 4 is a top view of the memory 100.

[0088] The peripheral circuit 20 is used to control access to the memory array 10. For example, the peripheral circuit 20 can control writing data to the memory array 10, or control reading data from the memory array 10.

[0089] For example, referring to FIG. 4, the peripheral circuit 20 can include a plurality of sense amplifiers (SA) and a plurality of sub-word line driver circuits (SWD).

[0090] Referring to FIG. 4, a pair of bit lines BL arranged adjacent to each other in the memory array 10 are electrically connected to the same sense amplifier SA, so that during driving of the memory array 10 by the peripheral circuit 20, the sense amplifier SA can amplify a voltage difference between the two bit lines BL electrically connected thereto, thereby achieving selection of one of the bit lines BL, that is, achieving selection of a plurality of memory cells G connected to the bit line BL.

[0091] Referring to FIG. 4, the word lines WL in the memory array 10 can be electrically connected to the sub-word line driver circuits SWD, for example, one sub-word line driver circuit SWD can be electrically connected to two word lines WL arranged adjacent to each other at the same time, thereby achieving driving of a plurality of memory cells G connected to the two word lines WL, and the sense amplifiers SA and the sub-word line driver circuits SWD jointly determine an address of a memory cell G to be accessed.

[0092] For example, the peripheral circuit 20 can further include a control circuit and a read-write circuit, etc.

[0093] For example, during a read-write operation on the memory array 10, the read-write circuit transmits a control signal to the sense amplifiers SA and the sub-word line driver circuits SWD through the control circuit, thereby determining an address of a memory cell G to be accessed, and achieving reading or writing of data.

[0094] The embodiment of the present application further provides a memory array 10.

[0095] FIG. 5 is a top view of the memory array 10 provided by the embodiment of the present application.

[0096] In some embodiments, as shown in FIG. 5, the storage array 10 includes a substrate 1, a plurality of storage matrices 2, a plurality of bit lines BL and a plurality of word lines WL, and a plurality of first external connection structures.

[0097] The substrate 1 serves as a carrier plate for carrying the plurality of storage matrices 2, the N groups of bit line groups A1-A N The substrate 1, the plurality of storage matrices 2, the N groups of bit line groups A1-A

[0098] Exemplarily, the material of the substrate 1 can include at least one of single crystal silicon (Si), single crystal germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), a group III-V compound semiconductor material, a group II-VI compound semiconductor material, or other semiconductor materials known in the art, or can also be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0099] It can be understood that the substrate 1 can be removed during the preparation of the storage array 10 or after the preparation is completed, or can be retained, which is not limited in the present application.

[0100] FIG. 6 is a cross-sectional view of the storage array 10 according to an embodiment of the present application.

[0101] Referring to FIGS. 5 and 6, the storage matrix 2 is disposed on the substrate 1. Referring to FIG. 5, the plurality of storage matrices 2 are arranged in a first direction X and a second direction Y.

[0102] Referring to FIGS. 5 and 6, the first direction X and the second direction Y are both parallel to the substrate 1, and the first direction X and the second direction Y intersect each other, for example, can be perpendicular to each other. For example, the first direction X can be the row direction in FIG. 5, and the second direction Y can be the column direction in FIG. 5.

[0103] Exemplarily, referring to FIG. 5, the length (the size in the first direction X) of one storage matrix 2 is approximately the length of one bit line BL, and the width (the size in the second direction Y) of one storage matrix 2 is approximately the length of one word line WL.

[0104] Exemplarily, referring to FIG. 5, the spacing between two storage matrices 2 arranged adjacent in the first direction X (for example, the spacing between two word lines WL belonging to the two storage matrices 2 and arranged adjacent) is greater than the spacing between two word lines WL arranged adjacent in the same storage matrix 2, so as to realize external connection of the bit line BL between the two storage matrices 2 arranged adjacent in the first direction X.

[0105] For example, referring to FIG. 5, the interval between two storage matrices 2 (for example, the interval between two bit lines BL belonging to the two storage matrices 2 and arranged adjacently) arranged adjacently along the second direction Y is greater than the interval between two bit lines BL arranged adjacently in the same storage matrix 2, so as to realize the external connection of the word lines WL between the two storage matrices 2 arranged adjacently along the second direction Y.

[0106] Referring to FIG. 5, each storage matrix 2 includes N sub-matrices B1-BN arranged at intervals along the first direction X. N Wherein, N is a positive integer, and N≥2, for example, N can be 2, 3, 4, 5, etc., that is, each storage matrix 2 can be divided into two, or three, or four, or five, etc. sub-matrices.

[0107] For example, referring to FIG. 5, each storage matrix 2 can be divided into two sub-matrices B1 and B2, that is, N=2. Or for example, each storage matrix 2 can be divided into four sub-matrices B1, B2, B3 and B4 (not shown in the figure), that is, N=4.

[0108] For example, referring to FIG. 5, the interval between two sub-matrices arranged adjacently along the first direction X (for example, the interval between two bit lines BL belonging to the two sub-matrices and arranged adjacently) is greater than the interval between two bit lines WL arranged adjacently in the same sub-matrix, that is, not simply regionally divided, but structurally divided, for example, the interval between the adjacent sub-matrices in the storage matrix 2 is more obvious, so as to realize the external connection of the bit lines BL between the two sub-matrices arranged adjacently along the first direction X.

[0109] Referring to FIG. 5, each sub-matrix (B1-BN in FIG. 5) includes a plurality of storage units G. N Each of the plurality of storage units G is arranged in an array along the first direction X and the second direction Y.

[0110] FIG. 7 is a circuit architecture diagram of a storage unit G provided by an embodiment of the present application.

[0111] Referring to FIG. 7, each storage unit G includes at least one transistor T.

[0112] Exemplarily, as shown in FIG. 7, the storage unit G can have a 1T1C (1-transistor-1-capacitor) structure (or a 1TnC structure, n is an integer greater than 1), that is, the storage unit G can include one transistor T and one (or n) capacitor C, the source of the transistor T is electrically connected with a bit line (BL), the drain is electrically connected with one electrode (for example, a storage electrode, also known as a storage node SN, please refer to FIG. 6) of the capacitor C, the gate is electrically connected with a word line (WL), and the other electrode (for example, a common electrode) of the capacitor C is electrically connected with a plate line (PL).

[0113] It can be understood that, in order to avoid forming an obstruction, the structure of the transistor T is not shown in FIG. 6, which does not mean that the transistor T does not exist, and the connection relationship of the transistor T in FIG. 6 can be referred to FIG. 7.

[0114] The circuit architecture of the storage unit G in the embodiments of the present application is not limited to the foregoing examples, and any circuit architecture that includes at least one transistor T and can achieve charge storage is within the protection scope of the embodiments of the present application, for example, the storage unit G in the embodiments of the present application can be a circuit architecture including a ferroelectric capacitor or a ferroelectric transistor.

[0115] It can be understood that, the foregoing "array arrangement" refers to arranging in rows along the first direction X and arranging in columns along the second direction Y, thereby forming a structure of multiple rows and multiple columns, for example, the array arrangement of the plurality of storage matrices 2 refers to forming multiple rows of storage matrices 2 and multiple columns of storage matrices 2, each row of storage matrices 2 and each column of storage matrices 2 includes a plurality of storage matrices 2, and similarly, the array arrangement of the plurality of storage units G refers to forming multiple rows of storage units G and multiple columns of storage units G, each row of storage units G and each column of storage units G includes a plurality of storage units G.

[0116] Referring to FIG. 5, the plurality of bit lines BL and the plurality of word lines WL are arranged in an array along the first direction X and the second direction Y, that is, the plurality of bit lines BL can be arranged in the first direction X and the second direction Y, and the plurality of word lines WL can be arranged in the first direction X and the second direction Y.

[0117] Referring to FIG. 5, the bit line BL extends along the first direction X, the word line WL extends along the second direction Y, the word line WL intersects with the bit line BL, and the intersection position of the two is the arrangement position of the storage unit G, thereby facilitating the electrical connection of the storage unit G with the word line WL and the bit line BL, forming the circuit architecture as shown in FIG. 7, and achieving the input and output of the signal of the storage unit G.

[0118] As can be understood with reference to Fig. 5, each word line WL is electrically connected with a plurality of bit lines BL arranged along the second direction Y so as to form a column of memory cells G in the memory matrix 2, and each bit line BL is electrically connected with a plurality of word lines WL arranged along the first direction X so as to form a row of memory cells G in the memory matrix 2, thereby forming the memory cells G arranged in an array.

[0119] As can be understood with reference to Fig. 5, each bit line BL is electrically connected with a plurality of memory cells G arranged along the first direction X in a sub-matrix of N number arranged along the first direction X, i.e., each bit line BL can span N number of sub-matrices, for example, a bit line BL can span N sub-matrices B1-BN in a memory matrix 2, or for example, a bit line BL can span the Nth sub-matrix BN in a memory matrix 2 to the 1st sub-matrix B1 to the N-1st sub-matrix BN-1 in an adjacent memory matrix 2. N , or for example, a bit line BL can span the Nth sub-matrix BN in a memory matrix 2 to the 1st sub-matrix B1 to the N-1st sub-matrix BN-1 in an adjacent memory matrix 2. N . N-1 .

[0120] That is, the length of each bit line BL is approximately the size of a memory matrix 2 in the first direction X, but each bit line BL does not span the entire memory matrix 2, but can also span part of the sub-matrices in multiple memory matrices 2.

[0121] As can be understood with reference to Fig. 5, each word line WL is electrically connected with a plurality of memory cells G arranged along the second direction Y in a memory matrix 2, i.e., a column of memory cells G. That is, the length of each word line WL is approximately the size of a memory matrix 2 in the second direction Y.

[0122] As can be understood with reference to Fig. 5, each sub-matrix is electrically connected with a plurality of word lines WL arranged along the first direction X at intervals, for example, as can be understood with reference to Fig. 5, four word lines WL are arranged in the region of each sub-matrix.

[0123] As can be understood with reference to Fig. 5, the spacing L1 between two word lines WL electrically connected with two sub-matrices arranged adjacent to each other along the first direction X and arranged adjacent to each other is greater than the spacing L2 between two word lines WL electrically connected with the same sub-matrix and arranged adjacent to each other.

[0124] As can be understood with reference to Fig. 5, the spacing L1 between two word lines WL electrically connected with two sub-matrices arranged adjacent to each other along the first direction X and arranged adjacent to each other includes the spacing L1 between two word lines WL arranged adjacent to each other in the region of two sub-matrices arranged adjacent to each other in the same memory matrix 2 and the spacing L1 between the two closest word lines WL in two memory matrices 2 arranged adjacent to each other along the first direction X.

[0125] That is, a large space is designed between two adjacent sub-matrices and between two adjacent memory matrices 2, so as to facilitate the subsequent setting of the first external connection structure M1.

[0126] Referring to FIG. 6, the first external connection structure M1 is arranged on a side of the substrate 1 away from the plurality of memory matrices 2, or on a side of the plurality of memory matrices 2 away from the substrate 1 (not shown in the figure), each of the first external connection structures M1 is electrically connected with a bit line BL, so as to facilitate the external connection of the bit line BL to the side of the substrate 1 away from the plurality of memory matrices 2, or to the side of the plurality of memory matrices 2 away from the substrate 1, so as to realize the electrical connection between the memory array 10 and other structures, for example, realize the electrical connection (for example, hybrid bonding) between the memory array 10 and the periphery circuit 20 arranged in a stack, or realize the electrical connection (for example, hybrid bonding) between two memory arrays 10 arranged in a stack.

[0127] Exemplarily, referring to FIG. 5, the first external connection structure M1 extends along the first direction X.

[0128] FIG. 8 is a partial enlarged view of a top view of the memory array 10 provided by the embodiment of the present application.

[0129] Exemplarily, as shown in FIG. 6 and FIG. 8, the memory array 10 can further include a plurality of first pads P1 arranged in a stack along the third direction Z on a side of the memory matrix 2, and the memory array 10 needs to realize hybrid bonding with the pads of other structures (for example, other memory arrays 10 or periphery circuits) through the first pads P1.

[0130] In the current memory 100, the spacing between two adjacent bit lines BL and the spacing between two adjacent word lines WL are relatively small, for example, the minimum spacing can reach the order of tens of nanometers, while the size and spacing of the pads (for example, the first pads P1) used to realize hybrid bonding are relatively large, for example, can reach the order of hundreds of nanometers or even several microns, and the difference between the two orders of magnitude is large.

[0131] For example, one first pad P1 can span a plurality of bit lines BL along the second direction Y, for example, three bit lines BL (as shown in FIG. 8), five bit lines BL or even dozens of bit lines BL, for example, two first pads P1 arranged adjacent along the first direction X can be spaced apart by a plurality of bit lines BL.

[0132] It can be understood that, in order to facilitate the structural diagram, only the relative position relationship of the first pad P1, the first external connection structure M1, the bit line BL and the word line WL is simply shown in Figure 8, and the actual size is not shown. It can be understood that, in the actual product, the first pad P1 in Figure 8 can cover more word lines WL and bit lines BL, and more word lines WL and bit lines BL can be spaced between two adjacent first pads P1, that is, the size of the first pad P1 and the spacing between adjacent first pads P1 are not limited in the embodiments of the present application and the drawings.

[0133] Referring to Figure 6, in order to avoid conflicts with other structures in the storage matrix 2, such as the positions of the bit line WL, the transistor T or the capacitor C, the word line BL cannot be directly externally connected to the first pad P1 stacked in the storage matrix 2, and therefore the bit line BL needs to be connected to the first pad P1 through the first external connection structure M1.

[0134] Referring to Figure 5, among the plurality of first external connection structures M1, the first contact Q1 of a part of the first external connection structures M1 is located between at least one pair of sub-matrices belonging to the same storage matrix 2 and arranged adjacent in the first direction (for example, between the first sub-matrix B1 and the second sub-matrix B2 in Figure 5), and the first contact Q1 of another part of the first external connection structures M1 is located between at least one pair of storage matrices 2 arranged adjacent in the first direction X. The first contact Q1 refers to the part of the first external connection structure M1 for electrical connection with the bit line BL.

[0135] For example, referring to Figure 5, the first contact Q1 of the first external connection structure M1 for electrical connection with the first group of bit line groups A1 is located between the first sub-matrix B1 and the second sub-matrix B2, and the first contact Q1 of the first external connection structure M1 for electrical connection with the second group of bit line groups A2 is located between two storage matrices 2.

[0136] It can be understood that each bit line BL needs to be externally connected, that is, a first external connection structure M1 and a first pad P1 need to be provided for each bit line BL.

[0137] In some embodiments, the first contacts Q1 of the plurality of first external connection structures M1 for implementing the bit line BL external connection are all located between two adjacent storage matrices 2, which causes the plurality of first external connection structures M1 to be concentrated in the setting position, thereby causing a larger parasitic capacitance, including increasing the parasitic capacitance generated between adjacent first external connection structures M1, and increasing the parasitic capacitance generated between adjacent connection columns V0 (see FIG. 6) for connecting the first external connection structure M1 and the bit line BL, affecting the electrical performance of the storage array 10, and in some embodiments, in order to avoid the position conflict between the plurality of first external connection structures M1 concentrated between two adjacent storage matrices 2 and other structures (for example, the third external connection structure M3 for implementing the word line WL external connection in FIG. 13), the plurality of first external connection structures M1 also need to be divided and arranged in multiple layers stacked along the third direction Z, which increases the difficulty of manufacturing the storage array 10.

[0138] In the storage array 10 provided by the embodiments of the present application, the storage matrix 2 is divided into N sub-matrices B1-BN along the first direction X, and the first external connection structure M1 is arranged in each sub-matrix B1-BN. N The interval between adjacent sub-matrices and the interval between adjacent storage matrices 2 are both larger than the interval L2 between two adjacent word lines WL in the same sub-matrix, thereby increasing the area available for the first external connection structure M1, so that part of the first external connection structure M1 can be arranged between adjacent storage matrices 2, and the remaining part of the first external connection structure M1 can be arranged between adjacent sub-matrices, thereby achieving the dispersed arrangement of the plurality of first external connection structures M1, avoiding the concentration of the plurality of first external connection structures M1 between adjacent storage matrices 2, thereby reducing the parasitic capacitance generated between two adjacent first external connection structures M1, and reducing the parasitic capacitance generated between adjacent connection columns V0 (see FIG. 6) for connecting the first external connection structure M1 and the bit line BL, thereby improving the electrical performance of the storage array 10.

[0139] In addition, after the plurality of first external connection structures M1 are dispersedly arranged, the interval between at least part of the adjacent first external connection structures M1 is increased, and the positional constraint between them is reduced, thereby increasing the flexibility in deforming the shape of a single first external connection structure M1, for example, there is more space for the first external connection structure M1 to be designed in axial symmetry or central symmetry (see subsequent FIG. 11 and FIG. 5), so as to flexibly adjust the extension direction, setting area, etc. of the first external connection structure M1 according to the setting position of other structures (for example, the third external connection structure M3 in subsequent FIG. 13), avoiding the positional conflict between the first external connection structure M1 and other structures, or avoiding a larger parasitic capacitance between the first external connection structure M1 and other structures.

[0140] In addition, in the case that the first external connection structures M1 are dispersedly arranged, the first pads P1 electrically connected with the first external connection structures M1 can also be dispersedly arranged, so as to avoid the problem that the large parasitic capacitance is caused by the concentrated arrangement of the plurality of first pads P1, and further optimize the electrical performance of the storage array 10. Similarly, in the case that the first external connection structures M1 are dispersedly arranged, the connection columns for electrically connecting the first external connection structures M1 and the bit lines BL can also be dispersedly arranged, and the generation of the parasitic capacitance can also be reduced.

[0141] It can be understood that, in the storage array 10 provided by the embodiments of the present application, only by increasing the spacing between the opposite two word lines WL in the adjacent sub-matrices and prolonging the bit lines BL by a short length (for example, the length of the prolongation is the increased spacing between the opposite two word lines WL in the adjacent sub-matrices), the dispersed arrangement of the plurality of first external connection structures M1 can be realized, without the need to increase the design space of the first external connection structures M1 in a large area between the adjacent storage matrices 2, and without the need to arrange the film layer in which the plurality of first external connection structures M1 are arranged, so that the influence on the storage density and the preparation difficulty of the storage array 10 is small.

[0142] In some embodiments, referring to FIG. 5, N groups of bit line groups A1-A N That is, the plurality of bit lines BL for electrically connecting with the plurality of storage units G in a row of storage matrices 2 are divided into N groups of bit line groups A1-A N For example, referring to FIG. 5, the first row of storage matrices 2 is correspondingly arranged with two groups of bit line groups (N=2), that is, the first group of bit line groups A1 and the second group of bit line groups A2.

[0143] Referring to FIG. 5, the N groups of bit line groups A1-A N are arranged along the second direction Y, each group of bit line groups includes a plurality of rows of bit lines BL arranged at intervals along the second direction Y, each row of bit lines BL includes a plurality of bit lines BL arranged at intervals along the first direction X, and each bit line BL extends along the first direction X.

[0144] For example, referring to FIG. 5, the first group of bit line groups A1 includes four rows of bit lines BL, that is, the first row of bit lines BL, the third row of bit lines BL, the fifth row of bit lines BL and the seventh row of bit lines BL, and the second group of bit line groups A2 also includes four rows of bit lines BL, that is, the second row of bit lines BL, the fourth row of bit lines BL, the sixth row of bit lines BL and the eighth row of bit lines BL.

[0145] Referring to FIG. 5, the N groups of bit line groups A1-A NIn the first group of bit line groups A1, each bit line BL is electrically connected to a plurality of memory cells G arranged along the first direction X in one of the memory matrices 2, i.e. each bit line BL electrically connected to a row of memory cells G in one of the complete memory matrices 2 belongs to the first group of bit line groups A1 to A N In the first group of bit line groups A1, each bit line BL is electrically connected to a plurality of memory cells G arranged along the first direction X in one of the memory matrices 2, i.e. each bit line BL electrically connected to a row of memory cells G in one of the complete memory matrices 2 belongs to the first group of bit line groups A1 to A

[0146] For example, referring to Fig. 5, each of the first, third, fifth and seventh bit lines BL corresponds to the region of one complete memory matrix 2, i.e. each bit line BL in the first group of bit line groups A1 does not span a plurality of memory matrices 2 along the first direction X.

[0147] Referring to Fig. 5, the N groups of bit line groups A1 to A N In the M+1th group of bit line groups A M+1 In the M+1th group of bit line groups A M+1 each bit line BL is electrically connected to a plurality of memory cells G arranged along the first direction X in the M+1th sub-matrix B N to the Nth sub-matrix B M of one of the memory matrices 2, as well as to a plurality of memory cells G arranged along the first direction X in the first sub-matrix B1 to the Mth sub-matrix B M+1 of the adjacent memory matrix 2, i.e. a bit line BL electrically connected to a row of memory cells G in the M+1th sub-matrix B N to the Nth sub-matrix B M of one of the two memory matrices 2, as well as to a row of memory cells G in the first sub-matrix B1 to the Mth sub-matrix B N of the other one of the two memory matrices 2 belongs to the M+1th group of bit line groups A M+1 In the M+1th group of bit line groups A M+1 each bit line BL is electrically connected to a plurality of memory cells G arranged along the first direction X in the M+1th sub-matrix B M and the Nth sub-matrix B M+1 of one of the memory matrices 2, as well as to a plurality of memory cells G arranged along the first direction X in the first sub-matrix B1 to the Mth sub-matrix B

[0148] where M is a positive integer and M+1 < N, for example M = 1 for N = 2, or for example M can be 1, 2, 3 or 4 for N = 5.

[0149] For example, referring to FIG. 5, N = 2, M = 1, each of the second row of bit lines BL, the fourth row of bit lines BL, the sixth row of bit lines BL and the eighth row of bit lines BL corresponds to be arranged in two adjacent storage matrices 2, the second sub-matrix of the left storage matrix 2 and the first sub-matrix of the right storage matrix 2, that is, each of the second group of bit lines A2 in FIG. 5 crosses the adjacent sub-matrices of the two storage matrices 2 in the first direction X.

[0150] By dividing the storage matrix 2 into N sub-matrices B1-B N , and correspondingly dividing the plurality of bit lines BL into N groups of bit lines A1-A N , and designing the arrangement positions of the N groups of bit lines A1-A N according to the foregoing rules, so that the bit lines BL in different groups of bit lines cross at least one different sub-matrix, thereby facilitating the arrangement position of the first external connection structure M1 to be designed correspondingly according to the arrangement rule of the bit lines BL, for example, the end of the first external connection structure M1 is electrically connected with the bit line BL, then the ends of the bit lines BL in different groups of bit lines are regularly located between different sub-matrices, and the plurality of first external connection structures M1 are also regularly distributed between different sub-matrices, facilitating the plurality of first external connection structures M1 to be more evenly distributed, thereby making the parasitic capacitances at different positions of the storage array 10 approximately the same, and improving the consistency of the electrical performance of the storage units G at different positions of the storage array 10.

[0151] FIGS. 9 and 10 are other top views of the storage array 10 provided by the embodiments of the present application.

[0152] In some embodiments, referring to FIGS. 5, 9 and 10, the plurality of rows of bit lines BL in the first group of bit lines A1 to the plurality of rows of bit lines BL in the Nth group of bit lines A N are arranged in turn along the second direction Y.

[0153] That is, after the first row of bit lines BL in the first group of bit lines A1 to the first row of bit lines BL in the Nth group of bit lines A N are arranged in turn along the second direction Y, the second row of bit lines BL in the first group of bit lines A1 to the second row of bit lines BL in the Nth group of bit lines A N are arranged in turn, and the Nth row of bit lines BL in the first group of bit lines A1 to the Nth row of bit lines BL in the Nth group of bit lines A N are arranged in turn.

[0154] For example, referring to FIG. 5, N = 2, each row of the storage matrix 2 corresponds to 2 groups of bit lines, the first group of bit lines A1 includes the bit lines BL in the odd rows among the multiple rows of bit lines BL arranged at intervals along the second direction Y, and the second group of bit lines A2 includes the bit lines BL in the even rows among the multiple rows of bit lines BL arranged at intervals along the second direction Y.

[0155] That is, all the bit lines BL in the odd rows belong to the first group of bit lines A1, and all the bit lines BL in the even rows belong to the second group of bit lines A2. In the case of N = 2, the N groups of bit lines A1-A N

[0156] For example, referring to FIG. 9 and FIG. 10, the number of storage units G in each storage matrix 2 is large, and the number of first external connection structures M1 to be arranged is also large. The storage matrix 2 can be divided into more sub-matrices, and the bit lines BL can be divided into more groups of bit lines, so that compared with FIG. 5, the area available for arranging the first external connection structures M1 is further increased.

[0157] For example, N = 3, referring to FIG. 9 and FIG. 10, each storage matrix 2 is divided into 3 sub-matrices, each row of the storage matrix 2 corresponds to 3 groups of bit lines, among the multiple rows of bit lines BL arranged at intervals along the second direction Y, the bit lines BL in the 1st row, the 4th row, the 7th row, and the 10th row belong to the first group of bit lines A1, the bit lines BL in the 2nd row, the 5th row, the 8th row, and the 11th row belong to the second group of bit lines A2, and the bit lines BL in the 3rd row, the 6th row, the 9th row, and the 12th row belong to the third group of bit lines A3.

[0158] By arranging the multiple rows of bit lines BL in the first group of bit lines A1 to the multiple rows of bit lines BL in the Nth group of bit lines A N That is, all the bit lines BL in the odd rows belong to the first group of bit lines A1, and all the bit lines BL in the even rows belong to the second group of bit lines A2. In the case of N = 2, the N groups of bit lines A1-A

[0159] ​For example, referring to FIG. 5, the first external connection structure M1 electrically connected to the bit line BL in the first group of bit line groups A1 and the first external connection structure M1 electrically connected to the bit line BL in the second group of bit line groups A2 are staggered with each other in the second direction Y, so that the first external connection structures M1 corresponding to different groups of bit line groups do not have a facing area, thereby avoiding parasitic capacitance between the first external connection structures M1 corresponding to different groups of bit line groups. In addition, the first external connection structures M1 corresponding to two adjacent rows of bit lines (e.g., the first row of bit lines BL and the third row of bit lines BL) in the first group of bit line groups A1 are spaced apart by one row of bit lines BL in the second direction Y, thereby reducing parasitic capacitance between the first external connection structures M1 corresponding to the same group of bit line groups.

[0160] For example, referring to FIG. 9 and FIG. 11, the first external connection structure M1 electrically connected to the bit line BL in the first group of bit line groups A1, the first external connection structure M1 electrically connected to the bit line BL in the second group of bit line groups A2, and the first external connection structure M1 electrically connected to the bit line BL in the third group of bit line groups A3 are staggered with each other in the second direction Y, so that the first external connection structures M1 corresponding to different groups of bit line groups do not have a facing area, thereby avoiding parasitic capacitance between the first external connection structures M1 corresponding to different groups of bit line groups. In addition, the first external connection structures M1 corresponding to two adjacent rows of bit lines (e.g., the first row of bit lines BL and the fourth row of bit lines BL) in the first group of bit line groups A1 are spaced apart by two rows of bit lines BL in the second direction Y, thereby reducing parasitic capacitance between the first external connection structures M1 corresponding to the same group of bit line groups.

[0161] FIG. 11 and FIG. 12 are other top views of the storage array 10 according to embodiments of the present application.

[0162] In some embodiments, referring to FIG. 11 and FIG. 12, the first group of bit line groups A1 to the Nth group of bit line groups AN are arranged in the second direction Y. N are arranged in the second direction Y.

[0163] That is, the N groups of bit line groups A1 to AN are arranged in the second direction Y. N are arranged in the second direction Y.

[0164] For example, referring to FIG. 11, N=2, and each row of the storage matrix 2 corresponds to two groups of bit line groups. Each row of the storage matrix 2 is divided into a first part 21 and a second part 22, and the first part 21 and the second part 22 are arranged in the second direction Y. The first group of bit line groups A1 is arranged in the region of the first part 21, and the second group of bit line groups A2 is arranged in the region of the second part 22.

[0165] For example, referring to FIG. 12, each storage matrix 2 is divided into three sub-matrices, and each row of the storage matrix 2 corresponds to three groups of bit line groups. The first group of bit line groups A1, the second group of bit line groups A2, and the third group of bit line groups AN are arranged in the second direction Y.

[0166] Exemplarily, in this embodiment, each group of bit line groups can include 2 rows of bit lines BL or more rows of bit lines BL, for example, in FIG. 11 and FIG. 12, the structure is schematically shown by taking an example of each group of bit line groups BL containing 4 rows of bit lines BL.

[0167] By setting the 1st group of bit line groups A1 to the Nth group of bit line groups A N Similarly, by changing the setting position of the bit line groups, the different first external connection structures M1 belonging to different bit line groups are located between different sub-matrices, so that the different first external connection structures M1 are staggered with each other in the second direction Y, thereby reducing the parasitic capacitance.

[0168] Exemplarily, referring to FIG. 11 and FIG. 12, in this embodiment, the first external connection structures M1 electrically connected by the two rows of bit lines BL located in the same group of bit line groups and arranged adjacent to each other are staggered with each other in the second direction Y, thereby avoiding the parasitic capacitance between the first external connection structures M1 corresponding to the same group of bit line groups.

[0169] On the basis of the foregoing embodiment of increasing the setting area of the first external connection structure M1 to reduce the parasitic capacitance, the arrangement rule of the first external connection structure M1 can also be designed to further reduce the parasitic capacitance, for details, refer to the following embodiments.

[0170] In some embodiments, as shown in FIG. 9, a plurality of first external connection structures M1 can be arranged in sequence along the second direction Y to form a plurality of columns of first external connection structures M1, and two first external connection structures M1 adjacent to each other along the second direction Y can be symmetrical, and the plurality of first external connection structures M1 are regularly arranged, which can reduce the preparation difficulty of the storage array 10 while achieving the dispersed arrangement of the first external connection structure M1 and reducing the parasitic capacitance.

[0171] In some embodiments, as shown in FIG. 5 and FIG. 10, at least one pair of first external connection structures M1 in the plurality of first external connection structures M1 are arranged in central symmetry, and the first contact points Q1 of the two first external connection structures M1 arranged in central symmetry are located on the same straight line extending along the second direction Y, and the two first external connection structures M1 extend along the first direction X and extend in opposite directions respectively from the first contact points Q1 thereof as the starting points.

[0172] For example, referring to FIG. 5, in the first column of first contact points Q1 on the left, the second first contact point Q1 and the third first contact point Q1 from top to bottom correspond to two first external connection structures M1 arranged in central symmetry, and one extends to the left and the other extends to the right.

[0173] For example, referring to FIG. 10, two first external connection structures M1 corresponding to every two adjacent first contact points Q1 in the second direction Y are arranged in central symmetry, and one extends to the left and the other extends to the right.

[0174] By arranging at least one pair of first external connection structures M1 in central symmetry, the opposite area of the pair of first external connection structures M1 in the second direction Y can be reduced, thereby further reducing the parasitic capacitance generated between at least one pair of adjacent first external connection structures M1, and further optimizing the electrical performance of the storage array 10.

[0175] For example, referring to FIG. 10, in the case that the storage array 10 is electrically connected to the peripheral circuit 20, a sensitive amplifier SA in the peripheral circuit 20 can be arranged between two first external connection structures M1 arranged adjacent in the first direction X, so as to realize the electrical connection between the sensitive amplifier SA and the two first external connection structures M1 arranged adjacent.

[0176] In some embodiments, as shown in FIGS. 11 and 12, at least one pair of first external connection structures M1 in the plurality of first external connection structures M1 are arranged in axial symmetry, and the axis of symmetry extends in the second direction Y. The first contact points Q1 of the two first external connection structures M1 arranged in axial symmetry are respectively electrically connected to opposite two ends of two bit lines BL arranged adjacent in the first direction X. The two first external connection structures M1 extend in the first direction X and extend in opposite directions respectively from the first contact points Q1 thereof.

[0177] For example, referring to FIGS. 11 and 12, two first external connection structures M1 arranged adjacent in the first direction X are arranged in central symmetry, and one extends to the left and the other extends to the right.

[0178] By arranging at least one pair of first external connection structures M1 in axial symmetry in the first direction X, the pair of first external connection structures M1 can be close to each other in the first direction X, thereby facilitating the electrical connection of the pair of first external connection structures M1 to the same sensitive amplifier SA in the peripheral circuit 20.

[0179] For example, referring to FIG. 11, in the case that the storage array 10 is electrically connected to the peripheral circuit 20, a sensitive amplifier SA in the peripheral circuit 20 can be arranged between two first external connection structures M1 arranged adjacent in the first direction X. Referring to FIGS. 11 and 12, the two first external connection structures M1 arranged in axial symmetry in the first direction X are close to each other, and the sensitive amplifier SA can be connected to the two first external connection structures M1 without long-distance wiring, thereby reducing the difficulty of manufacturing the memory 100.

[0180] It can be understood that, in order to avoid forming an obstruction, only one sensitive amplifier SA is used to schematically show the setting position in FIGS. 10 and 11, and it does not mean that no sensitive amplifier SA is set at other positions. The sensitive amplifiers SA can be set between every two first external connection structures M1 in pairs along the first direction X.

[0181] It can be understood that, FIGS. 5, 9, 10, 11 and 12 are only exemplary. In other embodiments, the first external connection structures M1 in FIGS. 5, 9 and 10 can be arranged in axial symmetry, and the first external connection structures M1 in FIGS. 11 and 12 can be arranged in central symmetry, or in other embodiments, part of the first external connection structures M1 can be arranged in axial symmetry, and part of the first external connection structures M1 can be arranged in central symmetry, and the embodiments of the present application do not limit this.

[0182] In some embodiments, referring to FIGS. 5, 9 and 10, the first contact Q1 of the first external connection structure M1 can be arranged at the middle region (i.e., the region except the two ends) of a bit line BL.

[0183] For example, referring to FIG. 5, the first contact Q1 of the first external connection structure M1 is arranged at the midpoint of the bit line BL. In the case of N=2, the midpoint of the bit line BL in the first bit line group A1 is located between two adjacent sub-matrices (i.e., the first sub-matrix B1 and the second sub-matrix B2 in FIG. 5) in the same memory matrix 2, and the midpoint of the bit line BL in the second bit line group A2 is located between two adjacent memory matrices 2. Arranging the first contact Q1 of the first external connection structure M1 at the midpoint of the corresponding bit line BL can make the plurality of first external connection structures M1 be uniformly and regularly arranged between the two sub-matrices and between the two memory matrices 2 according to the change rule of the bit line BL.

[0184] For example, referring to FIGS. 9 and 10, the first contacts Q1 of the first external connection structures M1 are arranged at the one-third positions of the bit lines BL. In the case of N = 3, the one-third positions of the bit lines BL in the first group A1 are located between the first and second adjacent sub-matrices (the first sub-matrix B1 and the second sub-matrix B2 in FIG. 9) in the same memory matrix 2, the one-third positions of the bit lines BL in the second group A2 are located between the second and third adjacent sub-matrices (the second sub-matrix B2 and the third sub-matrix B3 in FIG. 9) in the same memory matrix 2, and the one-third positions of the bit lines BL in the third group A3 are located between the two adjacent memory matrices 2. Arranging the first contacts Q1 of the first external connection structures M1 at the one-third positions of the corresponding bit lines BL can also make the first external connection structures M1 regularly and uniformly arranged between the two sub-matrices and the two memory matrices 2 according to the variation of the bit lines BL. The same applies to the case of N = 3 in FIG. 12 and the case of other values of N in other embodiments.

[0185] In some embodiments, referring to FIGS. 11 and 12, the first contacts Q1 of the first external connection structures M1 can be arranged at the end portions of the bit lines BL.

[0186] For example, referring to FIG. 11, in the case of N = 2, the end portions of the bit lines BL in the first group A1 are located between the two adjacent memory matrices 2, and the end portions of the bit lines BL in the second group A2 are located between the first and second adjacent sub-matrices (the first sub-matrix B1 and the second sub-matrix B2 in FIG. 11) in the same memory matrix 2. Arranging the first contacts Q1 of the first external connection structures M1 at the end portions of the corresponding bit lines BL can also make the first external connection structures M1 regularly and uniformly arranged between the two sub-matrices and the two memory matrices 2 according to the variation of the bit lines BL. The same applies to the case of N = 3 in FIG. 12 and the case of other values of N in other embodiments, which will not be described herein again.

[0187] It can be understood that in other embodiments, the first contacts Q1 of some of the first external connection structures M1 can be arranged at the middle regions of the bit lines BL and the first contacts Q1 of the other first external connection structures M1 can be arranged at the end portions of the bit lines BL according to the arrangement positions of other structures (for example, the third external connection structures M3 in FIG. 13 or other conductive structures). For example, the first contacts Q1 of the first external connection structures M1 in FIGS. 5, 9 and 10 can be arranged at the end portions of the bit lines BL, or for example, the first contacts Q1 of some of the first external connection structures M1 in FIGS. 11 and 12 can be arranged at the middle regions of the bit lines BL and the first contacts Q1 of the other first external connection structures M1 can be arranged at the end portions of the bit lines BL, which is not limited in the present application.

[0188] In some embodiments, referring to FIG. 5, FIG. 9, FIG. 10, FIG. 11 and FIG. 12, at least one row of bit lines BL is arranged between the first contacts Q1 of two first external connection structures M1 arranged adjacently along the second direction Y, so as to further reduce the parasitic capacitance generated between the two first external connection structures M1 arranged adjacently along the second direction Y.

[0189] For example, referring to FIG. 5, one row of bit lines BL can be arranged, or referring to FIG. 9 and FIG. 10, two rows of bit lines BL can be arranged, or in other embodiments, more rows of bit lines BL can be arranged, and the value of N can be determined according to the tolerance of the parasitic capacitance and the storage density of the storage unit G (i.e. the density of the bit lines BL). For example, referring to FIG. 9, FIG. 10 and FIG. 12, in the case that the storage unit G has a high density in a storage matrix 2, the storage matrix 2 can be divided into three or more sub-matrices, so that the first external connection structures M1 are arranged more dispersedly, for example, more rows of bit lines BL are arranged between the first contacts Q1 of two first external connection structures M1 arranged adjacently along the second direction Y, so as to increase the degree of reduction of the parasitic capacitance, and improve the electrical performance of the storage array 10 as needed.

[0190] FIG. 13 and FIG. 14 are other top views of the storage array 10 according to embodiments of the present application, and FIG. 15 is another sectional view of the storage array 10 according to embodiments of the present application.

[0191] In some embodiments, referring to FIG. 13 and FIG. 14, the storage array 10 includes a plurality of word lines WL, and the plurality of word lines WL are arranged along the first direction X and the second direction Y, and each word line WL is electrically connected to the plurality of storage units G arranged along the second direction Y in one storage matrix 2 (refer to FIG. 7).

[0192] Referring to FIG. 13 and FIG. 14, the word lines WL arranged adjacently along the second direction Y are electrically connected in pairs, and the connection positions are located between two storage matrices 2, so that when electrically connected to the peripheral circuit 20, the sub-word line driving circuit SWD in the peripheral circuit 20 can simultaneously drive two word lines WL.

[0193] Referring to FIG. 13 and FIG. 14, in the plurality of columns of word lines WL arranged along the first direction X, the connection positions of each pair of word lines WL in the odd-numbered columns of word lines WL are staggered with the connection positions of each pair of word lines WL in the even-numbered columns of word lines WL along the first direction X, so as to facilitate the subsequent arrangement of the third external connection structures M3.

[0194] In some embodiments, referring to FIG. 13 and FIG. 14, the memory array 10 further comprises a plurality of third external connection structures M3 for implementing external connection of the word lines WL, for example, implementing connection between the word lines WL and the sub-word line driving circuit SWD in the peripheral circuit 20.

[0195] Exemplarily, referring to FIG. 13 and FIG. 14, the third external connection structures M3 extend along the second direction Y.

[0196] The plurality of third external connection structures M3 are arranged on the same side of the substrate as the plurality of first external connection structures M1, for example, referring to FIG. 6 and FIG. 15, the first external connection structures M1 and the third external connection structures M3 are both arranged on the side of the substrate 1 away from the memory matrix 2.

[0197] Referring to FIG. 13 and FIG. 14, the third external connection structures M3 are arranged apart from the first external connection structures M1 to avoid mutual interference of electrical signals between the word lines WL and the bit lines BL.

[0198] Referring to FIG. 13 and FIG. 14, each of the third external connection structures M3 is electrically connected with a pair of electrically connected word lines WL, and the third contact Q3 of the third external connection structure M3 has a projection on the substrate 1 that coincides with the projection on the substrate 1 of the connection position of the pair of word lines WL, that is, the third contact Q3 of the third external connection structure M3 is also located between the memory matrices 2 arranged adjacent along the second direction Y.

[0199] Here, the third contact Q3 refers to the part of the third external connection structure M3 for electrical connection with the pair of electrically connected word lines WL.

[0200] Referring to FIG. 13 and FIG. 14, the connection positions of each pair of word lines WL in the odd-numbered column word lines WL are staggered with the connection positions of each pair of word lines WL in the even-numbered column word lines WL in the first direction X, and the third contacts Q3 of the third external connection structures M3 in the corresponding odd-numbered column are also staggered with the third contacts Q3 of the third external connection structures M3 in the even-numbered column, avoiding the problem of too close distance between two third external connection structures M3 in the first direction X leading to high parasitic capacitance, and also optimizing the electrical performance of the memory array 10.

[0201] In some embodiments, referring to FIG. 13 and FIG. 14, among the plurality of third external connection structures M3, at least one pair of third external connection structures M3 are arranged in central symmetry, and the third contacts Q3 of the two third external connection structures M3 arranged in central symmetry are located on the same straight line extending along the first direction X, and the two third external connection structures M3 extend along the second direction Y and extend in opposite directions respectively from their own third contacts Q3 as the starting point.

[0202] For example, referring to FIG. 13 and FIG. 14, the first and second third contacts Q3 between the first and second storage matrices 2 are arranged in a center-symmetrical manner from left to right, and one extends downward and the other extends upward. The same applies to FIG. 14.

[0203] By arranging at least one pair of third external connection structures M3 in a center-symmetrical manner, the facing area of the pair of third external connection structures M3 in the first direction X can be reduced, thereby further reducing the parasitic capacitance between at least one pair of adjacent third external connection structures M3, and further optimizing the electrical performance of the storage array 10.

[0204] In some embodiments, referring to FIG. 13, a plurality of pairs of third external connection structures M3 arranged in a center-symmetrical manner are arranged in an array along the first direction X and the second direction Y, and at least part of the first external connection structure M1 is arranged between two third external connection structures M3 arranged adjacent to each other along the first direction X, so that the adjacent first and third external connection structures M1 and M3 are arranged in a substantially windmill manner, thereby avoiding a long facing area between the conductive structures (the first and third external connection structures M1 and M3) in the same direction (for example, the first direction X or the second direction Y), thereby reducing the parasitic capacitance.

[0205] For example, referring to FIG. 13, in the case where a plurality of pairs of third external connection structures M3 arranged in a center-symmetrical manner are arranged in an array along the first direction X and the second direction Y, the pairs of first external connection structures M1 are also arranged in a center-symmetrical manner, which can maximize the use of design space while avoiding position conflicts between the first and third external connection structures M1 and M3.

[0206] In some embodiments, referring to FIG. 14, among a plurality of pairs of third external connection structures M3 arranged in a center-symmetrical manner, two pairs of third external connection structures M3 arranged adjacent to each other along the first direction X are arranged in an axial-symmetrical manner, and the axis of symmetry extends along the second direction Y. At least part of the first external connection structure M1 is arranged between two third external connection structures M3 having a larger spacing in the first direction among the two pairs of third external connection structures M3 arranged in an axial-symmetrical manner, so that in the case where at least one pair of first external connection structures M1 is arranged in an axial-symmetrical manner among a plurality of first external connection structures M1, the adjacent first and third external connection structures M1 and M3 can still be arranged in a substantially windmill manner, thereby avoiding a long facing area between the conductive structures (the first and third external connection structures M1 and M3) in the same direction (for example, the first direction X or the second direction Y), thereby reducing the parasitic capacitance.

[0207] It can be understood that in other embodiments, the arrangement of the third external connection structures M3 can be designed according to different arrangement rules of the first external connection structures M1, and the embodiments of the present application do not limit the same.

[0208] Exemplarily, referring to FIG. 15, similar to the first pad P1, each third external connection structure M3 is also correspondingly provided with a third pad P3, so as to realize hybrid bonding of the memory array 10 and other structures (the peripheral circuit 20 or other memory arrays 10).

[0209] Exemplarily, in the case that the memory array 10 is electrically connected with the peripheral circuit 20, the orthographic projection of the sub-word line driving circuit SWD in the peripheral circuit 20 on the substrate 1 can overlap with the orthographic projection of the third pad P3 on the substrate 1, that is, the sub-word line driving circuit SWD can be directly connected to the third pad P3 without long-distance wiring.

[0210] In some embodiments, referring to FIG. 6, the memory array 10 can further include a plurality of first adapters E1, which are arranged between the layer where the first external connection structure M1 is located and the layer where the plurality of bit lines BL are located, and the first external connection structure M1 and the bit line BL are electrically connected through the first adapter E1, so as to avoid deep hole digging in the process of electrical connection between the first external connection structure M1 and the bit line BL, and reduce the preparation difficulty of the memory array 10.

[0211] In some embodiments, referring to FIG. 15, the memory array 10 can further include a plurality of second adapters E2, which are arranged between the layer where the third external connection structure M3 is located and the layer where the plurality of word lines WL are located, and the third external connection structure M3 and the word line WL are electrically connected through the second adapter E2, so as to avoid deep hole digging in the process of electrical connection between the third external connection structure M3 and the word line WL, and reduce the preparation difficulty of the memory array 10.

[0212] Exemplarily, referring to FIG. 6 and FIG. 15, in the case that the memory cell G includes the capacitor C, the first adapter E1 and the second adapter E2 can be arranged in the layer where one plate of the capacitor C is located, for example, in the film layer where the storage node SN is located.

[0213] In some embodiments, as shown in FIG. 6, the memory array 10 can further include a plurality of second external connection structures M2, which are respectively arranged on two sides of the substrate 1 with the plurality of first external connection structures M1, for example, referring to FIG. 6, the plurality of first external connection structures M1 are located below the substrate 1, and the plurality of second external connection structures M2 are located above the substrate 1, that is, the first external connection structure M1 is used for externally connecting the bit line BL to one side of the substrate 1, and the second external connection structure M2 is used for externally connecting the bit line BL to the other side of the substrate 1, so that both sides of the memory array 10 can be electrically connected with other structures, for example, the side of the memory array 10 where the first external connection structure M1 is arranged can be electrically connected with the peripheral circuit 20, and the side of the memory array 10 where the second external connection structure M2 is arranged can be electrically connected with another memory array 10.

[0214] Exemplarily, each second external connection structure M2 is electrically connected with a bit line BL, and in the plurality of second external connection structures M2, second contacts Q2 of a part of the second external connection structures M2 are located between at least one pair of sub-matrices which are adjacently arranged along the first direction X and belong to the same memory matrix 2, and second contacts Q2 of another part of the second external connection structures M2 are located between at least one pair of memory matrices 2 which are adjacently arranged along the first direction X, so as to ensure that the side where the second external connection structures M2 of the memory array 10 are located also has a smaller parasitic capacitance. The setting rule and effect of the second external connection structures M2 are similar to those of the first external connection structures M1, and thus will not be described herein again.

[0215] The second contact Q2 refers to a part of the second external connection structure M2 for electrical connection with the bit line BL. The second contact Q2 is similar to the first contact Q1, and thus will not be described herein again.

[0216] Exemplarily, the second external connection structure M2 can be symmetrically arranged with the first external connection structure M1 in the third direction Z.

[0217] Exemplarily, referring to FIG. 6, each second external connection structure M2 is also electrically connected with a second pad P2, so as to realize hybrid bonding of the memory array 10 and other structures. The second pad P2 is similar to the first pad P1, and thus will not be described herein again.

[0218] In some embodiments, as shown in FIG. 15, the memory array 10 can further include a plurality of fourth external connection structures M4. The plurality of fourth external connection structures M4 are arranged on two sides of the substrate 1 respectively with the plurality of third external connection structures M3, and are used for externally connecting the word lines WL to the two sides of the substrate 1 respectively with the third external connection structures M3. The fourth external connection structures M4 are similar to the second external connection structures M2, and thus will not be described herein again.

[0219] Exemplarily, the fourth external connection structure M4 is similar to the second external connection structure M2 in the setting rule and effect, and thus will not be described herein again.

[0220] Exemplarily, referring to FIG. 15, each fourth external connection structure M4 is also electrically connected with a fourth pad P4, so as to realize hybrid bonding of the memory array 10 and other structures. The fourth pad P4 is similar to the first pad P1, and thus will not be described herein again.

[0221] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory array comprising: The application relates to a memory device, comprising: a substrate; a plurality of memory matrices arranged on the substrate, the plurality of memory matrices being arranged in an array along a first direction and a second direction; each of the memory matrices comprises N sub-matrices arranged in an array along the first direction, each of the sub-matrices comprises a plurality of memory cells arranged in an array along the first direction and the second direction, the first direction and the second direction are parallel to the substrate and cross each other, N is a positive integer and N>=2; a plurality of bit lines and a plurality of word lines, the plurality of bit lines and the plurality of word lines are arranged in an array along the first direction and the second direction, the bit lines extend along the first direction and the word lines extend along the second direction, the word lines cross the bit lines and the cross positions of the word lines and the bit lines are the positions of the memory cells, each of the bit lines is electrically connected to a plurality of memory cells in N sub-matrices, and each of the word lines is electrically connected to a plurality of memory cells in one memory matrix, the distance between two word lines arranged adjacent to each other and electrically connected to two sub-matrices arranged adjacent to each other along the first direction is greater than the distance between two word lines arranged adjacent to each other and electrically connected to the same sub-matrix; a plurality of first external connection structures arranged on a side of the substrate away from the plurality of memory matrices or arranged on a side of the plurality of memory matrices away from the substrate, each of the first external connection structures is electrically connected to one of the bit lines, a first contact point of a part of the first external connection structures is located between at least one pair of sub-matrices belonging to the same memory matrix and arranged adjacent to each other, and a first contact point of another part of the first external connection structures is located between at least one pair of memory matrices arranged adjacent to each other along the first direction, the first contact point is a part of the first external connection structure for electrical connection with the bit line.

2. The storage array of claim 1, wherein, N groups of bit lines are arranged in each row of the memory matrices along the first direction, the N groups of bit lines are arranged in an array along the second direction, each of the groups of bit lines comprises a plurality of rows of bit lines arranged in an array along the second direction, and each of the rows of bit lines comprises a plurality of bit lines arranged in an array along the first direction; in the N groups of bit lines, each of the bit lines in the first group of bit lines is electrically connected to a plurality of memory cells in one memory matrix, and in the N groups of bit lines, each of the bit lines in the M+1th group of bit lines is electrically connected to a plurality of memory cells in the M+1th to Nth sub-matrices of one memory matrix and the 1st to Mth sub-matrices of the adjacent memory matrix; M is a positive integer and M+1<=N.

3. The storage array of claim 2, wherein, the rows of bit lines in the first group of bit lines to the rows of bit lines in the Nth group of bit lines are arranged in an array along the second direction.

4. The storage array of claim 2 or 3, wherein, N=2, the first group of bit line groups includes the bit lines located at odd rows among the bit lines arranged in multiple rows in the second direction, and the second group of bit line groups includes the bit lines located at even rows among the bit lines arranged in multiple rows in the second direction.

5. The storage array of claim 2, wherein, The first group of bit line groups to the Nth group of bit line groups are arranged in sequence in the second direction.

6. The storage array of claim 2 or 5, wherein, N=2, each row of the storage matrix is divided into a first part and a second part, and the first part and the second part are arranged in the second direction. The first group of bit line groups is arranged in the region where the first part is located, and the second group of bit line groups is arranged in the region where the second part is located.

7. The storage array of any of claims 1-6, wherein, Among the plurality of first external connection structures, at least one pair of first external connection structures is arranged in central symmetry, and the first contact points of the two first external connection structures arranged in central symmetry are located on the same straight line extending in the second direction. The two first external connection structures extend in the first direction and extend in opposite directions respectively with the first contact points thereof as starting points.

8. The storage array of any of claims 1-7, wherein, Among the plurality of first external connection structures, at least one pair of first external connection structures is arranged in axial symmetry, and the axis of symmetry extends in the second direction. The first contact points of the two first external connection structures arranged in axial symmetry are respectively electrically connected with the opposite two end portions of the two adjacent bit lines. The two first external connection structures extend in the first direction and extend in opposite directions respectively with the first contact points thereof as starting points.

9. The storage array of any of claims 1-8, wherein, The first contact points of two first external connection structures arranged adjacent in the second direction are spaced apart by at least one row of bit lines.

10. The storage array of any of claims 1-9, wherein, Further comprising: a plurality of second external connection structures arranged on both sides of the substrate separately from the plurality of first external connection structures, each second external connection structure being electrically connected with a bit line; Among the plurality of second external connection structures, the second contact points of a part of the second external connection structures are located between at least one pair of adjacent sub-matrices belonging to the same storage matrix, and the second contact points of another part of the second external connection structures are located between at least one pair of adjacent storage matrices in the first direction. The second contact point is a part of the second external connection structure for electrically connecting with the bit line.

11. The storage array of any of claims 1-10, wherein, Further comprising: a plurality of first transfer parts arranged between the layer where the first external connection structure is located and the layer where the plurality of bit lines are located, and the first external connection structure and the bit line are electrically connected through the first transfer part.

12. The storage array according to any one of claims 1-11, wherein, The word lines arranged adjacent in the second direction are electrically connected in pairs, and the connection positions are located between two storage matrices. Among the plurality of columns of word lines arranged in the first direction, the connection positions of each pair of word lines in the odd column of word lines are staggered with the connection positions of each pair of word lines in the even column of word lines in the first direction. The storage array further comprises: A plurality of third external connection structures are disposed on the same side of the substrate as the plurality of first external connection structures and are spaced apart from the plurality of first external connection structures; each of the third external connection structures is electrically connected to a pair of electrically connected word lines; a normal projection of a third contact point of the third external connection structure on the substrate coincides with a normal projection of a connection position of the pair of electrically connected word lines on the substrate; and the third contact point is a part of the third external connection structure for electrically connecting to the pair of electrically connected word lines.

13. The storage array of claim 12, wherein, Among the plurality of third external connection structures, at least one pair of the third external connection structures are arranged in a central symmetry, and third contact points of two third external connection structures arranged in a central symmetry are located on the same straight line extending in the first direction, the two third external connection structures extend in the second direction and extend in opposite directions respectively from the third contact points thereof.

14. The storage array of claim 13, wherein, A plurality of pairs of third external connection structures arranged in a central symmetry are arranged in an array along the first direction and the second direction; at least part of the first external connection structure is arranged between two third external connection structures arranged adjacent to each other in the first direction.

15. The storage array of claim 13, wherein, Among the plurality of pairs of third external connection structures arranged in a central symmetry, two pairs of third external connection structures arranged adjacent to each other in the first direction are arranged in an axial symmetry, and an axis of symmetry extends in the second direction; at least part of the first external connection structure is arranged between two third external connection structures having a larger spacing in the first direction among the two pairs of third external connection structures arranged in an axial symmetry.

16. A memory, comprising: Comprising: The memory array according to any one of claims 1-15; A peripheral circuit is stacked on one side of the memory array and is electrically connected to the memory array.

17. The memory of claim 16, wherein, The peripheral circuit includes a plurality of sense amplifiers and a plurality of sub-word line driving circuits, the memory array includes a plurality of first external connection structures and a plurality of third external connection structures; At least one pair of first external connection structures arranged adjacent to each other in the first direction are electrically connected to the same sense amplifier, and the sub-word line driving circuit is electrically connected to the third external connection structure.

18. An electronic device, comprising: Comprising: The memory according to claim 16 or 17; A bus is electrically connected to the memory.

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