Semiconductor device and operating method therefor, system, and computer-readable storage medium

Abstract

The present disclosure provides a semiconductor device and an operating method therefor, a system, and a computer-readable storage medium. The semiconductor device comprises a storage array and a peripheral circuit coupled to the storage array, wherein the storage array comprises a plurality of storage blocks; and in an operation stage using the semiconductor device, the peripheral circuit is configured to: apply a first read voltage to a target word line coupled to a target storage block; apply respective input voltages to a plurality of first select lines coupled to the target memory block; apply a first turn-on voltage to a non-target word line coupled to the target memory block; and sense a current on a bit line coupled to the target memory block.

Description

Semiconductor device and operating method, system, computer-readable storage medium thereof

[0001] Cross-reference to Related Applications

[0002] The present disclosure is based on and claims priority to Chinese Patent Publication No. 202411061486.X, filed on August 2, 2024, the entire contents of which are hereby incorporated by reference into the present disclosure. TECHNICAL FIELD

[0003] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and operating method, system, computer-readable storage medium thereof. BACKGROUND

[0004] In the classical von Neumann computing architecture, the memory and the processor are separated, and data transmission is performed between the two through a data bus. When executing a command, the processor first reads data from the memory, and after processing, the updated data is written back to the memory. Frequent data movement brings huge power consumption and time overhead. In addition, due to the limited bandwidth of the memory, the processing speed of the processor is limited by the access speed of the memory, which greatly affects the computing performance. With the rise of big data and artificial intelligence applications, the processing of massive data makes the von Neumann computing architecture bottleneck more and more prominent. SUMMARY

[0005] Therefore, the present disclosure provides a semiconductor device and operating method, system, computer-readable storage medium thereof.

[0006] In a first aspect, the present disclosure provides a semiconductor device, comprising a memory array and a peripheral circuit coupled to the memory array, the memory array comprising a plurality of memory blocks, during an operation phase using the semiconductor device, the peripheral circuit is configured to: apply a first read voltage to a target word line coupled to a target memory block; apply a respective input voltage to a plurality of first select lines coupled to the target memory block; apply a first turn-on voltage to a non-target word line coupled to the target memory block; and sense a current on a bit line coupled to the target memory block.

[0007] In an optional implementation, during the operation phase using the semiconductor device, the peripheral circuit is configured to: pre-charge a sensing node coupled to a bit line coupled to the target memory block to a target voltage.

[0008] In an alternative embodiment, the memory cells in the target memory block are configured to store one bit of data, the plurality of memory cells in the target memory block have a first memory state and a second memory state, the threshold voltage of a memory cell having the first memory state is less than the threshold voltage of a memory cell having the second memory state; the first read voltage is greater than the threshold voltage of a memory cell having the first memory state and less than the threshold voltage of a memory cell having the second memory state.

[0009] In an alternative embodiment, the current on the bit line coupled to the target memory block is a sum of output currents of a plurality of memory cell strings in the target memory block coupled to the bit line; the output current of a memory cell string is greater than or equal to a preset current in a case that the input voltage applied to a first select line coupled to the memory cell string causes a select transistor coupled to the first select line to be in an on state, and a memory cell in the memory cell string coupled to the target word line has the first memory state.

[0010] In an alternative embodiment, the memory cells in the target memory block are configured to store m bits of data, the plurality of memory cells in the target memory block are configured to have 2 m memory states, the first read voltage is between threshold voltage distributions corresponding to two adjacent memory states; the m is an integer greater than 1.

[0011] In an alternative embodiment, during the operation phase using the semiconductor device, the peripheral circuit is configured to apply a second read voltage to the target word line coupled to the target memory block, the second read voltage is between threshold voltage distributions corresponding to two adjacent memory states, the first read voltage is different from the second read voltage.

[0012] In an alternative embodiment, during the operation phase using the semiconductor device, the peripheral circuit is configured to apply a second on voltage to a plurality of second select lines coupled to the target memory block respectively.

[0013] In an alternative embodiment, the first select line is one of a top select line and a bottom select line, the second select line is the other of the top select line and the bottom select line.

[0014] In an alternative embodiment, the peripheral circuit is configured to apply a corresponding program voltage to the target word line coupled to the target memory block to program a memory cell coupled to the target word line before the operation phase using the semiconductor device.

[0015] In an alternative embodiment, at least two of the plurality of memory blocks are target memory blocks, and the peripheral circuit is configured to:

[0016] applying a respective first read voltage to a target word line coupled to each of the at least two target memory blocks;

[0017] applying a respective input voltage to a first select line coupled to each of the at least two target memory blocks;

[0018] applying a first pass voltage to a non-target word line coupled to each of the at least two target memory blocks;

[0019] sensing a current on a bit line coupled to the at least two target memory blocks.

[0020] In an alternative embodiment, the memory array includes a plurality of memory planes, each of the memory planes including a plurality of memory blocks; and the peripheral circuit is configured to: obtain a result corresponding to each of the memory planes based on a current on a bit line coupled to the target memory blocks in the memory plane; and perform a logical operation based on the results corresponding to the plurality of memory planes.

[0021] In an alternative embodiment, the memory plane includes a plurality of memory banks, each of the memory banks including a plurality of memory blocks; and the peripheral circuit is configured to: apply a first pass voltage to a non-target word line coupled to each of the plurality of memory banks.

[0022] In an alternative embodiment, the peripheral circuit is configured to: sequentially apply a first read voltage to a target word line coupled to each of a plurality of memory banks in a predetermined order, and sequentially apply a respective input voltage to a first select line coupled to each of the plurality of memory banks in the predetermined order; and sequentially sense a current on a bit line coupled to the memory banks in the predetermined order.

[0023] In an alternative embodiment, the peripheral circuit is configured to: apply a respective first read voltage to a target word line coupled to each of a plurality of memory blocks of a memory bank; apply a respective input voltage to a first select line coupled to each of the plurality of memory blocks of the memory bank; and sense a current on a bit line coupled to the plurality of memory blocks of the memory bank.

[0024] In an alternative embodiment, the peripheral circuit includes: an analog-to-digital conversion circuit, a digital-to-analog conversion circuit, a voltage generator, a column decoder, and a control logic; the analog-to-digital conversion circuit is coupled to the column decoder and the control logic; and the digital-to-analog conversion circuit is coupled to the voltage generator and the control logic.

[0025] In an alternative embodiment, the semiconductor device includes a three-dimensional NAND memory.

[0026] In an optional implementation, the semiconductor device includes a first semiconductor structure and a second semiconductor structure; the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are stacked along a thickness direction of the semiconductor device.

[0027] In a second aspect, the embodiments of the present disclosure provide a system, including: at least one semiconductor device as described in any of the above embodiments; and a controller coupled to the at least one semiconductor device and configured to send input data to the semiconductor device and receive an operation result of the semiconductor device.

[0028] In a third aspect, the embodiments of the present disclosure provide an operation method of a semiconductor device. In an operation phase of the semiconductor device, the operation method includes: applying a first read voltage to a target word line coupled to a target memory block; applying a corresponding input voltage to each of a plurality of first selection lines coupled to the target memory block; applying a first conduction voltage to a non-target word line coupled to the target memory block; and sensing a current on a bit line coupled to the target memory block.

[0029] In an optional implementation, in the operation phase of the semiconductor device, the operation method further includes: pre-charging a sensing node coupled to the bit line to a target voltage.

[0030] In an optional implementation, a storage unit in the target memory block is configured to store one bit of data, a plurality of storage units in the target memory block have a first memory state and a second memory state, a threshold voltage of a storage unit having the first memory state is less than a threshold voltage of a storage unit having the second memory state; the first read voltage is greater than the threshold voltage of the storage unit having the first memory state and less than the threshold voltage of the storage unit having the second memory state.

[0031] In an optional implementation, the current on the bit line coupled to the target memory block is a sum of output currents of a plurality of storage unit strings in the target memory block coupled to the bit line; in a case where the input voltage applied to the first selection line coupled to the storage unit string causes a selection transistor coupled to the first selection line to be in a conduction state, and a storage unit in the storage unit string coupled to the target word line has the first memory state, the output current of the storage unit string is greater than or equal to a preset current.

[0032] In an alternative embodiment, the memory cells in the target memory block are configured to store m-bit data, the plurality of memory cells in the target memory block are configured to have 2 m memory states, the first read voltage is located between threshold voltage distributions corresponding to two adjacent memory states, and the m is an integer greater than 1.

[0033] In an alternative embodiment, during the operation phase using the semiconductor device, the operation method further comprises: applying a second read voltage to the target word line coupled with the target memory block, the second read voltage is located between threshold voltage distributions corresponding to two adjacent memory states, and the first read voltage is different from the second read voltage.

[0034] In an alternative embodiment, during the operation phase using the semiconductor device, the operation method further comprises: applying a second read voltage to the target word line coupled with the target memory block, the second read voltage is located between threshold voltage distributions corresponding to two adjacent memory states, and the first read voltage is different from the second read voltage.

[0035] In an alternative embodiment, the first selection line is one of a top selection line and a bottom selection line, and the second selection line is the other of the top selection line and the bottom selection line.

[0036] In an alternative embodiment, the operation method further comprises: before the operation phase using the semiconductor device, applying a corresponding programming voltage to the target word line coupled with the target memory block to program the memory cells coupled with the target word line.

[0037] In an alternative embodiment, the memory array comprises a plurality of memory planes, and each of the memory planes comprises a plurality of memory blocks; the operation method further comprises: obtaining an operation result corresponding to the memory plane based on a current on a bit line coupled with the target memory block in the memory plane; and performing a logical operation based on the operation results corresponding to the plurality of memory planes.

[0038] In an alternative embodiment, the memory plane comprises a plurality of memory banks, and each of the memory banks comprises a plurality of memory blocks; the applying the first conductive voltage to the non-target word line coupled with the target memory block comprises: applying a first conductive voltage to the non-target word line coupled with each of the plurality of memory banks, respectively.

[0039] In an alternative implementation, the applying the first read voltage to the target word line coupled to the target memory block and the applying the respective input voltage to the first select line coupled to the target memory block include: sequentially applying the first read voltage to the target word line coupled to each of the plurality of memory banks in a preset order and sequentially applying the respective input voltage to the first select line coupled to each of the plurality of memory banks in the preset order; and the sensing the current on the bit line coupled to the target memory block includes sequentially sensing the current on the bit line coupled to each of the plurality of memory banks in the preset order.

[0040] In an alternative implementation, the applying the first read voltage to the target word line coupled to the target memory block includes applying the first read voltage to the target word line coupled to each of the plurality of memory blocks of the memory bank; the applying the respective input voltage to the first select line coupled to the target memory block includes applying the respective input voltage to the first select line coupled to each of the plurality of memory blocks of the memory bank; and the sensing the current on the bit line coupled to the target memory block includes sensing the current on the bit line coupled to each of the plurality of memory blocks of the memory bank.

[0041] In a fourth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. When the computer program is executed by a processor, the computer program performs the operation method of any of the above embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0042] FIG. 1 is a schematic diagram of a three-dimensional NAND memory according to an embodiment of the present disclosure.

[0043] FIG. 2 is a schematic diagram of a distribution of memory cells of a three-dimensional NAND memory according to an embodiment of the present disclosure.

[0044] FIG. 3 is a schematic diagram of an exemplary semiconductor device including a peripheral circuit according to an embodiment of the present disclosure.

[0045] FIG. 4 is a schematic diagram of a cross-section of a memory array including strings of memory cells according to an embodiment of the present disclosure.

[0046] FIG. 5 is a schematic diagram of a semiconductor device including a peripheral circuit and a memory array according to an embodiment of the present disclosure.

[0047] FIG. 6 is a schematic diagram of a semiconductor device including a peripheral circuit and a memory array according to an embodiment of the present disclosure.

[0048] FIG. 7 is a schematic diagram of inputting an input voltage to a memory block from a word line according to an embodiment of the present disclosure.

[0049] FIG. 8a is a schematic diagram of inputting a voltage into a memory block from a top select line, according to one embodiment of the present disclosure.

[0050] FIG. 8b is a schematic diagram of inputting a voltage into a memory block from a bottom select line, according to one embodiment of the present disclosure.

[0051] FIG. 9 is a schematic diagram of threshold voltage distribution of memory cells coupled to a target word line, according to one embodiment of the present disclosure.

[0052] FIG. 10a is a schematic diagram of a plurality of memory cell strings coupled to one bit line, according to one embodiment of the present disclosure.

[0053] FIG. 10b is a voltage curve for performing an operation using a semiconductor device, according to one embodiment of the present disclosure.

[0054] FIG. 11a is a schematic diagram of a memory bank, according to one embodiment of the present disclosure.

[0055] FIG. 11b is a voltage curve for performing an operation using a semiconductor device, according to one embodiment of the present disclosure.

[0056] FIG. 12 is a schematic diagram of threshold voltage distribution of memory cells coupled to a target word line, according to another embodiment of the present disclosure.

[0057] FIG. 13 is a flow diagram of a method of operating a semiconductor device, according to one embodiment of the present disclosure.

[0058] FIG. 14a is a schematic diagram of a system, according to one embodiment of the present disclosure.

[0059] FIG. 14b is a schematic diagram of a system, according to one embodiment of the present disclosure.

[0060] FIG. 15 is a schematic diagram of an exemplary memory card having a memory system, according to one embodiment of the present disclosure.

[0061] FIG. 16 is a schematic diagram of an exemplary solid state drive having a memory system, according to one embodiment of the present disclosure.

[0062] FIG. 17 is a schematic diagram of a computer readable storage medium, according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0063] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be embodied in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0064] In the following description, numerous specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the disclosure can be practiced without one or more of the specific details. In other instances, well-known features are not described in order to avoid obscuring the disclosure.

[0065] In the drawings, like reference numerals refer to same parts throughout the various views.

[0066] It should be understood that spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0067] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0068] In the classical von Neumann computing architecture, the memory and the processor are separated, and data transmission is performed between the two through a data bus. When executing a command, the processor first reads data from the memory, and after processing, the updated data is written back to the memory. Frequent data movement results in huge power consumption and time overhead. In addition, due to the limited memory bandwidth, the processing speed of the processor is limited by the access speed of the memory, which greatly affects the computing performance. With the rise of big data and artificial intelligence applications, the processing of massive data makes the von Neumann computing architecture bottleneck more and more prominent. In order to solve the bottleneck of the classical von Neumann computing architecture, the memory-compute integrated chip architecture emerges as the times require. The basic idea is to embed computing functions in the memory and directly use the memory for logical calculation, thereby reducing the data transmission amount and transmission distance between the memory and the processor, reducing power consumption and improving computing performance, so as to build a high-computing, high-bandwidth, and high-energy-efficiency computing system.

[0069] The memory-compute integrated chip has both storage and computing capabilities due to its physical characteristics. The storage capability refers to the ability of different memories to store numerical values by changing their conductance values according to their physical characteristics. The computing capability refers to the ability to perform vector matrix multiplication calculations within a certain time by constructing an array of memory devices based on Ohm's law and Kirchhoff's law. The memory-compute integrated chip includes but is not limited to static random access memory (SRAM), NAND flash memory, and dynamic random access memory (DRAM). Among them, NAND flash memory is a type of non-volatile memory with large capacity, and therefore has become a widely focused object in memory-compute integrated chips. In the following, the relevant content of NAND flash memory will be introduced accordingly.

[0070] FIG. 1 schematically shows a structure of a three-dimensional NAND memory, and FIG. 2 schematically shows a distribution of memory cells of the three-dimensional NAND memory. The three-dimensional NAND memory includes a memory array and a peripheral circuit coupled to the memory array. As shown in FIG. 1, the memory array can include a plurality of memory planes, for example, four memory planes, Plane 0, Plane 1, Plane 2, and Plane 3, each of which includes a plurality of memory blocks. As shown in FIG. 2, the memory array of the three-dimensional NAND memory is composed of a plurality of rows of memory cell strings arranged in parallel and offset in parallel with gate isolation structures, and every four rows of memory cell strings are separated by gate isolation structures and selection gate isolation structures, each row of memory cell strings includes a plurality of memory cell strings arranged in an X direction, and one memory cell in each memory cell string is shown in the figure, and the remaining memory cells are arranged in a Z direction in a stacked manner. The selection gate isolation structure herein can be a top selection gate isolation structure, which divides a top selection gate into a plurality of top selection lines. The selection gate isolation structure can also be a bottom selection gate isolation structure, which divides a bottom selection gate into a plurality of bottom selection lines. The gate isolation structure can include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory array into a plurality of memory blocks, and a plurality of second gate isolation structures can divide the memory blocks into a plurality of finger storage areas, and the selection gate isolation structure arranged in the middle of each finger storage area can divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. The one memory block shown in FIG. 2 contains six memory slices, and in actual applications, the number of memory slices in a memory block is not limited thereto. FIG. 2 only schematically shows one memory block of the memory, but the memory includes a plurality of memory blocks as shown in FIG. 2, and adjacent memory blocks are separated by the first gate isolation structure, and a plurality of memory blocks can be arranged in a Y direction.

[0071] It should be noted that the number of rows of memory cell strings between the gate isolation structures and the selection gate isolation structures shown in FIG. 2 is only an example and is not used to limit the number of rows of memory cell strings included in one finger storage area of the three-dimensional NAND memory in the present disclosure. In actual applications, the number of rows of memory cell strings included in one finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0072] Figure 3 is a schematic diagram of an exemplary semiconductor device including a peripheral circuit, according to embodiments of the disclosure. The semiconductor device 300 can include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. By way of example, the memory array 301 is a three-dimensional NAND-type memory array, in which the memory cells 306 are NAND memory cells provided in an array of memory cell strings 308, each of which extends vertically. In some embodiments, each memory cell string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, e.g., a voltage or a charge, that depends on the number of electrons captured within a region of the memory cell 306. Each memory cell 306 can be a floating gate type of memory cell that includes a floating gate transistor, or a charge trap type of memory cell that includes a charge-trapping transistor.

[0073] In some embodiments, each memory cell 306 is a single level cell (SLC) that has two possible memory states and thus can store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell that can store more than a single bit of data in four or more memory states, e.g., a multi-level cell (MLC) that stores two bits per cell, a triple level cell (TLC) that stores three bits per cell, or a quad-level cell (QLC) that stores four bits per cell.

[0074] As shown in FIG. 3, each memory cell string 308 can include a bottom select gate (BSG) 310 at its source end and a top select gate (TSG) 312 at its drain end. The bottom select gate 310 and the top select gate 312 can be configured to activate a selected memory cell string 308 during read and program operations. In some embodiments, the sources of the memory cell strings 308 in the same memory block 304 can be coupled by a common source line (CSL) 314. In other words, all memory cell strings 308 in the same memory block 304 have a common source (ACS). According to some embodiments, the top select gate 312 of each memory cell string 308 is coupled to a respective bit line 316 from which data can be read or written via an output bus (not shown). In some embodiments, each memory cell string 308 is configured to be selected or deselected by applying a select voltage (e.g., a voltage higher than a threshold voltage of the top select gate 312) or a deselect voltage (e.g., 0 V) to the respective top select gate 312 through one or more top select lines (TSL) 313 and / or by applying a select voltage (e.g., a voltage higher than a threshold voltage of the bottom select gate 310) or a deselect voltage (e.g., 0 V) to the respective bottom select gate 310 through one or more bottom select lines (BSL) 315.

[0075] As shown in FIG. 3, the memory cell strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314. In some embodiments, each memory block 304 is a basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase the memory cells 306 in a selected memory block, the common source line 314 coupled to the selected memory block and to unselected memory blocks in the same face as the selected memory block can be biased with an erase voltage. It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory cell strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0076] FIG. 4 illustrates a cross-sectional schematic view of an exemplary memory array including a string of memory cells 308, according to some aspects of the present disclosure. As shown in FIG. 4, a stack structure 410 includes a plurality of gate layers 411 and a plurality of insulating layers 412 alternately and sequentially stacked, and a string of memory cells 308 vertically penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 can be alternately stacked, and two adjacent gate layers 411 are separated by one insulating layer 412. The number of memory cells included in the memory array is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stack structure 410.

[0077] The constituent material of the gate layers 411 can include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 can include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack structure 410 can extend laterally as a top select line, the gate layer 411 at the bottom of the stack structure 410 can extend laterally as a bottom select line, and the gate layers 411 extending laterally between the top select line and the bottom select line can serve as word line layers.

[0078] In some embodiments, the stack structure 410 can be disposed on a semiconductor layer 401. The semiconductor layer 401 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. In other embodiments, the semiconductor device can also not include such a semiconductor layer.

[0079] In some embodiments, the storage cell string 308 includes a channel structure extending vertically through the stack structure 410. In some implementations, the channel structure includes a channel hole filled with a semiconductor material(s) (e.g., as a semiconductor channel) and a dielectric material(s) (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a “charge trapping / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a column shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0080] Referring back to FIG. 3, the peripheral circuit 302 can be coupled to the storage array 301 through the bit lines 316, the word lines 318, the source lines 314, the BSLs 315, and the TSLs 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the storage array 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target storage cell 306 via the bit lines 316, the word lines 318, the source lines 314, the BSLs 315, and the TSLs 313. The peripheral circuit 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor technology.

[0081] FIG. 5 is a schematic diagram of a semiconductor device including a peripheral circuit and a storage array according to an embodiment of the present disclosure. In conjunction with FIGS. 3 and 5, the peripheral circuit 302 can include a control logic 512, a digital-to-analog conversion circuit 501 coupled to the control logic 512 and the storage array 301, and an analog-to-digital conversion circuit 502 coupled to the storage array 301 and the control logic 512. During a computation phase using the semiconductor device, the digital-to-analog conversion circuit 501 can convert digital signals to voltage signals required by the storage array 301 in the memory-compute-in-one chip. The analog-to-digital conversion circuit 502 can convert current signals output by the storage array 301 to digital signals. The control logic 512 can be coupled to the peripheral circuit and configured to control the operation of the peripheral circuit. The control logic 512 can also be used to receive input data sent by a controller and send computation results to the controller.

[0082] FIG. 6 is a schematic diagram of a second example of a semiconductor device, according to embodiments of the disclosure. In addition to the circuitry shown in FIG. 5, the peripheral circuitry 302 can also include a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a register 514, an interface 516, and a data bus 518. It should be appreciated that in some examples, additional peripheral circuitry not shown in FIG. 5 and FIG. 6 can also be included.

[0083] The page buffer / sense amplifier 504 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page of the memory array 301. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 306 coupled to a selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to an identifiable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more strings of memory cells 308 by applying a bit line voltage generated from the voltage generator 510.

[0084] The row decoder / word line driver 508 can be configured to be controlled by the control logic 512 and select / deselect a memory block 304 of the memory array 301 and select / deselect a word line 318 of the memory block 304. The row decoder / word line driver 508 can also be configured to drive the word line 318 using a word line voltage generated from the voltage generator 510. In some implementations, the row decoder / word line driver 508 can also select / deselect and drive the BSL 315 and the TSL 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a program operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic 512 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc., input voltages), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0085] The registers 514 can be coupled to the control logic 512 and include state registers, command registers, and address registers for storing state information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from the host-side device and relay them to the control logic 512, as well as buffer state information received from the control logic 512 and relay them to the host-side device. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay them to or from the memory array 301.

[0086] In some embodiments, as shown in FIG. 6, the digital-to-analog conversion circuit 501 can be connected with the control logic 512 and the voltage generator 510 in particular, and the analog-to-digital conversion circuit 502 can be connected with the control logic 512 and the column decoder / BL driver 506 in particular. In the operation phase using the three-dimensional NAND type memory, the control logic can receive the input data sent by the controller, the digital-to-analog conversion circuit converts the input data into a voltage signal required to be applied to the word line or the bit line, the voltage generator generates the corresponding voltage required to be applied to the word line or the bit line, and the row decoder / word line driver is configured to drive the selected word line using the word line voltage generated from the voltage generator, or the column decoder / bit line driver is configured to drive the selected bit line using the bit line voltage generated from the voltage generator. The analog operation result obtained after the operation is transmitted to the analog-to-digital conversion circuit through the page buffer and the column decoder, the analog operation result is converted into a digital operation result through the analog-to-digital conversion circuit, and the final digital operation result is transmitted to the control logic.

[0087] In some embodiments, for the in-memory computing chip, it is necessary to implement the product operation or the product accumulation operation of the input data and the weight matrix, the input data can be an input vector or an input matrix composed of multiple elements, the weight matrix is composed of multiple weights, and each element in the input data needs to be multiplied and accumulated with multiple weights in the weight matrix to obtain the corresponding element in the output data.

[0088] To realize the above operation function, the storage array 301 in the semiconductor device 300 can be configured to store the weight matrix, specifically, the weights in the weight matrix can be written into the storage array 301 according to a certain mapping rule, and each storage unit 306 in the storage array 301 can be configured to store a weight. In the inference operation phase, the semiconductor device 300 can receive input data from the controller, and the input data can be an input vector or an input matrix composed of multiple elements, and each element in the input data can be converted into an input voltage by the digital-to-analog conversion circuit 501 and input into the storage array 301 by the bit line 316 or the word line 318.

[0089] In some specific examples, FIG. 7 is a schematic diagram of inputting an input voltage into a storage block by a word line. As shown in FIG. 7, the storage units coupled with the target word line WLn can be configured to store the weight matrix, specifically, the threshold voltage corresponding to the memory state of the storage unit can correspond to a weight. The input voltage V in may be applied to the target word line WLn, and the on voltage V pass may be applied to the non-target word lines coupled with the same storage block, so that the storage units coupled with the non-target word lines are all in the on state, in which case whether each storage unit string produces a significant current only depends on whether the threshold voltage of the storage unit coupled with the target word line WLn is greater than the input voltage V in . When the input voltage V in is greater than the threshold voltage of the storage unit, the storage unit string to which the storage unit belongs is on and produces a significant current, and when the input voltage V in is less than the threshold voltage of the storage unit, the storage unit string to which the storage unit belongs is off and does not produce a significant current, in which case the current on each bit line can be detected at the end of the bit line coupled with the sensing circuit, for example, the current I0 on the bit line BL0 corresponds to the multiplication of the input data corresponding to the input voltage V in and the weights w 00 , w 10 , w 20 and the accumulation result of the product, the current I1 on the bit line BL1 corresponds to the multiplication of the input data corresponding to the input voltage V in and the weights w 01 , w 11 , w 21 and the accumulation result of the product, and the current I2 on the bit line BL2 corresponds to the multiplication of the input data corresponding to the input voltage V in and the weights w 02 , w 12 , w 22 and the accumulation result of the product.

[0090] In the above example, only one element in the input data and the weight matrix can be operated at a time, and the flexibility of the operation is low. When the input data is an input vector or an input matrix including multiple elements, the input voltage corresponding to the multiple elements needs to be input from the target word line WLn in sequence, resulting in a long operation period and low operation efficiency. Therefore, it is necessary to further optimize the operation scheme of the semiconductor device including the three-dimensional NAND type memory.

[0091] To this end, the present disclosure proposes the following embodiments.

[0092] The present disclosure provides a semiconductor device, referring back to FIG. 1, FIG. 3 and FIG. 6, the semiconductor device includes a storage array 301 and a peripheral circuit 302 coupled to the storage array 301, the storage array 301 includes a plurality of storage blocks, during an operation phase using the semiconductor device, the peripheral circuit is configured to: apply a first read voltage to a target word line coupled to a target storage block; apply a corresponding input voltage to each of a plurality of first selection lines coupled to the target storage block; apply a first conduction voltage to a non-target word line coupled to the target storage block; and sense a current on a bit line coupled to the target storage block.

[0093] In an embodiment of the present disclosure, the input voltage corresponding to an element in the input data can be input by a first selection line, the first selection line can be one of a top selection line and a bottom selection line, FIG. 8a is a schematic diagram of inputting an input voltage into a storage block by a top selection line provided by an embodiment of the present disclosure, FIG. 8b is a schematic diagram of inputting an input voltage into a storage block by a bottom selection line provided by an embodiment of the present disclosure, FIG. 9 is a schematic diagram of threshold voltage distribution of a storage unit coupled to a target word line provided by an embodiment of the present disclosure, FIG. 10a is a schematic diagram of a plurality of storage unit strings coupled to one bit line provided by an embodiment of the present disclosure, and FIG. 10b is a voltage curve for an operation using a semiconductor device provided by an embodiment of the present disclosure.

[0094] It should be noted that the number of bit lines, the number of storage unit strings coupled to each bit line, and the number of storage units in each storage unit string shown in FIG. 8a, FIG. 8b and FIG. 10a are only examples, and the present disclosure does not limit the specific number of each structure.

[0095] In some embodiments, during the operation phase using the semiconductor device, the peripheral circuit is configured to: apply a second conduction voltage to each of a plurality of second selection lines coupled to the target storage block.

[0096] In an embodiment of the present disclosure, the first selection line is one of the top selection line and the bottom selection line, and the second selection line is the other of the top selection line and the bottom selection line.

[0097] In some specific examples, as shown in FIG. 8a, the first selection line is a top selection line, and the second selection line is a bottom selection line. The input voltage corresponding to an element in the input data can be input by multiple top selection lines. In the operation phase using the semiconductor device, the peripheral circuit is configured to: apply a first read voltage V rd , to a target word line WLn coupled to the target storage block, apply a respective input voltage to each of the multiple top selection lines coupled to the target storage block, for example, input voltages V in0 , V in1 , V in2 , to a non-target word line coupled to the target storage block, for example, a first conduction voltage V pass1 , to a bottom selection line coupled to the target storage block, for example, a second conduction voltage V pass2 . The operation result can be obtained by sensing the current on the bit line coupled to the target storage block and converting the current on the bit line, for example, by sensing the current I0 on the bit line BL0 and converting the current I0, the sum of the product of the corresponding element and the weight w in0 , the product of the corresponding element and the weight w 00 , and the product of the corresponding element and the weight w in1 , the product of the corresponding element and the weight w 10 , and the product of the corresponding element and the weight w in2 , the product of the corresponding element and the weight w 20 .

[0098] In some specific examples, as shown in FIG. 8b, the first selection line is a bottom selection line, and the second selection line is a top selection line. The input voltage corresponding to an element in the input data can be input by multiple bottom selection lines. In the operation phase using the semiconductor device, the peripheral circuit is configured to: apply a first read voltage V rd , to a target word line WLn coupled to the target storage block, apply a respective input voltage to each of the multiple bottom selection lines coupled to the target storage block, for example, input voltages V in0 ', V in1 ', V in2 ', to a non-target word line coupled to the target storage block, for example, a first conduction voltage V pass1 ', to a top selection line coupled to the target storage block, for example, a second conduction voltage V pass2The computation result can be obtained by sensing the current on the bit line coupled to the target memory block and converting the current on the bit line. For example, by sensing the current I0 on the bit line BL0 and converting the current I0, the result can be obtained by converting the current I0 relative to the input voltage V. in0 'Corresponding element and weight w 00 The product of the input voltage V in1 'Corresponding element and weight w 10 The product of the input voltage V in2 'Corresponding element and weight w 20 The sum of the product of these three.

[0099] The following will describe the implementation of the calculation scheme provided in this embodiment, taking the first selection line as the top selection line, the second selection line as the bottom selection line, and the input voltage corresponding to the element in the input data as input by multiple top selection lines.

[0100] In some embodiments, the peripheral circuitry is configured to apply a corresponding programming voltage to a target word line coupled to the target memory block to program the memory cell coupled to the target word line before performing operations using the semiconductor device.

[0101] In some specific examples, as shown in Figure 9, the memory cells in the target memory block are configured to store one bit of data. Multiple memory cells in the target memory block have a first memory state and a second memory state. The threshold voltage of a memory cell with the first memory state is less than the threshold voltage of a memory cell with the second memory state. The first read voltage V... rd The threshold voltage is greater than that of the memory cell with the first memory state and less than that of the memory cell with the second memory state. Here, the memory cell in the target memory block can be a single-level cell (SLC) storing one bit of data, the first memory state can be an erase state (E), and the second memory state can be a programmable state (P). The peripheral circuit can be configured to perform a programming operation on the memory cell coupled to the target word line before performing the operation, writing weights to the memory cell according to a certain mapping rule. For a single-level cell, the weight writing process includes applying a corresponding programming voltage to adjust the threshold voltage of a portion of the memory cells coupled to the target word line to the range of the threshold voltage distribution corresponding to the second memory state.

[0102] In some embodiments, during the computation phase using semiconductor devices, the peripheral circuitry is configured to precharge the sensing node coupled to the bit line coupled to the target memory block to the target voltage. Referring back to FIG6, the sensing node coupled to the bit line is located in the page buffer / sensor amplifier 504.

[0103] In some specific examples, after the transistor between the sensing node and the bit line is turned on, if the storage unit string coupled with the bit line is turned on and generates current, the voltage of the sensing node will start to drop from the target voltage, and the current on the bit line can be obtained based on the voltage change of the sensing node within a fixed time period and the length of the fixed time period.

[0104] In some embodiments, with reference to FIGS. 10a and 10b, taking an example that the target memory block includes eight storage unit strings coupled with the bit line BL0, four of the storage units coupled with the target word line WLn are in the first memory state (erased state E), and the other four storage units are in the second memory state (programmed state P), the input data can be input from eight top selection lines TSL0 to TSL7, specifically, the input data can be an input vector including eight elements, the eight elements can include five “1” and three “0”, the digital-to-analog conversion circuit can convert each element of the input vector into a corresponding voltage signal, and the voltage signal is converted into an input voltage required to be applied to the top selection line by the voltage generator, and the input voltage is transmitted to the top selection line by the driver coupled with the top selection line. Specifically, the eight input voltages can be applied to the eight top selection lines at the same time. The input voltage corresponding to “1” includes V in0 , V in1 , V in4 , V in5 , and V in6 , which can make the top selection transistors TSG0, TSG1, TSG4, TSG5, and TSG6 coupled with the top selection lines TSL0, TSL1, TSL4, TSL5, and TSL6, respectively, turn on. The input voltage corresponding to “0” includes V in2 , V in3 , V in7 , which can make the top selection transistors TSG2, TSG3, and TSG7 coupled with the top selection lines TSL2, TSL3, and TSL7, respectively, turn off.

[0105] In some embodiments, with reference to FIGS. 10a and 10b, during the operation stage using the semiconductor device, the peripheral circuit is configured to: apply a first turn-on voltage V pass1 to all the storage units coupled with the non-target word lines, so as to turn on all the storage units coupled with the non-target word lines; and apply a second turn-on voltage V pass2 to all the bottom selection transistors coupled with the bottom selection line BSL, so as to turn on all the bottom selection transistors coupled with the bottom selection line BSL. Here, the non-target word lines can include WL0-WLn-1 and WLn+1-WL_end, WL0 represents the first word line coupled with the memory block, and WL_end represents the last word line coupled with the memory block.

[0106] It should be noted that in the embodiments of the present disclosure, the target word line WLn is taken as an example which includes non-target word lines on both sides, but the present disclosure is not limited thereto, and the target word line WLn can be any word line in the target storage block which is coupled to the storage unit storing the weight.

[0107] In some embodiments, the first conductive voltage applied on different non-target word lines can be different in size, and the second conductive voltage applied on different bottom selection lines BSL can also be different in size. Here, only one bottom selection line BSL is taken as an example which is coupled to the storage unit string, but the present disclosure is not limited thereto, and each storage unit string can also include multiple bottom selection transistors, and the second conductive voltage applied on different bottom selection lines coupled to the same storage unit string can also be different in size.

[0108] In some specific examples, during the operation stage using the semiconductor device, the peripheral circuit can also be configured to apply a voltage lower than the target voltage on the sensing node to the common source ACS, so that when the transistor between the sensing node and the bit line is turned on, and the storage unit string coupled to the bit line is turned on, the storage unit string can generate a current flowing towards the common source ACS.

[0109] In the embodiments of the present disclosure, during the operation stage using the semiconductor device, the peripheral circuit is configured to sense the current on the bit line coupled to the target storage block, and obtain the operation result according to the current. Specifically, the current on the bit line coupled to the target storage block is the sum of the output currents of the multiple storage unit strings coupled to the bit line in the target storage block; in the case that the input voltage applied to the first selection line coupled to the storage unit string makes the selection transistor coupled to the first selection line in the conductive state, and the storage unit coupled to the target word line in the storage unit string has the first memory state, the output current of the storage unit string is greater than or equal to the preset current.

[0110] Here, the size of the preset current can be based on the read voltage V rdThe size of the current on the bit line, the size of the target voltage on the sensing node coupled with the bit line, and the threshold voltage of the storage unit in the first memory state are set, and in addition, in the case that the input voltage applied to the first selection line coupled with the storage unit string causes the selection transistor coupled with the first selection line to be in the on state, and the storage unit in the storage unit string coupled with the target word line has the first memory state, the output current of the storage unit string is greater than or equal to the preset current, and the output current greater than or equal to the preset current generated by the storage unit string coupled with the same bit line is substantially equal; and in the case that the input voltage causes the selection transistor coupled with the first selection line to be in the off state and / or the storage unit in the storage unit string coupled with the target word line has the second memory state, the storage unit string can also generate a current, but the current generated by the storage unit string should be much smaller than the preset current. Thus, the operation result can be obtained according to the multiple relationship between the current on the bit line and the output current greater than or equal to the preset current.

[0111] In a specific example, referring to FIG. 10a, the current I0 on the bit line BL0 is the sum of the output currents of the eight storage unit strings coupled with the bit line BL0, wherein the input voltage on the top selection line coupled with the storage unit strings Str0, Str4 and Str5 causes the top selection transistors TSG0, TSG4 and TSG5 to be in the on state, and the storage units in the storage unit strings Str0, Str4 and Str5 coupled with the target word line WLn have the first memory state (the erase state E), so that the storage unit strings Str0, Str4 and Str5 are turned on and can generate a current greater than or equal to the preset current, the current I0 on the bit line BL0 is substantially equal to the sum of the output currents of the storage unit strings Str0, Str4 and Str5, and the multiple of the current I0 relative to the current generated by any of the storage unit strings Str0, Str4 and Str5 is about 3. If the weight value stored by the storage unit in the first memory state is equivalent to “1” and the weight value stored by the storage unit in the second memory state is equivalent to “0”, then the operation performed by the eight storage unit strings coupled with the bit line BL0 can be equivalent to: 1*1+1*0+0*1+0*0+1*1+1*1+1*0+0*0=3.

[0112] Based on the above specific example, when the storage unit strings coupled with the bit line BLx in the target storage block are Y+1, the Y+1 elements corresponding to the input voltages input by the Y+1 first selection lines are a0, a1, …, aY+1, respectively. Y The weights stored by the Y+1 storage units coupled with the target word line WLn are w0, w1, …, wY+1, respectively. Y Then, the operation result equivalent to the multiple of the current on the bit line BLx relative to the output current greater than or equal to the preset current can be a0w0+a1w1+…+aY+1wY+1. 0* w0+α 1*w1+…+α Y* w Y In the multiplication accumulation operation, Y+1 multiplication operations are included, and the multipliers a0, a1, …, a Y are different, and for the entire target memory block, the multipliers of the multiplication operations performed by the memory cell strings coupled to different first selection lines can be different, thereby improving the flexibility of the operation and facilitating the implementation of more complex operations by the semiconductor device. In addition, the input voltages corresponding to multiple elements in the input data can be input simultaneously without being input sequentially, thereby improving the efficiency of the operation on the basis of improving the flexibility of the operation.

[0113] In some embodiments, the semiconductor device can include a plurality of memory blocks, and at least two memory blocks of the plurality of memory blocks are target memory blocks. The peripheral circuit can be configured to perform an operation simultaneously using the at least two memory blocks. Specifically, the peripheral circuit is configured to: apply a respective first read voltage to a target word line coupled to each of the at least two target memory blocks; apply a respective input voltage to a plurality of first selection lines coupled to each of the at least two target memory blocks; apply a first turn-on voltage to a non-target word line coupled to each of the at least two target memory blocks; and sense a current on a bit line coupled to the plurality of target memory blocks.

[0114] In some specific examples, the peripheral circuit is configured to: simultaneously apply a respective first read voltage to a target word line coupled to each of the at least two target memory blocks; simultaneously apply a respective input voltage to a plurality of top first selection lines coupled to each of the at least two target memory blocks; simultaneously apply a first turn-on voltage to a non-target word line coupled to each of the at least two target memory blocks; and simultaneously sense a current on a bit line coupled to the plurality of target memory blocks. In this way, the plurality of memory blocks in the semiconductor device can perform operations in parallel, thereby improving the computing power of the semiconductor device.

[0115] In some specific examples, a plurality of memory blocks coupled to the same bit line can perform operations simultaneously, and the current on the bit line is the accumulation result of the multiplication operations performed by all the memory cell strings coupled to the bit line. In this way, the input data can include more elements.

[0116] It should be noted that when the plurality of memory blocks are used to perform operations simultaneously, the input data input to different memory blocks can be different, and the first read voltage applied to the target word lines coupled to different memory blocks can also be different.

[0117] In some embodiments, referring back to FIG. 1, the storage array can include a plurality of storage planes, each of which includes a plurality of storage blocks, and the peripheral circuit can be configured to perform operations using the plurality of storage planes simultaneously, so as to further improve the computing power of the semiconductor device. Specifically, the plurality of storage planes each include a target storage block, and the peripheral circuit can be configured to obtain an operation result corresponding to a storage plane based on a current on a bit line coupled to the target storage block in the storage plane, and perform a logical operation based on the operation results corresponding to the plurality of storage planes, i.e., the peripheral circuit can further perform a logical operation on the operation results output by different storage planes. For example, the peripheral circuit can be configured to add the operation results output by at least two storage planes simultaneously.

[0118] In some embodiments, the storage plane can include a plurality of banks, and each bank includes a plurality of storage blocks; and the peripheral circuit can be configured to apply a first conduction voltage to non-target word lines respectively coupled to the plurality of banks.

[0119] In some embodiments, the peripheral circuit can be further configured to sequentially apply a first read voltage to target word lines respectively coupled to the plurality of banks in a preset order, and sequentially apply corresponding input voltages to first selection lines respectively coupled to the plurality of banks in the preset order; and sequentially sense currents on bit lines coupled to the banks in the preset order.

[0120] In a specific example, FIG. 11a is a schematic diagram of a plurality of banks in a storage plane, and FIG. 11b is a voltage curve for performing an operation using the plurality of banks in the storage plane. Here, it is assumed that the storage plane includes two banks, Bank 0 and Bank 1, the first selection line is a top selection line, and the preset order is from Bank 0 to Bank 1.

[0121] With reference to FIGS. 11a and 11b, in the stage of performing an operation using the plurality of banks in the storage plane, the peripheral circuit can be configured to simultaneously apply a first conduction voltage V pass1 to non-target word lines (Bank 0Unsel WL) coupled to Bank 0 and non-target word lines (Bank 1Unsel WL) coupled to Bank 1, and the voltage establishment stage S0 can overlap. In the first operation stage S1, an operation is performed using Bank 0, a first read voltage V rd is applied to a target word line (Bank 0Sel WL) coupled to Bank 0, and a corresponding input voltage V in, and the current on the bit line BL coupled with the memory bank Bank 0 is sensed, and the operation result of the memory bank Bank 0 can be obtained based on the current on the bit line BL. Then, in the second operation stage S2, the operation is performed by using the memory bank Bank 1, the first read voltage V rd , and the corresponding input voltage V in is applied to the first selection line (Bank 1 TSG) coupled with the memory bank Bank 1, and the current on the bit line BL coupled with the memory bank Bank 1 is sensed, and the operation result of the memory bank Bank 1 can be obtained based on the current on the bit line BL. Here, the input voltage V in is only illustrative, and the specific voltage application manner of the first selection line is similar to the manner of applying the corresponding input voltage to the first selection line based on the input data in the above embodiment, which will not be described herein again.

[0122] In the embodiments of the present disclosure, when the operation needs to be performed by using multiple memory banks, the first conduction voltage can be applied to the non-target word lines in the multiple memory banks at the same time, thereby the voltage establishment stage of the first conduction voltage applied to the non-selection word lines coupled with different memory banks can be overlapped, compared with the manner of applying the first conduction voltage to the non-selection word lines coupled with different memory banks respectively in different operation stages, the overall operation time can be shortened, and the operation efficiency of the operation performed by using multiple memory banks can be improved.

[0123] Further, for each memory bank, the operation can be performed by using multiple memory blocks in the memory bank at the same time, and the peripheral circuit can be configured to: apply the first read voltage to the target word lines respectively coupled with the multiple memory blocks of the memory bank; apply the corresponding input voltage to the multiple first selection lines respectively coupled with the multiple memory blocks of the memory bank; and sense the current on the bit line coupled with the multiple memory blocks of the memory bank. Specifically, referring to FIGS. 11a and 11b, taking the first operation stage S1 as an example, the first read voltage V rd is applied to the target word lines respectively coupled with the multiple memory blocks Block 0-Block N in the memory bank Bank 0 at the same time, the corresponding input voltage V in is applied to the multiple first selection lines respectively coupled with the multiple memory blocks Block 0-Block N at the same time, and the current on the bit line coupled with the multiple memory blocks Block 0-Block N is sensed, and the current on the bit line is the accumulated result after the multiplication operation performed by all the memory cells coupled with the bit line. In this way, the multiple memory blocks can perform the operation in parallel, thereby the operation efficiency and the computing power of the semiconductor device can be further improved.

[0124] In this embodiment, more complex operations can be performed without significant changes to the semiconductor device. Specifically, different input data and operations on the weight matrix in the storage array can be achieved simply by adjusting the input voltage applied to the first selection line. The adjustment of the input voltage on the first selection line can be achieved through the peripheral circuit module shown in FIG6 without adding additional circuitry, thereby improving the computing performance of the semiconductor device without occupying more chip area.

[0125] The above embodiments use a single-level cell (SLC) in a semiconductor device as an example to store one bit of data. In other embodiments, the storage cells in the target memory block are configured to store m bits of data, and the multiple storage cells in the target memory block are configured to have 2 m There are several memory states, where m is an integer greater than 1. During the computation phase using semiconductor devices, the first read voltage applied to the target word line can be located between the threshold voltage distributions corresponding to two adjacent memory states.

[0126] In some embodiments, the peripheral circuitry is further configured to apply a second read voltage to a target word line coupled to the target memory block. The second read voltage is located between threshold voltage distributions corresponding to two adjacent memory states, and the first read voltage differs from the second read voltage. Here, both the first and second read voltages may be located between two adjacent threshold voltage distributions, or the two threshold voltage distributions closest to the first read voltage may differ from the two threshold voltage distributions closest to the second read voltage. The following explanation uses the example of the two threshold voltage distributions closest to the first read voltage being different from the two threshold voltage distributions closest to the second read voltage.

[0127] In some specific examples, taking a multi-level cell (MLC) storing two bits of data as an example, Figure 12 is a schematic diagram of the threshold voltage distribution of the multi-level cell coupled to the target word line according to an embodiment of this disclosure. As shown in Figure 12, when the storage cell is a multi-level cell (MLC), the storage cell coupled to the target word line can have four memory states, including erase state E, programming state P1, programming state P2, and programming state P3. Then, the first read voltage and the second read voltage applied to the target word line can be located between the threshold voltage distributions corresponding to two adjacent memory states. For example, the first read voltage or the second read voltage can be V located between the threshold voltage distribution corresponding to the erase state E and the threshold voltage distribution corresponding to the programming state P1. rd1 Alternatively, the first or second read voltage can be V located between the threshold voltage distribution corresponding to programming state P1 and the threshold voltage distribution corresponding to programming state P2. rd2, or the first read voltage or the second read voltage can be V rd3 , and the first read voltage and the second read voltage are different. In this case, after performing a program operation once to write the weight into the memory cell, the weight stored in the memory cell can be changed only by applying different read voltages to the target word line, for example, when the read voltage is equal to V rd1 , the memory cell in the erase state E stores the weight of “1”, and the memory cells in the program states P1, P2 and P3 store the weight of “0”, while when the read voltage is equal to V rd2 , the memory cells in the program states E and P1 store the weight of “1”, and the memory cells in the program states P2 and P3 store the weight of “0”, while when the read voltage is equal to V rd3 , the memory cells in the program states P1 and P2 store the weight of “1”, and the memory cell in the program state P3 stores the weight of “0”. In this way, the first read voltage and the second read voltage can be applied to the target word line respectively to operate the same input data with different weight matrices, so as to update the weight stored in the memory cell without reprogramming the memory cell, thereby saving the time of weight update and further improving the flexibility of the operation function of the semiconductor device.

[0128] In some embodiments, the semiconductor device in the above embodiments includes a three-dimensional NAND type memory.

[0129] In some embodiments, the semiconductor device in the above embodiments includes a first semiconductor structure and a second semiconductor structure, the memory array is located in the first semiconductor structure, and the peripheral circuit is located in the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device.

[0130] In some embodiments, the semiconductor device includes a first semiconductor structure, a bonding layer and a second semiconductor structure stacked along the thickness direction of the semiconductor device; the memory array is located in the first semiconductor structure, and the peripheral circuit is located in the second semiconductor structure, and the peripheral circuit and the memory array are coupled through the bonding structure in the bonding layer.

[0131] In the embodiments of the present disclosure, the first semiconductor structure and the second semiconductor structure of the semiconductor device can be formed by bonding two wafers, for example, the first semiconductor structure can be formed on one wafer, the second semiconductor structure can be formed on another wafer, and then the two wafers are bonded, and the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device. In other embodiments, the first semiconductor structure and the second semiconductor structure of the semiconductor device can also be formed on the same wafer, but the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device. The architecture of stacking the first semiconductor structure and the second semiconductor structure along the thickness direction of the semiconductor device can save the area of the semiconductor device.

[0132] Based on the similar concept as the above semiconductor device, the present disclosure also provides an operation method of a semiconductor device. FIG. 13 is a flowchart of an operation method of a semiconductor device provided by an embodiment of the present disclosure. As shown in FIG. 13, the operation method of the semiconductor device includes the following steps.

[0133] Step S10: applying a first read voltage to a target word line coupled with a target storage block.

[0134] Step S20: applying a corresponding input voltage to each of a plurality of first selection lines coupled with the target storage block.

[0135] Step S30: applying a first conduction voltage to a non-target word line coupled with the target storage block.

[0136] Step S40: sensing a current on an output of a bit line coupled with the target storage block.

[0137] In some embodiments, during the operation stage using the semiconductor device, the operation method further includes: pre-charging a sensing node coupled with the bit line coupled with the target storage block to a target voltage.

[0138] In some embodiments, the storage unit in the target storage block is configured to store one bit of data, the plurality of storage units in the target storage block have a first memory state and a second memory state, the threshold voltage of the storage unit having the first memory state is less than the threshold voltage of the storage unit having the second memory state; the first read voltage is greater than the threshold voltage of the storage unit having the first memory state and less than the threshold voltage of the storage unit having the second memory state.

[0139] In some embodiments, the current on the bit line coupled to the target storage block is a sum of output currents of a plurality of storage cell strings in the target storage block coupled to the bit line; the output current of the storage cell string is greater than or equal to a preset current in a case that an input voltage applied to a first select line coupled to the storage cell string is such that a select transistor coupled to the first select line is in a conductive state, and a storage cell in the storage cell string coupled to a target word line has a first memory state.

[0140] In some embodiments, the storage cell in the target storage block is configured to store m-bit data, the plurality of storage cells in the target storage block are configured to have 2 m memory states, the first read voltage is between threshold voltage distributions corresponding to two adjacent memory states; m is an integer greater than 1.

[0141] In some embodiments, during the operation phase using the semiconductor device, the operation method further includes: applying a second read voltage to a target word line coupled to the target storage block, the second read voltage being between threshold voltage distributions corresponding to two adjacent memory states, and the first read voltage being different from the second read voltage.

[0142] In some embodiments, during the operation phase using the semiconductor device, the operation method further includes: applying a second conductive voltage to a plurality of second select lines coupled to the target storage block respectively.

[0143] In embodiments of the present disclosure, the first select line is one of a top select line and a bottom select line, and the second select line is the other of the top select line and the bottom select line.

[0144] In some embodiments, the operation method further includes: before the operation using the semiconductor device, applying a corresponding program voltage to a target word line coupled to the target storage block to program a storage cell coupled to the target word line.

[0145] In some embodiments, the storage array includes a plurality of storage planes, a storage plane including a plurality of storage blocks, and the operation method further includes: obtaining an operation result corresponding to a storage plane based on a current on a bit line coupled to a target storage block in the storage plane; and performing a logical operation based on the operation results corresponding to the plurality of storage planes.

[0146] In some embodiments, a storage plane includes a plurality of storage banks, a storage bank including a plurality of storage blocks; and applying the first conductive voltage to the non-target word line coupled to the target storage block includes: applying the first conductive voltage to non-target word lines coupled to the plurality of storage banks respectively.

[0147] In some embodiments, the applying the first read voltage to the target word line coupled with the target storage block, and the applying the respective input voltage to the plurality of first selection lines coupled with the target storage block, include: sequentially applying the first read voltage to the target word line coupled with each of the plurality of storage banks in a preset order, and sequentially applying the respective input voltage to the first selection line coupled with each of the plurality of storage banks in the preset order; and the sensing the current on the bit line coupled with the target storage block includes: sequentially sensing the current on the bit line coupled with each of the plurality of storage banks in the preset order.

[0148] In some embodiments, the applying the first read voltage to the target word line coupled with the target storage block includes: applying the first read voltage to the target word line coupled with each of the plurality of storage blocks of the storage bank; the applying the respective input voltage to the plurality of first selection lines coupled with the target storage block includes: applying the respective input voltage to the plurality of first selection lines coupled with each of the plurality of storage blocks of the storage bank; and the sensing the current on the bit line coupled with the target storage block includes: sensing the current on the bit line coupled with each of the plurality of storage blocks of the storage bank.

[0149] In the embodiments of the present disclosure, the operation method of the semiconductor device includes inputting a plurality of input voltages corresponding to input data from a plurality of first selection lines coupled with a target storage block to the storage block respectively, and applying a read voltage to a target word line coupled with the target storage block, and applying a turn-on voltage to a non-target word line coupled with the target storage block, so that the multipliers used in the multiplication operation performed by the storage units coupled with different first selection lines are different, thereby improving the flexibility of the operation performed by the semiconductor device including the three-dimensional NAND type memory. In addition, the plurality of input voltages corresponding to the input data are input to the storage block at the same time, and the plurality of storage blocks can perform the operation in parallel, and the plurality of storage surfaces can also perform the operation in parallel, thereby improving the efficiency of the operation and the computing power of the semiconductor device including the three-dimensional NAND type memory.

[0150] Based on the similar concept as the above semiconductor device, the present disclosure also provides a system, including: at least one semiconductor device as any of the above embodiments, and a controller coupled with the semiconductor device.

[0151] In some embodiments, the controller is configured to send an input vector or an input matrix to the semiconductor device, and receive the operation result of the semiconductor device. Here, the operation result of the semiconductor device is the operation result after analog-to-digital conversion.

[0152] In some embodiments, the system in the above embodiments can be a memory system 102 as shown in FIG. 14a, the memory system 102 includes a memory controller 106 and a memory device 104 coupled with the memory controller 106, the controller in the above embodiments can be the memory controller 106, and the semiconductor device can be the memory device 104.

[0153] In other embodiments, the system in the above embodiments can be a system 100 as shown in FIG. 14a, the system 100 includes a host 108 and a memory system 102 coupled with the host 108, the controller in the above embodiments can be a control part independent of the memory controller 106, for example, can be a CPU in the host device.

[0154] According to some embodiments, as shown in FIG. 14a, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the operation of the memory device 104, such as reading, erasing, programming, computing operation. The memory controller 106 can manage the data stored in the memory device 104, and communicate with the host 108.

[0155] In some embodiments, the system in the above embodiments can be a system 200 as shown in FIG. 14b, the system 200 includes a host 108 and a memory device 104 which can directly communicate with the host 108, the controller in the above embodiments can be a CPU in the host 108, and the semiconductor device in the above embodiments can be the memory device 104.

[0156] In one example as shown in FIG. 15, the system can be integrated into a memory card 202, the semiconductor device in the system can be the memory 104 in the memory card 202, and the controller in the system can be the memory controller 106 in the memory card 202. The memory card 202 can be one of a compact flash card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as Mini SD card, Micro SD card, SDHC card, etc., and a universal flash storage. The memory card 202 can further include a memory card connector 204 to couple the memory card 202 with a host. In another example as shown in FIG. 16, the system can be integrated into a solid state disk (SSD) 206, the semiconductor device in the system can be the memory device 104 in the SSD 206, and the controller in the system can be the memory controller 106 in the SSD 206. The SSD 206 can further include a SSD connector 208 to couple the SSD 206 with a host device. In some embodiments, the SSD 206 has a larger storage capacity and / or a higher operating speed than the memory card 202.

[0157] In some other embodiments, the system can be integrated in a terminal device, and the controller can be a central processing unit (CPU) of the terminal device. The terminal device can include, but is not limited to, any terminal device or portable terminal device such as a mobile phone, a smart television, a smart speaker, a wearable device, a tablet computer, a desktop computer, an all-in-one computer, a handheld computer, a notebook computer, a server, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), a laptop, a mobile computer, an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, etc.

[0158] Based on the similar concept as the operation method of the semiconductor device, the disclosure also provides a computer readable storage medium, and FIG. 17 is a schematic diagram of the computer readable storage medium provided by the embodiment of the disclosure. The computer readable storage medium 601 stores a computer program, and when the computer program is executed by the processor 602, the operation method of the semiconductor device in any of the above embodiments can be implemented.

[0159] In some specific embodiments, the computer readable storage medium 601 can be a ferromagnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc. It can also be various devices including one or any combination of the above memory devices.

[0160] The features disclosed in the several device embodiments of the disclosure can be combined arbitrarily without conflict to obtain new device embodiments.

[0161] The methods disclosed in the several method embodiments of the disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

[0162] The above is only a specific implementation of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the disclosure, which should be covered within the protection scope of the disclosure.

Claims

1. A semiconductor device comprising a memory array and a peripheral circuit coupled to the memory array, the memory array comprising a plurality of memory blocks, during an operation phase with the semiconductor device, the peripheral circuit is configured to: apply a first read voltage to a target word line coupled to a target memory block; apply respective input voltages to a plurality of first select lines coupled to the target memory block, respectively; apply a first pass voltage to a non-target word line coupled to the target memory block; and sense a current on a bit line coupled to the target memory block. during the operation phase with the semiconductor device, the peripheral circuit is configured to: pre-charge a sensing node coupled to the bit line coupled to the target memory block to a target voltage. a memory cell in the target memory block is configured to store one bit of data, a plurality of memory cells in the target memory block have a first memory state and a second memory state, a threshold voltage of a memory cell having the first memory state is less than a threshold voltage of a memory cell having the second memory state; the first read voltage is greater than the threshold voltage of the memory cell having the first memory state and less than the threshold voltage of the memory cell having the second memory state. the current on the bit line coupled to the target memory block is a sum of output currents of a plurality of memory cell strings in the target memory block coupled to the bit line; the output current of a memory cell string is greater than or equal to a preset current, in a case that the input voltage applied to a first select line coupled to the memory cell string causes a select transistor coupled to the first select line to be in a pass state and a memory cell in the memory cell string coupled to the target word line has the first memory state. during the operation phase with the semiconductor device, the peripheral circuit is configured to: apply a second read voltage to the target word line coupled to the target memory block, the second read voltage is between threshold voltage distributions corresponding to two adjacent memory states, the first read voltage is different from the second read voltage. during the operation phase with the semiconductor device, the peripheral circuit is configured to: apply a second pass voltage to a plurality of second select lines coupled to the target memory block, respectively. the first select line is one of a top select line and a bottom select line, the second select line is the other of the top select line and the bottom select line. the peripheral circuit is configured to: before the operation phase with the semiconductor device, apply a respective program voltage to the target word line coupled to the target memory block to program a memory cell coupled to the target word line. at least two memory blocks of the plurality of memory blocks are target memory blocks, the peripheral circuit is configured to: apply respective first read voltages to target word lines coupled to the at least two target memory blocks, respectively; apply respective input voltages to a plurality of first select lines coupled to the at least two target memory blocks, respectively; apply a first pass voltage to a non-target word line coupled to the at least two target memory blocks, respectively. ​ ​ ​ ​ 2. The semiconductor device of claim 1, wherein, ​ ​ 3. The semiconductor device of claim 1, wherein, ​ ​ 4. The semiconductor device of claim 3, wherein, ​ ​ 5. The semiconductor device of claim 1, wherein, The memory cells in the target memory block are configured to store m-bit data, a plurality of memory cells in the target memory block are configured to have 2 m memory states, the first read voltage is located between threshold voltage distributions corresponding to two adjacent memory states; the m is an integer greater than 1.

6. The semiconductor device of claim 5, wherein, ​ ​ 7. The semiconductor device of claim 1, wherein, ​ ​ 8. The semiconductor device of claim 7, wherein, ​ 9. The semiconductor device of claim 1, wherein, ​ ​ 10. The semiconductor device of claim 1, wherein, ​ ​ ​ ​ Sensing a current on a bit line coupled with the target memory block.

11. The semiconductor device of claim 1, wherein, The memory array includes a plurality of memory planes, each of the memory planes including a plurality of memory blocks; and the peripheral circuit is configured to: obtain a calculation result corresponding to the memory plane based on a current on a bit line coupled with the target memory block in the memory plane; perform a logical operation based on the calculation results corresponding to the plurality of memory planes.

12. The semiconductor device of claim 11, wherein, The memory plane includes a plurality of memory banks, each of the memory banks including a plurality of memory blocks; and the peripheral circuit is configured to: apply a first conductive voltage to non-target word lines respectively coupled with each of the plurality of memory banks.

13. The semiconductor device of claim 12, wherein, The peripheral circuit is configured to: apply a first read voltage to target word lines respectively coupled with each of the plurality of memory banks in a preset order, and apply corresponding input voltages to first selection lines respectively coupled with each of the plurality of memory banks in the preset order; sense a current on a bit line coupled with the memory bank in the preset order.

14. The semiconductor device of claim 13, wherein, The peripheral circuit is configured to: apply the first read voltage to target word lines respectively coupled with a plurality of memory blocks of the memory bank; apply corresponding input voltages to a plurality of first selection lines respectively coupled with the plurality of memory blocks of the memory bank; sense a current on a bit line coupled with the plurality of memory blocks of the memory bank.

15. The semiconductor device of claim 1, wherein, The peripheral circuit includes: an analog-to-digital conversion circuit, a digital-to-analog conversion circuit, a voltage generator, a column decoder, and a control logic; the analog-to-digital conversion circuit is coupled with the column decoder and the control logic; and the digital-to-analog conversion circuit is coupled with the voltage generator and the control logic.

16. The semiconductor device of claim 1, wherein, The semiconductor device includes a three-dimensional NAND type memory.

17. The semiconductor device of claim 1, wherein, The semiconductor device includes a first semiconductor structure and a second semiconductor structure; the memory array is located in the first semiconductor structure, and the peripheral circuit is located in the second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked along a thickness direction of the semiconductor device.

18. A system, comprising: at least one semiconductor device as claimed in any one of claims 1 to 17; a controller coupled with the at least one semiconductor device and configured to send input data to the semiconductor device and receive a calculation result of the semiconductor device.

19. An operating method of a semiconductor device, the operating method comprising, in a calculation phase using the semiconductor device: applying a first read voltage to a target word line coupled with a target memory block; applying corresponding input voltages to a plurality of first selection lines respectively coupled with the target memory block; applying a first conductive voltage to a non-target word line coupled with the target memory block; sensing a current on a bit line coupled with the target memory block.

20. The method of operation of claim 19, wherein, In the calculation phase using the semiconductor device, the operating method further comprises: pre-charging a sensing node coupled with the bit line coupled with the target memory block to a target voltage.

21. The method of operating of claim 19, wherein, The memory cells in the target memory block are configured to store one bit of data, and a plurality of memory cells in the target memory block have a first memory state and a second memory state, a threshold voltage of a memory cell having the first memory state is less than a threshold voltage of a memory cell having the second memory state; The first read voltage is greater than the threshold voltage of the memory cell having the first memory state and less than the threshold voltage of the memory cell having the second memory state.

22. The method of operating according to claim 21, wherein, The current on the bit line coupled to the target memory block is a sum of output currents of a plurality of memory cell strings in the target memory block coupled to the bit line; In a case that the input voltage applied to the first selection line coupled to the memory cell string causes a selection transistor coupled to the first selection line to be in a conductive state, and a memory cell in the memory cell string coupled to the target word line has the first memory state, the output current of the memory cell string is greater than or equal to a preset current.

23. The method of operating of claim 19, wherein, The memory cells in the target memory block are configured to store m-bit data, a plurality of memory cells in the target memory block are configured to have 2 m memory states, the first read voltage is located between threshold voltage distributions corresponding to two adjacent memory states; the m is an integer greater than 1.

24. The method of operating of claim 23, wherein, In the operation phase using the semiconductor device, the operation method further includes: applying a second read voltage to the target word line coupled to the target memory block, the second read voltage being between threshold voltage distributions corresponding to two adjacent memory states, and the first read voltage being different from the second read voltage.

25. The method of operating of claim 19, wherein, In the operation phase using the semiconductor device, the operation method further includes: applying a second conductive voltage to a plurality of second selection lines coupled to the target memory block, respectively.

26. The method of operating of claim 25, wherein, The first selection line is one of a top selection line and a bottom selection line, and the second selection line is the other of the top selection line and the bottom selection line.

27. The method of operating of claim 19, wherein, The operation method further includes: before the operation phase using the semiconductor device, applying a corresponding programming voltage to the target word line coupled to the target memory block to program a memory cell coupled to the target word line.

28. The method of operating of claim 19, wherein, The memory array includes a plurality of memory planes, and each memory plane includes a plurality of memory blocks; the operation method further includes: obtaining an operation result corresponding to the memory plane based on a current on a bit line coupled to the target memory block in the memory plane; and performing a logical operation based on operation results corresponding to a plurality of memory planes.

29. The method of operating of claim 28, wherein, The memory plane includes a plurality of memory banks, and each memory bank includes a plurality of memory blocks; the applying of the first conductive voltage to the non-target word line coupled to the target memory block includes: applying a first conductive voltage to a non-target word line coupled to each of the plurality of memory banks, respectively.

30. The method of operating of claim 29, wherein, The applying of the first read voltage to the target word line coupled to the target memory block and the applying of a corresponding input voltage to a plurality of first selection lines coupled to the target memory block include: sequentially applying a first read voltage to a target word line coupled to each of a plurality of memory banks in a preset order, and sequentially applying a corresponding input voltage to a first selection line coupled to each of the plurality of memory banks in a preset order; The sensing of the current on the bit line coupled to the target memory block includes: sequentially sensing a current on a bit line coupled to the memory bank in a preset order.

31. The method of operating of claim 30, wherein, The applying the first read voltage to the target word line coupled with the target memory block comprises: applying the first read voltage to the target word line coupled with each of the plurality of memory blocks of the memory bank respectively; The applying the respective input voltages to the plurality of first selection lines coupled with the target memory block comprises: applying the respective input voltages to the plurality of first selection lines coupled with each of the plurality of memory blocks of the memory bank respectively; The sensing the current on the bit line coupled with the target memory block comprises: sensing the current on the bit line coupled with each of the plurality of memory blocks of the memory bank.

32. A computer readable storage medium, having stored thereon a computer program, wherein the computer program is executed by a processor to perform the operation method of any one of claims 19 to 31.

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