Semiconductor device structure, gate-source structure, and preparation method therefor

Abstract

The present invention belongs to the technical field of semiconductors, and relates to a semiconductor device structure, a gate-source structure, and a preparation method therefor. The semiconductor device comprises a functional layer, and the preparation method for the gate-source structure comprises: providing a first structural layer above a first region of the functional layer, the first structural layer at least comprising a gate metal layer, and providing a first dielectric layer above the first structural layer, the first dielectric layer at least covering the gate metal layer; etching downward from the first dielectric layer above the gate metal layer to obtain a first recess; providing a second dielectric layer and covering at least a sidewall of the first recess; etching the second dielectric layer in the first recess to retain the second dielectric layer on the sidewall of the first recess at a first preconfigured thickness; and providing a metal in the first recess in which the second dielectric layer having the first preconfigured thickness is retained on the current sidewall to obtain a source of the semiconductor device. According to embodiments of the present invention, a gate-source spacing can be shortened and controlled, and device manufacturing costs can be reduced.

Description

Semiconductor device structure, gate-source structure and preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device structure, a gate-source structure and a preparation method thereof. BACKGROUND

[0002] In a semiconductor device, the specific on-resistance (Rsp, the product of the chip area of the device and the on-resistance) is an important indicator for measuring the performance of the device. On the premise of meeting other electrical properties, the smaller the Rsp is, the smaller the area of the device is, and the lower the cost is. At present, in order to reduce the Rsp, reduce the die area and reduce the cost, the commonly used method is to shorten the distance between the gate and the source of the device as much as possible. For example, in the current mainstream gallium nitride high electron mobility transistor (GaN HEMT) manufacturing process, the preparation steps of the gate and the source are separated, and the electrodes are mainly formed by using a stripping or etching process to form functional zones such as a gate functional zone, a source functional zone, a drain functional zone and the like. Therefore, the gate-source distance depends on the exposure accuracy and the alignment accuracy of the photolithography machine, and the manufacturing difficulty is great. In addition, the metal morphology of the electrode is difficult to control, and the abnormal metal morphology can easily lead to device failure, affecting the wafer yield. Therefore, in order to ensure the manufacturability of the device, the horizontal distance between the gate and the source of the general GaN HEMT is maintained between 3-5um, which will result in a large Rsp of the device, and cannot effectively reduce the cost, and is not conducive to the performance release of the power device. SUMMARY

[0003] In view of the technical problems in the prior art, the present application provides a semiconductor device structure, a gate-source structure and a preparation method thereof, to shorten and control the gate-source distance.

[0004] According to one aspect of the present application, a gate-source structure preparation method of a semiconductor device is provided, the semiconductor device comprising a functional layer, the functional layer comprising at least a channel layer and a barrier layer, a two-dimensional carrier gas being formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer being a III-V compound; the method comprising the following steps:

[0005] providing a first structure layer above a first region of the functional layer, the first structure layer comprising, in sequence from bottom to top, a gate dielectric layer or a P-type material layer and a gate metal layer, at least part of the gate metal layer serving as a gate of the semiconductor device;

[0006] providing a first dielectric layer above the first structure layer, the first dielectric layer covering at least the gate metal layer;

[0007] a first recess is etched from a first dielectric layer above the first region downwards, a bottom of the first recess is located at any position between a lower surface of the gate metal layer and the two-dimensional carrier gas in the channel layer, wherein sidewalls of the first recess from top to bottom are the first dielectric layer and the first structure layer in sequence;

[0008] a second dielectric layer is provided above the current structure and covers at least the sidewalls of the first recess;

[0009] the second dielectric in the first recess is etched, and the second dielectric layer with a first preset thickness is reserved on the sidewalls of the first recess; and

[0010] a metal is provided in the first recess with the sidewalls of which the second dielectric layer with the first preset thickness is reserved to obtain a source electrode of the semiconductor device.

[0011] Optionally, when the second dielectric in the first recess is etched, after the second dielectric at the bottom of the first recess is etched away, the etching continues downwards to etch part of the barrier layer or all of the barrier layer or part of the channel layer in the functional layer.

[0012] According to another aspect of the present application, the present application further provides a method for preparing a semiconductor device structure, comprising the following steps:

[0013] a semiconductor epitaxial wafer is provided as a functional layer, the functional layer at least comprising a channel layer and a barrier layer, a two-dimensional carrier gas being formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V compound;

[0014] a gate, a source and a drain are formed in the functional layer, the source and the drain being capable of being electrically connected or disconnected through the two-dimensional carrier gas in the functional layer; and

[0015] a passivation layer and a plurality of pads are formed above the current structure, the passivation layer covering the gate, the source and the drain, the plurality of pads being formed above the passivation layer, the plurality of pads being electrically connected to the gate, the source and the drain through dielectric vias to obtain a gate pad, a source pad and a drain pad;

[0016] wherein the gate and the source are formed according to the method for preparing a gate-source structure of the semiconductor device.

[0017] Optionally, when the first dielectric layer is provided above the first structure layer, the first dielectric layer extends to a preset drain region, correspondingly, a second recess is etched from the first dielectric layer downwards to the functional layer in the preset drain region at the same time when the first recess is etched, or a second recess is etched from the first dielectric layer downwards to the functional layer after the gate and the source are formed; a metal is provided in the second recess to obtain a drain.

[0018] Optionally, when the first recess and the second recess are formed simultaneously, the second dielectric layer is provided above the current structure, the second dielectric layer is provided above the first dielectric layer, and the second dielectric layer covers at least the sidewall of the first recess and the sidewall of the second recess; the method further comprises: etching the second dielectric in the second recess, leaving the second dielectric layer of a second preset thickness on the sidewall of the second recess or etching away all the second dielectric in the second recess; providing metal in the second recess with the sidewall of which the second preset thickness is left to form the drain electrode, or providing metal in the second recess with all the second dielectric etched away to form the drain electrode.

[0019] Optionally, when the first structure layer is provided above the first region of the functional layer, the first structure layer extends from the first region to a preset drain region, the method further comprises: etching downward from the first dielectric layer to form a second recess in the preset drain region, the bottom of the second recess being located at any position between the lower surface of the gate metal layer and the two-dimensional carrier gas in the channel layer; correspondingly, when the second dielectric layer is provided above the current structure, the second dielectric layer is provided above the first dielectric layer, and the second dielectric layer covers at least the sidewall of the first recess and the sidewall of the second recess; the method further comprises: etching the second dielectric in the second recess, leaving the second dielectric layer of a second preset thickness on the sidewall of the second recess; providing metal in the second recess with the sidewall of which the second preset thickness is left to form the drain electrode.

[0020] Optionally, when the first structure layer is provided, it comprises:

[0021] providing a gate dielectric layer or a P-type material layer above the functional layer;

[0022] providing a patterned metal layer above the gate dielectric layer, or providing a metal layer above the P-type material layer and patterning the P-type material layer and the metal layer; wherein the patterned metal layer comprises a gate metal layer located in the first region and a drain metal layer located in the preset drain region;

[0023] Correspondingly, when the first dielectric layer is provided, the first dielectric layer covers at least the gate metal layer and the drain metal layer.

[0024] Optionally, the method for preparing the semiconductor device structure further comprises: electrically connecting the drain metal layer and the drain electrode or drain pad through a dielectric via.

[0025] According to another aspect of the present application, the application further provides a semiconductor device structure, comprising a functional layer, a dielectric layer, an electrode and a pad, the functional layer at least comprising a channel layer and a barrier layer, a two-dimensional carrier gas being formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer being a III-V compound; the dielectric layer at least comprising a gate dielectric layer or a P-type material layer, a first dielectric layer, a second dielectric layer and a passivation layer; the electrode comprising a gate, a source and a drain;

[0026] The first region of the functional layer is above a first structure layer, the first structure layer comprising a gate dielectric layer or a P-type material layer and a gate metal layer from bottom to top, at least part of the gate metal layer serving as a gate; the first structure layer is above a first dielectric layer; a first recess is formed in the first structure layer from the first dielectric layer above the first region, the bottom of the first recess being located at any position between the lower surface of the gate metal layer and the two-dimensional carrier gas in the channel layer, the sidewall of the first recess being covered with a first preset thickness of a second dielectric layer; the metal provided in the first recess with the sidewall retaining the first preset thickness of the second dielectric layer forms the source; a preset drain region of the functional layer is formed with a second recess, the metal provided in the second recess forming the drain; the source and the drain can be electrically connected or disconnected through the two-dimensional carrier gas in the functional layer;

[0027] The passivation layer is above the electrode and the first dielectric layer, a plurality of pads being formed above the passivation layer, the plurality of pads being electrically connected to the gate, the source and the drain through dielectric vias to obtain a gate pad, a source pad and a drain pad;

[0028] The distance between the source and the gate is the thickness of the second dielectric layer of the sidewall of the first recess, the distance between the source and the gate being controlled by the thickness of the second dielectric layer of the sidewall of the first recess.

[0029] Optionally, the preset drain region comprises a first dielectric layer extending from the first region.

[0030] Optionally, the preset drain region comprises a drain metal layer and a first dielectric layer, the first dielectric layer being above the drain metal layer; the drain metal layer being electrically connected to the drain or the drain pad through a dielectric via.

[0031] Optionally, the horizontal spacing region between the drain metal layer and the gate metal layer comprises a first dielectric or passivation layer dielectric.

[0032] Optionally, the preset drain region comprises a first structure layer and a first dielectric layer extending from the first region, the first dielectric layer being above the first structure layer; the sidewall of the second recess being covered with a second preset thickness of a second dielectric layer.

[0033] According to another aspect of the present application, the application further provides a gate-source structure of a semiconductor device, comprising:

[0034] a functional layer, the functional layer comprising at least a channel layer and a barrier layer, a two-dimensional carrier gas being formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer being a III-V compound;

[0035] a first structure layer, the first structure layer being located above a first region of the functional layer, the first structure layer comprising, from bottom to top, a gate dielectric layer or a P-type material layer and a gate metal layer, at least part of the gate metal layer serving as a gate;

[0036] a first dielectric layer, the first dielectric layer being located above the first structure layer;

[0037] wherein a first recess is formed from the first dielectric layer above the first region downwardly through the gate metal layer in the first structure layer, a bottom of the first recess being located at any position between a lower surface of the gate metal layer and the two-dimensional carrier gas in the channel layer, a sidewall of the first recess being covered with a second dielectric layer of a first preset thickness; a metal provided in the first recess with the sidewall remaining the second dielectric layer of the first preset thickness forming a source;

[0038] a spacing between the source and the gate being a thickness of the second dielectric layer of the sidewall of the first recess, the spacing between the source and the gate being controlled by the thickness of the second dielectric layer of the sidewall of the first recess.

[0039] The embodiment of the present application achieves the purpose of shortening and controlling the gate-source spacing by controlling the thickness of the dielectric between the gate and the source, thereby maintaining the yield of the device and effectively reducing the cost of the device. BRIEF DESCRIPTION OF DRAWINGS

[0040] Hereinafter, preferred embodiments of the present application will be described in further detail with reference to the accompanying drawings, in which:

[0041] Fig. 1 is a flow chart of a method for preparing a semiconductor device structure according to an embodiment of the present application;

[0042] Fig. 2 is a schematic diagram of a structure principle obtained after a semiconductor epitaxial wafer is provided as a functional layer 10 according to the embodiment of the present application;

[0043] Fig. 3 is a schematic diagram of a structure principle after a first structure layer 20 is provided on the functional layer 10 according to the embodiment of the present application;

[0044] Fig. 4 is a schematic diagram of a structure principle after a first dielectric layer 301 is provided above the first structure layer 20 according to the embodiment of the present application;

[0045] Fig. 5 is a schematic diagram of a structure after etching a groove according to an embodiment of the present application;

[0046] Fig. 6 is a schematic diagram of a structure after providing a second dielectric layer 302 according to an embodiment of the present application;

[0047] Fig. 7 is a schematic diagram of a structure after etching a second dielectric in the groove according to an embodiment of the present application;

[0048] Fig. 8 is a schematic diagram of a structure after providing a metal to form a source 22 and a drain 23 in the groove according to an embodiment of the present application;

[0049] Fig. 9 is a schematic diagram of a structure of a semiconductor device according to an embodiment of the present application;

[0050] Fig. 10 is a flow chart of a method of fabricating a gate-source structure of a semiconductor device according to an embodiment of the present application;

[0051] Fig. 11 is a schematic diagram of a structure of a semiconductor device corresponding to each step in a fabrication process according to an embodiment of the present application;

[0052] Fig. 12 is a schematic diagram of a structure of a semiconductor device according to an embodiment of the present application;

[0053] Fig. 13 is a schematic diagram of a structure of a semiconductor device corresponding to each step in a fabrication process according to an embodiment of the present application; and

[0054] Fig. 14 is a schematic diagram of a structure of a semiconductor device corresponding to each step in a fabrication process according to an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0056] In the following detailed description, reference can be made to the accompanying drawings that form a part of the specification, illustrating the present application and, together with the description, describing the specific embodiments of the present application. In the drawings, like reference numerals refer to like elements throughout the various figures. The various specific embodiments of the present application are described in sufficient detail to enable one of ordinary skill in the art and knowledge of the relevant art to make and use the technical solutions of the present application. It should be understood that other embodiments or structural, logical, or electrical changes can be made to the embodiments of the present application.

[0057] The present application provides a semiconductor device structure, a gate-source structure and a preparation method thereof. The thickness of the medium between the gate and the source is controlled to shorten and control the distance between the gate and the source. The present application is described in detail below through specific examples.

[0058] Example One

[0059] Figure 1 is a flow chart of the preparation method of the semiconductor device structure according to the first embodiment of the present application. The preparation method of the semiconductor device structure in the present embodiment includes the following steps:

[0060] Step S1, a semiconductor epitaxial wafer is provided as a functional layer 10. The functional layer 10 includes at least a channel layer and a barrier layer, and a two-dimensional carrier gas 111 is formed in the channel layer near the barrier layer; the channel layer and the barrier layer are III-V compound.

[0061] Step S2, a gate 21, a source 22 and a drain 23 are formed on the functional layer 10 respectively. The source 22 and the drain 23 are electrically connected or disconnected through the two-dimensional carrier gas 111 in the functional layer 10.

[0062] Step S3, a passivation layer 40 and a plurality of pads 50 are formed above the current structure. The plurality of pads 50 are electrically connected to the gate 21, the source 22 and the drain 23 through the medium via holes to obtain a gate pad, a source pad and a drain pad.

[0063] Referring to Figure 2, which is a schematic diagram of the structure obtained after the semiconductor epitaxial wafer is provided as the functional layer 10 according to the first embodiment of the present application. The semiconductor epitaxial wafer in step S1 includes a substrate 100 and an epitaxial layer 110, which is obtained by epitaxially forming a channel layer and a barrier layer on the surface of the substrate 100 in sequence through epitaxial process, and is used as the functional layer 10 for preparing the semiconductor device in step S1. The material of the substrate 100 is, for example, intrinsic GaN or materials such as silicon (Si), silicon carbide (SiC) or sapphire (main component: Al2O3). The material of the substrate 100 in the present embodiment is Si. When the substrate 100 is a non-intrinsic substrate, a buffer layer (not shown in the figure) can be further introduced to reduce the impact of lattice difference. The buffer layer can be aluminum nitride (AlN), gallium nitride (GaN), gallium aluminum nitride (AlGaN), indium gallium nitride (InGaN) or the like. X Ga (1-X)one or more of AlN, GaN, InN, AlGaN, InGaN, AlInN and AlGaInN, to reduce the impact of the difference in lattice constant and thermal expansion coefficient between the substrate 100 and the epitaxial layer 110, effectively avoiding the nitride epitaxial layer 110 from cracking and the like. The buffer layer is an optional structure, and the buffer layer can be a multi-layer structure, wherein each layer is composed of different materials. A nucleation layer can also be introduced between the substrate 100 and the buffer layer to avoid the melt-back effect. The material of the channel layer is, for example, GaN, and the material of the barrier layer is, for example, Al X Ga (1-X) N, and the channel layer and the barrier layer constitute a heterojunction, in which a two-dimensional carrier gas 111, such as a two-dimensional electron gas (2DEG) or a two-dimensional hole gas (2DHG), is provided. The materials of the channel layer and the barrier layer constituting the heterojunction can also be other III-V semiconductor materials, such as AlN, GaN, InN, and compounds of these materials, such as AlGaN, InGaN, AlInGaN, etc.

[0064] In step S2, the process of forming the gate 21 and the source 22 is shown in FIG. 10, which is a flowchart of a method for preparing a gate-source structure of a semiconductor device according to Embodiment One of the present application. In this embodiment, the method for preparing the gate-source structure includes:

[0065] In step S21, a first structure layer 20 is provided above the first region 101 of the functional layer 10. The first structure layer 20 includes, from bottom to top, a gate dielectric layer 201 (or a P-type material layer) and a gate metal layer 202, and part or all of the gate metal layer 202 can serve as the gate 21. In this embodiment, the first structure layer 20 extends to the second region 102, which is the drain region, as shown in FIG. 3, which is a schematic diagram of the structure after the first structure layer 20 is provided on the functional layer 10 according to Embodiment One of the present application. In the drawings shown in FIG. 3 and subsequent drawings, the first region 101 and the second region 102 are marked at the bottom of the functional region in order to clearly show the other structures above the functional layer, so as not to affect the expression of the other structures above the functional region.

[0066] In step S22, a first dielectric layer 301 is provided above the first structure layer 20. The first dielectric layer 301 covers at least the gate metal layer 202, as shown in FIG. 4, which is a schematic diagram of the structure after the first dielectric layer 301 is provided above the first structure layer 20 according to Embodiment One of the present application.

[0067] Step S23, etching down from the first dielectric layer 301 above the gate metal layer 202 of the first region 101 to the functional layer 10 to obtain a first recess 31. The bottom of the first recess 31 can be located at any position between the lower surface of the gate metal layer 202 and the two-dimensional carrier gas 111 in the channel layer. In the embodiment, the gate metal layer 202 and the gate dielectric layer 201 in the first structure layer 20 are etched away, and the bottom of the first recess 31 is located on the upper surface of the epitaxial layer 110 in the functional layer 10. The sidewall of the first recess 31 from top to bottom is the first dielectric layer 301 and the first structure layer 20 in sequence. At the same time, etching down from the first dielectric layer 301 above the gate metal layer 202 of the second region 102 to the functional layer 10 to obtain a second recess 32, the bottom position of the second recess 32 is the same as that of the first recess 31, see FIG. 5 for details, which is a schematic structural diagram after etching the recess according to the embodiment of the present application.

[0068] Step S24, providing a second dielectric layer 302 above the current structure. The second dielectric layer 302 covers the bottom and inner wall of the first recess 31 and the second recess 32, see FIG. 6 for details, which is a schematic structural diagram after providing the second dielectric layer 302 according to the embodiment of the present application.

[0069] Step S25, etching the second dielectric layer 302, and retaining the second dielectric layer 302 with a first preset thickness on the sidewall of the first recess 31. In the embodiment, the second dielectric in the second recess 32 is also etched, and the second dielectric layer 302 with a second preset thickness on the sidewall of the second recess is retained. In the embodiment, the second dielectric on the surface of the first dielectric layer 301 and the bottom of the recess is etched away, and the second dielectric layer 302 with a preset thickness on the sidewall is retained according to the design parameters. The second dielectric layer 302 with the first preset thickness on the sidewall of the first recess and the second preset thickness on the sidewall of the second recess can be the same or different. In addition, when etching the second dielectric layer 302 at the bottom of the first recess 31 and the second recess 32, the etching can stop at the surface of the barrier layer, or the etching can continue to etch away part or all of the barrier layer in the functional layer 10 at the bottom of the recess, as shown in the figure, etching away all of the barrier layer at the bottom of the recess, and part of the channel layer can also be etched away, so as to facilitate the metal in the recess to form ohmic contact with the functional layer 10, see FIG. 7 for details, which is a schematic structural diagram after etching the second dielectric in the recess according to the embodiment of the present application.

[0070] Step S26, metal is provided in the first recess 31 of the second dielectric layer 302 with the first preset thickness reserved on the current sidewall to obtain the source electrode 22. In the embodiment, metal is simultaneously provided in the second recess 32 of the second dielectric layer 302 with the second preset thickness reserved on the current sidewall to obtain the drain electrode 23, wherein the part of the gate metal layer 202 between the first recess 31 and the second recess 32 serves as the gate electrode 21. Referring to FIG. 8, which is a schematic diagram of a structure after metal is provided in the recess to form the source electrode 22 and the drain electrode 23 according to the embodiment of the present application. The source electrode 22 and the drain electrode 23 form ohmic contact with the functional layer 10, so that the two-dimensional carrier gas 111 in the functional layer 10 can be electrically connected or disconnected.

[0071] In the embodiment, the gate electrode 21 is below the gate dielectric layer 201, such as silicon nitride, titanium nitride, aluminum oxide, etc. When no driving voltage is applied between the gate electrode and the source electrode, the source electrode 22 and the drain electrode 23 are electrically connected through the two-dimensional carrier gas 111. When a driving voltage is applied between the gate electrode and the source electrode, the two-dimensional carrier gas 111 below the gate dielectric layer 201 is depleted, so that the electrical connection between the source electrode 22 and the drain electrode 23 is disconnected, i.e., a depletion-mode semiconductor device is obtained. When the gate dielectric layer 201 is aluminum nitride, etc., the gate metal layer 202 can form a Schottky junction with the functional layer 10 through certain process conditions, i.e., the gate structure is a Schottky gate, and a depletion-mode semiconductor device is also obtained. When the gate electrode 21 is below a layer of P-type material (such as p-GaN, p-AlGaN, etc.), the P-type material layer depletes the two-dimensional carrier gas 111 in the channel layer below the P-type material layer when no driving voltage is applied between the gate electrode and the source electrode, so that the source electrode 22 and the drain electrode 23 are not electrically connected. When a driving voltage is applied between the gate electrode and the source electrode, the two-dimensional carrier gas 111 is generated in the channel layer below the P-type material layer, so that the electrical connection between the source electrode 22 and the drain electrode 23 is connected, i.e., an enhancement-mode semiconductor device is obtained.

[0072] The source 22 and the drain 23 are prepared simultaneously. The material of the first dielectric layer 301 is, for example, silicon nitride, silicon oxide, high-k dielectric (such as aluminum oxide, aluminum nitride, etc.), etc., and the material of the gate dielectric layer 201 is, for example, silicon nitride, aluminum oxide, etc. Before etching from the first dielectric layer 301 in step S23, a photoresist is first used to define the first recess 31 region and the second recess 32 region on the upper surface of the first dielectric layer 301 corresponding to the first region 101 and the second region 102, and then a high-selectivity etching method is used for etching. The etching gas used has different etching rates for different structure layers. For example, when the first dielectric layer 301 is silicon nitride, CF4, SF6, or F-based mixed gas is first used to etch the first dielectric layer 301, then chlorine-based gas is used to etch the gate metal layer 202, and then F-based gas or F-based mixed gas is used to etch the gate dielectric layer 201 to the surface of the functional layer 10. In this embodiment, the etching rate of F-based gas or F-based mixed gas for the gate dielectric layer 201 and the functional layer 10 (such as the barrier layer) is greater than or equal to 70:1, for example.

[0073] In step S3, the passivation layer 40 can include multiple layers. For example, after the source and the drain are obtained in step S2, a passivation layer is deposited thereon, then a pad metal layer is grown thereon and patterned, and then a passivation layer is deposited at appropriate positions above the pad metal layer to cover part of the pad metal layer while exposing part of the pad metal layer, and the exposed part of the pad metal layer forms multiple pads 50, as shown in FIG. 9, which is a schematic diagram of a semiconductor device structure according to Embodiment One of the present application. In addition, the pads are respectively electrically connected to the gate 21, the source 22, and the drain 23 through dielectric vias to obtain a gate pad, a source pad, and a drain pad.

[0074] The gate metal layer 202 in the present application is a composite metal layer deposited by electron beam evaporation or sputtering, such as TiAl, TiAl, TiN, etc., or a composite structure of aluminum oxide, aluminum nitride, and metal or titanium nitride and metal.

[0075] In addition, when the metal is provided in the first recess 31 and the second recess 32 to form the source 22 and the drain 23, a multilayer Ti / Al / Ni / Au sequence can be evaporated by electron beam evaporation process, and each layer has a thickness determined according to specific requirements, and then an ohmic contact for the drain / source metal is prepared by a rapid thermal annealing process, thereby ensuring the stability of the source 22 and the drain 23.

[0076] The gate 21, the source 22 and the drain 23 in the application can also include corresponding field plates, taking the gate field plate as an example, when the first structure layer 20 is provided above the first region 101 of the functional layer 10, after the gate dielectric layer 201 is provided, the gate metal layer 202 is provided first, one or more layers of field plate dielectric are provided first, the field plate dielectric is etched by a photolithography method to form corresponding multi-stage steps in the gate region, and then the gate metal layer 202 is provided, and the field plate preparation process of the source 22 and the drain 23 is similar, and details are not described here.

[0077] The first dielectric layer 301 in the application completely covers the gate metal layer 202, so as to wrap and passivate the gate metal layer 202. The material of the first dielectric layer 301 is silicon nitride, silicon oxide, high-k dielectric (aluminum oxide aluminum nitride, etc.), which can be provided by chemical vapor deposition (CVD), atomic layer deposition (ALD) and the like. The first dielectric layer 301 serves as a passivation layer of the gate metal layer 202, protects the gate metal layer 202 from other processes, and also serves as a sacrifice layer when etching the second dielectric layer 302, to protect the upper surface of the gate metal layer 202, and also serves as an isolation layer of the upper surface of the gate metal layer 202, to avoid interconnection when the source-drain metal layer is provided later.

[0078] The material of the second dielectric layer 302 can be silicon nitride, silicon oxide, high-k dielectric (aluminum oxide aluminum nitride, etc.), and various dielectric layers can be provided by CVD, ALD and the like. The embodiment controls the thickness of the second dielectric layer 302 on the side wall of the first groove to control the gate-source spacing, and the second dielectric layer 302 also serves as a passivation layer to reduce the risk of device leakage. When the second dielectric is a high-k material, the second dielectric in the second groove can improve the voltage resistance of the drain 23 and reduce the risk of device breakdown, thereby improving the overall performance of the device.

[0079] The semiconductor device structure provided in the embodiment comprises a functional layer 10, a dielectric layer, electrodes and pads, the dielectric layer at least comprises a gate dielectric layer 201, a first dielectric layer 301, a second dielectric layer 302 and a passivation layer 40, the electrodes comprise a gate 21, a source 22 and a drain 23. The functional layer 10 at least comprises a channel layer and a barrier layer, a two-dimensional carrier gas 111 is formed in the channel layer near the barrier layer; the channel layer and the barrier layer are III-V compound. The gate dielectric layer 201 is deposited on the upper surface of the barrier layer, the gate metal layer 202 is deposited on the upper surface of the gate dielectric layer 201, and the first dielectric layer 301 is above the gate metal layer 202; the first recess 31 is formed from the first dielectric layer 301 downwardly and penetrates the gate metal layer 202 and the gate dielectric layer 201 to the functional layer 10, and the sidewall of the first recess 31 is covered with the second dielectric layer 302 with a first preset thickness. The source 22 is formed by the metal provided from the first recess 31; the drain 23 is formed by the metal provided from the second recess 32 of the preset drain region of the functional layer 10, and the source 22 and the drain 22 are respectively electrically connected through the two-dimensional carrier gas 111 in the functional layer 10. The passivation layer 40 is above the electrodes and the first dielectric layer 301, and the plurality of pads 50 are formed on the passivation layer 40, and the plurality of pads 50 are respectively electrically connected with the gate 21, the source 22 and the drain 23 through the dielectric vias to obtain the gate pad, the source pad and the drain pad.

[0080] In the embodiment, the distance between the source 22 and the gate 21 is the thickness of the second dielectric layer 302 of the sidewall of the first recess, which can be obtained in etching according to the design parameters of the device, so that the distance between the source 22 and the gate 21 in the semiconductor device in the embodiment can be controlled by the thickness of the dielectric, so that the required gate-source distance can be made according to the design parameters, and the device yield can be maintained in the manufacturing process, thereby effectively reducing the cost of the device.

[0081] Embodiment two

[0082] Referring to FIG. 11, FIG. 11 is a schematic diagram of the device structure corresponding to each step in the preparation process of the semiconductor device structure according to the second embodiment of the present application. The preparation method in the embodiment comprises the following steps:

[0083] Step S31, providing a semiconductor epitaxial wafer as the functional layer 10.

[0084] Step S32, providing a first structure layer 20 above the first region 101 of the functional layer 10.

[0085] Step S33, providing a first dielectric layer 301 above the first structure layer 20. The first dielectric layer 301 covers the gate metal layer 202 in the first structure layer 20 and extends above the second region 102 which is pre-set as a drain region.

[0086] Step S34, etching down from the first dielectric layer 301 above the gate metal layer 202 in the first region 101 until reaching the functional layer 10 to obtain a first recess 31, and etching down from the first dielectric layer 301 above the second region 102 until reaching the functional layer 10 to obtain a second recess 32.

[0087] Step S35, providing a second dielectric layer 302 above the current structure.

[0088] Step S36, etching the second dielectric layer 302, leaving the second dielectric layer 302 with a first pre-set thickness on the side wall of the first recess 31 and leaving the second dielectric layer 302 with a second pre-set thickness on the side wall of the second recess 32. The first pre-set thickness and the second pre-set thickness can be equal or not equal.

[0089] Step S37, providing a metal in the first recess 31 with the second dielectric layer 302 with the first pre-set thickness on the side wall and in the second recess 32 with the second dielectric layer 302 with the second pre-set thickness on the side wall to obtain a source 22 and a drain 23.

[0090] Step S38, forming a passivation layer 40 and a plurality of pads 50 above the current structure, the plurality of pads 50 being electrically connected with the gate 21, the source 22 and the drain 23 through dielectric vias to obtain a gate pad, a source pad and a drain pad.

[0091] In the present embodiment, the gate metal layer 202 is only provided above the first region 101, and by controlling the distance between the second recess 32 and the gate metal layer 202 in the first region 101, the purpose of controlling the distance between the drain and the gate can be achieved, thereby meeting the requirements of different voltage levels of the device.

[0092] Embodiment Three

[0093] Referring to FIG. 12, FIG. 12 is a schematic diagram of the structure of a semiconductor device according to Embodiment Three of the present application. The gate dielectric layer 201 in the semiconductor device structure in the present embodiment extends from the first region 101 to the second region 102, and the preparation steps are referred to Embodiment Two. When the first structure layer 20 is provided above the first region 101 of the functional layer 10, the gate dielectric layer 201 extends from the first region 101 to the second region 102, and the gate metal layer 202 is only provided above the gate dielectric layer 201 in the first region 101.

[0094] In addition, although the upper surface of the first dielectric layer 301 in the structure shown in FIG. 11 and FIG. 12 is a horizontal plane, it can also not be a horizontal plane, for example, the structure corresponding to step S32 in FIG. 11, after the first structure layer 20 is formed in the first region 101, the upper surface of the device structure forms a stepped shape, and then a layer of the first dielectric layer 301 is deposited above the current stepped device structure. At this time, the first dielectric layer 301 covers the upper surface of the stepped device structure, and the following preparation steps can be continued on the current structure, or the thickness of the deposited first dielectric layer 301 can be increased, and then the structure corresponding to step S33 in FIG. 11 and the structure shown in FIG. 12 can be obtained by a planarization process.

[0095] Embodiment Four

[0096] Referring to FIG. 13, FIG. 13 is a schematic diagram of the device structure corresponding to each step in the preparation process of a semiconductor device structure according to Embodiment Four of the present application. The preparation method in this embodiment includes the following steps:

[0097] Step S41, providing a semiconductor epitaxial wafer as the functional layer 10.

[0098] Step S42, providing the first structure layer 20 above the first region 101 of the functional layer 10.

[0099] Step S43, providing the first dielectric layer 301 above the first structure layer 20, the first dielectric layer 301 extending to the second region 102 which is pre-set as the drain region.

[0100] Step S44, etching the first dielectric layer 301 above the gate metal layer 202 of the first region 101 downward until reaching the functional layer 10 to obtain the first recess 31.

[0101] Step S45, providing the second dielectric layer 302 above the current structure.

[0102] Step S46, etching the second dielectric layer 302, leaving the second dielectric layer 302 with a first pre-set thickness on the sidewall of the first recess.

[0103] Step S47, providing metal in the first recess 31 with the current sidewall of the second dielectric layer 302 remaining a first pre-set thickness to obtain the source 22.

[0104] Step S48, etching the first dielectric layer 301 of the second region 102 downward until reaching the functional layer 10 to obtain the second recess 32.

[0105] Step S49, providing metal in the second recess 32 to obtain the drain 23.

[0106] Step S410, a passivation layer 40 and a plurality of pads 50 are formed above the current structure, the plurality of pads 50 are electrically connected with the gate 21, the source 22 and the drain 23 respectively through the medium via to obtain the gate pad, the source pad and the drain pad.

[0107] In this embodiment, after the gate and source electrodes are completed, the drain electrode 23 is obtained in the same way in the preset drain region. In addition, in step S45, when the second medium layer 302 is provided above the current structure, although in the structure shown in the figure, the second medium layer 302 also covers the first medium layer 301 above the second region 102 as the drain region, it can be known that the second medium layer 302 can also not cover the second region 102 as the drain region.

[0108] Embodiment five

[0109] Referring to FIG. 14, FIG. 14 is a schematic diagram of the device structure corresponding to each step in the process of preparing the semiconductor device structure according to the fifth embodiment of the present application. The preparation method in this embodiment includes the following steps:

[0110] Step S51, a semiconductor epitaxial wafer is provided as the functional layer 10.

[0111] Step S52, a first structure layer 20 is provided above the first region 101 of the functional layer 10. First, a gate medium layer 201 is provided above the functional layer 10, and then a patterned metal layer 200 is provided above, the patterned metal layer 200 at least includes a gate metal layer 202 above the first region 101 and a drain metal layer 203 above the second region 102. In addition, when a P-type material layer is used instead of the gate medium layer 201, the P-type material layer and the metal layer 200 can also be patterned together.

[0112] Step S53, a first medium layer 301 is provided above the first structure layer 20, the first medium layer 301 covers the gate metal layer 202 and the drain metal layer 203 above the second region 102.

[0113] Step S54, the first medium layer 301 above the gate metal layer 202 of the first region 101 is etched down to the lower surface of the gate metal layer 202 to obtain a first recess 31, and the first medium layer 301 above the second region 102 is etched down to the lower surface of the gate metal layer 202 to obtain a second recess 32.

[0114] Step S55, a second medium layer 302 is provided above the current structure.

[0115] Step S56, etching the second dielectric layer 302 to reserve the second dielectric layer 302 with a first preset thickness on the sidewall of the first recess and a second preset thickness on the sidewall of the second recess. The first preset thickness and the second preset thickness can be equal or not equal. In the embodiment, the barrier layer is etched away when etching the second dielectric layer on the bottom of the two recesses.

[0116] Step S57, providing metal in the first recess 31 with the first preset thickness of the second dielectric layer 302 on the sidewall and in the second recess 32 with the second preset thickness of the second dielectric layer 302 on the sidewall to obtain the source 22 and the drain 23, wherein the gate metal layer 202 above the first region 101 serves as the gate 21, the drain metal layer 203 above the second region 102 is electrically connected with the metal provided in the second recess 32 through a dielectric via to serve as the drain 23 together, or is electrically connected with a drain pad.

[0117] Step S58, forming a passivation layer 40 and a plurality of pads 50 above the current structure, the plurality of pads 50 are electrically connected with the gate 21, the source 22 and the drain 23 through dielectric vias to obtain a gate pad, a source pad and a drain pad.

[0118] Due to the gate metal layer 202 and the drain metal layer 203, the first dielectric layer 301 in the embodiment presents a recess between the gate 21 and the drain 23, as the structure corresponding to step S57 in FIG. 14. It can be known that the recess can be filled with passivation dielectric when the passivation layer 40 is provided, as the structure corresponding to step S58 in FIG. 14, or the recess can not be presented by increasing the deposition thickness of the first dielectric layer 301 and then planarizing the surface when the first dielectric layer 301 is provided in step S53, that is, the intermediate region between the gate metal layer 202 and the drain metal layer 203 includes the first dielectric or the passivation dielectric.

[0119] In addition, the bottom of the first recess 31 in each embodiment of the present application can be located at any position between the lower surface of the gate metal layer 202 and the two-dimensional carrier gas 111 in the channel layer. For example, only the gate metal layer 202 in the first structure layer is etched when etching the first recess 31. For another example, part of the thickness of the barrier layer can be etched without affecting the two-dimensional carrier gas 111 when etching the first recess 31. Similarly, the bottom of the second recess 32 in Embodiment One, Embodiment Two, Embodiment Three and Embodiment Five can be located at any position between the lower surface of the gate metal layer 202 and the two-dimensional carrier gas 111 in the channel layer. In addition, the bottom position of the source and drain in the present application can also be deep into the channel layer, such as close to or beyond the two-dimensional carrier gas 111. The specific implementation mode can be, for example, when etching the second medium in the recess, after etching the second medium at the bottom of the recess, the barrier layer in the functional layer and part of the thickness of the channel layer are etched downward.

[0120] As can be seen from the foregoing embodiments, the gate-source structure of the semiconductor device provided by the present application is unique, so that the distance between the gate 21 and the source 22 is determined by the thickness of the medium on the side wall of the recess, which can be controlled during etching, and the manufacturing difficulty is small, and is not affected by the metal morphology of the electrode, so that Rsp can be reduced, the cost can be effectively reduced, and the yield requirement of the device can be met. The medium structure at the drain 23 in the semiconductor device provided by the present application can have various structures, for example, the second recess 32 can include a second medium layer 302, or can not include a second medium layer 302; the drain region from the functional layer 10 can only include the first medium layer 301, or can include the drain metal layer 203 and the first medium layer 301 from bottom to top, or can include the gate medium layer 201, the drain metal layer 203 and the first medium layer 301 from bottom to top. When the drain region includes the drain metal layer 203, the drain metal layer 203 is electrically connected to the metal in the second recess 32 through the medium via, and is at the same potential as the drain 23. In addition, the horizontal spacing region between the drain metal layer 203 and the gate metal layer 202 includes a medium, such as a first medium or a passivation layer medium.

[0121] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Those skilled in the art can make various changes and modifications without departing from the scope of the present application, therefore, all equivalent technical solutions shall belong to the scope disclosed by the present application.

Claims

1. A method for manufacturing a gate-source structure of a semiconductor device, the semiconductor device comprising a functional layer, the functional layer comprising at least a channel layer and a barrier layer, a two-dimensional carrier gas being formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer being a III-V compound; characterized in that, The method comprises: providing a first structure layer above a first region of the functional layer, the first structure layer comprising, from bottom to top, a gate dielectric layer or a P-type material layer and a gate metal layer, at least part of the gate metal layer serving as a gate of the semiconductor device; providing a first dielectric layer above the first structure layer, the first dielectric layer covering at least the gate metal layer; etching from the first dielectric layer above the first region downward to obtain a first recess, a bottom of the first recess being located at any position between a lower surface of the gate metal layer and a two-dimensional carrier gas in the channel layer; providing a second dielectric layer above the current structure and covering at least a sidewall of the first recess; etching the second dielectric in the first recess, leaving a first preset thickness of the second dielectric layer on the sidewall of the first recess; and providing a metal in the first recess with the first preset thickness of the second dielectric layer remaining on the sidewall to obtain a source of the semiconductor device.

2. The method of claim 1, wherein the method further comprises: When etching the second dielectric in the first recess, after etching the second dielectric at the bottom of the first recess, continue to etch downward to part of the barrier layer or the entire barrier layer or part of the channel layer in the functional layer.

3. A method of fabricating a semiconductor device structure, characterized by, Comprise: providing a semiconductor epitaxial wafer as a functional layer, the functional layer comprising at least a channel layer and a barrier layer, a two-dimensional carrier gas being formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer being a III-V compound; forming a gate, a source and a drain on the functional layer, the source and the drain being capable of electrical connection or disconnection through the two-dimensional carrier gas in the functional layer; and forming a passivation layer and a plurality of pads above the current structure, the passivation layer covering the gate, the source and the drain, the plurality of pads being formed above the passivation layer, the plurality of pads being electrically connected to the gate, the source and the drain through a dielectric via to obtain a gate pad, a source pad and a drain pad; wherein the gate and the source are formed according to the method of claim 1 or 2.

4. The method of fabricating a semiconductor device structure of claim 3, wherein, When providing a first dielectric layer above the first structure layer, the first dielectric layer extends to a preset drain region, and correspondingly, when etching to obtain the first recess, etch downward from the first dielectric layer in the preset drain region until reaching the functional layer to obtain a second recess, or after forming the gate and the source, etch downward from the first dielectric layer in the preset drain region until reaching the functional layer to obtain a second recess; provide a metal in the second recess to obtain a drain.

5. The method of fabricating a semiconductor device structure according to claim 4, wherein When obtaining the first recess and the second recess simultaneously, when providing a second dielectric layer above the current structure, provide a second dielectric layer above the first dielectric layer, and the second dielectric layer covers at least the sidewall of the first recess and the sidewall of the second recess; the method further comprises: etching the second dielectric in the second recess, leaving a second preset thickness of the second dielectric layer on the sidewall of the second recess or etching away all the second dielectric in the second recess; providing a metal in the second recess with the second preset thickness of the sidewall remaining to obtain a drain, or providing a metal in the second recess with all the second dielectric etched away to obtain a drain.

6. The method of fabricating a semiconductor device structure of claim 3, wherein, In the method, the first structure layer is provided above the first region of the functional layer, and the first structure layer extends from the first region to the preset drain region; the method further comprises: etching the second recess from the first dielectric layer downward in the preset drain region, and the bottom of the second recess is located at any position between the lower surface of the gate metal layer and the two-dimensional carrier gas in the channel layer; correspondingly, the second dielectric layer is provided above the current structure, and the second dielectric layer covers at least the sidewall of the first recess and the sidewall of the second recess; the method further comprises: etching the second dielectric in the second recess, and retaining the second dielectric layer with a second preset thickness on the sidewall of the second recess; and providing metal in the second recess with the sidewall retaining the second preset thickness to obtain the drain.

7. The method of producing a semiconductor device structure according to claim 3 or 6, wherein In the method of providing the first structure layer, the method comprises: providing a gate dielectric layer or a P-type material layer above the functional layer; providing a patterned metal layer above the gate dielectric layer, or providing a metal layer above the P-type material layer, and patterning the P-type material layer and the metal layer; wherein the patterned metal layer comprises a gate metal layer located in the first region and a drain metal layer located in the preset drain region; correspondingly, in the method of providing the first dielectric layer, the first dielectric layer covers at least the gate metal layer and the drain metal layer.

8. The method of producing a semiconductor device structure according to claim 7, wherein The method further comprises: electrically connecting the drain metal layer and the drain or the drain pad through a dielectric via.

9. A semiconductor device structure, characterized by The method comprises a functional layer, a dielectric layer, an electrode and a pad, the functional layer at least comprises a channel layer and a barrier layer, a two-dimensional carrier gas is formed in a region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V compound; the dielectric layer at least comprises a gate dielectric layer or a P-type material layer, a first dielectric layer, a second dielectric layer and a passivation layer; the electrode comprises a gate, a source and a drain; wherein a first structure layer is above a first region of the functional layer, the first structure layer comprises a gate dielectric layer or a P-type material layer and a gate metal layer from bottom to top, and at least part of the gate metal layer serves as a gate; a first dielectric layer is above the first structure layer; a first recess is formed downward from the first dielectric layer above the first region, the first recess penetrates the gate metal layer in the first structure layer, the bottom of the first recess is located at any position between the lower surface of the gate metal layer and the two-dimensional carrier gas in the channel layer, and the sidewall of the first recess is covered with a second dielectric layer with a first preset thickness; the metal provided in the first recess with the sidewall retaining the second dielectric layer with the first preset thickness forms the source; a second recess is formed in a preset drain region of the functional layer, and the metal provided in the second recess forms the drain; the source and the drain can be electrically connected or disconnected through the two-dimensional carrier gas in the functional layer; the passivation layer is above the electrode and the first dielectric layer, a plurality of pads are formed above the passivation layer, and the plurality of pads are respectively electrically connected with the gate, the source and the drain through dielectric vias to obtain a gate pad, a source pad and a drain pad; The interval between the source and the gate is the thickness of the second dielectric layer of the first recess sidewall, and the interval between the source and the gate is controlled by the thickness of the second dielectric layer of the first recess sidewall.

10. The semiconductor device structure of claim 9, wherein, The preset drain region comprises a first dielectric layer extending from the first region.

11. The semiconductor device structure of claim 10, wherein, The preset drain region comprises a drain metal layer and a first dielectric layer, and the first dielectric layer is located above the drain metal layer; the drain metal layer is electrically connected to the drain or the drain pad through a dielectric via.

12. The semiconductor device structure of claim 11, wherein, The horizontal interval region between the drain metal layer and the gate metal layer comprises a first dielectric or passivation layer dielectric.

13. The semiconductor device structure of claim 9, wherein, The preset drain region comprises a first structure layer and a first dielectric layer extending from the first region, and the first dielectric layer is located above the first structure layer; the inside wall of the second recess is covered with a second dielectric layer of a second preset thickness.

14. A gate-source structure of a semiconductor device, characterized by comprising: Comprise: The functional layer comprises at least a channel layer and a barrier layer, and a two-dimensional carrier gas is formed in the region of the channel layer close to the barrier layer; the channel layer and the barrier layer are III-V compounds; The first structure layer is located above the first region of the functional layer, and the first structure layer comprises a gate dielectric layer or a P-type material layer and a gate metal layer from bottom to top, and at least part of the gate metal layer serves as a gate; The first dielectric layer is located above the first structure layer; Wherein, the first recess penetrating the gate metal layer is formed downward from the first dielectric layer above the first region, the bottom of the first recess is located at any position between the lower surface of the gate metal layer and the two-dimensional carrier gas in the channel layer, the first recess sidewall is covered with a second dielectric layer of a first preset thickness; the metal provided in the first recess with the first preset thickness of the second dielectric layer remaining on the sidewall forms a source; The interval between the source and the gate is the thickness of the second dielectric layer of the first recess sidewall, and the interval between the source and the gate is controlled by the thickness of the second dielectric layer of the first recess sidewall.

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