Novel gate core structure with reduced size

Abstract

Disclosed in the present invention is a novel gate core structure with a reduced size. In the present invention, a gate used for internal regulation is enclosed within a semiconductor, with its structural configuration ranging from single-sided to multi-sided, and can be made in different shapes; and when no metal is contained, reverse doping of a conductive channel can be performed. Such an inner gate structure can be used as a gate alone or in combination with an outer gate structure. The inner gate structure fully utilizes the outer surface of the gate, has a gate control capability different from that of an outer gate, a flexible gate control capability, and a small occupied area, and facilitates the miniaturization of a device. Since inside a semiconductor, the shape restrictions on the inner gate are significantly fewer than those on the outer gate, the outer gate needs to change with the outer surface of the semiconductor, while the inner gate can change arbitrarily without affecting arbitrary changes in the shape of the semiconductor. In this way, both the semiconductor and the gate have shape adjustability, making the design easier. The design of a semiconductor device model under the inner gate can easily change with a regulated current, thereby improving the current control capability.

Description

A new type of gate core structure of next generation with size miniaturization TECHNICAL FIELD

[0001] The application belongs to the technical field of gate core, and particularly relates to a new type of gate core structure of next generation with size miniaturization. BACKGROUND

[0002] The gate structure is a core component in a semiconductor device, and its main function is to control the movement of carriers (electrons or holes) in the semiconductor channel through an electric field, thereby realizing switch control. The performance of the gate structure directly affects the switching speed, power consumption, reliability and the like of the device. The semiconductor device structure is mainly composed of a source electrode, a drain electrode, a gate electrode and a semiconductor channel. The source electrode and the drain electrode are two important electrodes in the semiconductor device, and the semiconductor channel between them undertakes the task of current transmission. In the prior art, the gate electrode is located above or on the side of the semiconductor channel, and the electric field in the channel is adjusted by applying a voltage, thereby controlling the flow of carriers. The outer gate structure, as the name implies, refers to a structure in which the gate electrode is located outside the semiconductor material. It is mainly composed of an insulating layer and a conductive layer. In the outer gate structure, the gate electrode controls the movement of carriers in the semiconductor channel through an electric field, thereby realizing switch control. The advantage of the outer gate structure is that the process is simple and easy to manufacture. However, since the gate electrode is outside the semiconductor channel, it cannot completely regulate the inside of the channel, which limits the switching speed and power consumption performance of the device, and the shape is subject to the shape of the semiconductor. The inner gate structure, that is, a structure in which the gate electrode is located inside the semiconductor material. It is also mainly composed of an insulating layer and a conductive layer. The advantage of the inner gate structure is that the gate electrode exists in the semiconductor channel, and the gate control capability is stronger or more flexible, thereby improving the switching speed and power consumption performance of the device, or providing different levels of functions. However, the existing gate core structure cannot meet the needs of different degrees of conduction and control the degree of conduction. Such an inner gate structure can only be used as a gate electrode alone, and the outer surface of the gate electrode cannot be fully utilized, which occupies a relatively large space in the process of device miniaturization. SUMMARY

[0003] The purpose of the present application is to solve the above-mentioned problems, and to provide a new type of gate core structure of next generation with size miniaturization.

[0004] The technical scheme adopted by the present application is as follows: a new type of gate core structure of next generation with size miniaturization, the gate core structure comprising: a gate insulating layer and a conductor layer (may not contain, and is reversely doped as an insulating layer),

[0005] The gate electrode is located inside the semiconductor and is surrounded by the semiconductor material;

[0006] The insulating layer can be selected as silicon dioxide as an isolation layer, or is reversely doped as a channel;

[0007] The conductor layer may be selected as polycrystalline silicon or other materials that are gate-controlled within the insulating layer, or it may be absent.

[0008] The gate is connected to an external circuit via a wire, or there may be no connection.

[0009] In a preferred embodiment, the gate is located inside the semiconductor and is surrounded by the semiconductor; the gate is spherical in shape, the gate control surface is a single curved surface, the gate material is metal, the insulating layer material is silicon dioxide, and the gate is directly connected to an external circuit.

[0010] In a preferred embodiment, the gate is located inside the semiconductor and is surrounded by the semiconductor; the gate shape is an annular cylindrical surface, the gate control surface is two curved surfaces, the gate material is polycrystalline silicon, the conductive channel is reverse doped, and the insulating layer material is silicon nitride; the gate is connected to an external circuit through a metal wire.

[0011] In a preferred embodiment, the gate is completely surrounded by a semiconductor, the gate is cuboid in shape with a hexagonal gate facet, the gate material is metal, the insulating layer material is silicon dioxide, and the gate is connected to an external circuit via a metal wire.

[0012] In a preferred embodiment, the design method of the gate core structure includes the following steps:

[0013] S1: Determine the location, number, and shape of the gates:

[0014] The gate is located inside the semiconductor and is completely or partially surrounded by semiconductor material;

[0015] The number of gate shapes is designed according to requirements.

[0016] Single-sided gate control: The gate is located inside the semiconductor and is surrounded by a single curved surface;

[0017] Multi-faceted gate control: The gate is located inside the semiconductor and is surrounded by a multi-faceted shape;

[0018] Partially or fully surrounded: The gate is partially or fully surrounded by semiconductors;

[0019] The gate shape is designed in straight bar, ring, spiral, etc., to meet different conductivity requirements and control the degree of conductivity;

[0020] S2: Select gate material:

[0021] The gate material can be a metal (such as tungsten, nickel, etc.) or polysilicon.

[0022] If a non-metallic material is chosen, the conductive channel can be reverse-doped in the insulating layer to achieve conductivity.

[0023] S3: Design the insulation layer:

[0024] The insulating layer material can be selected from silicon dioxide, silicon nitride, etc., and is used to isolate the gate and semiconductor materials.

[0025] The thickness of the insulation layer can be adjusted according to requirements to achieve different gate control capabilities.

[0026] S4: Connection Design:

[0027] The gate connection method can be designed according to requirements, for example:

[0028] Direct connection: The gate is directly connected to the external circuit.

[0029] Indirect connection: Connecting the gate to an external circuit via a metal wire or other connection method.

[0030] S5: Integrated into semiconductor devices:

[0031] The designed internal gate structure is integrated into semiconductor devices, such as MOSFETs and FinFETs.

[0032] The inner gate structure can be used alone or in combination with the outer gate structure to achieve more flexible gate control capabilities.

[0033] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0034] 1. In this invention, the gate is internally controlled, situated within a semiconductor enclosure. It can be single-sided or multi-sided, and can be made in various shapes to meet different conductivity requirements and control conductivity levels. This inner gate can contain metal (or polysilicon, etc.) or not contain metal (or polysilicon, etc.). When it does not contain metal, it can be used for reverse doping of the conductive channel. This type of inner gate structure can be used alone as a gate or in combination with an outer gate structure. This type of inner gate structure fully utilizes the outer surface of the gate, possessing different gate control capabilities, flexible gate control capabilities, and a smaller footprint compared to the outer gate. Applying this structure allows for better miniaturization of semiconductor devices. Because it fully utilizes the outer surface of the gate, the volume occupied is reduced significantly, facilitating device miniaturization. Since it is inside the semiconductor, the shape restrictions are significantly less than for the outer gate. The outer gate needs to follow changes in the semiconductor's outer surface, while the inner gate can change arbitrarily without affecting the shape of the semiconductor. Thus, both the semiconductor and the gate have shape adjustability, making design easier. The semiconductor device model design under the inner gate can more easily follow changes in the controlled current, further improving current control capabilities.

[0035] 2. In this invention, the gate is completely surrounded by semiconductor material, increasing the contact area between the gate and the semiconductor, thereby improving gate control capability and enabling more precise current control. The ring structure facilitates uniform current distribution, further enhancing gate control capability. The insulating layer effectively isolates the gate and semiconductor material, preventing short circuits and ensuring gate control stability; the inner gate structure places the gate inside the semiconductor, fully utilizing the outer surface of the gate, resulting in a smaller gate area compared to the outer gate structure, thus improving current control accuracy. The ring structure can better control current distribution, further improving current control accuracy. The inner gate structure places the gate inside the semiconductor, resulting in a smaller gate area compared to the outer gate structure, thereby achieving device miniaturization. The compact ring structure further reduces device size.

[0036] 3. In this invention, the inner gate structure can be designed in different shapes, such as rings or spirals, to meet different conductivity requirements and control the degree of conductivity. The inner gate structure can be placed in different positions inside the semiconductor to meet different design needs. The inner gate structure can be connected to external circuits through different connection methods, such as metal wire connections or contact connections. The number of gates can also be adjusted according to requirements.

[0037] 4. In this invention, the inner gate structure is compatible with existing semiconductor manufacturing processes without requiring large-scale process modifications. The manufacturing process of the inner gate structure is relatively simple and easy to achieve large-scale production. In summary, the annular fully enclosed inner gate structure of this invention has significant advantages such as high gate control capability, high current control accuracy, miniaturization, design flexibility, ease of manufacturing, and wide application. It is expected to become the mainstream gate structure for future semiconductor devices, driving the performance improvement and miniaturization of semiconductor devices. Attached Figure Description

[0038] Figure 1 is a schematic diagram of the combined use of the inner grid structure and the outer grid of the present invention;

[0039] Figure 2 shows the inner gate used alone in this invention;

[0040] Figure 3 is a schematic diagram of the inner grating structure that undergoes shape transformation in this invention;

[0041] Figure 4 is a schematic diagram of the multi-inner-gate structure in this invention;

[0042] Figure 5 is a schematic diagram of the wiring positions in this invention;

[0043] Figure 6 is a schematic diagram of the manufacturing process of the inner-gate NMOS in this invention.

[0044] Figure 7 is a schematic diagram of the overview technical route of the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0046] Refer to Figure 1-6.

[0047] A novel gate chip structure for miniaturization, comprising: a gate insulating layer and a conductor layer (optional, with the insulating layer reverse-doped).

[0048] The gate is located inside the semiconductor and is surrounded by semiconductor material;

[0049] The insulating layer may be silicon dioxide used as an isolation layer, or it may be reverse-doped for the channel;

[0050] The conductor layer may be selected as polycrystalline silicon or other materials that are gate-controlled within the insulating layer, or it may be absent.

[0051] The gate is connected to an external circuit via a wire, or there may be no connection.

[0052] The gate is located inside the semiconductor and is surrounded by the semiconductor; it is spherical in shape, the gate control surface is a single curved surface, the gate material is metal, the insulating layer material is silicon dioxide, and the gate is directly connected to an external circuit.

[0053] The gate is located inside the semiconductor and is surrounded by semiconductors; the gate shape is a ring-shaped cylinder, the gate control surface is two curved surfaces, the gate material is polycrystalline silicon, and the conductive channel is reverse doped; the insulating layer material is silicon nitride; the gate is connected to the external circuit through a metal wire.

[0054] The gate is completely surrounded by semiconductors, has a cuboid shape, and a six-sided gate control surface. The gate material is metal, the insulating layer material is silicon dioxide, and the gate is connected to an external circuit through a metal wire.

[0055] The design method for the gate core structure includes the following steps:

[0056] S1: Determine the location, number, and shape of the gates:

[0057] The gate is located inside the semiconductor and is completely or partially surrounded by semiconductor material;

[0058] The number of gate shapes is designed according to requirements.

[0059] Single-sided gate control: The gate is located inside the semiconductor and is surrounded by a single curved surface;

[0060] Multi-faceted gate control: The gate is located inside the semiconductor and is surrounded by a multi-faceted shape;

[0061] Partially or fully surrounded: The gate is partially or fully surrounded by semiconductors;

[0062] The gate shape is designed in straight bar, ring, spiral, etc., to meet different conductivity requirements and control the degree of conductivity;

[0063] S2: Select gate material:

[0064] The gate material can be a metal (such as tungsten, nickel, etc.) or polysilicon.

[0065] If a non-metallic material is chosen, the conductive channel can be reverse-doped in the insulating layer to achieve conductivity.

[0066] S3: Design the insulation layer:

[0067] The insulating layer material can be selected from silicon dioxide, silicon nitride, etc., and is used to isolate the gate and semiconductor materials.

[0068] The thickness of the insulation layer can be adjusted according to requirements to achieve different gate control capabilities.

[0069] S4: Connection Design:

[0070] The gate connection method can be designed according to requirements, for example:

[0071] Direct connection: The gate is directly connected to the external circuit.

[0072] Indirect connection: Connecting the gate to an external circuit via a metal wire or other connection method.

[0073] S5: Integrated into semiconductor devices:

[0074] The designed internal gate structure is integrated into semiconductor devices, such as MOSFETs and FinFETs.

[0075] The inner gate structure can be used alone or in combination with the outer gate structure to achieve more flexible gate control capabilities.

[0076] In this invention, the gate is internally controlled, situated within a semiconductor enclosure. This internal gate can be single-sided or multi-sided, and can be configured in various shapes to meet different conductivity requirements and control conductivity levels. This internal gate may contain metal (or polysilicon, etc.) or not; when metal-free, it can be used for reverse doping of the conductive channel. This type of internal gate structure can be used alone as the gate or in combination with an external gate structure. This internal gate structure fully utilizes the outer surface of the gate, possessing different gate control capabilities, flexible gate control, and a smaller footprint compared to the external gate. Applying this structure allows for better miniaturization of semiconductor devices. Because it fully utilizes the outer surface of the gate, the volume occupied is significantly reduced, facilitating device miniaturization. Since it is inside the semiconductor, shape restrictions are significantly less than for the external gate. While the external gate needs to follow changes in the semiconductor's outer surface, the internal gate can change arbitrarily without affecting the semiconductor's shape. Thus, both the semiconductor and the gate have shape adjustability, making design easier. The semiconductor device model design under the internal gate can more easily follow changes in the controlled current, further improving current control capabilities.

[0077] In this invention, the gate is completely surrounded by semiconductor material, increasing the contact area between the gate and the semiconductor, thereby improving gate control capability and enabling more precise current control. The ring structure facilitates uniform current distribution, further enhancing gate control capability. The insulating layer effectively isolates the gate and semiconductor material, preventing short circuits and ensuring gate control stability; the inner gate structure places the gate inside the semiconductor, fully utilizing the outer surface of the gate, resulting in a smaller gate area compared to the outer gate structure, thus improving current control accuracy. The ring structure can better control current distribution, further improving current control accuracy. The inner gate structure places the gate inside the semiconductor, resulting in a smaller gate area compared to the outer gate structure, thereby achieving device miniaturization. The compact ring structure further reduces device size.

[0078] In this invention, the inner gate structure can be designed in different shapes, such as rings or spirals, to meet different conductivity requirements and control the degree of conductivity. The inner gate structure can be placed at different locations inside the semiconductor to meet different design needs. The inner gate structure can be connected to external circuits through different connection methods, such as metal wire connections or contact connections. Furthermore, the number of gates can be adjusted according to requirements.

[0079] In this invention, the inner gate structure is compatible with existing semiconductor manufacturing processes without requiring large-scale process modifications. The manufacturing process of the inner gate structure is relatively simple and easy to achieve mass production. In summary, the annular fully enclosed inner gate structure of this invention has significant advantages such as high gate control capability, high current control accuracy, miniaturization, design flexibility, ease of manufacturing, and wide application. It is expected to become the mainstream gate structure for future semiconductor devices, driving the performance improvement and miniaturization of semiconductor devices.

[0080] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0081] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A new type of gate core structure of the next generation of size reduction, characterized by: The gate core structure includes a gate insulating layer and a conductor layer (may not contain, reverse doping as an insulating layer) The gate is located inside the semiconductor and is surrounded by semiconductor material. The insulating layer can be silicon dioxide used as an isolation layer, or reverse doped as a channel. The conductor layer can be polysilicon or other materials inside the insulating layer for gate control, or not. The gate is connected to the external circuit by a wire, or not.

2. A new type of gate core structure of the next generation of size reduction, according to claim 1, characterized in that: The gate is located inside the semiconductor and is surrounded by semiconductor; the gate shape is spherical, the gate control surface is a single curved surface, the gate material is metal, the insulating layer material is silicon dioxide, and the gate is directly connected to the external circuit.

3. A new type of gate core structure of size-reduced next generation, according to claim 1, characterized in that: The gate is located inside the semiconductor and is surrounded by semiconductor; the gate shape is a ring-shaped cylinder, the gate control surface is two curved surfaces, the gate material is polysilicon, and the conductive channel is reverse doped, and the insulating layer material is silicon nitride. The gate is connected to the external circuit by a metal wire.

4. A new type of gate core structure of size-reduced next generation, according to claim 1, characterized in that: The gate is completely surrounded by semiconductor, the gate shape is a rectangular prism, the gate control surface is six faces, the gate material is metal, the insulating layer material is silicon dioxide, and the gate is connected to the external circuit by a metal wire.

5. A new class of gate core structures with size shrink according to claim 1, characterized in that: The design method of the gate core structure includes the following steps: S1: Determine the gate position, number and shape: The gate is located inside the semiconductor and is completely or partially surrounded by semiconductor material; The number of gate shapes is designed according to requirements, Single-sided gate control: the gate is located inside the semiconductor and is surrounded by a single curved surface; Multi-edge gate control: the gate is located inside the semiconductor and is surrounded by multiple surfaces; Partial or full enclosure: the gate is partially or fully surrounded by semiconductor; The gate shape is designed as a straight line, a ring, a spiral, etc. to meet different conductive requirements and control the degree of conduction; S2: Select gate material: The gate material is selected from metal or polysilicon, etc. If non-metallic materials are selected, conductive channel reverse doping can be performed in the insulating layer to achieve conduction function; S3: Design the insulating layer: The insulating layer material is selected from silicon dioxide, silicon nitride, etc. to isolate the gate and semiconductor material; The thickness of the insulating layer can be adjusted according to requirements to achieve different gate control capabilities; S4: Design the connection method: The gate connection method can be designed according to requirements, including: Direct connection: the gate is directly connected to the external circuit; Indirect connection: the gate is connected to the external circuit through a metal wire or other connection method; S5: Integrated into semiconductor devices: Integrate the designed inner gate structure into semiconductor devices, including MOSFET, FinFET, etc. The inner gate structure can be used alone or combined with the outer gate structure to achieve more flexible gate control capabilities.

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