Plasma supply system and method for detecting instabilities in same

Abstract

The invention relates to a method and a device for detecting instabilities, in particular for arc detection, in a plasma supply system (51) having a power supply (50) for supplying a plasma processing device (13), wherein the power supply (50) is designed to generate an alternating current and / or an alternating voltage at a fundamental frequency (7), which is in particular in a first frequency range of 1 kHz to 1 MHz, wherein the method comprises the following steps: - a provision step (61), in which a measurement input signal (11) is provided, - an analysis step (63), in which the measurement input signal (11) is analysed by means of a multiple suppression filter (10), wherein the multiple suppression filter (10) is tuned i) to a first suppression filter frequency (49) of the fundamental frequency (7) and ii) to a second suppression filter frequency (491) at a first harmonic (8), in particular to a third suppression filter frequency (492) at a second harmonic (9), particularly preferably to further predetermined suppression frequencies at further harmonics of the fundamental frequency (7). This enables discharge monitoring in a plasma process which operates faster and more reliably and is easy to set up.

Description

[0001] Title: Plasma supply system and method for detecting instabilities in this

[0002] Description

[0003] The invention relates to a method for detecting instabilities, in particular for arc detection, in a plasma supply system with a power supply for supplying a plasma processing device, wherein the power supply is configured to generate an alternating current and / or an alternating voltage at a fundamental frequency, which is in particular in a first frequency range of 1 kHz to 1 MHz.

[0004] The coating of substrates, e.g., glass surfaces, by means of cathode sputtering, e.g., the so-called sputtering in plasma processes, both reactive and conventional, is known, for example, from semiconductor manufacturing or architectural glass coating. For this purpose, a plasma is generated with a current or voltage source, which removes material from a target that is deposited onto the substrate, e.g., the semiconductor wafer or the glass sheet. Before deposition, the atoms can bond with gas atoms or molecules in a reactive process, depending on the desired coating.

[0005] Medium-frequency generators (MF generators), typically operating at a frequency of 1 kHz to 1 MHz, are frequently used, particularly in reactive processes. Pulsed generators, especially bipolar pulsed generators, are also common. All these generators are collectively referred to as power supplies with a periodically changing power output signal. The output voltage of this power supply is often applied to two electrodes in a plasma process chamber, which alternately act as cathode and anode, each connected to a target. There are so-called free-running power supplies or power supplies that operate at a controlled frequency. Particularly in reactive processes, these power supplies also experience flashovers, which often extinguish themselves with the next voltage reversal or at least after a few periods, resulting in so-called micro-areas.However, more energetic and longer-lasting arcs, known as arcs (ARES), can also occur. It is important to detect such arcs reliably and quickly. Ares are often detected by checking the output voltage for a voltage dip or the output current for a current increase. Alternatively, an arc can be detected by the difference between the currents to the individual electrodes. A threshold for are detection can be set by the operator. A challenge is that with a periodically changing power output signal from the generator, a fixed value for a voltage dip or current increase cannot be defined, as current and voltage are inherently subject to constant change. Various detection methods have been developed in the past. One method involves determining the RMS value of the current and voltage.Since such an investigation must take place over several periods, this type of detection of an are is usually far too slow and often takes several hundred milliseconds.

[0006] However, when using generators in semiconductor manufacturing processes, particularly in flat-panel display (FPD) production, higher demands are placed on the generators. Here, ares must be detected within a few microseconds or even below one microsecond.

[0007] EP1801946A1 describes a method for arc detection in which time intervals are determined within which an evaluation signal exceeds or falls below reference values. This step is repeated for a subsequent half-wave of the same polarity. An arc is detected if the corresponding time intervals differ by more than a predefined tolerance. This method requires multiple reference values ​​and multiple tolerances for each reference value to reliably detect arcs, which is complex. Even with a very large number of reference values ​​and very well-defined tolerances, this method can lead to falsely detected arcs.DE102013110883B3 describes a method for arc detection in which an arc is detected when a signal waveform differs from a preceding one by at least a predetermined distance, where the distance is determined by combining a minimum time difference and a minimum signal amplitude difference. This method involves considerable setup effort.

[0008] The object of the present invention is to provide a method and a device for monitoring a discharge in a plasma process that works faster and more reliably and is easy to set up.

[0009] This problem is solved by an object having the features of claim 1 and further dependent claims. Advantageous embodiments of the invention are specified in the dependent claims and the description. In one aspect, a method for detecting instabilities, in particular for arc detection, in a plasma supply system is disclosed, comprising a power supply for powering a plasma processing device, wherein the power supply is configured to generate an alternating current and / or an alternating voltage at a fundamental frequency, which is in particular in a first frequency range of 1 kHz to 1 MHz, wherein the method comprises the following steps:

[0010] - a provisioning step in which a measurement input signal is provided,

[0011] - an analysis step in which the measurement input signal is analyzed using a multiple blocking filter, wherein the multiple blocking filter is tuned to i) a first blocking frequency of the fundamental frequency and ii) a further predetermined blocking frequency at a first harmonic, in particular to an additional blocking frequency at a second harmonic, and most preferably to further predetermined blocking frequencies at further harmonics of the fundamental frequency. The fundamental frequency can be a constant, fixed fundamental frequency. Alternatively, the fundamental frequency can be a frequency that varies in a second frequency range, wherein the second frequency range lies within the first frequency range and is smaller than the first frequency range.

[0012] The first frequency range, from 1 kHz to 1 MHz, is also referred to as the medium frequency (MF). From the perspective of plasma applications, it is characterized by the fact that in this frequency range, the ions are accelerated from one electrode to the other, and the frequency of the electric field in the plasma chamber is still low enough that the ions have sufficient time to strike the electrodes and process them.

[0013] The term power supply here refers to the component of the plasma supply system that is required to provide the electrical energy to power the plasma processing device.

[0014] The measurement input signal can be suitable for describing the alternating current, voltage, or power profile of the plasma processing device. The measurement input signal can also be suitable, for example, for describing the impedance or conductance of the plasma processing device. The measurement input signal can also be suitable, for example, for describing the power reflected from the plasma processing device.

[0015] The specific tuning of the multi-band blocking filter to the fundamental frequency and the relevant harmonics contributes to the system's robustness against frequency fluctuations, which improves the reliability of the detection method in variable operating conditions.

[0016] The measurement input signal contains components of the fundamental frequency. These components of the fundamental frequency can account for the majority of the power of the measurement input signal; that is, more than half of the power of the measurement input signal can be located at the fundamental frequency. Further significant components can be found at the harmonics of the fundamental frequency.

[0017] The first harmonic refers to a power output at a frequency twice as high as the fundamental frequency.

[0018] The second harmonic refers to the power at a frequency three times higher than the fundamental frequency. A notch filter, also called a "notch filter," is typically a particularly narrowband type of band-stop filter. In an ideal configuration, its transfer function has only one zero, meaning it attenuates not a broad frequency band, but rather, in this ideal configuration, precisely one frequency as strongly as possible. The special feature of the multi-frequency notch filter presented here is that the notch filter functionality is provided not only at one frequency, but at several frequencies—specifically, at the fundamental frequency and at least one, and in particular several, of its harmonics, all of which are very narrowband.The term "narrowband" here primarily means that the filter's zero points—that is, its frequencies of highest attenuation—occur precisely at the frequency to be blocked. The steepness of the attenuation curve is not so important. A typical narrowband attenuation curve of a multi-band blocking filter is shown in the figures and described below.

[0019] The multi-band cutoff filter can be designed to be fully digital.

[0020] In one aspect, the multi-band blocking filter can be configured as an FIR filter. "FIR filter" stands for "finite impulse response filter," also known as a "filter with a finite impulse response." A characteristic of such an FIR filter is that it generates an impulse response of finite length. This is preferably achieved by not including any information storage and, consequently, using only a limited amount of data at its input to calculate the filter result. As a result, an FIR filter, regardless of the filter parameters, cannot become unstable and therefore cannot be excited into self-oscillation.

[0021] In one aspect, the multi-band notch filter can be designed as an adaptive filter. An adaptive filter in signal processing is a special type of analog or digital filter that can independently change its transfer function and frequency during operation.

[0022] In one aspect, the multi-blocking filter can be designed as an adaptive FIR filter.

[0023] In one aspect, the analysis step comprises the following steps: - a sampling step in which a clocked signal is generated by sampling the measurement input signal with a predetermined sampling frequency, wherein in particular the sampling frequency is preferably at least twice greater than the frequency of the highest first harmonic, second harmonic, or further harmonic filtered by the multiple blocking filter;

[0024] - a first summing input signal generation step in which an initial summing input signal is generated, in particular by changing, preferably by multiplying, the clocked signal (12) by an initial constant filter coefficient (20), wherein the initial constant filter coefficient (20) is preferably equal to 1;

[0025] - a delay step in which a delayed signal is generated by delaying the clocked signal by a predetermined number of clock cycles;

[0026] - a second summing input signal generation step in which a first summing input signal is generated, in particular by changing the delayed signal with a first constant filter coefficient, wherein the first constant filter coefficient is equal to the initial constant filter coefficient multiplied by -1, preferably equal to -1;

[0027] - a first output signal generation step in which an output signal is generated by summing the initial summing input signal and the first summing input signal.

[0028] A “clocked signal” refers to a digitized signal, obtained, for example, from the input signal by sampling with an ADC and providing a sequence of digital data that describes the input signal.

[0029] "-1 times the initial constant filter coefficient" means that the first constant filter coefficient has the opposite sign to the initial constant filter coefficient. For example, if the initial constant filter coefficient is 1, then the first constant filter coefficient is -1. This is preferred, but not the only possibility. For example, if the initial constant filter coefficient is 2, then the first constant filter coefficient is -2.

[0030] In one aspect, a multiplier is used for multiplication. This refers to an electrical circuit that generates the product of two or more signals. A multiplier can be a digital multiplier, also called a "multiplier." This is an electrical circuit that determines the product of two or more digital numbers using the mathematical operation of multiplication. In processors, the multiplier can be part of the arithmetic logic unit (ALU) and appear there as a multiplication accumulator (MAC), but in programmable digital circuits such as FPGAs, it can also be implemented as an independent functional unit. Such a multiplier can be either a fixed-point multiplier, designed to multiply fixed-point numbers, or a floating-point multiplier, designed to multiply floating-point numbers. Fixed-point multipliers are preferably used here.

[0031] In one aspect, multiplying a signal by a factor of 1 can be achieved by simply passing the signal on unchanged. A complex digital multiplier is not required for this, for example.

[0032] In one aspect, multiplying a clocked signal by a factor of -1 can be achieved by shifting one or more bits or by modifying a single bit and then passing the modified clocked signal on. Here too, a complex digital multiplier is not required.

[0033] In one aspect, multiplying a clocked signal by, for example, one of the following factors (2, 4, 8, 16, etc.) can be achieved by shifting one or more bits or modifying a single bit and then passing the modified clocked signal on. Here, too, a complex digital multiplier is not required.

[0034] Other binary operations to simplify digitally complex multiplication are conceivable.

[0035] A multiplier is particularly preferred only when a multiplication needs to be performed that cannot be done using one of these much simpler methods, such as bit shifting, bit addition or bit substitution.

[0036] In one aspect, the delay step is implemented by a first delay element. A delay element can delay a digital signal, for example, by one clock cycle. The duration of a clock cycle is defined by the sampling frequency fs, thus having, for example, the time of one sampling interval as 1 / fs, or the time of several sampling intervals as n / fs, where n is a positive integer. In one aspect, the analysis step comprises the following steps:

[0037] - an additional further delay step in which a second delayed signal is generated, in particular an additional third delayed signal, and especially preferably additional delayed signals are generated, preferably by delaying the delayed signal and at least one second, third, or further delayed signal, each by a predetermined number of clock cycles, in particular by means of a first delay element.

[0038] The delay step is implemented in one aspect by means of an additional second delay element, particularly preferably by means of further additional delay elements.

[0039] All delay elements can be arranged in series, so that each subsequent delay element further delays the signal delayed by the preceding delay element.

[0040] In one aspect, the sum of the delayed clock cycles by all delay elements preferably arranged in series is the period T of the fundamental frequency or less, preferably by a factor of at least 0.8 less.

[0041] In one aspect, the analysis step includes the following step:

[0042] - a further summing input signal generation step in which a second summing input signal is generated, and in particular additionally a third summing input signal, and especially preferably additionally further summing input signals are generated, in particular by changing the second delayed signal with a second constant filter coefficient, preferably by changing the third delayed signal with a third constant filter coefficient, and especially preferably by changing further delayed signals, each with a further constant filter coefficient.

[0043] In one aspect, the analysis step includes the following step:

[0044] - an extended output signal generation step in which an output signal is generated by summing the initial summing input signal, the first summing input signal, the second summing input signal, preferably additionally the third summing input signal, and particularly preferably additionally further summing input signals.

[0045] In one aspect, the method with the device elements is designed such that the summing output signal assumes a predetermined constant value in the steady state and without error detection, which is in particular equal to 0 (zero).

[0046] In one aspect, the second summing input signal generation step, and in particular the subsequent summing input signal generation step, each comprise the following step:

[0047] - a feedback signal generation step, and preferably a further feedback signal generation step in which, preferably in which, a common feedback signal is generated from the output signal by weighting, in particular by multiplying, the summing output signal with a feedback weighting factor.

[0048] The feedback signal is preferably a fraction of the summing output signal. The feedback weighting factor can be, for example, 1 / 512, 1 / 1024, or 1 / 2048. The feedback signal can also preferably be negative. In this case, the feedback weighting factor can be, for example, -1 / 512, -1 / 1024, or -1 / 2048.

[0049] In one aspect, the second summing input signal generation step, and in particular the subsequent summing input signal generation step, each comprise the following step:

[0050] - an update signal generation step and preferably at least one further update signal generation step, in which, and preferably in which, a first filter coefficient update signal is generated by weighting the first delayed signal with the common feedback signal, preferably additionally a second filter coefficient update signal by weighting the second delayed signal with the common feedback signal, particularly preferably additionally a third filter coefficient update signal by weighting the third delayed signal with the common feedback signal, and in particular further filter coefficient update signals are generated by weighting the further delayed signals with the common feedback signal. In this way, the filter coefficient update signals can be weighted with a fraction of the summing output signal.This fraction can be determined by the feedback weighting factor.

[0051] In one aspect, the second summing input signal generation step, and in particular the subsequent summing input signal generation step, each comprise the following step:

[0052] - a first integration step and preferably a further integration step in which, and preferably in which, a first variable filter coefficient is generated by integrating the first filter coefficient update signal, preferably additionally a second variable filter coefficient by integrating the second filter coefficient update signal, particularly preferably additionally a third variable filter coefficient by integrating the third filter coefficient update signal, in particular additionally further variable filter coefficients are generated by integrating the further filter coefficient update signals.

[0053] The integration step(s) are preferably carried out using an integrator.

[0054] "Integration" refers to the summation of the input signal, in this case the first filter coefficient update signal, over time at a fixed clock frequency. The clock frequency is as described above and is also smaller than the period T of the fundamental frequency. In this way, one or more variable filter coefficients can be generated, each of which is incremented with each clock cycle by the value of the filter coefficient update signal currently present at the integrator's input. By generating one or more variable filter coefficients, these variable filter coefficients can be used for the notch filter, either as an alternative or in addition to the constant filter coefficient(s).

[0055] In one aspect, the second summing input signal generation step, and in particular the subsequent summing input signal generation step, each comprise the following step:

[0056] - a first weighting step and preferably a further weighting step in which, and preferably in which, a first summing input signal is generated by weighting, in particular multiplying, the first delayed signal with the first variable filter coefficient, and additionally, in particular, a second summing input signal is generated by weighting, in particular multiplying, the second delayed signal with the second variable filter coefficient, and particularly preferably, additionally, a third summing input signal is generated by weighting, in particular multiplying, the third delayed signal with the third variable filter coefficient, and in particular, several further summing input signals are generated by weighting, in particular multiplying, the further delayed signals with the further variable filter coefficients.

[0057] Summing input signals can thus be generated using the basis of the variable filter coefficients. This allows for the operation of an adaptive filter.

[0058] A multiplier can also be used for multiplication here. Such a multiplier has the same properties as described previously.

[0059] In one aspect, the method includes a detection step in which the summing output signal is analyzed, in particular to detect an instability, preferably an arc, in a plasma processing device.

[0060] The detection step enables continuous monitoring of the summing output signal, allowing for early detection and response to anomalies such as instabilities or ares in a plasma processing device.

[0061] In one aspect, a control unit is provided, comprising a computing unit, set up to carry out the procedural parts of the procedure described above and below.

[0062] The control unit can be: a programmable logic device, an FPGA, a microprocessor, or a digital signal processor. The programmable logic device can, in particular, be programmed non-volatilely with logic that configures it to execute the procedural steps of the procedure described above and below.

[0063] In one aspect, a control unit is provided comprising a program memory, in particular a non-volatile program memory, containing a computer program designed to execute the process components of the method described above and below. The control unit and program memory are preferably semiconductor-based integrated circuits integrated on a printed circuit board (PCB). The control unit and program memory can be designed for additional control tasks related to the power supply. For this purpose, they can be designed to acquire further measured values ​​and generate additional summed output signals.

[0064] In one aspect, a plasma power supply system is disclosed with a power supply described above and below, wherein the power supply is configured to generate an alternating current and / or an alternating voltage at a fundamental frequency, in particular within a frequency range of 1 kHz to 1 MHz. The plasma power supply system comprises:

[0065] - an analog-to-digital converter (ADC) for converting a measurement input signal into a clocked signal and a control unit as described above and below.

[0066] The ability to generate an alternating current or voltage across a wide frequency range allows for precise adaptation to the requirements of various plasma applications, resulting in optimized process control.

[0067] The use of an analog-to-digital converter for signal conversion contributes to improved signal processing by enabling precise digitization of analog measurement input signals, which increases the accuracy of the control.

[0068] The integration of a control unit configured according to the preceding claims can lead to improved synchronization between power supply and process control, which can increase the efficiency and stability of the plasma supply system.

[0069] The present development thus reveals potential solutions to the problem of instability detection, particularly arc detection, in a plasma power supply system with a power supply for a plasma processing device. Specifically, the development offers improvements through an instability detection method based on the analysis of a measurement input signal using a multi-bandstop filter. The multi-bandstop filter is tuned to block the fundamental frequency of the power supply and predetermined harmonics of the fundamental frequency. By using a clocked signal generated at a predetermined sampling frequency and by applying summing and delay steps, various summing input signals are generated, which are ultimately combined into a summing output signal.This method enables precise detection of instabilities, particularly arcs, in the plasma supply system, thus improving the safety and efficiency of the plasma processing equipment. Further aspects of the development are described in more detail below with reference to several exemplary embodiments and diagrams shown in the following figures.

[0070] Figure 1 shows a plasma supply system with a power supply; Figure 2 shows a first embodiment of a multi-band blocking filter; Figure 3 shows a second embodiment of a multi-band blocking filter; Figure 4 shows a third embodiment of a multi-band blocking filter; Figure 5 shows a fourth embodiment of a multi-band blocking filter; Figure 6 shows a blocking filter frequency diagram;

[0071] Figure 7 shows a phase diagram;

[0072] Figure 8 shows a flowchart diagram to illustrate a process flow;

[0073] Figure 9 shows the output signal over time in ps;

[0074] Figure 10 shows the squared output signal over time;

[0075] Figure 11 shows the input signal over time; Figure 12 shows the input signal over time; Figure 13 shows the variable filter coefficients as a function of the sampling rate.

[0076] Figure 1 shows plasma supply system 51 with a power supply 50.

[0077] In detail, the schematic diagram shows a plasma supply system 51 which includes the following components: - A power supply 50 which is responsible for providing an alternating current / alternating voltage.

[0078] - A plasma processing device 13 in which the plasma (PLASMA) is generated.

[0079] - An analog-to-digital converter (ADC) 17 that converts the measurement input signal 11 into a clocked signal 12 with a sampling frequency fs.

[0080] - A control unit 21 comprising the following components:

[0081] - A program memory 23, which contains the computer program necessary for control.

[0082] - A multiple-band notch filter 10, which exhibits attenuation at specific frequencies, such as the fundamental frequency 7 and the harmonics, e.g., the first harmonic 8 and the second harmonic 9. The notch filter frequencies of the multiple-band notch filter 10 are designated 49, 491, 492.

[0083] - A computing unit 25, which is responsible for carrying out the procedural parts of the described procedure. The computing unit is preferably configured to carry out the procedural parts of the procedural steps described here:

[0084] - Provisioning step 61, in which the measurement input signal 11 is provided,

[0085] - Analysis step 63, in which the measurement input signal 11 is analyzed using the multiple blocking filter 10, wherein the multiple blocking filter 10 is tuned to a first blocking filter frequency of the fundamental frequency 7 and to a second blocking filter frequency 491 at a first harmonic 8, in particular to a third blocking filter frequency 492 at a second harmonic 9, and especially preferably to further predetermined blocking frequencies at further harmonics of the fundamental frequency 7.

[0086] - Detection step 64, in which the summing output signal 44 is analyzed, in particular to detect an instability, preferably an arc, in a plasma processing device 13.

[0087] These process steps are described in more detail above and below, particularly in connection with the description of Fig. 8. The computing unit is preferably configured to perform all process components of the process steps described here.

[0088] The plasma supply system 51 further includes the following components:

[0089] - A first measuring arrangement 31 and a second measuring arrangement 33 for recording data from the plasma processing device 13, e.g. by current or voltage or power measurement.

[0090] - An arc treatment circuit 35, which serves to treat instabilities such as arcs. This can preferably also be arranged in the power supply 50.

[0091] The following components can each be arranged individually or in combination within the energy supply 50:

[0092] - first measuring setup 31

[0093] - second measuring setup 33

[0094] - Arc treatment circuit 35

[0095] - Analog-to-digital converter (ADC) 17

[0096] - Control unit 21

[0097] The ADC 17 can be part of the control unit 21 or at least be located in close proximity to the control unit 21.

[0098] The ADC 17 can be part of the first measurement arrangement 31 and / or the second measurement arrangement 33, or at least be arranged in the immediate vicinity of the first measurement arrangement 31 and / or the second measurement arrangement 33. Figure 2 shows a first embodiment of a multiple blocking filter 10.

[0099] The circuit diagram shown illustrates the configuration of a multi-band notch filter 10 for signal analysis, which can be used to detect instabilities such as arcing in a plasma power supply system 51. The input stage contains a measurement input signal 11, which is converted into a clocked signal 12 by the analog-to-digital converter 17 using a clock signal with a sampling frequency fs. This signal is then fed to the first delay element 16, which is responsible for generating a first delayed signal 14. Simultaneously, the clocked signal 12 is processed by the initial multiplier 22 using an initial constant filter coefficient 20 to generate an initial summing input signal 18. Subsequently, the delayed signal 14 is passed through a first filter coefficient multiplier 28, which is connected to a first constant filter coefficient 26, to form a first summing input signal 24.The initial summing input signal 18 and the first summing input signal 24 feed into the summing element (2) 46, which combines them to form a summing output signal 44.

[0100] The following process steps can be carried out with this multiple blocking filter 10: a provisioning step 61 in which a measurement input signal 11 is provided, an analysis step 63 in which the measurement input signal 11 is analyzed using the multiple blocking filter 10, wherein the multiple blocking filter 10 is tuned to i) a first blocking frequency of the fundamental frequency 7 and ii) a further predetermined blocking frequency at a first harmonic 8, in particular to an additional blocking frequency at a second harmonic 9, and especially preferably to further predetermined blocking frequencies at further harmonics of the fundamental frequency.

[0101] Figure 3 shows a second embodiment of a multi-bandstop filter 10. As in Figure 2, the measurement input signal 11 is located in the input section and is converted into a clocked signal 12 by the ADC 17 using a clock signal with a sampling frequency fs. The clocked signal 12 is fed to the first delay element 16, which is responsible for generating a first delayed signal 14. In parallel, the clocked signal 12 is processed by the initial multiplier 22 using an initial constant filter coefficient 20 to generate an initial summing input signal 18. Subsequently, the first delayed signal 14 is passed through a first filter coefficient multiplier 28, which is connected to a first constant filter coefficient 26, to form a first summing input signal 24.

[0102] The first delayed signal 14 is routed to a second delay element 161. The second delay element 161 generates a second delayed signal 141. The second delayed signal 141 is routed to a third delay element 162. The third delay element 162 generates a third delayed signal 142.

[0103] The second delayed signal 141 is passed through a second filter coefficient multiplier 281, which is connected to a second constant filter coefficient 261 to form a second summing input signal 241.

[0104] The third delayed signal 142 is passed through a third filter coefficient multiplier 282, which is connected to a third constant filter coefficient 262 to form a third summing input signal 241. In this way, even more summing input signals can be formed from further delayed signals and further constant filter coefficients.

[0105] The initial summing input signal 18 and the first summing input signal 24, the second summing input signal 241, and the third summing input signal 242 are fed into the summing element 46, which combines them into a summing output signal 44. If further summing input signals are generated, they can be fed to the summing element 46 analogously.

[0106] Figure 4 shows a third embodiment of a multiple blocking filter 10.

[0107] Here too, the measurement input signal 11 is located in the input section. This signal is converted into a clocked signal 12 by the ADC 17 using a clock signal with a sampling frequency fs. In this illustration, the initial multiplier 22 was omitted during the generation of the initial summing input signal 18, using an initial constant filter coefficient 20 instead. As mentioned above, in a preferred embodiment, the initial constant filter coefficient 20 can be equal to 1 (one). In this case, a multiplier can be omitted. This is how it has been presented here and is, in principle, conceivable in all embodiments.

[0108] The embodiment shown in Fig. 4 is a further development of the embodiment shown in Fig. 2. As in Fig. 2, the first delayed signal 14 is passed through a first filter coefficient multiplier 28 to form a first summing input signal 24, which is fed to the buzzer 46. Instead of the first constant filter coefficient 26, the first filter coefficient multiplier 28 is connected to a first variable filter coefficient 36.

[0109] The first variable filter coefficient 36 is generated as follows:

[0110] - first, the summing output signal 44 is subjected to a feedback-

[0111] Multiplier 39 is fed in. The feedback multiplier 39 provides a common feedback signal 32 at its output. This is generated by weighting, in particular multiplying, the summing output signal 44 by a feedback weighting factor 37.

[0112] The first delayed signal 14 is weighted, specifically multiplied, by this common feedback signal 32. For this purpose, the two signals, namely the first delayed signal 14 and the common feedback signal 32, are fed to the first feedback multiplier 34. A first filter coefficient update signal 30 is generated at the output of the first feedback multiplier 34.

[0113] This first filter coefficient update signal 30 is fed to a first integrator 38. The first variable filter coefficient 36 is generated at the output of the first integrator 38.

[0114] In this way, an adaptive multi-blocking filter 10 is implemented.

[0115] The first delay element 16, the first feedback multiplier 34, the first integrator 38, and the first filter coefficient multiplier 28 together form the first summing input generation module 41.

[0116] The first variable filter coefficient 36 is weighted using a feedback component of the summing output signal 44. The resulting filter coefficient update signal 30 is continuously integrated. Thus, with a constant input signal 11, the multi-bandstop filter 10 settles to a constant summing output signal 44, particularly one close to zero. However, as soon as a change in the input signal 11 is applied to the multi-bandstop filter 10, the summing output signal 44 changes away from this constant value. This change can be used to detect instabilities. Figure 5 shows a fourth embodiment of a multi-bandstop filter 10.

[0117] The embodiment shown in Fig. 5 is a further development of the embodiment shown in Fig. 3, which is itself a further development of the embodiment shown in Fig. 4.

[0118] In contrast to the embodiment shown in Fig. 4, two further summing input generation modules are shown here, namely a second summing input generation module 411 and a third summing input generation module 412, which are arranged and connected in series one after the other and following the summing input generation module 41.

[0119] The second delay element 161, the second feedback multiplier 341, the second integrator 381, and the second filter coefficient multiplier 281 together form the second summing input generation module 411.

[0120] The third delay element 162, the third feedback multiplier 342, the third integrator 382, ​​and the third filter coefficient multiplier 282 together form the third summing input generating module 412.

[0121] The summing input generation modules 441 and 442 function analogously to the first summing input generation module 41. Further summing input generation modules are conceivable in this respect.

[0122] This way, instabilities can be detected even better.

[0123] Since the summing input generation modules are purely logically structured digitally, it is possible to identify which of these modules contribute little or nothing to the detection of instabilities typical for the respective process. The corresponding summing input generation modules that contribute little to the detection of instabilities typical for the respective process can be deactivated or used less frequently. This saves computing power. This is important because, for example, multiplications are often a very computationally intensive step.

[0124] Figure 6 shows a typical blocking filter frequency diagram 43 of a multiple blocking filter 10 described here.

[0125] The schematic diagram depicts the attenuation curve 48 of a multi-band notch filter 10. This is shown scaled on the vertical axis of the notch filter attenuation in dB (decibels) and on the horizontal axis of the normalized frequency 45. The attenuation curve 48 shows distinct dips at the points corresponding to the notch frequencies: the first notch filter frequency 49 corresponds to the fundamental frequency 7, the second notch filter frequency 491 to the first harmonic 8, and the third notch filter frequency 492 to another harmonic. The purpose of this multi-band notch filter is to filter out specific frequency ranges from the signal in order to eliminate, for example, interference or unwanted signal components.

[0126] The attenuation curve also exhibits a DC blocking filter frequency of 490 at the normalized frequency 0 (DC).

[0127] Figure 7 shows a phase diagram 53. In this phase diagram 53, the dependence of the phase of a signal on the normalized frequency is illustrated using the phase response of the notch filter 58. The vertical axis 57 shows the range of values ​​of the phase, starting here at 0 degrees and decreasing with negative values. The horizontal axis 55 represents the normalized frequency from 1 to 0.5. The phase response illustrates how the phase of the signal changes with increasing frequency. This response is characteristic of the phase reaction of a multi-band notch filter 10 described here. The observed decrease in phase with increasing frequency indicates the properties of a notch filter in which certain frequencies experience a phase shift.

[0128] Figure 8 shows a flowchart diagram to illustrate the process flow. The block diagram illustrates the process, beginning with the provisioning step 61, in which the measurement input signal 11 is provided. This is followed by the analysis step 63, which analyzes the signal with a multi-band notch filter 10.

[0129] The detection step 64 follows, in which the summing output signal 44 is analyzed to detect an instability, preferably an arc, in a plasma processing device 13. The individual steps are connected by arrows that represent the processing flow.

[0130] Analysis step 63 comprises the following steps: a sampling step 65 in which a clocked signal 12 is generated by sampling the measurement input signal 11 with a predetermined sampling frequency fs, wherein in particular the sampling frequency fs is at least twice greater than the frequency of the highest first harmonic 8, second harmonic 9, or further harmonics filtered by the multiple blocking filter 10; a first summing input signal generation step 66 in which an initial summing input signal 18 is generated, in particular by modifying, preferably by multiplying, the clocked signal 12 by an initial constant filter coefficient 20, wherein the initial constant filter coefficient 20 is preferably equal to 1; a delay step 67 in which a delayed signal 14 is generated by delaying the clocked signal 12 by a predetermined number of clock cycles; a second summing input signal generation step 68,in which a first summing input signal 24 is generated, in particular by modifying the delayed signal 14 with a first constant filter coefficient 26, wherein the first constant filter coefficient 26 is equal to the initial constant filter coefficient 20 multiplied by -1, preferably equal to -1 times the initial constant filter coefficient 20, preferably equal to -1; a first output signal generation step 69, in which an output signal 44 is generated by summing the initial summing input signal 18 and the first summing input signal 24; an additional further delay step 671, in which a second delayed signal 141 is generated, in particular additionally a third delayed signal 142, particularly preferably additionally further delayed signals are generated, preferably by delaying the delayed signal 14 and at least one second, third, or further delayed signal, each by a predetermined number of clock cycles;a further summing input signal generation step 681, in which a second summing input signal 241 is generated, and in particular additionally a third summing input signal 242, and more preferably additionally further summing input signals are generated, in particular by changing the second delayed signal 141 with a second constant filter coefficient 261, more preferably by changing the third delayed signal 142 with a third constant filter coefficient 262, more preferably by changing further delayed signals with each a further constant filter coefficient, an extended output signal generation step 691, in which an output signal 44 is generated by summing the initial summing input signal 18, the first summing input signal 24, the second summing input signal 241, more preferably additionally the third summing input signal 242, more preferably additionally further summing input signals are generated,

[0131] - a feedback signal generation step 68a, and preferably a further feedback signal generation step 681a, in which a common feedback signal 32 is generated from the output signal 44 by weighting, in particular by multiplying, the summing output signal 44 with a feedback weighting factor 37,

[0132] - an update signal generation step 68b and preferably at least one further update signal generation step 681b, in which a first filter coefficient update signal 30 is generated by weighting the first delayed signal 14 with the common feedback signal 32, preferably additionally a second filter coefficient update signal 301 by weighting the second delayed signal 141 with the common feedback signal 32, particularly preferably additionally a third filter coefficient update signal 302 by weighting the third delayed signal 142 with the common feedback signal 32, in particular further filter coefficient update signals are generated by weighting the further delayed signals each with the common feedback signal 32,

[0133] - a first integration step 68c and in particular a further integration step 681c, in which a first variable filter coefficient 36 is generated by integrating the first filter coefficient update signal 30, preferably additionally a second variable filter coefficient 361 by integrating the second filter coefficient update signal 301, particularly preferably additionally a third variable filter coefficient 362 by integrating the third filter coefficient update signal 302, in particular additionally further variable filter coefficients are generated by integrating the further filter coefficient update signals, and - a first weighting step 68d and in particular a further weighting step 681d, in which a first summing input signal 24 is generated by weighting, in particular multiplying, the first delayed signal 14 with the first variable filter coefficient 36,and additionally, in particular, a second summing input signal 241 is generated by weighting, in particular multiplying, the second delayed signal 141 with the second variable filter coefficient 361, and particularly preferably, additionally, a third summing input signal 242 is generated by weighting, in particular multiplying, the third delayed signal 142 with the third variable filter coefficient 362, and in particular, several further summing input signals are generated by weighting, in particular multiplying, the further delayed signals with the further variable filter coefficients.

[0134] The next step is sampling step 65, in which the clocked signal 12 is generated. This is followed by the first summing input signal generation step 66.

[0135] Figure 9 shows a first diagram 70 of the summing output signal 44 over time t c. Here, a time-dependent signal waveform is depicted, where the horizontal axis represents time t in microseconds and the vertical axis represents the summing output signal. This could, for example, be a measured voltage. At the left end of the diagram, the signal waveform begins with large peaks, which characterize the settling-in phase 73. After a certain period of time, the summing output signal 44 stabilizes and enters the steady-state phase 72, which is characterized by a more uniform waveform with smaller peaks. The summing output signal 44 exhibits an almost constant value close to 0 (zero). At the right end of the diagram, larger peaks are observed, indicating the instability detection phase 74.Here, a deviation from the normal signal waveform is detected, which could indicate an instability, such as an electric arc, also called an arc in the plasma domain. The time of instability detection 75 is marked on the horizontal axis at approximately 400 ps. Figure 10 shows a second diagram of the squared summing output signal 44 over time t, also in qs. The time axes of Figures 9 and 10 are identical, and the time profiles correspond to each other. Here, the input signal is plotted squared as a function of time, with the horizontal axis t representing the time profile and the vertical axis 81 representing the intensity or another relevant parameter of the signal. By squaring the summing output signal 44, both positive and negative deflections of the summing output signal 44 are amplified, thus facilitating evaluation.A striking feature is a series of high peaks in the transient phase, labeled 83, which gradually transition into a smoother line with lower amplitude over time, the steady-state phase 82. Towards the end of the time axis, further peaks appear, marked by the instability detection phase 84. These could indicate a recurring event or an instability in the system. Additionally, the time of instability detection 85 is marked on the time axis.

[0136] Figure 11 shows a third diagram 90 of the input signal 11 over time t in ps. The waveform is characterized by many harmonics, as is typical in an unstable system such as a plasma process power supply. The vertical axis 91 of the third diagram 90 represents, for example, the voltage over time as the input signal 11.

[0137] The irregularity at the time of instability detection 95 is hardly detectable by any other method.

[0138] Figure 12 shows a fourth diagram 92 of the input signal 11 over time t in ps; the time axes of Figures 11 and 12 are identical and the time profiles correspond to each other. At the time of instability detection 95, the signal profile of the squared summing output signal 44 shows a peak in the instability detection range 94.

[0139] One possibility for the detection step 64, in which the summing output signal 44 is analyzed, particularly to detect an instability, preferably an arc, in a plasma processing device 13, is shown here with the signal profile of the adaptive detection threshold 96. This signal 96 follows the squared summing output signal 44, amplified in the positive direction, i.e., squared again or multiplied by a factor at approximately the same rate. However, it decays more slowly. Such a profile is known as an "attack and decay profile." If, due to the slower decay, this signal is not yet at 0 (zero) when the next pulse of the squared summing output signal 44 arrives, this signal is activated again. In this way, frequent triggering of the squared summing output signal 44 is amplified and can lead to reliable instability detection when a threshold is exceeded.

[0140] Figure 13 shows a fifth diagram 100 of the variable filter coefficients versus the harmonic numbers. Here, the curve 103 of the variable filter coefficients 36, 361, 362 versus the harmonic numbers is illustrated. The vertical axis 101 represents the values ​​of the variable filter coefficients 36, 361, 362, which range from -1 to 1. The horizontal axis 105 plots the harmonic numbers, which represent the frequencies at which the filter coefficients 36, 361, 362 are applied. The numbers range from 1 to over 24. The variable filter coefficient of the 21st harmonic 104 is particularly noticeable, showing a clear deviation from zero and thus highlighting that an adjustment of the coefficient takes place at this point. The flat part of the curve shows that the filter coefficients for most harmonics are close to zero and therefore do not have a significant influence on the signal.The deviations in certain harmonics indicate that the filters are modified at these points to influence specific frequency components of the signal.

Claims

Patent claims 1. Method for detecting instabilities, in particular for arc detection, in a plasma supply system (51) with a power supply (50) for supplying a plasma processing device (13), wherein the power supply (50) is configured to generate an alternating current and / or an alternating voltage at a fundamental frequency (7), which in particular is in a first frequency range of 1 kHz to 1 MHz, wherein the method comprises the following steps: - a provisioning step (61) in which a measurement input signal (11) is provided, - an analysis step (63) in which the measurement input signal (11) is analyzed by means of a multiple blocking filter (10), wherein the multiple blocking filter (10) is tuned to i) a first blocking filter frequency (49) of the fundamental frequency (7) and ii) to a second blocking filter frequency (491) at a first harmonic (8), in particular to a third blocking filter frequency (492) at a second harmonic (9), particularly preferably to further predetermined blocking frequencies at further harmonics of the fundamental frequency (7).

2. The method of claim 1, wherein the analysis step (63) comprises the following steps: - a sampling step (65) in which a clocked signal (12) is generated by sampling the measurement input signal (11) with a predetermined sampling frequency (fs), wherein in particular the sampling frequency (fs) is at least twice greater than the frequency of the highest first harmonic (8), second harmonic (9), or further harmonics filtered by the multiple blocking filter (10); - a first summing input signal generation step (66) in which an initial summing input signal (18) is generated, in particular by changing, preferably by multiplying, the clocked signal (12) by an initial constant filter coefficient (20), wherein the initial constant filter coefficient (20) preferably equal to 1, - a delay step (67) in which a delayed signal (14) is generated by delaying the clocked signal (12) by a predetermined number of clock cycles; - a second summing input signal generation step (68) in which a first summing input signal (24) is generated, in particular by changing the delayed signal (14) with a first constant filter coefficient (26), wherein the first constant filter coefficient (26) is equal to the initial constant filter coefficient (20) multiplied by -1, preferably equal to -1; - a first output signal generation step (69) in which an output signal (44) is generated by summing the initial summing input signal (18) and the first summing input signal (24).

3. The method of claim 2, wherein the analysis step (63) comprises the following steps: - an additional further delay step (671) in which a second delayed signal (141) is generated, in particular an additional third delayed signal (142), and especially preferably further delayed signals are generated, preferably by delaying the delayed signal (14) and at least one second, third, or further delayed signal, each by a predetermined number of clock cycles, - a further summing input signal generation step (681) in which a second summing input signal (241) is generated, and in particular additionally a third summing input signal (242), and especially preferably additionally further summing input signals are generated, in particular by changing the second delayed signal (141) with a second constant filter coefficient (261), preferably by changing the third delayed signal (142) with a third constant filter coefficient (262), and especially preferably by changing further delayed signals, each with a further constant filter coefficient, - an extended output signal generation step (691) in which an output signal (44) is generated by summing the initial summing input signal (18), of the first summing input signal (24), of the second summing input signal (241), preferably additionally of the third summing input signal (242), particularly preferably additionally of further summing input signals, is generated.

4. Method according to one of claims 2-3, wherein the second summing input signal generation step (68), and in particular the further summing input signal generation step (681), each comprises the following step: - a feedback signal generation step (68a), and preferably a further feedback signal generation step (681a) in which a common feedback signal (32) is generated from the output signal (44) by weighting, in particular by multiplying, the summing output signal (44) with a feedback weighting factor (37).

5. The method of claim 4, wherein the second summing input signal generation step (68), and in particular the further summing input signal generation step (681), each comprises the following step: - an update signal generation step (68b) and preferably at least one further update signal generation step (681b) in which a first filter coefficient update signal (30) is generated by weighting the first delayed signal (14) with the common feedback signal (32), preferably additionally a second filter coefficient update signal (301) by weighting the second delayed signal (141) with the common feedback signal (32), particularly preferably additionally a third filter coefficient update signal (302) by weighting the third delayed signal (142) with the common feedback signal (32), in particular further filter coefficient update signals are generated by weighting the further delayed signals each with the common feedback signal (32).

6. The method of claim 5, wherein the second summing input signal generation step (68), and in particular the further summing input signal generation step (681), each comprises the following step: - a first integration step (68c) and in particular a further integration step (681c) in which a first variable filter coefficient (36) is generated by integrating the first filter coefficient update signal (30), preferably additionally a second variable filter coefficient (361) by integrating the second filter coefficient update signal (301), particularly preferably additionally a third variable filter coefficient (362) by integrating the third filter coefficient update signal (302), in particular additionally further variable filter coefficients are generated by integrating the further filter coefficient update signals.

7. The method of claim 6, wherein the second summing input signal generation step (68), and in particular the further summing input signal generation step (681), each comprises the following step: - a first weighting step (68d) and in particular a further weighting step (681d) in which a first summing input signal (24) is generated by weighting, in particular multiplying, the first delayed signal (14) with the first variable filter coefficient (36), and additionally in particular a second summing input signal (241) by weighting, in particular multiplying, the second delayed signal (141) with the second variable filter coefficient (361), particularly preferably additionally a third summing input signal (242) by weighting, in particular multiplying, the third delayed signal (142) with the third variable filter coefficient (362), in particular several further summing input signals are generated by weighting, in particular multiplying, the further delayed signals with the further variable filter coefficients.

8. Method according to one of the preceding claims, characterized by a detection step (64) in which the summing output signal (44) is analyzed, in particular to detect an instability, preferably an arc, in a plasma processing device (13).

9. Control unit (21) comprising a computing unit (25) configured to carry out the process parts of the process according to one of the preceding claims.

10. Control unit (21), in particular according to claim 9, comprising a program memory (23), in particular a non-volatile program memory, with a computer program stored therein, which is designed to carry out the process parts of the method according to any one of the preceding claims 1 - 9.

11. Plasma supply system (51) with a power supply (50), wherein the power supply (50) is configured to generate an alternating current and / or an alternating voltage at a fundamental frequency (7), in particular within a frequency range of 1 kHz to 1 MHz, wherein the plasma supply system (51) comprises: - an analog-to-digital converter (ADC, 17) for converting a measurement input signal (11) into a clocked signal (12), - a control unit (21) according to one of the preceding claims 9 - 10.

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