Method for manufacturing electronic component, electronic component intermediate, interposer with dummy pattern section, and resin composition for underfill

Abstract

This method for manufacturing an electronic component comprises: a step for forming, on an interposer, a plurality of wiring patterns for bonding with a semiconductor chip; a step for forming a dummy pattern section on the interposer so as to cover the periphery of the wiring patterns in plan view; a step for bonding the semiconductor chip to the wiring patterns via a solder joint; and a step for supplying a resin composition for underfill to a gap between the interposer and the semiconductor chip to form a sealing resin part.

Description

Manufacturing method for electronic component, intermediate product of electronic component, interposer with dummy pattern portion, and resin composition for underfill

[0001] The present disclosure relates to a method for manufacturing an electronic component, an intermediate electronic component, an interposer with a dummy pattern portion, and a resin composition for underfill.

[0002] In recent years, in order to accommodate the ever-increasing density of wiring in electronic devices, flip-chip bonding has come to be used as a mounting method for semiconductor chips that employ a system-in-package. Packages obtained by flip-chip bonding are called flip-chip packages (FC-PKGs). In FC-PKGs, the gap between the semiconductor chip and the substrate is generally sealed with a liquid resin composition known as an underfill material.

[0003] In recent years, there has been an increase in demand for FC-PKGs for mobile applications, and in particular an increase in semiconductor modules that use small flip-chip chip size packages (FC-CSPs).Currently, the FC-CSP PKG size is approximately 20mm x 20mm x 2mm, and further miniaturization is required.

[0004] One of the problems associated with underfill materials for semiconductors that seal the gap between a semiconductor chip and a substrate is bleeding. Bleeding in FC-PKGs is a phenomenon in which the liquid components in the semiconductor encapsulant, which is a liquid resin composition, spread and seep out onto the surface of the solder resist applied to the substrate below the semiconductor chip. Bleeding can contaminate the connection circuits near where the FC-PKG is placed.

[0005] It is desirable to lower the viscosity of underfill materials used in flip chip mounting to increase their fluidity and improve their penetration into gaps, but lowering the viscosity of underfill materials can make them more susceptible to bleeding.

[0006] To prevent bleeding, improvements have been made to underfill materials. For example, Patent Document 1 proposes a liquid encapsulating resin composition comprising (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) a silicone copolymer, wherein component (D) is a copolymer of an alkylpropenoic acid ester and an alkylpropenoic acid polysiloxane ester. Furthermore, Patent Document 2 proposes a liquid encapsulating resin composition comprising (A) a liquid epoxy resin, (B) an aromatic amine, (C) an inorganic filler, (D) a liquid silicone compound having a polyether group, and (E) a liquid silicone compound having an amino group.

[0007] JP 2011-6618 A JP 2012-107149 A

[0008] However, in package manufacturing using CoWoS (Chip on Wafer on Substrate) technology, semiconductor packages are densely mounted on a wafer, so the spacing between the semiconductor packages becomes finer, making it difficult to control bleeding simply by improving the underfill material as in Patent Documents 1 and 2.

[0009] The present disclosure has been made in consideration of the above-mentioned conventional circumstances, and aims to provide a method for manufacturing an electronic component that can suppress contamination due to bleeding in an interposer, an electronic component intermediate and an interposer with a dummy pattern portion that can suppress contamination due to bleeding in an interposer, and an underfill resin composition that can be used in this manufacturing method and that can suppress contamination due to bleeding in an interposer.

[0010] Specific means for achieving the above object are as follows: <1> A method for manufacturing an electronic component, comprising: a step of forming a wiring pattern on an interposer for bonding to a semiconductor chip; a step of forming a dummy pattern on the interposer so as to cover the periphery of the wiring pattern in a plan view; a step of bonding the semiconductor chip to the wiring pattern via a solder joint; and a step of supplying an underfill resin composition into a gap between the interposer and the semiconductor chip to form a sealing resin portion. <2> The method for manufacturing an electronic component according to <1>, in the step of forming the sealing resin portion, an electronic component intermediate including the interposer and the semiconductor chip is placed on a heated stage, the resin composition is supplied into the gap between the interposer and the semiconductor chip, and the supplied resin composition is cured while the electronic component intermediate is heated and pressurized, thereby forming the sealing resin portion. <3> The method for manufacturing an electronic component according to <1> or <2>, in which the step of forming the wiring pattern and the step of forming the dummy pattern are performed simultaneously. <4> The method for manufacturing an electronic component according to any one of <1> to <3>, wherein the height of the dummy pattern is 0.5 to 2 times the height of the wiring pattern. <5> The method for manufacturing an electronic component according to any one of <1> to <4>, wherein, after the step of forming the sealing resin portion, the shortest distance between an end of the dummy pattern and the semiconductor chip in a plan view is 1 mm to 5 mm. <6> The method for manufacturing an electronic component according to any one of <1> to <5>, wherein the wiring pattern has a wiring width of 10 μm to 40 μm and a spacing between adjacent wirings of 10 μm to 40 μm. <7> An electronic component intermediate comprising: an interposer having a wiring pattern for bonding to a semiconductor chip; a dummy pattern portion arranged to cover the periphery of the wiring pattern in a plan view; a semiconductor chip bonded to the wiring pattern via a solder joint; and a sealing resin portion provided in a gap between the interposer and the semiconductor chip. <8> An interposer with a dummy pattern portion, comprising: a wiring pattern for bonding to a semiconductor chip; and a dummy pattern portion arranged so as to cover the periphery of the wiring pattern in a plan view.<9> A resin composition for underfill, which has a viscosity at 110°C of 0.01 Pa·s to 0.2 Pa·s and is used in the method for producing an electronic component according to any one of <1> to <6>.

[0011] According to the present disclosure, there are provided a method for manufacturing an electronic component that can suppress contamination due to bleeding in an interposer, an electronic component intermediate and an interposer with a dummy pattern portion that can suppress contamination due to bleeding in an interposer, and an underfill resin composition that can be used in this manufacturing method and that can suppress contamination due to bleeding in an interposer.

[0012] 1 is a schematic plan view of an intermediate electronic component according to the present disclosure, which includes an interposer, a plurality of semiconductor chips, and a dummy pattern portion, and FIG. 2 is a cross-sectional view taken along line AA in FIG.

[0013] In the present disclosure, a numerical range indicated using "to" means a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively. In the numerical ranges described in stages in the present disclosure, the upper or lower limit of a certain numerical range may be replaced with the upper or lower limit of another numerical range. The upper or lower limit of a numerical range described in the present disclosure may be replaced with a value shown in the Examples. A stepped numerical range may be created by selecting a numerical value from the upper and lower limit numerical values ​​described in stages in the present disclosure. The upper and lower limit numerical values ​​described in the present disclosure may be replaced with a value shown in the Examples. In the present disclosure, each component may contain multiple corresponding substances. When multiple substances corresponding to each component are present in the composition, the content or amount of each component means the total content or amount of the multiple substances present in the composition, unless otherwise specified. In the present disclosure, the particles corresponding to each component may contain multiple types of particles. When multiple types of particles corresponding to each component are present in a composition, the particle size of each component means the value for a mixture of the multiple types of particles present in the composition, unless otherwise specified.

[0014] <Method for manufacturing electronic components> The method for manufacturing electronic components disclosed herein includes the steps of forming a wiring pattern on an interposer for bonding to a semiconductor chip, forming a dummy pattern portion on the interposer so as to cover the periphery of the wiring pattern in a plan view, bonding the wiring pattern to the semiconductor chip via a solder joint, and supplying an underfill resin composition into the gap between the interposer and the semiconductor chip to form a sealing resin portion.

[0015] In the manufacturing process for the electronic component of the present disclosure, after the interposer and the semiconductor chip are flip-chip connected, an underfill resin composition is filled into the gap between the interposer and the semiconductor chip. As a result, the underfill resin composition fills the space in the gap except for the solder joint. The filled resin composition is cured to form an encapsulating resin portion.

[0016] By disposing the dummy pattern portion on the surface of the interposer, even if the underfill resin composition spreads (bleeds) on the interposer surface outside the area where the semiconductor chip is disposed in a plan view, the dummy pattern portion can block the spreading resin composition, thereby making it possible to suppress contamination of the interposer due to bleeding.

[0017] For example, when multiple semiconductor chips are bonded to wiring patterns arranged on an interposer, the interposer may include multiple wiring patterns, and a dummy pattern may be formed to cover the periphery of each wiring pattern on which one semiconductor chip is arranged in a plan view. This allows adjacent semiconductor chips to be separated by dummy patterns in an electronic component intermediate including an interposer and multiple semiconductor chips, thereby preventing contamination due to bleeding between adjacent semiconductor chips. Incidentally, "the interposer includes multiple wiring patterns" means that the interposer includes multiple wiring patterns connected to one semiconductor chip, spaced apart from each other (e.g., spaced apart by 2 mm to 10 mm at the shortest distance between adjacent wiring patterns).

[0018] The manufacturing method of the present disclosure includes a step of forming a wiring pattern on an interposer for bonding to a semiconductor chip, and further includes a step of forming a dummy pattern portion on the interposer so as to surround the wiring pattern in a plan view.

[0019] The method for forming the wiring pattern and the dummy pattern portion is not particularly limited, and examples thereof include electrolytic plating, electroless plating, sputtering, etc. The wiring pattern or the dummy pattern portion may be formed by electrolytic copper plating or electroless copper plating. Examples of materials for the wiring pattern and the dummy pattern portion include copper, silver, gold, chromium, lead, nickel, tin, and zinc.

[0020] The process of forming the wiring pattern and the process of forming the dummy pattern portion may be carried out simultaneously or separately. By carrying out the processes simultaneously, the wiring pattern and the dummy pattern portion can be formed efficiently.

[0021] The dummy pattern portion and the wiring pattern may be made of the same material or different materials. Since the dummy pattern portion and the wiring pattern can be simultaneously formed on the surface of the interposer, the dummy pattern portion and the wiring pattern may be made of the same material.

[0022] Furthermore, when the interposer has a plurality of wiring patterns, dummy pattern portions may be formed so as to separate the wiring patterns arranged at intervals. For example, in a plan view, the dummy pattern portions may be formed in a grid pattern on the interposer, and one wiring pattern may be arranged within one grid of the dummy pattern portions.

[0023] The height of the dummy pattern is preferably 0.5 to 2 times the height of the wiring pattern, more preferably 0.8 to 1.2 times, and even more preferably 0.9 to 1.1 times. The height of the wiring pattern and the height of the dummy pattern refer to the height of the wiring pattern and the height of the dummy pattern when the surface of the interposer is used as the reference.

[0024] The height of the dummy pattern portion may be 2.5 μm to 55 μm, or may be 2.5 μm to 30 μm.

[0025] In the wiring pattern, the wiring width may be 10 μm to 40 μm, and the spacing between adjacent wirings may be 10 μm to 40 μm. The wiring width may be 15 μm to 30 μm, and the spacing between adjacent wirings may be 15 μm to 30 μm.

[0026] The manufacturing method of the present disclosure includes a step of joining a semiconductor chip to a wiring pattern via a solder joint. The semiconductor chip and the interposer may be joined via solder bumps formed on the wiring pattern of the interposer or on the semiconductor chip. After printing a solder paste on the wiring pattern or the semiconductor chip, the solder paste may be reflowed to form the solder bumps.

[0027] The manufacturing method of the present disclosure includes a step of joining an interposer and a semiconductor chip via a solder joint, and then supplying an underfill resin composition into the gap between the interposer and the semiconductor chip to form an encapsulating resin portion. The resin composition is filled into the space in the gap between the interposer and the semiconductor chip excluding the solder joint. The encapsulating resin portion is formed by curing the filled resin composition by heating, pressurizing, or the like.

[0028] For example, in the step of forming the encapsulating resin portion, an electronic component intermediate including an interposer and a semiconductor chip may be placed on a heated stage, and the resin composition may be supplied into the gap between the interposer and the semiconductor chip. Furthermore, the encapsulating resin portion may be formed by curing the resin composition supplied into the gap while heating and pressurizing the electronic component intermediate.

[0029] After the process of forming the sealing resin portion, the shortest distance between the end of the dummy pattern portion and the semiconductor chip in a planar view may be 1 mm to 5 mm, or 1 mm to 3 mm, from the viewpoint of miniaturizing the electronic component and suppressing the spread of bleeding.

[0030] The manufacturing method of the present disclosure may include other processes after the process of forming the encapsulating resin portion. When the electronic component intermediate obtained after the process of forming the encapsulating resin portion is to mount multiple semiconductor chips, examples of such processes include a process of cutting the electronic component intermediate into one or more semiconductor chips, and a process of mounting the cut electronic component intermediate on another member. An electronic component may be manufactured from the electronic component intermediate through other processes. For example, the other processes may include a process of encapsulating the semiconductor chip with a solid or liquid encapsulant, a process of backgrinding at least one of the interposer side and the semiconductor chip side, a process of forming an insulating film such as a polyimide film on the interposer side, a process of plating bumps on the insulating film, a process of singulating the semiconductor chip into one or more semiconductor chips, a process of reflow-mounting the singulated interposer onto a package substrate, and a process of supplying a resin composition between the interposer and the package substrate and then curing and sealing the interposer.

[0031] An interposer is a member interposed between a semiconductor chip and a substrate such as a printed circuit board (PCB) or a package substrate, and may be an organic interposer or an inorganic interposer such as a glass interposer or a silicon interposer. The inorganic interposer may have a TSV (through silicon via), a TGV (through glass via), or the like. The shape of the interposer is not particularly limited, and may be a disk shape or a polygonal plate shape.

[0032] The semiconductor chip may be a graphic processing unit (GPU), a volatile memory such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), a non-volatile memory such as a flash memory, an RF chip, a silicon photonics chip, a micro electro mechanical system (MEMS), a sensor chip, etc. The semiconductor chip may have a through silicon via (TSV). For example, the semiconductor chip may be one in which semiconductor elements are stacked.

[0033] The electronic component manufactured by the manufacturing method of the present disclosure may be a 2.xD (x is an integer) semiconductor package in which multiple semiconductor chips are mounted on a single interposer and housed in a single package. For example, it may be a 2.5D semiconductor package with a silicon interposer, or a 2.1D or 2.3D semiconductor package with an organic interposer.

[0034] The resin composition for underfill may be a conventionally known resin composition, such as a resin composition containing an epoxy resin, a curing agent, and an inorganic filler.

[0035] The epoxy resin may be a liquid epoxy resin or a solid epoxy resin. A solid epoxy resin may be used in combination with a liquid epoxy resin.

[0036] The type of epoxy resin is not particularly limited. Examples of the epoxy resin include naphthalene-type epoxy resins, diglycidyl ether-type epoxy resins such as bisphenol A, bisphenol F, bisphenol AD, bisphenol S, and hydrogenated bisphenol A, epoxidized novolak resins of phenols and aldehydes, such as orthocresol novolak-type epoxy resins, glycidyl ester-type epoxy resins obtained by reacting epichlorohydrin with polybasic acids such as phthalic acid and dimer acid, and glycidylamine-type epoxy resins obtained by reacting epichlorohydrin with amine compounds such as diaminodiphenylmethane and isocyanuric acid.

[0037] Examples of the curing agent include amine-based curing agents, acid anhydride-based curing agents, and phenol-based curing agents, among which amine-based curing agents are preferred.

[0038] Examples of the amine curing agent include amine curing agents having an aromatic ring, and specific examples thereof include diethyltoluenediamine, 1,3,5-triethyl-2,6-diaminobenzene, 3,3'-diethyl-4,4'-diaminodiphenylmethane, and 3,5,3',5'-tetramethyl-4,4'-diaminodiphenylmethane.

[0039] Examples of inorganic fillers include powders of silica such as spherical silica and crystalline silica, calcium carbonate, clay, alumina, silicon nitride, silicon carbide, boron nitride, calcium silicate, potassium titanate, aluminum nitride, beryllia, zirconia, zircon, fosterite, steatite, spinel, mullite, titania, etc., as well as beads obtained by spheronizing these, and glass fibers.

[0040] The underfill resin composition may contain other components in addition to the epoxy resin, curing agent, and inorganic filler, such as a curing accelerator, a flexibilizer, a surfactant, an ion trapping agent, a coupling agent, an antioxidant, an organic solvent, a colorant such as carbon black, a dye, a diluent, a leveling agent, and an antifoaming agent.

[0041] The viscosity of the underfill resin composition is not particularly limited. In particular, from the viewpoint of high fluidity, the viscosity is preferably 0.01 Pa·s to 0.2 Pa·s at 110°C, and more preferably 0.05 Pa·s to 0.15 Pa·s. The viscosity of the resin composition is measured at 110°C using an E-type viscometer (cone angle 3°, rotation speed 10 rpm).

[0042] <Electronic Component Intermediate> The electronic component intermediate of the present disclosure includes an interposer having a wiring pattern for bonding to a semiconductor chip, a dummy pattern portion arranged to cover the periphery of the wiring pattern in a plan view, a semiconductor chip bonded to the wiring pattern via a solder joint, and an encapsulating resin portion provided in the gap between the interposer and the semiconductor chip. For example, the electronic component intermediate of the present disclosure can be obtained by performing each step in the manufacturing method of the present disclosure described above, and finally performing a step of forming the encapsulating resin portion. An electronic component is manufactured by performing the other steps described above on the electronic component intermediate.

[0043] The electronic component intermediate of the present disclosure may include a plurality of semiconductor chips on an interposer, each of which is joined to a wiring pattern arranged at intervals via a solder joint, and each of which may be provided with a sealing resin portion in a gap between the interposer and the semiconductor chip.

[0044] <Interposer with Dummy Pattern> The interposer with dummy pattern of the present disclosure includes a wiring pattern for bonding to a semiconductor chip and a dummy pattern arranged to surround the wiring pattern in a plan view. The interposer with dummy pattern is, for example, a member obtained by performing the steps of forming a wiring pattern and forming a dummy pattern on an interposer, as described in the manufacturing method above. The aforementioned electronic component intermediate is obtained by performing the steps of bonding to a semiconductor chip and forming a sealing resin on this member.

[0045] 1 and 2 show an example of an electronic component intermediate of the present disclosure. Fig. 1 is a schematic plan view of an electronic component intermediate of the present disclosure including an interposer, a plurality of semiconductor chips, and a dummy pattern portion. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1.

[0046] 1 and 2, an electronic component intermediate 10 includes an interposer 1 having a plurality of wiring patterns 3, a plurality of semiconductor chips 5, a sealing resin portion 6, and a dummy pattern portion 4. The sealing resin portion 6 is provided in the gap between the interposer 1 and the semiconductor chip 5.

[0047] The wiring pattern 3 and the semiconductor chip 5 face each other, and the interposer 1 and the semiconductor chip 5 are joined via the wiring pattern 3 and the solder joints 7 .

[0048] The dummy pattern portion 4 is arranged on the interposer 1 so as to cover the periphery of the wiring pattern 3. In Fig. 1, the dummy pattern portion 4 is arranged in a grid pattern, and the wiring pattern 3 is arranged within one grid of the dummy pattern portion 4, and the arranged wiring pattern 3 and the semiconductor chip 5 are joined via solder joints 7.

[0049] The shape of the dummy pattern portion 4 in plan view is not limited to a grid shape, and multiple dummy pattern portions 4 may be arranged so that independent dummy pattern portions 4 surround the periphery of the wiring pattern 3. The shape of the dummy pattern portion surrounding the periphery of the wiring pattern in plan view is not limited to a square shape as shown in Fig. 1, and may be a rectangular shape, a polygonal shape, an ellipse, a circle, or the like.

[0050] By arranging the dummy pattern portion 4 so as to cover the periphery of the wiring pattern 3, the underfill resin composition that wets and spreads can be blocked by the dummy pattern portion 4. For example, as shown in Figure 2, when the resin composition wets and spreads in the region 8 between the dummy pattern portion 4 and the sealing resin portion 6 on the surface of the interposer 1, the resin composition is blocked by the dummy pattern portion 4. This makes it possible to suppress contamination of the interposer due to bleeding.

[0051] All publications, patent applications, and technical standards mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication, patent application, or technical standard was specifically and individually indicated to be incorporated by reference.

[0052] REFERENCE SIGNS LIST 1 interposer 3 wiring pattern 4 dummy pattern portion 5 semiconductor chip 6 sealing resin portion 7 solder joint portion 8 region 10 electronic component intermediate

Claims

1. A method for manufacturing an electronic component, comprising: a step of forming a wiring pattern on an interposer for bonding to a semiconductor chip; a step of forming a dummy pattern portion on the interposer so as to cover the periphery of the wiring pattern in a plan view; a step of bonding the wiring pattern to the semiconductor chip via a solder joint; and a step of supplying an underfill resin composition into the gap between the interposer and the semiconductor chip to form a sealing resin portion.

2. A method for manufacturing an electronic component according to claim 1, wherein in the step of forming the sealing resin portion, an electronic component intermediate comprising the interposer and the semiconductor chip is placed on a heated stage, the resin composition is supplied into the gap between the interposer and the semiconductor chip, and the sealing resin portion is formed by hardening the supplied resin composition while heating and pressurizing the electronic component intermediate.

3. The method for manufacturing an electronic component according to claim 1 or 2, wherein the step of forming the wiring pattern and the step of forming the dummy pattern portion are carried out simultaneously.

4. A method for manufacturing an electronic component according to any one of claims 1 to 3, wherein the height of the dummy pattern portion is 0.5 to 2 times the height of the wiring pattern.

5. A method for manufacturing an electronic component according to any one of claims 1 to 4, wherein after the step of forming the sealing resin portion, the shortest distance between the end of the dummy pattern portion and the semiconductor chip in a planar view is 1 mm to 5 mm.

6. A method for manufacturing an electronic component according to any one of claims 1 to 5, wherein the wiring pattern has a wiring width of 10 μm to 40 μm and a spacing between adjacent wirings of 10 μm to 40 μm.

7. An electronic component intermediate comprising: an interposer having a wiring pattern for bonding to a semiconductor chip; a dummy pattern portion arranged to surround the wiring pattern in a plan view; a semiconductor chip bonded to the wiring pattern via a solder joint; and a sealing resin portion provided in a gap between the interposer and the semiconductor chip.

8. An interposer with a dummy pattern portion, comprising: a wiring pattern for bonding to a semiconductor chip; and a dummy pattern portion arranged so as to surround the wiring pattern in a plan view.

9. A resin composition for underfill, having a viscosity of 0.01 Pa·s to 0.2 Pa·s at 110°C, for use in the method for manufacturing electronic components according to any one of claims 1 to 6.

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