Semiconductor device

Abstract

The present invention provides a semiconductor device in which a transmission distance between a semiconductor chip and a rewiring layer is reduced. A semiconductor device 1 comprises: a rewiring layer 10 including a wiring layer 40 and an insulating layer 50; and a first semiconductor chip 100. The insulating layer 50 is formed of an inorganic material, and a connection layer 110 of the first semiconductor chip 100 and a first pad 24 are directly joined to the insulating layer 50 of the rewiring layer 10 and a first chip pad 121, respectively.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] As disclosed in Patent Document 1, a semiconductor device is known in which a semiconductor chip is connected to a redistribution layer via a substrate in which a through silicon via (TSV) is formed. In the semiconductor device of Patent Document 1, a gap fill layer is formed around the connection portion between the through silicon via and the redistribution layer.

[0003] JP 2024-84140 A

[0004] The above-described conventional semiconductor device has a problem in that the transmission distance between the semiconductor chip and the rewiring layer is long, because the semiconductor chip and the rewiring layer are connected via through silicon vias.

[0005] An object of the present invention is to provide a semiconductor device in which the transmission distance between the semiconductor chip and the rewiring layer is shortened.

[0006] The semiconductor device of the present invention is a semiconductor device comprising a redistribution layer including a wiring layer and an insulating layer, and a first semiconductor chip, wherein the insulating layer is formed of an inorganic material, and the insulating layer and metal electrode of the first semiconductor chip are directly bonded to the insulating layer and metal electrode of the redistribution layer, respectively.

[0007] According to the present invention, it is possible to provide a semiconductor device in which the transmission distance between the semiconductor chip and the rewiring layer is shortened.

[0008] FIG. 1 is a cross-sectional view of a first configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a second configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a third configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 4 is a cross-sectional view of a fourth configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 5 is a cross-sectional view of a fifth configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 6 is a cross-sectional view of a sixth configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 7 is a cross-sectional view of a seventh configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 8 is a cross-sectional view of an eighth configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 9A is a cross-sectional view of components constituting a semiconductor device according to an embodiment of the present invention, illustrating a manufacturing process of the semiconductor device according to an embodiment of the present invention. FIG. 9B is a cross-sectional view of components constituting a semiconductor device according to an embodiment of the present invention, illustrating a manufacturing process of the semiconductor device according to an embodiment of the present invention. FIG. 9C is a cross-sectional view of components constituting a semiconductor device according to an embodiment of the present invention, illustrating a manufacturing process of the semiconductor device according to an embodiment of the present invention. FIG. 9D is a cross-sectional view of components constituting a semiconductor device according to an embodiment of the present invention, illustrating a manufacturing process of the semiconductor device according to an embodiment of the present invention. FIG. 9E is a cross-sectional view of components constituting a semiconductor device according to an embodiment of the present invention, illustrating a manufacturing process of the semiconductor device according to an embodiment of the present invention. FIG. 9F is a cross-sectional view of components constituting a semiconductor device according to an embodiment of the present invention, illustrating a manufacturing process of the semiconductor device according to an embodiment of the present invention. FIG. 9G is a cross-sectional view of components constitu FIG. 9H is a cross-sectional view of components constituting a semiconductor device, illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention.

[0009] (Overview of Semiconductor Device) A semiconductor device 1 according to an embodiment of the present invention will be described with reference to FIG. 1. FIG. 1 is a cross-sectional view of the semiconductor device 1. The semiconductor device 1 shown in FIG. 1 is referred to as a semiconductor device 1 of Configuration Example 1. The semiconductor device 1 of Configuration Example 1 includes a redistribution layer 10, a first semiconductor chip 100, and a covering layer 500. FIG. 1 shows an X direction and a Y direction. The X direction is a direction parallel to the main surface of the redistribution layer 10. The Y direction is a direction perpendicular to the main surface of the redistribution layer 10. The X direction and the Y direction are orthogonal to each other.

[0010] The two main surfaces of the redistribution layer 10 that face each other in the Y direction are called the first main surface 11 and the second main surface 12. The first main surface 11 is the main surface to which the first semiconductor chip 100 is connected. The redistribution layer 10 is a layer that fans out wiring from the first main surface 11 to the second main surface 12.

[0011] The first semiconductor chip 100 is connected to the first main surface 11. The first main surface 11 and the first semiconductor chip 100 are hybrid bonded. Hybrid bonding refers to directly bonding an insulating layer and a metal electrode on one side to an insulating layer and a metal electrode on the other side, respectively. The first semiconductor chip 100 can be, for example, a logic chip such as an LSI.

[0012] An end face of the first semiconductor chip 100 extending along the Y direction is called a first end face 151. Here, the end face includes all four faces extending along the Y direction when the shape of the first semiconductor chip 100 is, for example, a rectangular parallelepiped shape. The covering layer 500 is provided on the first main surface 11 so as to cover the first end face 151. Each of these will be described in order below.

[0013] (Rewiring Layer) The rewiring layer 10 includes an electrode layer, a wiring layer 40, and an insulating layer 50. The electrode layer includes a first electrode layer 21 and a second electrode layer 22.

[0014] The first electrode layer 21 is an electrode layer located on the first main surface 11. The second electrode layer 22 is an electrode layer located on the second main surface 12. The first electrode layer 21 includes a plurality of first pads 24. The second electrode layer 22 includes a plurality of second pads 25. The pad means a metal electrode.

[0015] A plurality of wiring layers 40 and insulating layers 50 are alternately stacked. Wiring 42 is provided in the wiring layer 40. Vias are provided in the insulating layer 50. The vias connect an electrode layer and the wiring layer 40, or connect one wiring layer 40 to another wiring layer 40.

[0016] The first pad 24 and the second pad 25 are connected via a wiring 42 formed in the redistribution layer 10 and a via formed in the insulating layer 50. FIG. 1 illustrates the wiring layer 40 and a portion of the vias. For example, only the first via 31 and the second via 32 are shown. The first via 31 is a via formed in the insulating layer 50 between the first electrode layer 21 and the wiring layer 40. The second via 32 is a via formed in the insulating layer 50 between the wiring layer 40 and the second electrode layer 22.

[0017] The pads, wiring 42, and vias are made of, for example, copper. The insulating layer is made of an inorganic material. Examples of inorganic materials that form the insulating layer include silicon oxides such as silicon dioxide, and silicon nitride.

[0018] The distance in the X direction between adjacent first pads 24 is defined as distance L1. The distance in the X direction between adjacent second pads 25 is defined as distance L2. Distance L2 is longer than distance L1. Furthermore, the density of the first pads 24 on the first main surface 11 is higher than the density of the second pads 25 on the second main surface 12. In this way, in the redistribution layer 10, wiring is fanned out from the first main surface 11 toward the second main surface 12.

[0019] The pad density can be evaluated as follows. The area of ​​a region including all of the first pads 24 formed on one first semiconductor chip 100 of interest is compared with the area of ​​a region including all of the second pads 25 corresponding to the first pads 24. For example, the number of the first pads 24 is the same as the number of the second pads 25. Therefore, a region with a smaller area can be evaluated as having a higher density. The density of the first pads 24 is higher than the density of the second pads 25.

[0020] The distance in the X direction between adjacent first vias 31 is defined as distance L11. The distance in the X direction between adjacent second vias 32 is defined as distance L12. Distance L12 is longer than distance L11. In this way, the distance between adjacent vias tends to increase from the first main surface 11 toward the second main surface 12.

[0021] The tendency for the distance between adjacent vias to increase from the first main surface 11 toward the second main surface 12 can be evaluated as follows: For each first via 31, the distance to the other first via 31 with the shortest distance in the X direction is determined. This distance is called the shortest adjacent distance. The shortest adjacent distances for all first vias 31 are determined and averaged. The averaged distance is called the average shortest adjacent distance. The average shortest adjacent distance is determined in the same manner for the second via 32. By comparing the average shortest adjacent distances, the distance between adjacent vias can be evaluated. The average shortest adjacent distance of the second via 32 is longer than the average shortest adjacent distance of the first via 31. Note that when the redistribution layer 10 has multiple layers (e.g., four or more layers), the distance between adjacent vias may be the same in some vertically overlapping layers.

[0022] Note that no through-holes (TDVs (Through Dielectric Vias)) that linearly penetrate the two main surfaces of the redistribution layer 10, such as TSVs (Through Silicon Vias) or TGVs (Through-Glass Vias), are formed in the redistribution layer 10. That is, the redistribution layer 10 is composed only of the wiring layer 40, the insulating layer 50, blind vias such as the first via 31 and the second via 32, buried vias, and pads such as the first pad 24 and the second pad 25. If the insulating layer is made of an inorganic material, it may be difficult or expensive to form through-holes. In the semiconductor device 1, there is no need to form through-holes. This makes it easier to manufacture the semiconductor device 1.

[0023] Furthermore, although the first semiconductor chip 100 is connected to the first main surface 11 of the redistribution layer 10, no semiconductor chip is connected to the second main surface 12 of the redistribution layer 10. In other words, the second main surface 12 of the redistribution layer 10 does not have a portion for connecting a semiconductor chip (semiconductor chip connection portion). For example, another substrate is connected to the second main surface 12 via the second pads 25 by solder bumps or the like.

[0024] The first main surface 11 and the second main surface 12 of the redistribution layer 10 may both be flat surfaces.

[0025] The thickness of the redistribution layer 10 in the Y direction is indicated by a thickness T1, which may be, for example, 10 μm or more and 20 μm or less.

[0026] (First Semiconductor Chip) The two main surfaces of the first semiconductor chip 100 that face each other in the Y direction are called the first chip main surface 101 and the second chip main surface 102. The first chip main surface 101 is the main surface that is connected to the redistribution layer 10.

[0027] First chip pads 121 are provided on first chip main surface 101 at positions corresponding to first pads 24. The material of first chip pads 121 is the same as that of first pads 24. For example, if first pads 24 are made of copper, first chip pads 121 are also made of copper.

[0028] A connection layer 110 is provided in a portion of the first chip main surface 101 where the first pads 24 are not provided. The connection layer 110 is formed of the same material as the material forming the insulating layer 50 of the redistribution layer 10. The connection layer 110 is an insulating layer. For example, if the insulating layer 50 is formed of silicon dioxide, the connection layer 110 is also formed of silicon dioxide.

[0029] By using the same material for the contacting portions of the first main surface 11 and the first chip main surface 101, hybrid bonding between the rewiring layer 10 and the first semiconductor chip 100 becomes easy.

[0030] (Coating Layer) A coating layer 500 is provided on the first main surface 11 of the redistribution layer 10. The coating layer 500 is provided so as to cover the first main surface 11 of the redistribution layer 10, as well as the first end face 151 of the first chip main surface 101 and the second chip main surface 102. The coating layer 500 is formed, for example, from an insulating inorganic material. An example of an inorganic material for forming the coating layer 500 is silicon oxide. Silicon oxide is preferably used because its linear expansion coefficient is similar to that of silicon, the main material of the chip, making it less likely to generate thermal stress during temperature changes, and its thermal conductivity is higher than that of organic materials, making it advantageous for heat dissipation. The coating layer 500 may be formed from the same material as the insulating layer 50 of the redistribution layer 10.

[0031] The thickness in the Y direction of the semiconductor device 1 other than the redistribution layer 10 is indicated by a thickness T2. The thickness T2 can be set to, for example, 50 μm or more and 750 μm or less.

[0032] In the semiconductor device 1, the first semiconductor chip 100 and the redistribution layer 10 are hybrid-bonded together, so that the transmission distance between the first semiconductor chip 100 and the redistribution layer 10 can be shortened.

[0033] In the semiconductor device 1, the insulating layer 50 of the redistribution layer 10 is made of an inorganic material, particularly silicon oxide. Also, the first end face 151 of the first semiconductor chip 100 and the like are covered with an inorganic material, particularly silicon oxide. Therefore, heat generated from the first semiconductor chip 100 and the like is easily dissipated.

[0034] The semiconductor device 1 according to the embodiment of the present invention can have a variety of different configurations. Other configuration examples of the semiconductor device 1 according to the embodiment of the present invention will be described with reference to Figs. 2 to 8. Figs. 2 to 8 are cross-sectional views of other configuration examples of the semiconductor device 1 according to the embodiment of the present invention. In the following description, differences between each configuration example and the other configuration examples will be mainly described. Items not specifically described can be the same as the other configuration examples.

[0035] (Configuration Example 2) The semiconductor device 1 of Configuration Example 2 will be described with reference to Figure 2. The semiconductor device 1 of Configuration Example 2 differs from the semiconductor device 1 of Configuration Example 1 in that two or more first semiconductor chips 100 are connected to one redistribution layer 10. Of the two first semiconductor chips 100, one first semiconductor chip 100 is referred to as first semiconductor chip A 100A. The other first semiconductor chip 100 is referred to as second semiconductor chip B 100B.

[0036] In configuration example 2, vias and wiring for electrically connecting the first semiconductor chip A 100A and the second semiconductor chip B 100B are formed in the redistribution layer 10. In the example shown in Fig. 2, the first semiconductor chip A 100A and the second semiconductor chip B 100B are electrically connected through vias 33 and wiring 43. The semiconductor chip in configuration example 2 may be a logic semiconductor only, a memory semiconductor only, or a combination of a logic semiconductor and a memory semiconductor.

[0037] (Configuration Example 3) A semiconductor device 1 of Configuration Example 3 will be described with reference to FIG. 3 . Unlike the semiconductor device 1 of Configuration Example 2, the semiconductor device 1 of Configuration Example 3 includes a second semiconductor chip 200. The second semiconductor chip 200 is a semiconductor chip that is hybrid-bonded to the first semiconductor chip 100. The second semiconductor chip 200 can be, for example, a logic or memory chip. Configuration Example 3 includes two second semiconductor chips 200. The second semiconductor chip 200 that is hybrid-bonded to the first semiconductor chip A 100A is referred to as the second semiconductor chip A 200A. The second semiconductor chip 200 that is hybrid-bonded to the first semiconductor chip B 100B is referred to as the second semiconductor chip B 200B. The outer shapes of the first semiconductor chip 100 and the second semiconductor chip 200 may be the same or different.

[0038] The two main surfaces of the second semiconductor chip 200 that face each other in the Y direction are called a third chip main surface 203 and a fourth chip main surface 204. The third chip main surface 203 is the main surface that is connected to the first semiconductor chip 100.

[0039] The second chip main surface 102 and the third chip main surface 203 are provided with a connection layer 110 similar to that on the first chip main surface 101 .

[0040] Chip pads similar to the first chip pads 121 on the first chip main surface 101 are provided on the second chip main surface 102 and the third chip main surface 203. The chip pads provided on the second chip main surface 102 are called second chip pads 122. The chip pads provided on the third chip main surface 203 are called third chip pads 223. The second chip pads 122 and the third chip pads 223 are provided at corresponding positions.

[0041] By making the positions and materials of the pads and the positions and materials of the connection layer 110 the same on the second chip main surface 102 and the third chip main surface 203, hybrid bonding between the first semiconductor chip 100 and the second semiconductor chip 200 is facilitated. Specifically, hybrid bonding between the first semiconductor chip A 100A and the second semiconductor chip A 200A, and hybrid bonding between the first semiconductor chip B 100B and the second semiconductor chip B 200B is facilitated.

[0042] In configuration example 3, covering layer 500 is provided to cover second end face 152 and fourth chip main surface 204 of second semiconductor chip 200 in addition to first end face 151 of first semiconductor chip 100 .

[0043] (Configuration Example 4) A semiconductor device 1 of Configuration Example 4 will be described with reference to FIG. 4 . The semiconductor device 1 of Configuration Example 4 further includes a third semiconductor chip 300 in addition to the semiconductor device 1 of Configuration Example 3. The third semiconductor chip 300 may be, for example, a memory chip. The memory chip may be, for example, a high bandwidth memory (HBM), which is a three-dimensionally stacked memory. Configuration Example 4 includes two third semiconductor chips 300. One third semiconductor chip 300 is referred to as a third semiconductor chip A 300A, and the other third semiconductor chip 300 is referred to as a third semiconductor chip B 300B. The third semiconductor chip 300 is connected to the redistribution layer 10 at a position adjacent to the first semiconductor chip 100. In the example shown in FIG. 4 , the third semiconductor chip A 300A is disposed adjacent to the first semiconductor chip A 100A in the X direction. The third semiconductor chip B 300B is disposed adjacent to the first semiconductor chip B 100B in the X direction.

[0044] The two main surfaces of the third semiconductor chip 300 that face each other in the Y direction are called a fifth chip main surface 305 and a sixth chip main surface 306. The fifth chip main surface 305 is the main surface that is connected to the redistribution layer 10.

[0045] The third semiconductor chip 300 is connected to the redistribution layer 10 via solder bumps 310. The solder bumps 310 are provided on a fifth chip main surface 305 of the third semiconductor chip 300.

[0046] In addition to the first pads 24, bump pads 26 are formed on the first main surface 11 of the redistribution layer 10. The area of ​​the bump pads 26 is larger than the area of ​​the first pads 24. The third semiconductor chip 300 is connected to the redistribution layer 10 at the bump pads 26. The distance in the X direction between adjacent bump pads 26 is defined as distance L3. Distance L3 is larger than distance L1. Distance L3 is larger than distance L1 and smaller than distance L2.

[0047] In configuration example 4, vias and wiring for electrically connecting the third semiconductor chip 300 and the adjacent first semiconductor chip 100 are formed in the redistribution layer 10. In the example shown in Fig. 2, the third semiconductor chip A 300A and the first semiconductor chip A 100A are electrically connected through vias 34 and wiring 44. The third semiconductor chip B 300B and the second semiconductor chip B 100B are also electrically connected in a similar manner.

[0048] In configuration example 4, the covering layer 500 is provided to cover the third end face 153 and the sixth chip main surface 306 of the third semiconductor chip 300, in addition to the first end face 151, the second end face 152, and the fourth chip main surface 204. An underfill material may be provided between the fifth chip main surface 305 of the third semiconductor chip 300 and the first main surface 11. As the underfill material, a resin material or a material in which inorganic particles are dispersed in a resin material can be used.

[0049] (Configuration Example 5 to Configuration Example 8) The semiconductor device 1 of Configuration Example 5 to Configuration Example 8 will be described with reference to FIGS. 5 to 8. In Configuration Example 5 to Configuration Example 8, a second silicon substrate 620 is provided at a position facing the covering layer 500 in the Y direction. Configuration Example 5 has a configuration in which the second silicon substrate 620 is provided in Configuration Example 1. Configuration Example 6 has a configuration in which the second silicon substrate 620 is provided in Configuration Example 2. Configuration Example 7 has a configuration in which the second silicon substrate 620 is provided in Configuration Example 3. Configuration Example 8 has a configuration in which the second silicon substrate 620 is provided in Configuration Example 4.

[0050] The semiconductor device 1 of configuration examples 5 to 8 includes a second silicon substrate 620 in addition to the redistribution layer 10 and the semiconductor chip. This allows for more efficient heat dissipation from the semiconductor chip and the like. Furthermore, the strength of the semiconductor device 1 can be increased. Furthermore, warping of the semiconductor device 1 can be suppressed.

[0051] The second silicon substrate 620 is directly bonded to the second chip main surface 102 of the first semiconductor chip 100 and the covering layer surface 510 of the covering layer 500, for example, by fusion bonding.

[0052] 5 to 8, the thickness of the semiconductor chip or the covering layer 500 is greater than the thickness of the redistribution layer 10, and the thickness of the second silicon substrate 620 is greater than the thickness of the redistribution layer 10. This makes it possible to suppress warping of the semiconductor device 1. For example, the thickness of the covering layer 500 may be five times or more, or even ten times or more, the thickness of the redistribution layer 10. Furthermore, the thickness of the second silicon substrate 620 may be five times or more, or even ten times or more, the thickness of the redistribution layer 10.

[0053] 5 to 8, the covering layer 500 and the main surface of the semiconductor chip are flattened to be flush with each other, and the second silicon substrate 620 is disposed on this flattened surface, thereby improving the heat dissipation of the semiconductor device 1.

[0054] 6 to 8, the covering layer 500 and the main surfaces of the semiconductor chips are flattened to be flush with each other, and the second silicon substrate 620 is disposed on this flattened surface, thereby further improving the heat dissipation of the semiconductor device 1.

[0055] 5 to 7, the semiconductor device 1 has a semiconductor chip and a covering layer 500 disposed between the redistribution layer 10 and the second silicon substrate 620, and no solder is present. By eliminating the use of solder connections, the wiring length can be shortened. Furthermore, since there is no reduction in heat dissipation due to the thermal resistance of the solder, the heat dissipation of the semiconductor device 1 can be improved.

[0056] In addition, in the semiconductor device 1 of configuration example 8 shown in Figure 8, the first semiconductor chip 100 and the second semiconductor chip 200, which are stacked by hybrid bonding, and the third semiconductor chip 300, which is a single semiconductor element, are disposed between the redistribution layer 10 and the second silicon substrate 620. The stacked first semiconductor chip 100 and the second semiconductor chip 200 are hybrid bonded to the redistribution layer, and the stacked semiconductor chips and the single semiconductor element are fusion bonded to the silicon substrate. This enables high-density mounting of semiconductor chips and the like. Furthermore, the wiring length can be shortened and the heat dissipation of the semiconductor device 1 can be improved.

[0057] 5 and 6, the thickness of the semiconductor chip is the same as the thickness of the covering layer 500. In the semiconductor device 1 of Configuration Examples 7 and 8 shown in Figures 7 and 8, the thickness of the semiconductor chips stacked by hybrid bonding, i.e., the total thickness of the first semiconductor chip 100 and the second semiconductor chip 200, is the same as the thickness of the covering layer 500.

[0058] 1 to 8, there is no resin layer such as an underfill layer and no air gap layer between the first semiconductor chip 100 and the redistribution layer 10. In the semiconductor device 1 of configuration examples 5 to 7 shown in Figures 5 to 7, there is no resin layer and no air gap layer between the second silicon substrate 620 and the redistribution layer 10.

[0059] (Manufacturing Method) A method for manufacturing the semiconductor device 1 will be described with reference to Figures 9A to 9H. Figures 9A to 9H are cross-sectional views of components constituting the semiconductor device 1. Figures 9A to 9H show the manufacturing process of the semiconductor device 1 in this order. In the following explanation, the method for manufacturing the semiconductor device 1 will be described using the manufacturing method of the semiconductor device 1 of Configuration Example 6 shown in Figure 6 as an example. Semiconductor devices 1 of other configuration examples can also be manufactured in the same manner as the method described below.

[0060] 9A, a first silicon substrate 610 is prepared. The first silicon substrate 610 is a member that will serve as a substrate when forming each layer of the semiconductor device 1. Note that the substrate when forming each layer of the semiconductor device 1 is not limited to a silicon substrate. For example, the substrate can also be a glass substrate.

[0061] 9B , a release layer 700 is formed on one surface of the first silicon substrate 610. The material of the release layer 700 may be, for example, primarily composed of carbon. As will be described later, after the redistribution layer 10 and semiconductor chips are formed on the first silicon substrate 610, the first silicon substrate 610 is peeled off from the redistribution layer 10. Forming the release layer 700 on the first silicon substrate 610 makes it easier to peel off the first silicon substrate 610 from the redistribution layer 10.

[0062] 9C, the redistribution layer 10 is formed on the surface of the release layer 700. The redistribution layer 10 can be formed by, for example, a back end of line (BEOL) process. As described above, the redistribution layer 10 is a multi-layer wiring layer.

[0063] Next, as shown in FIG. 9D , the first semiconductor chip 100 is bonded to the first main surface 11 of the redistribution layer 10. The redistribution layer 10 and the first semiconductor chip 100 are bonded by hybrid bonding. Therefore, before bonding, a connection layer 110 is formed on the first chip main surface 101 of the first semiconductor chip 100. The connection layer 110 is formed of the same material as the material forming the insulating layer 50 of the redistribution layer 10. Next, the first main surface 11 of the redistribution layer 10 and the first chip main surface 101 of the first semiconductor chip 100 are planarized. This planarization can be performed by, for example, CMP (Chemical Mechanical Polishing). After planarization is complete, the redistribution layer 10 and the first semiconductor chip 100 are bonded by hybrid bonding. In hybrid bonding, first, the surfaces of opposing insulating materials are bonded by partially forming siloxane bonds. Subsequent annealing causes the water near the interface of the insulating material to diffuse, increasing the number of covalent bonds and strengthening the bond. Meanwhile, at the electrode surface, the copper on the electrode surface interdiffuses as the electrode surfaces come into contact, forming a bond.

[0064] 9E , a covering layer 500 is provided on the first main surface 11 side of the redistribution layer 10. The covering layer 500 is provided so as to cover the first end face 151 of the first semiconductor chip 100 and the second chip main surface 102 of the first semiconductor chip 100. The material of the covering layer 500 can be, for example, an insulating inorganic material such as silicon dioxide. The covering layer 500 can be provided by, for example, CVD.

[0065] 9F, coating layer surface 510 of coating layer 500 and, if necessary, second chip main surface 102 of first semiconductor chip 100 are polished. By this polishing, coating layer surface 510 and second chip main surface 102 are flattened to be flush with each other.

[0066] Next, as shown in FIG. 9G , a second silicon substrate 620 is provided on the coating layer surface 510 of the coating layer 500 and the second chip main surface 102 of the first semiconductor chip 100. The bonding between the coating layer surface 510 and the second chip main surface 102 and the second silicon substrate 620 is performed by fusion bonding. Fusion bonding involves directly bonding the chip and the silicon substrate through hydrogen bonding. The second silicon substrate 620 can also be fusion bonded to the coating layer 500.

[0067] Next, as shown in FIG. 9H , the release layer 700 and the first silicon substrate 610 are peeled off from the second main surface 12 of the redistribution layer 10. The first silicon substrate 610 can be peeled off, for example, by a laser. By peeling off the first silicon substrate 610, the second pads 25 are exposed from the second main surface 12 of the redistribution layer 10. This completes the semiconductor device 1. Note that for matters not specifically described, such as solder bonding, the semiconductor device 1 can be manufactured using known techniques.

[0068] In the semiconductor device 1 of this embodiment, the first semiconductor chip 100 is hybrid-bonded to the redistribution layer 10. This shortens the transmission distance, suppresses degradation of high-speed signals, and suppresses increases in power consumption. Furthermore, by not using solder bumps to connect the first semiconductor chip 100 and the redistribution layer 10, it is possible to suppress a decrease in heat dissipation due to the thermal resistance of the solder bumps.

[0069] Furthermore, when a second semiconductor chip 200 is provided in addition to the first semiconductor chip 100, the second semiconductor chip 200 is hybrid-bonded to the first semiconductor chip 100. Therefore, the transmission distance can be shortened for the second semiconductor chip 200 as well, as with the first semiconductor chip 100. As a result, it becomes possible to achieve high-speed transmission, reduce power consumption, and improve heat dissipation.

[0070] Furthermore, no through-silicon vias (TSVs) are formed in the redistribution layer 10. This simplifies the manufacturing process and reduces manufacturing costs. It also reduces the time required for manufacturing and prevents a decrease in manufacturing yield.

[0071] Although the present invention has been described above as an embodiment, it is not limited to the above-described embodiment, and various changes, modifications, and combinations are possible.

[0072] <1> A semiconductor device comprising: a redistribution layer including an electrode layer, a wiring layer, and an insulating layer; and a first semiconductor chip, wherein the insulating layer is formed of an inorganic material; and the insulating layer and metal electrodes of the first semiconductor chip are directly bonded to the insulating layer and metal electrodes of the redistribution layer, respectively.

[0073] <2> The semiconductor device according to <1>, wherein the inorganic material is formed of silicon oxide.

[0074] <3> The semiconductor device according to <1> or <2>, wherein the rewiring layer includes a plurality of the wiring layers and a plurality of the insulating layers.

[0075] <4> The semiconductor device according to any one of <1> to <3>, wherein, when a main surface of the redistribution layer to which the first semiconductor chip is bonded is defined as a first main surface and the other main surface is defined as a second main surface, pads are provided on the first main surface and the second main surface, and a density of the pads on the first main surface is higher than a density of the pads on the second main surface.

[0076] <5> The semiconductor device according to any one of <1> to <4>, including a second semiconductor chip, wherein an insulating layer and a metal electrode of the second semiconductor chip are directly bonded to an insulating layer and a metal electrode of the first semiconductor chip, respectively.

[0077] <6> The semiconductor device according to any one of <1> to <5>, further comprising a third semiconductor chip, the third semiconductor chip being solder-connected to the rewiring layer.

[0078] <7> The semiconductor device according to any one of <1> to <6>, wherein the rewiring layer is provided with a covering layer made of an inorganic material, the covering layer covering at least an end face of the first semiconductor chip.

[0079] <8> The semiconductor device according to any one of <1> to <7>, wherein a silicon substrate is disposed on the side of the first semiconductor chip opposite to the rewiring layer.

[0080] <9> The semiconductor device according to any one of <1> to <8>, comprising: a second semiconductor chip, wherein an insulating layer and a metal electrode of the second semiconductor chip are directly bonded to an insulating layer and a metal electrode of the first semiconductor chip, respectively; a third semiconductor chip, wherein the third semiconductor chip is solder-connected to the redistribution layer; and a silicon substrate, wherein the silicon substrate is bonded to the second semiconductor chip and the third semiconductor chip.

[0081] <10> The semiconductor device according to <9>, wherein the silicon substrate is directly bonded to the second semiconductor chip and the third semiconductor chip.

[0082] <11> A method for manufacturing a semiconductor device comprising: a rewiring layer including a wiring layer and an insulating layer; and a semiconductor chip, the method comprising: a step of forming a release layer on a substrate; a step of forming a rewiring layer on a surface of the release layer; a step of directly bonding the insulating layer and metal electrode on the surface of the rewiring layer to the insulating layer and metal electrode of the semiconductor chip, respectively; and a step of peeling the release layer and the substrate from the rewiring layer.

[0083] <12> The method for manufacturing a semiconductor device described in <11>, comprising: a step of providing a covering layer that covers the semiconductor chip bonded to the rewiring layer, the covering layer being made of an inorganic material; a step of planarizing the covering layer and a main surface of the semiconductor chip so that they are flush with each other; and a step of directly bonding a silicon substrate to the planarized semiconductor chip before the step of peeling off the substrate.

[0084] 1 Semiconductor device 10 Rewiring layer 11 First main surface 12 Second main surface 21 First electrode layer 22 Second electrode layer 24 First pad 25 Second pad 26 Bump pad 31 First via 32 Second via 40 Wiring layer 42 Wiring 50 Insulating layer 100 First semiconductor chip 101 First chip main surface 102 Second chip main surface 110 Connection layer 121 First chip pad 122 Second chip pad 151 First end surface 152 Second end surface 153 Third end surface 200 Second semiconductor chip 203 Third chip main surface 204 Fourth chip main surface 223 Third chip pad 300 Third semiconductor chip 305 Fifth chip main surface 306 Sixth chip main surface 310 Bump 500 Covering layer 510 Covering layer surface 610 First silicon substrate 620 Second silicon substrate 700 Release layer

Claims

1. A semiconductor device comprising: a redistribution layer including a wiring layer and an insulating layer; and a first semiconductor chip, wherein the insulating layer is formed of an inorganic material; and the insulating layer and metal electrodes of the first semiconductor chip are directly bonded to the insulating layer and metal electrodes of the redistribution layer, respectively.

2. The semiconductor device according to claim 1, wherein the inorganic material is formed of silicon oxide.

3. The semiconductor device according to claim 1, wherein the rewiring layer includes a plurality of the wiring layers and a plurality of the insulating layers.

4. The semiconductor device according to claim 1 or 2, wherein, when the main surface of the redistribution layer to which the first semiconductor chip is bonded is defined as a first main surface and the other main surface is defined as a second main surface, pads are provided on each of the first main surface and the second main surface, and the density of the pads on the first main surface is higher than the density of the pads on the second main surface.

5. The semiconductor device according to claim 1 or 2, further comprising a second semiconductor chip, wherein an insulating layer and a metal electrode of said second semiconductor chip are directly bonded to an insulating layer and a metal electrode of said first semiconductor chip, respectively.

6. The semiconductor device according to claim 1 or 2, further comprising a third semiconductor chip, said third semiconductor chip being solder-connected to said rewiring layer.

7. The semiconductor device according to claim 1 or 2, wherein a coating layer made of an inorganic material is formed on the rewiring layer, covering at least the end face of the first semiconductor chip.

8. The semiconductor device according to claim 1 or 2, wherein a silicon substrate is disposed on the side of said first semiconductor chip opposite said rewiring layer.

9. The semiconductor device according to claim 1 or 2, comprising: a second semiconductor chip, wherein an insulating layer and a metal electrode of said second semiconductor chip are directly bonded to an insulating layer and a metal electrode of said first semiconductor chip, respectively; a third semiconductor chip, wherein said third semiconductor chip is solder-connected to said rewiring layer; and a silicon substrate, wherein said silicon substrate is bonded to said second semiconductor chip and said third semiconductor chip.

10. The semiconductor device according to claim 9, wherein the silicon substrate is directly bonded to the second semiconductor chip and the third semiconductor chip.

11. The semiconductor device according to claim 4, wherein the pads on the first main surface and the pads on the second main surface are connected via wiring provided in the wiring layer, and the wiring has a portion extending in a direction parallel to the first main surface.

12. A method for manufacturing a semiconductor device comprising a redistribution layer including a wiring layer and an insulating layer, and a semiconductor chip, the method comprising the steps of: forming a release layer on a substrate; forming a redistribution layer on the surface of the release layer; directly bonding the insulating layer and metal electrode on the surface of the redistribution layer to the insulating layer and metal electrode of the semiconductor chip, respectively; and peeling the release layer and the substrate from the redistribution layer.

13. A method for manufacturing a semiconductor device according to claim 12, comprising: a step of providing a covering layer that covers the semiconductor chip bonded to the rewiring layer, the covering layer being made of an inorganic material; a step of planarizing the covering layer and a main surface of the semiconductor chip so that they are flush with each other; and a step of directly bonding a silicon substrate to the planarized semiconductor chip before the step of peeling off the substrate.

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