Communication chip

Abstract

Provided is a communication chip comprising a control circuit, a transmission circuit, and a transmission coil. The control circuit transmits a transmission signal and a transmittable signal to the transmission circuit. The control circuit uses the transmittable signal to control whether the transmission circuit transmits or does not transmit the transmission signal to the transmission coil, and carries out communication on the basis of the transmission signal by inductive coupling generated between the transmission coil and a reception coil in another chip. The transmission circuit may carry out the control causing the transmission circuit not to transmit the transmission signal to the transmission coil by using the transmittable signal to set the transmission circuit to a high impedance.

Description

Communication Chip

[0001] The present invention relates to communication chips.

[0002] Patent Documents 1 and 2 describe a communication circuit and a communication method using electromagnetic field coupling. [Prior art documents] [Patent documents] [Patent document 1] Japanese Patent No. 7320861 [Patent document 2] Japanese Patent No. 7248249 General disclosure

[0003] In a first aspect of the present invention, a communications chip is provided, comprising a control circuit, a transmitting circuit, and a transmitting coil, wherein the control circuit transmits a transmitting signal and a transmit enable signal to the transmitting circuit, and the control circuit uses the transmit enable signal to control whether or not the transmitting circuit transmits the transmitting signal to the transmitting coil, and communication is performed by inductive coupling occurring between the transmitting coil and a receiving coil in another chip based on the transmitting signal.

[0004] The transmittable signal may cause the transmit circuit to have high impedance, thereby controlling the transmit circuit not to transmit a transmit signal to the transmit coil.The transmittable signal may cause the transmit circuit to have high impedance, thereby controlling the current flowing from the transmit circuit to the transmit coil when the control circuit is not transmitting a transmit signal to the transmit circuit.

[0005] The chip may further include a receiver circuit and a receiver coil, wherein the receiver coil generates an induced voltage due to inductive coupling between the receiver coil and a transmitter coil in another chip, and the control circuit transmits a transmit enable signal to the receiver circuit, which converts the induced voltage generated in the receiver coil into a received signal, and the control circuit uses the transmit enable signal to control whether the receiver circuit transmits the received signal to the control circuit.The chip may further include a logic gate disposed between the receiver circuit and the control circuit, and controls whether the receiver circuit transmits the received signal to the control circuit based on the transmit enable signal input to the logic gate.The receiver circuit may have a comparator that compares the voltage generated in the receiver coil with a threshold, and the control circuit may use the transmit enable signal to control the output of the comparator.

[0006] The device may further include a logic gate arranged between the control circuit and the transmitting circuit, to which a transmittable signal and an external signal for a test mode are input, and the logic gate may alternatively input the transmittable signal from the control circuit or the signal for the test mode to the transmitting circuit.

[0007] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0008] 1 is a plan view of a communications chip 10 according to an example of the present embodiment; FIG. 2 is a side cross-sectional view of the communications chip 10; FIG. 3 is a block diagram of the SoC unit 20; FIG. 4 is a schematic diagram showing clock signal distribution; FIG. 5 is a schematic diagram showing the connection relationship between the HSS setting register 224, the HSS input / output interface 230, etc.; FIG. 6 is a diagram for explaining the operation of signal transmission and reception in HSS in test mode; FIG. 7 is a block diagram of the transmission / reception circuit unit 70; FIG. 8 is an enlarged view of region A in FIG. 1; FIG. 9 is a schematic diagram showing two communications chips arranged horizontally; FIG. 10 is a schematic diagram showing two communications chips arranged vertically; FIG. 11 shows a state in which the two communications chips are tilted at an angle Da relative to each other; FIG. 12 is a schematic diagram showing a master chip 10M and a slave chip 10S communicating with each other; FIG. 13 is a schematic diagram showing an example of the format of an HSS signal transmitted from the master chip 10M; FIG. 14 is a schematic diagram showing an HSS signal using K code as an example; FIG. 15 is a diagram showing the operation (S10) when writing data from the master chip 10M to the slave chip 10S. The operation (S20) when the master chip 10M reads data from the slave chip 10S is shown.

[0009] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0010] Fig. 1 is a plan view of a communication chip 10 according to an embodiment of the present invention, and Fig. 2 is a side cross-sectional view of the communication chip 10. The communication chip 10 communicates with other communication chips via near-field magnetic coupling. The communication chip 10 is, for example, several hundred micrometers to several tens of millimeters square.

[0011] The communications chip 10 has a SoC (System on Chip) section 20, a transmitting / receiving circuit section 70, a transmitting coil 50, a receiving coil 60, and a pad section 80, which are formed on a multi-layer silicon die 12. The periphery of the multi-layer silicon die 12 is covered with a seal ring 82. The multi-layer silicon die 12 is housed in a package 86, and solder balls 88 are arranged on one surface of the package 86 (the bottom surface in FIG. 2 ).

[0012] The multi-layer silicon die 12 has a multi-layer structure, e.g., six layers, numbered from top to bottom as the first layer, the second layer, etc. As an example, the transmitter coil 50 is disposed on the fifth layer, and the receiver coil 60 is disposed on the third layer. The SoC unit 20, the transmitter / receiver circuit unit 70, and the pads are mainly provided on the sixth layer. Additionally, the SoC unit 20 is disposed on a layer below the transmitter coil 50 and the receiver coil 60 (i.e., a layer closer to the solder balls 88). The first, second, and fourth layers are wiring layers such as jumper wiring. The multi-layer silicon die 12 has alternating wiring layers including the transmitter coil 50 and the receiver coil 60 and insulating layers made of insulating films, and all of the wiring layers including the transmitter coil 50 and the receiver coil 60 are covered with insulating films.

[0013] The above configuration allows the SoC unit 20 and other components to be placed in a location that does not block communication between the transmitter coil 50 and receiver coil 60. The SoC unit 20 is primarily placed on a different layer from the transmitter coil 50 and receiver coil 60, making manufacturing easier. Furthermore, the SoC unit 20 can be formed regardless of the sizes of the transmitter coil 50 and receiver coil 60.

[0014] The pads 80 are metal terminals for supplying power to the circuits on the multi-layer silicon die 12 and for inputting and outputting signals to and from the outside. The solder balls 88 are used as contact points between the communications chip 10 and an external substrate. As an example, 49 solder balls 88 are evenly spaced, seven vertically and seven horizontally, at 0.5 mm intervals on the bottom surface of the package 86. Note that, in addition to the method of using the solder balls 88 shown in FIG. 2, other methods such as using solder paste can also be used to contact the communications chip 10 with an external substrate.

[0015] The solder balls 88 are located on the sixth layer side where the pad section 80 is arranged. This stacked structure is an example and does not have to be exactly like this. A package substrate 84 is provided between the sixth layer and the solder balls 88, and wiring between the terminals of the pad section 80 on the sixth layer and the solder balls 88 is formed in the rewiring layer of the package substrate 84. The bottom end of the sixth layer where the SoC section 20 is arranged is closer to the solder balls 88 than the transmitter coil 50 and receiver coil 60. This allows the wiring between the terminals of the pad section 80 on the sixth layer and the solder balls 88 to be shorter.

[0016] 1 , the SoC unit 20, the transmission / reception circuit unit 70, and the pad unit 80 are arranged inside the transmission coil 50 and the reception coil 60. Furthermore, the transmission / reception circuit unit 70, the transmission coil 50, and the reception coil 60 are arranged outside the outermost periphery of the power line 22.

[0017] The seal ring 82 is a metal wire that prevents moisture from entering the element formation region of the multi-layer silicon die 12. The seal ring 82 is provided around the outer edge of the multi-layer silicon die 12. Therefore, the seal ring 82 is provided outside the transmitter coil 50 and the receiver coil 60.

[0018] 1 has a cut portion 83 in the center of the upper edge. This prevents the seal ring 82 from forming a loop and functioning as a coil. The cut portion 83 only needs to be provided in at least one location on the seal ring 82, and may be provided on each side, for example, or in a portion of each side other than the center.

[0019] The package 86 is a package for protecting the communications chip 10 and providing external connectivity. As the package 86, a ceramic package, a WLCSP (Wafer Level Chip Size Package), or the like can be used.

[0020] 3 is a block diagram of the SoC unit 20. The SoC unit 20 is a control circuit for the communications chip 10. The SoC unit 20 has the following configuration.

[0021] The CPU core 200 is a processing device that executes programs and is also simply called a CPU. The temporary storage device 202 is, for example, an SRAM, and holds data while power is supplied to the communications chip 10. The FLASH (registered trademark) memory 204 is a storage device that can hold data even when power is not supplied to the communications chip 10.

[0022] The data / memory bus 206 is a bus that exchanges data between the CPU core 200, the temporary storage device 202, the FLASH (registered trademark) memory 204, and the DMA controller 210. The peripheral bus 208 is a bus that connects the CPU core 200, the temporary storage device 202, the FLASH (registered trademark) memory 204, and the DMA controller 210 with an external device, such as a personal computer connected to the communications chip 10. The DMA controller 210 provides a function for directly transferring data between the external device and the temporary storage device 202 and the FLASH (registered trademark) memory 204 via the data / memory bus 206 and the peripheral bus 208, without processing by the CPU core 200.

[0023] The JTAG input / output interface 212 is an interface for communicating between the SoC unit 20 and an external device such as a personal computer using serial communication defined by JTAG. The JTAG input / output interface 212 is connected to a JTAG terminal of the pad unit 80.

[0024] The UART0 input / output interface 214 is an interface for communication between the SoC unit 20 and external devices, such as other ICs mounted on the same board as the communications chip 10, via serial communication defined by UART. The SPI input / output interface 216 is an interface for communication between the SoC unit 20 and external devices via serial communication defined by SPI. The I2C input / output interface 218 is an interface for communication between the SoC unit 20 and external devices via serial communication defined by I2C. The GPIO interface 220 is a general-purpose input / output interface for exchanging signals between the SoC unit 20 and external devices. The UART0 input / output interface 214, the SPI input / output interface 216, the I2C input / output interface 218, and the GPIO interface 220 are connected to external terminals of the pad unit 80. The GPIO interface 220 is connected to the external terminals of the pad section 80, thereby connecting the SoC section 20 to external devices used for communication and testing as described below.

[0025] The clock input unit 222 receives a clock signal from an external device. In this embodiment, a 25 MHz clock signal is input from an external crystal oscillator. The clock input unit 222 is connected to the clock terminal of the pad unit 80.

[0026] The HSS (high speed serial communication) input / output interface 230 is an interface for communication between the SoC unit 20 and the transmitter / receiver circuit unit 70 via serial communication defined by UART. The UART1 input / output interface 240 is an interface for communication between the SoC unit 20 and the transmitter / receiver circuit unit 70 via serial communication defined by UART. A logic gate 40 is provided between the HSS input / output interface 230, the UART1 input / output interface 240, and the transmitter / receiver circuit unit 70.

[0027] 3 is an example, and may further include other components, such as a controller for debugging, a controller for controlling the operation of each block in response to an event, and a timer.

[0028] 4 is a schematic diagram showing clock signal distribution. Clock input unit 222 distributes and supplies an externally input 25 MHz clock signal to CPU core 200, system 270, UART0 input / output interface 214, etc. Here, system 270 is a general term for data memory bus 206, temporary storage device 202, FLASH (registered trademark) memory 204, DMA controller 210, JTAG input / output interface 212, and GPIO interface 220 shown in FIG. 3 for ease of explanation.

[0029] The UART0 input / output interface 214, the SPI input / output interface 216, the I2C input / output interface 218, the UART1 input / output interface 240, and the HSS input / output interface 230 are each provided with clock gates (CG) 260, 262, 264, 266, and 268. The clock gate 260 and the like control whether or not to supply a clock signal to the connected components based on instructions from the CPU core 200. In this way, clock signals can be supplied only to the components that are being used, and power consumption of the communications chip 10 can be reduced.

[0030] The communications chip 10 further includes a phase-locked loop circuit 250. An external 25 MHz clock signal is input to the phase-locked loop circuit 250. The phase-locked loop circuit 250 multiplies the 25 MHz clock signal by 16 to generate a 400 MHz clock signal, which is input to the HSS input / output interface 230. The HSS input / output interface 230 is driven by a faster clock than the UART1 input / output interface 240, and can provide faster serial communication.

[0031] 5 is a schematic diagram showing the connection relationship between the HSS setting register 224, the HSS input / output interface 230, the UART1 input / output interface 240, the logic gate 40, and the transmitting / receiving circuit unit 70. The transmitting / receiving circuit unit 70 has a transmitting circuit 710 and a receiving circuit 750.

[0032] The HSS input / output interface 230 has an HSS transmitter 232 and an HSS receiver 234. The HSS transmitter 232 outputs an HSS transmit signal (sometimes referred to as TX) and a transmit enable (sometimes referred to as TX enable or transmittable signal). The transmit enable is a signal that takes two values, High or Low, and is High when an HSS transmit signal is being output. The HSS receiver 234 receives and decodes a receive signal (sometimes referred to as RX) from the transmitter / receiver circuit unit 70.

[0033] The HSS setting register 224 is an area in the temporary storage device 202, and holds parameters for HSS communication and near-field magnetic coupling communication. The HSS setting register 224 is 32 bits wide, and each bit corresponds to a parameter shown in the following table.

[0034] The UART1 input / output interface 240 has a UART1 transmitter 242 and a UART1 receiver 244. The UART1 transmitter 242 outputs a transmission signal of UART1. The UART1 receiver 244 receives a reception signal from the transmission / reception circuit 70 and decodes it.

[0035] The logic gate 40 is disposed between the HSS input / output interface 230, the UART1 input / output interface 240, and the transmission / reception circuit unit 70. The logic gate 40 has a plurality of gates, which are used to select functions related to transmission and reception. The logic gate 40 is connected to a test mode input unit (ANTTEST) for the test mode and six general-purpose interfaces (GPIO0 to GPIO5) for external observation.

[0036] The following describes the signal transmission and reception operation of the HSS in normal mode. In normal mode, the control signal input to the test mode input unit is low, and the transmit signal debug selection signal (Debug_tx) and receive signal debug selection signal (Debug_rx) of the HSS setting register 224 are also low.

[0037] (1) Signal Transmission The settings for the operation of gate 1, gate 2, gate 3, and gate 4 during transmission are stored in the HSS setting register 224. When transmitting a signal, the HSS transmitter 232 outputs a transmission signal (TX) and a transmission enable (TX enable High).

[0038] The transmission signal is input to gate 1. Gate 1 is a selection unit that selects a communication interface. Gate 1 switches the communication interface connected to the transmission / reception circuit unit 70 according to the communication interface selection signal (Alt) in the HSS setting register 224. When the communication interface selection signal is High, it outputs a transmission signal from the UART1 transmission unit 242, and when the communication interface selection signal is Low, it outputs a transmission signal from the HSS transmission unit 232. Below, we will continue to explain the case when the communication interface selection signal is Low.

[0039] The output of gate 1 is input to gate 2. Gate 2 is a selection unit that selects polarity inversion of the transmission signal. The transmission signal is inverted between High and Low in accordance with a transmission signal polarity inversion control signal (Inv_tx) in the HSS setting register 224. The transmission signal polarity inversion control signal will be described later.

[0040] The output of gate 2 is input to gate 3. Gate 3 is a gate for transmission signal debug control. Gate 3 switches the output destination of the signal input to gate 3 according to the output of gate 13. Gate 13 is a gate that takes the logical OR of the signal from the test mode control unit and the transmission signal debug selection signal (Debug_tx). In normal mode, the test mode control signal and the transmission signal debug selection signal are both low, so the output of gate 13 is also low. At this time, gate 3 outputs the input signal to gate 4.

[0041] Gate 4 switches the signal output from gate 4 to the transmission circuit 710 according to the output of gate 13. In normal mode, the output of gate 13 is Low. At this time, gate 4 outputs the signal input from gate 3 to the transmission circuit 710. As with the transmission signal, the output destination of gate 5 and the input source of gate 6 for the transmission enable of the HSS transmission unit 232 are also selected according to the output of gate 13. In normal mode, the transmission enable is input from gate 5 via gate 6 to the transmission circuit 710 and the reception circuit 750.

[0042] (2) Signal Reception The HSS setting register 224 stores the settings for the operation of gates 7, 8, 9, 10, 11, and 12 during reception. A transmission enable signal is input to the reception circuit. When receiving a signal, the reception circuit 750 outputs a reception signal (also referred to as RX).

[0043] The received signal is input to gate 7. Gate 7 is a received signal debug control unit, and outputs the output of the receiving circuit 750 to the general-purpose input / output interface in accordance with the output of gate 14, which takes the logical sum of the received signal debug selection signal (Debug_rx) in the HSS setting register 224 and the test mode control signal. When the output of gate 14 is Low, i.e., in normal mode, gate 7 does not output the received signal to GPIO0. When the output of gate 14 is High, i.e., in test mode, gate 7 outputs the received signal to GPIO0.

[0044] The output of gate 7 is input to gate 8. When the output of gate 14 is low (normal mode), gate 8 outputs the signal input from gate 7 to gate 9. When the output of gate 14 is high (test mode), gate 8 outputs the signal from GPIO3 to gate 9. Gate 9 is a selection unit that selects the polarity inversion of the received signal. The received signal is inverted between high and low according to a received signal polarity inversion control signal (Inv_rx) in the HSS setting register 224. The received signal polarity inversion control signal will be described later.

[0045] The output of gate 9 is input to gate 10. Gate 10 switches the output destination between gate 11 and the UART1 receiver 244 according to the communication interface selection signal (Alt) in the HSS setting register 224. The output of gate 10 is input to gate 11. Gate 11 is a loopback control unit, and connects or disconnects the output of gate 10 to the received signal input of the HSS receiver 234 according to the loopback selection signal (Loopback_sel) of the HSS setting register 224. When the loopback selection signal is high and TX enable is high, the output of gate 12 is low, and the connection is established. When the loopback selection signal is high and TX enable is low, the output signal of gate 12 is low, and the connection is established. When the loopback selection signal is low and TX enable is high, the output of gate 12 is high, and the connection is established (in this case, high is always input to the received signal input of the HSS receiver 234). When the loopback select signal is low and the TX enable is low, the output signal of the gate 12 is low and connected.

[0046] The above is the signal transmission and reception operation in the HSS in normal mode. In Figure 5, the main signal flows in this operation are indicated by bold lines.

[0047] 6 is a diagram illustrating the signal transmission and reception operation of the HSS in test mode. In test mode, the control signal input to the test mode input unit is high, or the transmission signal debug selection signal or reception signal debug selection signal in the HSS setting register 224 is high. The test mode is used for the purpose of evaluating the transmission and reception circuit unit 70. Note that in test mode, all settings in the HSS setting register 224 are invalid.

[0048] (1) In the signal transmission test mode, the transmission signal (TX) and transmission enable (TX enable) output by the HSS transmission unit 232 are not input to the transmission circuit 710 by gates 3 and 5. In this case, the transmission signal (TX) output by the HSS transmission unit 232 is output to GPIO4. The transmission enable (TX enable) output by the HSS transmission unit 232 is output to GPIO5.

[0049] The signal input to GPIO1 is input to the transmitting circuit 710 as a transmission signal via gate 4. In addition, the signal input to GPIO2 is input to the transmitting circuit 710 via gate 6 as a transmission enable.

[0050] (2) In the signal reception test mode, the transmission enable (TX enable) of the HSS transmission unit 232 is not input to the reception circuit 750 by gate 6. The reception signal (RX) output by the reception circuit 750 is not input to the HSS reception unit 234 by gate 7. In this case, the signal input to GPIO2 is input to the reception circuit 750 as a transmission enable. Furthermore, the reception signal (RX) output by the reception circuit 750 is output to GPIO0. The signal input to GPIO3 is input to the HSS reception unit 234 as a reception signal via gate 8.

[0051] The above is the signal transmission and reception operation of the HSS in test mode. In Figure 6, the main signal flows in this operation are indicated by bold lines.

[0052] With the above configuration, logic gate 40 controls whether or not receiving circuit 750 transmits a received signal to HSS receiving unit 234 based on the transmit enable input to logic gate 40. Furthermore, with the above configuration, logic gate 40 selectively inputs to transmitting circuit 710 the transmit enable and transmit signal of HSS transmitting unit 232 and the transmit enable and transmit signal for the test mode.

[0053] 7 is a block diagram of the transmission / reception circuit section 70. The transmission / reception circuit section 70 has a transmission circuit 710 and a reception circuit 750. The transmission circuit 710 has buffer circuits 712 and 716, a single-ended signal-to-differential signal conversion circuit 714, and a driver circuit 718.

[0054] The buffer circuit 712 receives a transmission signal from the logic gate 40. In the case of HSS communication in normal mode, the buffer circuit 712 receives a transmission signal generated by the HSS transmitter 232. The buffer circuit 712 corrects the voltage level of the input signal.

[0055] The single-ended signal-to-differential signal conversion circuit 714 converts the single-ended transmission signal input from the buffer circuit 712 into a differential signal and outputs it. The buffer circuit 716 corrects the voltage level of the signal input to the single-ended signal-to-differential signal conversion circuit 714.

[0056] The drive circuit 718 receives a transmission enable signal from the logic gate 40. In the case of HSS communication in normal mode, the drive circuit 718 receives a transmission enable signal generated by the HSS transmission unit 232.

[0057] The drive circuit 718 switches the direction of the current flowing through the connected transmission coil 50 in response to the voltage level of the differential signal input from the buffer circuit 716. An H-bridge circuit can be used as the drive circuit 718.

[0058] The drive circuit 718 includes a tri-state buffer, and when the transmit enable is high, it passes current through the transmit coil 50, and when the transmit enable is low, it places the output in a high impedance (HiZ) state, preventing current from passing through the transmit coil 50. In other words, the SoC unit 20 can be said to use the transmit enable to control whether the transmit circuit 710 transmits a transmit signal to the transmit coil 50. This prevents unnecessary current from flowing from the drive circuit 718 to the transmit coil 50, even if the transmit signal is fixed high (or low) when no transmission is being performed from the communications chip 10, thereby reducing power consumption. In other words, when the HSS transmitter 232 is not transmitting a transmit signal to the transmit circuit 710, it is possible to control the current flowing from the transmit circuit 710 to the transmit coil 50.

[0059] 8 is an enlarged view of region A in FIG. 1. The drive circuit 718 is connected to the first transmit coil port 52 and the second transmit coil port 54 of the transmit coil 50. That is, the drive circuit 718 applies a voltage based on a transmit signal to both ends of the transmit coil 50, causing a current to flow through the transmit coil 50. The transmit coil 50 is coupled to a receive coil of another communications chip and is used to transmit data to the other communications chip by near-field magnetic coupling communication. The transmit coil 50 is formed by a wiring pattern on the multi-layer silicon die 12.

[0060] 7 converts the induced voltage generated in the receiving coil 60 into a receiving signal. The receiving circuit 750 includes a differential signal-single-ended signal conversion circuit 752, a hysteresis comparator circuit 754, and a coil midpoint potential generation circuit 756.

[0061] The hysteresis comparator circuit 754 receives as input a signal generated between the first and third receive coil ports 62 and 66, which are both ends of the receive coil 60. The hysteresis comparator circuit 754 also receives as input two types of bias voltages used to control the hysteresis width of the comparator.

[0062] The hysteresis comparator circuit 754 compares the voltage level induced across the receiving coil 60 with a threshold value having hysteresis, and outputs a high or low voltage level as a differential signal to the differential signal-single-ended signal conversion circuit 752 depending on the comparison result. The output of the hysteresis comparator circuit 754 is controlled by the transmit enable signal. When the transmit enable signal is high, the hysteresis comparator circuit 754 outputs a high signal regardless of the voltage level across the receiving coil 60. This prevents an induced voltage from being generated in the receiving coil 60 of the communications chip 10 due to the current flowing through the transmitting coil 50 while the communications chip 10 is transmitting, thereby preventing unnecessary receiving signals from being input to the receiving circuit 750. On the other hand, when the transmit enable signal is low, the hysteresis comparator circuit 754 outputs a value based on a comparison of the input voltage across the receiving coil 60 with a threshold value having hysteresis.

[0063] The coil midpoint potential generating circuit 756 generates a midpoint potential (also called an intermediate voltage) of the receiving coil 60 from two types of bias voltages, and applies it to the second receiving coil port 64, which is the midpoint of the receiving coil 60. The hysteresis comparator circuit 754 and the coil midpoint potential generating circuit 756 use the same bias voltage.

[0064] The differential signal-single-ended signal conversion circuit 752 converts the differential signal output from the hysteresis comparator circuit 754 into a single-ended signal, and outputs it to the HSS receiving unit 234 of the SoC unit 20 via the logic gate 40 .

[0065] 8 shows a first receive coil port 62, a second receive coil port 64, and a third receive coil port 66 of the receive coil 60. The receive coil 60 is used to couple with a transmit coil of another communication chip and receive data from the other communication chip by near-field magnetic coupling communication. The receive coil 60 is formed by a wiring pattern on the multi-layer silicon die 12.

[0066] 1 and 8, the receiving coil 60 is depicted as being disposed outside the transmitting coil 50, but their mutual arrangement is not limited to this. For example, the receiving coil 60 and the transmitting coil 50 may be formed on different layers without being in electrical contact with each other, and may be in the same position and of the same size so as to overlap each other in the plan view of FIG.

[0067] Furthermore, the length of one side of the transmitter coil 50 and the receiver coil 60, the number of turns, and the spacing between the wires may be the same. Preferably, the transmitter coil 50 has a thicker wire width or a larger cross-sectional area than the receiver coil. The SoC unit 20, the transmitter / receiver circuit unit 70, and the pad unit 80 are formed inside the transmitter coil 50 and the receiver coil 60 in the plan view of FIG. 1 . This allows for narrower spacing between the coils of adjacent communications chips, achieving more stable near-field magnetic coupling communication. Furthermore, a portion of any of the SoC unit 20, the transmitter / receiver circuit unit 70, and the pad unit 80 is provided on the same layer as the transmitter coil 50 or the receiver coil 60. This allows the communications chip 10 to be manufactured with fewer processes.

[0068] 9 is a schematic diagram of two communication chips arranged horizontally. The configurations of the communication chip 10A and the communication chip 10B are the same as those of the communication chip 10 shown in FIGS. 1 to 8. To simplify the illustration, the configuration other than the transmitter coil 50A of the communication chip 10A and the receiver coil 60B of the communication chip 10B is omitted.

[0069] When the two communication chips are arranged horizontally, the interlinkage magnetic flux generated in the transmitting coil 50A of the communication chip 10A penetrates the receiving coil 60B of the communication chip 10B in the opposite direction, so that the direction of the electromotive force generated in the receiving coil 60B of the communication chip 10B is opposite to the potential applied to the transmitting coil 50A of the communication chip 10A.

[0070] 10 is a schematic diagram of two communications chips arranged vertically. For simplicity of illustration, components other than the transmitter coil 50A and the receiver coil 60B are omitted.

[0071] When the two communications chips are arranged perpendicularly, the interlinkage magnetic flux generated in the transmitting coil 50A of the communications chip 10A penetrates the receiving coil 60B of the communications chip 10B in the same direction, so that the direction of the electromotive force generated in the receiving coil 60B of the communications chip 10B is the same as the direction of the potential applied to the transmitting coil 50A of the communications chip 10A.

[0072] 11 shows a state in which two communications chips are tilted at an angle Da relative to each other with the dashed-dotted line in the figure as the central axis. When the angle Da is between 0 and 90 degrees, the flux linkage generated in the transmitter coil 50A of the communications chip 10A penetrates the receiver coil 60B of the communications chip 10B in the opposite direction, as in FIG. 9. On the other hand, when the angle Da is between 90 and 180 degrees, the flux linkage generated in the transmitter coil 50A of the communications chip 10A penetrates the receiver coil 60B of the communications chip 10B in the same direction, as in FIG. 10.

[0073] Therefore, when the two communications chips are arranged such that the angle Da is between 0 and 90 degrees, the transmitting communications chip 10A sets the transmit signal polarity inversion control signal of the HSS setting register 224 to High. The receiving communications chip 10B sets the receive signal polarity inversion control signal of the HSS setting register 224 to Low. This allows the polarity of the transmit signal to be inverted and output from the transmitting coil 50A of the communications chip 10A, generating an electromotive force in the intended direction in the communications chip 10B.

[0074] On the other hand, when the two communications chips are arranged such that the angle Da is between 90 degrees and 180 degrees, the transmitting communications chip 10A sets the transmit signal polarity inversion control signal in the HSS setting register 224 to Low. The receiving communications chip 10B sets the receive signal polarity inversion control signal in the HSS setting register 224 to Low. This allows the transmit signal to be output from the transmitting coil 50A of the communications chip 10A without inverting its polarity, generating an electromotive force in the intended direction in the communications chip 10B.

[0075] When the communications chip 10A is the receiving side and the communications chip 10B is the transmitting side and the two communications chips are arranged at an angle Da between 0 and 90 degrees, the receiving communications chip 10A sets the received signal polarity inversion control signal of the HSS setting register 224 to High. The transmitting communications chip 10B sets the transmitted signal polarity inversion control signal of the HSS setting register 224 to Low. As a result, even if an electromotive force in the opposite direction to that of the communications chip 10B is generated in the communications chip 10A, the polarity of the resulting received signal can be inverted, allowing the communications chip 10A to obtain the intended received signal.

[0076] When the communications chip 10A is the receiving side and the communications chip 10B is the transmitting side and the two communications chips are arranged at an angle Da of 90 degrees to 180 degrees, the receiving communications chip 10A sets the received signal polarity inversion control signal in the HSS setting register 224 to Low. The transmitting communications chip 10B sets the transmitted signal polarity inversion control signal in the HSS setting register 224 to Low. This causes an electromotive force to be generated in the communications chip 10A in the same direction as that of the communications chip 10B, so that the polarity of the received signal is not inverted and the intended received signal can be obtained in the communications chip 10A.

[0077] In addition, when the arrangement is such that the interlinkage magnetic flux generated in the transmitting coil 50A of the communications chip 10A penetrates the receiving coil 60B of the communications chip 10B in the opposite direction, the transmit signal polarity inversion control signal and the receive signal polarity inversion control signal of the HSS setting register 224 are set to High. On the other hand, when the arrangement is such that the interlinkage magnetic flux generated in the transmitting coil 50A of the communications chip 10A penetrates the receiving coil 60B of the communications chip 10B in the same direction, the transmit signal polarity inversion control signal and the receive signal polarity inversion control signal of the HSS setting register 224 are set to Low.

[0078] In the above example, the transmit signal polarity inversion control signal and the receive signal polarity inversion control signal on the communications chip 10B side are fixed to Low, and then the transmit signal polarity inversion control signal and the receive signal polarity inversion control signal on the communications chip 10A side are set to High or Low based on the arrangement of the coils. Alternatively, the transmit signal polarity inversion control signal and the receive signal polarity inversion control signal on the communications chip 10A side may be fixed to Low, and then the transmit signal polarity inversion control signal and the receive signal polarity inversion control signal on the communications chip 10B side may be set to High or Low based on the arrangement of the coils.

[0079] Fig. 12 shows a schematic diagram of a master chip 10M and a slave chip 10S that communicate with each other. The master chip 10M and the slave chip 10S each have the same configuration as the communication chip 10 described in Fig. 1 to Fig. 8, but Fig. 12 omits some components.

[0080] 13 shows a schematic example of the format of an HSS signal transmitted from the master chip 10M. The HSS signal is composed of a start bit, a data section, a parity bit, and a stop bit. The start bit is a 0 signal that is inserted to detect the start of the HSS signal frame. The data section is 8 or 10 bits of data, and is 8 bits long if 8B10B coding is not applied, and 10 bits long if it is applied.

[0081] The parity bit is a bit used to detect errors in the HSS signal frame. The parity bit is inserted when Parity Enable is 1, and is not inserted when it is 0. The stop bit is a bit that indicates the end of the HSS signal frame, and has a value of 1. The number of stop bits can be set using a register.

[0082] The master chip 10M can access resources of the slave chip 10S via high-speed serial communication using the K code, which is an 8B10B code. The master chip 10M sets parameters for accessing the slave chip using the K code (hereinafter referred to as access control parameters) in the area shown in Table 2 below in the HSS setting register 224.

[0083] Figure 14 shows a schematic diagram of an HSS signal using a K code as an example. Each square in the HSS signal is a frame configured in the format shown in Figure 13. The first signal frame contains a K code, with K28.0 corresponding to a write command, K28.1 corresponding to a read command, and K28.2 corresponding to a read data command. In other words, the access control parameter is included in the first signal frame of the format that configures the transmission signal, and is a signal sequence that is the same length as a codeword obtained as a result of encoding the original signal to add redundancy, but is different from any codeword obtained as a result of encoding any original signal.

[0084] FIG. 15 shows the operation (S10) when data is written from the master chip 10M to the slave chip 10S.

[0085] The slave chip 10S is set to a standby state by enabling the following initial settings in advance (S120): The clock gate 268 of the HSS input / output interface 230 is set to High, putting the HSS input / output interface 230 into an operating state; The receive enable in the HSS setting register 224 is set to High, putting the slave chip 10S into a receive standby state; The 8B10B code enable in the HSS setting register 224 is set to High, enabling 8B10B code reception; The baud rate / parity settings in the HSS setting register 224 are set to the same values ​​as those in the master chip 10M; The transmit enable in the HSS setting register 224 is set to Low.

[0086] Here, the receive enable signal is input to a hysteresis comparator circuit 754 and controls the output of the hysteresis comparator circuit 754. When the receive enable signal is low, the hysteresis comparator circuit 754 outputs a high signal regardless of the voltage level across the receive coil 60. On the other hand, when the receive enable signal is high, the hysteresis comparator circuit 754 outputs a value based on a comparison of the input voltage across the receive coil 60 with a threshold value having hysteresis. In this case, as shown in FIG. 7 , a transmit enable signal may be input to the hysteresis comparator circuit 754, and an inverted signal of the transmit enable signal may be used as the receive enable signal within the hysteresis comparator circuit 754.

[0087] The master chip 10M sets the address of the memory area of ​​the slave chip 10S to which data is to be written in the "slave chip address" (S100), and sets the data to be written in the "slave chip data" (S102). At this point, the transmission enable and reception enable of the master chip 10M are set to Low.

[0088] In the master chip 10M, the first bit of the slave control command is set to "1", the second bit to "1", and the third bit to "0" (011). This sets an operation to write the data stored in the slave chip data to a memory area (hereinafter referred to as the data area) in the slave chip specified by the master chip 10M's slave chip address (S104).

[0089] The master chip 10M sets the transmission enable to High, and the HSS input / output interface 230 outputs the HSS signal shown in (1) "Write" in Fig. 14, which is transmitted by the transmission / reception circuit unit 70 (S106). The beginning of the HSS signal is a frame including 10 bits corresponding to K28.0.

[0090] When the transmission is completed, the HSS input / output interface 230 of the master chip 10M sets the first bit (bit 0) of the HSS setting register 224, in which the "slave chip control command" is written, to "0" (S110). Furthermore, the master chip 10M sets the transmission enable to Low.

[0091] When the HSS I / O interface 230 of the slave chip 10S receives K28.0 via the transmission / reception circuit unit 70 (S124), it reads the 32-bit address sent in the following four frames (S124). The HSS I / O interface 230 of the slave chip 10S then reads the 32-bit data sent in the following four frames (S126). The HSS I / O interface 230 of the slave chip 10S then writes the data to the data area 203 corresponding to the address (S128).

[0092] FIG. 16 shows the operation (S20) when the master chip 10M reads data from the slave chip 10S.

[0093] The slave chip 10S is set to a standby state by enabling the following initial settings in advance (S220): The clock gate 268 of the HSS input / output interface 230 is set to High, putting the HSS input / output interface 230 into an operating state; The receive enable in the HSS setting register 224 is set to High, putting the slave chip 10S into a receive standby state; The 8B10B code enable in the HSS setting register 224 is set to High, enabling 8B10B code reception; The baud rate / parity settings in the HSS setting register 224 are set to the same values ​​as those in the master chip 10M; The transmit enable in the HSS setting register 224 is set to Low.

[0094] The master chip 10M sets the receive enable of the HSS setting register 224 to High so that it can receive the read data frame (S200). At this point, the transmit enable and receive enable of the master chip 10M are set to Low. The master chip 10M sets the address of the memory area of ​​the slave chip 10S from which data is to be read in the "slave chip address" (S202).

[0095] The master chip 10M sets the first bit of the slave control command to "1" (i.e., the third, second, and first bits are (001) in that order), and an operation to read the data stored at the address in the memory area of ​​the slave chip set as the slave chip address is set (S204).

[0096] The master chip 10M sets the transmission enable to High, and the HSS input / output interface 230 outputs the HSS signal shown in (2) "Read" in Fig. 14, which is transmitted from the transmission / reception circuit unit 70 (S206). The first frame of the HSS signal is a frame including 10 bits corresponding to K28.1.

[0097] When the transmission is completed, the HSS input / output interface 230 of the master chip 10M sets the first bit (bit 0) of the HSS setting register 224, in which the "slave chip control command" is written, to "0" (S210). Furthermore, the master chip 10M sets the transmission enable to Low.

[0098] When the HSS input / output interface 230 of the slave chip 10S receives K28.1 via the transmission / reception circuit unit 70 (S222), it reads the 32-bit address sent in the following four frames (S224). The HSS input / output interface 230 of the slave chip 10S further reads the data from the data area 203 corresponding to the address (S226).

[0099] The slave chip 10S sets the transmission enable to High, and the HSS input / output interface 230 outputs the HSS signal shown in (3) "ReadData" in Figure 14 for the data read in step S226, and transmits it via the transmission / reception circuit unit 70 (S228). The first frame of the HSS signal is a frame containing 10 bits corresponding to K28.2. When transmission is complete, the slave chip 10S sets the transmission enable to Low.

[0100] When the HSS input / output interface 230 of the master chip 10M receives K28.2 via the transmission / reception circuit unit 70 (S212), it reads the 32-bit data sent in the next four frames (S214). The HSS input / output interface 230 of the master chip 10M further writes the data to the data area 203 specified by the address written in the slave chip data (S216).

[0101] When reception is complete, the HSS input / output interface 230 of the master chip 10M sets the third bit (bit 2) of the "slave chip control command" to "1" (S218). When the third bit of the HSS setting register 224 becomes "1", the CPU core 200 of the master chip 10M reads the data stored in the data area.

[0102] By using the control method described above, the CPU core 200 of the master chip 10M can transmit and receive data to and from the slave chip 10S using near-field magnetic coupling communication by setting the values ​​of the access control parameters (slave chip address, slave chip data, slave chip control command) held in the HSS setting register 224. The control of near-field magnetic coupling communication is performed by the HSS input / output interface 230, which has the advantage that the CPU core 200 can perform other processing during that time. As a result, there is the advantage that the root program executed by the CPU core 200 does not need to include processing for controlling near-field magnetic coupling communication.

[0103] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0104] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

Claims

1. A communications chip comprising a control circuit, a transmitting circuit, and a transmitting coil, wherein the control circuit transmits a transmit signal and a transmit enable signal to the transmitting circuit, and the control circuit uses the transmit enable signal to control whether or not the transmitting circuit transmits the transmit signal to the transmitting coil, and wherein communication is performed by inductive coupling generated between the transmitting coil and a receiving coil in another chip based on the transmit signal.

2. The communications chip according to claim 1, wherein the transmit enable signal causes the transmitting circuit to have high impedance, thereby controlling the transmitting circuit not to transmit the transmit signal to the transmitting coil.

3. The communications chip of claim 1, wherein the transmittable signal causes the transmitting circuit to enter a high impedance state, thereby controlling the current flowing from the transmitting circuit to the transmitting coil when the control circuit is not transmitting the transmit signal to the transmitting circuit.

4. The communications chip of claim 1, further comprising a receiving circuit and a receiving coil, wherein the receiving coil generates an induced voltage due to inductive coupling between the receiving coil and a transmitting coil in another chip, the control circuit transmits the transmittable signal to the receiving circuit, the receiving circuit converts the induced voltage generated in the receiving coil into a received signal, and the control circuit uses the transmittable signal to control whether or not the receiving circuit transmits the received signal to the control circuit.

5. The communications chip according to claim 4, further comprising a logic gate arranged between the receiving circuit and the control circuit, which controls whether the receiving circuit transmits the received signal to the control circuit or not based on the transmittable signal input to the logic gate.

6. The communications chip according to claim 4, wherein the receiving circuit has a comparator that compares the voltage generated in the receiving coil with a threshold value, and the control circuit uses the transmittable signal to control the output of the comparator.

7. The communications chip according to claim 1, further comprising a logic gate disposed between said control circuit and said transmission circuit, to which said transmit enable signal and an external signal for test mode are input, said logic gate selectively inputting said transmit enable signal from said control circuit or said signal for test mode to said transmission circuit.

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