Semiconductor device and method for producing semiconductor device

Abstract

Provided are a semiconductor device and a method for producing a semiconductor device, with which the thickness of a gate electrode can be suppressed and a threshold voltage can be controlled. A semiconductor device 100 is provided with a field effect transistor TR. A gate stack in the field effect transistor TR has a structure CS that includes a channel layer 30a, a gate insulating layer 70 which is in contact with the channel layer 30a, and an electrically conductive layer 81 which is in contact with the gate insulating layer 70 and comprises a prescribed metal compound as a primary component. The electrically conductive layer 81 further contains a prescribed element having an electronegativity that is at least 0.5 higher than the effective electronegativity of the prescribed metal compound.

Description

Semiconductor device and manufacturing method thereof

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Conventionally, as a semiconductor device of this type, there has been known a semiconductor device including an N-channel MOSFET and a P-channel MOSFET, characterized in that the gate electrode of the P-channel MOSFET has a laminated structure including a first conductive film containing oxygen at a first concentration, a second conductive film containing oxygen at a second concentration higher than the first concentration, and a third conductive film containing oxygen at a third concentration lower than the second concentration (see Patent Document 1).

[0003] JP 2008-84970 A

[0004] In the conventional semiconductor device, the threshold voltage is controlled by adjusting the thickness (film thickness) of the conductive layer (conductive film) of the gate electrode.

[0005] However, in recent years, semiconductor devices have been required to be further miniaturized, miniaturized, and integrated, and the thickness of the gate electrode tends to be limited, so there is a demand for controlling the threshold voltage by a method other than changing the thickness of the gate electrode.

[0006] The present invention has been made in view of the above circumstances, and one of its objects is to provide a semiconductor device and a method for manufacturing the semiconductor device that can control the threshold voltage while suppressing the thickness of the gate electrode.

[0007] A semiconductor device according to one aspect of the present invention includes a field-effect transistor, wherein the gate stack of the field-effect transistor has a structure including a channel layer, a gate insulating layer in contact with the channel layer, and a conductive layer in contact with the gate insulating layer and containing a predetermined metal compound as a main component, and the conductive layer further includes a predetermined element having an electronegativity that is 0.5 or more higher than the effective electronegativity of the predetermined metal compound.

[0008] A method for manufacturing a semiconductor device according to one aspect of the present invention includes the steps of forming a source electrode and a drain electrode of a field effect transistor, and forming a gate stack for the field effect transistor, the gate stack having a structure including a channel layer, a gate insulating layer, and a conductive layer, wherein the step of forming the gate stack includes forming a gate insulating layer in contact with the channel layer, and forming a conductive layer in contact with the gate insulating layer, the conductive layer including a predetermined metal compound as a main component and a predetermined element having an electronegativity that is 0.5 or more higher than the effective electronegativity of the predetermined metal compound.

[0009] According to the present invention, the threshold voltage can be controlled while suppressing the thickness of the gate electrode.

[0010] FIG. 1 is a perspective view showing an example of a schematic configuration of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view showing an example of a schematic configuration of a semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view showing an example of a schematic configuration of the gate electrode shown in FIGS. 1 and 2. FIG. 4 is an enlarged cross-sectional view of a main portion showing a first example of the schematic configuration of the structure shown in FIG. 3. FIG. 5 is a diagram for explaining the electronegativity and work function of a plurality of metal compounds. FIG. 6 is a graph showing an example of the relationship between the oxygen concentration in a conductive layer and the work function. FIG. 7 is an enlarged cross-sectional view of a main portion showing a second example of the schematic configuration of the structure shown in FIG. 3. FIG. 8 is a flowchart showing a first example of a method for manufacturing a semiconductor device according to an embodiment. FIG. 9 is an enlarged cross-sectional view of a main portion for explaining the formation of a gate insulating film in the first example of the method for manufacturing a semiconductor device shown in FIG. 8. FIG. 10 is an enlarged cross-sectional view of a main portion for explaining the formation of a conductive layer in the first example of the method for manufacturing a semiconductor device shown in FIG. 8. FIG. 11 is an enlarged cross-sectional view of a main portion for explaining the formation of a conductive layer in the first example of the method for manufacturing a semiconductor device shown in FIG. 8. FIG. 12 is an enlarged cross-sectional view of a main portion for explaining the formation of a conductive layer in the first example of the method for manufacturing a semiconductor device shown in FIG. 8. Fig. 13 is a flowchart showing a second example of a method for manufacturing a semiconductor device according to an embodiment. Fig. 14 is an enlarged cross-sectional view of a main portion for explaining the formation of a conductive layer and an adjustment layer in the second example of the method for manufacturing a semiconductor device shown in Fig. 13. Fig. 15 is an enlarged cross-sectional view of a main portion for explaining the formation of a conductive layer and an adjustment layer in the second example of the method for manufacturing a semiconductor device shown in Fig. 13. Fig. 16 is an enlarged cross-sectional view of a main portion for explaining the formation of a conductive layer and an adjustment layer in the second example of the method for manufacturing a semiconductor device shown in Fig. 13. Fig. 17 is an enlarged cross-sectional view of a main portion for explaining the formation of a conductive layer and an adjustment layer in the second example of the method for manufacturing a semiconductor device shown in Fig. 13. Fig. 18 is an enlarged cross-sectional view of a main portion for explaining the formation of a conductive layer and an adjustment layer in the second example of the method for manufacturing a semiconductor device shown in Fig. 13.

[0011] An embodiment of the present invention will be described below. In the following description of the drawings, identical or similar parts are denoted by identical or similar reference numerals. However, the drawings are schematic. Therefore, specific dimensions and the like should be determined in light of the following description. Furthermore, it goes without saying that the dimensional relationships and ratios of parts included in the drawings differ from one another. Furthermore, the technical scope of the present invention should not be interpreted as being limited to the embodiment.

[0012] First, a schematic configuration of a semiconductor device according to an embodiment will be described with reference to Figures 1 and 2. Figure 1 is a perspective view showing an example of the schematic configuration of a semiconductor device 100 according to an embodiment, and Figure 2 is a cross-sectional view showing an example of the schematic configuration of the semiconductor device 100 according to an embodiment.

[0013] [Semiconductor Device] As shown in FIGS. 1 and 2 , the semiconductor device 100 includes a field effect transistor (FET) TR. The field effect transistor TR typically has three terminals: a gate electrode (also simply referred to as "gate") GA, a source electrode (also simply referred to as "source") SO, and a drain electrode (also simply referred to as "drain") DR. The field effect transistor TR controls the density of electrons or holes by an electric field generated in a region between the source electrode SO and the drain electrode DR (hereinafter referred to as a "channel" or "channel region") by applying or not applying a predetermined voltage to the gate electrode, thereby controlling the current flowing from the source electrode SO to the drain electrode DR. Field effect transistors TR are classified into n-channel type (also simply referred to as "n-type") field effect transistors and p-channel type (also simply referred to as "p-type") field effect transistors depending on the type of channel.

[0014] The field-effect transistor TR of this embodiment includes, for example, a semiconductor substrate 10, an insulating layer 20, and a plurality of nanosheets 30. The semiconductor substrate 10 is, for example, a silicon (Si) substrate. The insulating layer 20 is formed by depositing silicon oxide (SiO ２The semiconductor substrate 10 is formed by depositing an insulating film made of silicon nitride (SiN) or the like. The semiconductor substrate 10 and the insulating layer 20 may be formed using an SOI (Silicon On Insulator) substrate. The semiconductor substrate 10 has a mesa structure that protrudes upward in a portion corresponding to the channel.

[0015] From the viewpoints of miniaturization, miniaturization, and integration, the field-effect transistor TR preferably has a stereoscopic or three-dimensional structure. Specifically, the field-effect transistor TR includes a plurality of nanosheets 30 (three in FIGS. 1 and 2 ) above a mesa structure of a semiconductor substrate 10. Each nanosheet 30 is primarily composed of, for example, silicon (Si), has a thin sheet shape, and has an elongated shape. These multiple nanosheets 30 form the channel of the field-effect transistor TR. Furthermore, a portion of each nanosheet 30 forms a channel layer 30a, which will be described later.

[0016] In this embodiment, an example in which the field-effect transistor TR includes three nanosheets 30 has been described, but the present invention is not limited to this. For example, the field-effect transistor TR may include one, two, or four or more nanosheets 30.

[0017] The gate electrode GA of the field effect transistor TR has a Gate All Around (GAA) structure that surrounds the surface of each nanosheet 30. The GAA structure is effective, for example, in suppressing power consumption and leakage current. The gate electrode GA in this embodiment corresponds to a part of the "gate stack" of the present invention. The term "gate stack" generally refers to a stacked structure (stack) of a gate electrode, a gate insulating film, and a channel.

[0018] 2, the field-effect transistor TR includes spacers 40 between the gate electrode GA and the source electrode SO, and between the gate electrode GA and the drain electrode DR. The field-effect transistor TR also includes, for example, two contacts 50, one of which is connected to the source electrode SO and the other of which is connected to the drain electrode DR. The field-effect transistor TR is configured so that a current flows between the source electrode SO and the drain electrode DR with each nanosheet 30 serving as a current path.

[0019] The field effect transistor TR is not limited to the examples shown in Figures 1 and 2. For example, the field effect transistor TR may be a MOS (Metal Oxide Semiconductor) type FET, a MIS (Metal-Insulator-Semiconductor) type FET that uses a material other than an oxide film as an insulating film, a junction type FET, or the like, and the type is not limited.

[0020] The field-effect transistor TR may be either an n-channel type or a p-channel type. Furthermore, the semiconductor device 100 may include a plurality of field-effect transistors TR, or may include both an n-channel type field-effect transistor and a p-channel type field-effect transistor. In this case, the semiconductor device 100 may include a complementary MOS circuit that is a complementary combination of an n-channel type field-effect transistor and a p-channel type field-effect transistor.

[0021] Next, the configuration of a gate electrode of a field effect transistor of a semiconductor device according to one embodiment will be described with reference to FIGS. 3 to 7 . FIG. 3 is a cross-sectional view showing an example of the schematic configuration of the gate electrode GA shown in FIGS. 1 and 2 . FIG. 4 is an enlarged cross-sectional view of a main portion showing a first example of the schematic configuration of the structure CS shown in FIG. 3 . FIG. 5 is a diagram for explaining the electronegativity and work function of a plurality of metal compounds. FIG. 6 is a graph showing an example of the relationship between the oxygen concentration and the work function in the conductive layer 81. FIG. 7 is an enlarged cross-sectional view of a main portion showing a second example of the schematic configuration of the structure CS shown in FIG. 3 . Note that FIG. 3 shows a cross section parallel to the YZ plane along line III-III shown in FIG. 2 .

[0022] 3, the gate electrode GA of the field-effect transistor TR includes a plurality of structures CS and a metal gate 60. The metal gate 60 is formed on the semiconductor substrate 10 so as to cover the plurality of structures CS. The metal gate 60 is intended to reduce the resistance value of the gate electrode GA, and is made of a material containing tungsten (W) as a main component, for example.

[0023] Each of the plurality of structural bodies CS, for example, three structural bodies CS in the example shown in FIG. 3, has a structure in which a plurality of layers are stacked.

[0024] For example, as shown in FIG. 4, the structure CS includes a channel layer 30 a that is a part of the nanosheet 30 , a gate insulating layer 70 , and a conductive layer 81 .

[0025] The gate insulating layer 70 is formed between the channel layer 30a and the conductive layer 81 in the structure CS, and is in contact with the channel layer 30a. The gate insulating layer 70 is made of a material having a high relative dielectric constant κ from the viewpoint of suppressing leakage current. More specifically, the main component of the gate insulating layer 70 is a high-κ insulator, and for example, a material having a relative dielectric constant κ of silicon dioxide (SiO ２ ) is preferably a compound having a viscosity of 4.0 or more, which is higher than that.

[0026] In this way, since the main component of the gate insulating layer 70 is a compound having a relative dielectric constant κ of 4.0 or more, the tunnel effect is less likely to occur, and the leakage current can be suppressed even when the thickness of the gate insulating layer 70 is reduced.

[0027] Specifically, the main component of the gate insulating layer 70 is hafnium oxide (HfO ２ ) is preferable. This makes it possible to easily realize (configure) the gate insulating layer 70 having a high relative dielectric constant and electrical insulation.

[0028] The conductive layer 81 is for adjusting the work function of the structure CS. The work function can be measured using a method such as ultraviolet photoelectron spectroscopy (UPS). The conductive layer 81 is in contact with the gate insulating layer 70 and contains a predetermined metal compound as a main component.

[0029] The conductive layer 81 further contains a predetermined element. This predetermined element has an electronegativity that is 0.5 or more greater than the effective electronegativity of the predetermined metal compound. The electronegativity in this application is the Pauling (also known as the "Pauling scale") electronegativity. The electronegativity of a compound can be determined by calculating the geometric mean of the electronegativity of each atom that constitutes the compound. The effective electronegativity is an electronegativity that can be calculated from the elements and composition of an object by analyzing the object using a method such as transmission electron microscopy-electron energy-loss spectroscopy (TEM-EELS).

[0030] Here, in the conductive layer 81, there is a correlation between the electronegativity and the work function. Therefore, when the difference in electronegativity between the predetermined metal compound and the predetermined element contained in the conductive layer 81 is 0.5 or more, it is possible to significantly change the work function of the structure CS of the gate electrode GA. Therefore, by changing the work function of the gate electrode GA, the threshold voltage of the field-effect transistor TR can be controlled and set to an appropriate value. Furthermore, by controlling the threshold voltage without changing the thickness of the gate electrode GA, it is possible to miniaturize the semiconductor device 100 and reduce power consumption.

[0031] More specifically, the electronegativity of the predetermined element is preferably equal to or greater than 3. This makes it possible to efficiently change the work function of the gate electrode GA.

[0032] Specifically, the predetermined element is oxygen (O). This makes it possible to realize (configure) a gate electrode GA whose work function can be easily changed.

[0033] On the other hand, the effective electronegativity of the predetermined metal compound is preferably 2.5 or less, which makes it easier to make the difference with the electronegativity of the predetermined element 0.5 or more.

[0034] Furthermore, it is preferable that the work function of the predetermined metal compound itself before the addition of the predetermined element is 4.3 eV or less, which makes it possible to change the work function to a value suitable for the gate electrode GA of both the n-channel and p-channel field-effect transistors TR.

[0035] Specifically, examples of the predetermined metal compounds include those shown in FIG.

[0036] That is, as shown in FIG. 5, titanium nitride (TiN) has an electronegativity of 2.22 and a work function of 4.0 eV. Titanium carbide (TiC) has an electronegativity of 2.03 and a work function of 3.8 eV. Tantalum carbide (TaC) has an electronegativity of 1.96 and a work function of 4.3 eV. Tantalum nitride (TaN) has an electronegativity of 2.14 and a work function of 4 eV. Hafnium nitride (HfN) has an electronegativity of 1.82 and a work function of 3.9 eV. Niobium carbide (NbC) has an electronegativity of 2.02 and a work function of 4.2 eV. Niobium nitride (NbN) has an electronegativity of 2.02 and a work function of 3.92 eV. Zirconium carbide (ZrC) has an electronegativity of 1.84 and a work function of 4 eV. Zirconium nitride (ZrN) has an electronegativity of 1.84 and a work function of 2.94 eV.

[0037] Thus, the predetermined metal compound is any one of titanium nitride (TiN), titanium carbide (TiC), tantalum carbide (TaC), tantalum nitride (TaN), hafnium nitride (HfN), niobium carbide (NbC), niobium nitride (NbN), zirconium carbide (ZrC), and zirconium nitride (ZrN). This makes it possible to realize (configure) a gate electrode GA whose work function can be easily changed.

[0038] In the following description, unless otherwise specified, the predetermined metal compound is titanium nitride (TiN) and the predetermined element is oxygen (O).

[0039] The conductive layer 81 contains a predetermined metal compound and a predetermined element, and therefore the main component of the conductive layer 81 is, for example, titanium oxynitride (TiON). The composition of the conductive layer 81 is, for example, (TiN). １－ｘ (TiO ２ ) ｘ where x is a real number between 0 and 1 (0≦x≦1). The composition of the conductive layer 81 can be measured using a transmission electron microscope-electron energy loss spectroscopy or the like.

[0040] In this case, the work function φ of the conductive layer 81 can be expressed by the following formula (1) using the electronegativity EN of the conductive layer 81: φ=2.3EN−1.08 (1)

[0041] Therefore, by adjusting the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81, it is possible to set the work function of the conductive layer 81 to an appropriate value.

[0042] Here, there exists a relationship between the oxygen concentration and the work function in the conductive layer 81 as shown in FIG.

[0043] For example, in an n-channel field-effect transistor TR, the work function of the gate electrode GA is preferably 4.5 eV or less. As shown in Fig. 6, when the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is 33 at% or less, the work function of the conductive layer 81 is 4.5 eV or less. Thus, when the predetermined metal compound is titanium nitride (TiN), the predetermined element is oxygen (O), and the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is greater than 0 at% and less than 33 at%, an n-channel field-effect transistor TR suitable for low-power consumption applications can be easily realized (configured).

[0044] Furthermore, in the n-channel field-effect transistor TR, it is more preferable that the work function of the gate electrode GA is 4.4 eV or less. As shown in Figure 6, when the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is 25 at% or less, the work function of the conductive layer 81 is 4.4 eV or less. In this way, the predetermined metal compound is titanium nitride (TiN), the predetermined element is oxygen (O), and the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is greater than 0 at% and less than 25 at%, thereby making it possible to easily realize (configure) an n-channel field-effect transistor TR suitable for normal (general-purpose) speed applications.

[0045] Furthermore, in the n-channel field-effect transistor TR, it is more preferable that the work function of the gate electrode GA is 4.3 eV or less. As shown in Figure 6, when the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is 20 at% or less, the work function of the conductive layer 81 is 4.3 eV or less. In this way, the predetermined metal compound is titanium nitride (TiN), the predetermined element is oxygen (O), and the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is greater than 0 at% and less than 20 at%, thereby making it possible to easily realize (configure) an n-channel field-effect transistor TR suitable for high-speed applications.

[0046] On the other hand, in the p-channel field-effect transistor TR, the work function of the gate electrode GA is preferably 4.7 eV or more. As shown in Figure 6, when the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is 45 at% or more, the work function of the conductive layer 81 is 4.7 eV or more. In this way, the predetermined metal compound is titanium nitride (TiN), the predetermined element is oxygen (O), and the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is 45 at% or more and less than 100 at%, so that a p-channel field-effect transistor TR suitable for low power consumption applications can be easily realized (configured).

[0047] Furthermore, in the p-channel field-effect transistor TR, it is more preferable that the work function of the gate electrode GA is 4.8 eV or more. As shown in Figure 6, when the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is 50 at% or more, the work function of the conductive layer 81 is 4.8 eV or more. In this way, the predetermined metal compound is titanium nitride (TiN), the predetermined element is oxygen (O), and the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is 50 at% or more and less than 100 at%, so that a p-channel field-effect transistor TR suitable for normal (general-purpose) speed applications can be easily realized (configured).

[0048] Furthermore, in the p-channel field-effect transistor TR, it is more preferable that the work function of the gate electrode GA is 4.9 eV or more. As shown in Figure 6, when the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is 55 at% or more, the work function of the conductive layer 81 is 4.9 eV or more. In this way, the predetermined metal compound is titanium nitride (TiN), the predetermined element is oxygen (O), and the oxygen concentration in the titanium oxynitride (TiON) of the conductive layer 81 is 55 at% or more and less than 100 at%, so that a p-channel field-effect transistor TR suitable for high-speed applications can be easily realized (configured).

[0049] The structure of the structure CS is not limited to the example shown in Fig. 4. For example, as shown in Fig. 7, the structure CS may further include an adjustment layer 83 in addition to the channel layer 30a, the gate insulating layer 70, and the conductive layer 81.

[0050] The adjustment layer 83 is for adjusting the concentration of a predetermined element in the conductive layer 81. The adjustment layer 83 is in contact with the conductive layer 81, and when the predetermined element is oxygen (O), the adjustment layer 83 contains an element that can reduce a metal element in a predetermined metal compound in the conductive layer 81. By including the adjustment layer 83 in the structure CS, even when it is difficult to directly control the concentration of the predetermined element in the conductive layer 81, the work function of the gate electrode GA can be changed and the threshold voltage of the field-effect transistor TR can be controlled.

[0051] [Method of Manufacturing Semiconductor Device] Next, a method of manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. 8 to 18 . FIG. 8 is a flowchart showing a first example of a method of manufacturing the semiconductor device 100 according to one embodiment. FIG. 9 is an enlarged cross-sectional view of a main portion for explaining the formation of the gate insulating film 70 in the first example of the method of manufacturing the semiconductor device 100 shown in FIG. 8 . FIGS. 10 to 12 are enlarged cross-sectional views of a main portion for explaining the formation of the conductive layers 81, 81′ in the first example of the method of manufacturing the semiconductor device 100 shown in FIG. 8 . FIG. 13 is a flowchart showing a second example of a method of manufacturing the semiconductor device 100 according to one embodiment. FIGS. 14 to 18 are enlarged cross-sectional views of a main portion for explaining the formation of the conductive layers 81, 81″ and the adjustment layers 83′, 83″ in the second example of the method of manufacturing the semiconductor device 100 shown in FIG. 13 . For ease of explanation, FIGS. 9 to 12 and 14 to 18 only show a portion of the semiconductor device 100 manufactured by the manufacturing method. Furthermore, in the following description, unless otherwise specified, the semiconductor device 100 is considered to include both an n-channel field-effect transistor TR and a p-channel field-effect transistor TR, and the region corresponding to the n-channel field-effect transistor is referred to as an "n-channel transistor region," and the region corresponding to the p-channel field-effect transistor is referred to as a "p-channel transistor region."

[0052] First Example First, a first example of a manufacturing method for a semiconductor device 100 will be described. As shown in FIG. 8 , the manufacturing method S200 first forms the source electrode SO and the drain electrode DR of the field-effect transistor TR (S210). Specifically, as described above, they are formed on the semiconductor substrate 10 on which the insulating layer 20 is formed, as shown in FIGS. 1 and 2 . In step S210, multiple nanosheets 30, which form a current path between the source electrode SO and the drain electrode DR, are also formed. For details of this step, a method disclosed in, for example, H. Mertens et al., “Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates,” VLSI Symp. Tech. Dig. (2016) can be used. The contents of this document are incorporated herein by reference.

[0053] In step S210, an example of forming the source electrode SO and the drain electrode DR of the field-effect transistor TR has been described, but the present invention is not limited to this. For example, the source electrode SO and the drain electrode DR may be formed separately in a step of forming the source electrode SO of the field-effect transistor TR and a step of forming the drain electrode DR of the field-effect transistor TR.

[0054] Next, the gate electrode GA of the field-effect transistor TR is formed. As described above, the gate electrode GA has a plurality of structures CS covered with the metal gate 60, and each structure CS includes a channel layer 30 a, a gate insulating layer 70, and a conductive layer 81.

[0055] The process of forming the gate electrode GA of the field effect transistor TR is divided into the following steps.

[0056] 8, a gate insulating layer 70 is formed in contact with the channel layer 30a (S221). That is, as shown in Fig. 9, a gate insulating layer 70 is formed in contact with the channel layer 30a in each of the n-channel transistor region and the p-channel transistor region. Specifically, a hafnium oxide (HfO ２ A compound having a high relative dielectric constant, such as SiO 2 , is deposited to form the gate insulating layer 70. The thickness of the gate insulating layer 70 is, for example, in the range of 2 nm or more to 5 nm or less.

[0057] Returning to FIG. 8 , next, a conductive layer 81 is formed on the gate insulating layer 70, containing a predetermined metal compound as a main component and a predetermined element (S222). Specifically, as shown in FIG. 10 , a predetermined metal compound such as titanium nitride (TiN) is deposited around the gate insulating layer 70 by, for example, atomic layer deposition, chemical vapor deposition, or the like, to form the conductive layer 81. The thickness of the conductive layer 81 is, for example, in the range of 2 nm to 20 nm. This predetermined metal compound such as titanium nitride (TiN) has a work function suitable for an n-channel field-effect transistor TR, for example, approximately 4 to 4.5 eV. The work function can be controlled by the concentration of added oxygen, as shown in FIG. 6 . For example, when titanium nitride (TiN) is used as the predetermined metal compound, the oxygen concentration is set to 33 atom % or less.

[0058] 8 , next, a predetermined element is added to the predetermined metal compound of the conductive layer 81 (S223). More specifically, in the p-channel transistor region, the predetermined element is added to the predetermined metal compound of the conductive layer 81, while in the n-channel transistor region, a mask layer 89 is formed on the surface of the conductive layer 81 opposite to the surface in contact with the gate insulating layer 70. Specifically, when the predetermined element is oxygen (O), as shown in FIG. 11 , a mask layer 89 made of, for example, SiN, which does not contain oxygen and serves as an oxygen barrier, is formed on the surface of the conductive layer 81 in the n-channel transistor region.

[0059] Next, as shown in FIG. 12 , the conductive layer 81 is subjected to a heat treatment in an oxygen atmosphere or to oxidation by wet processing, thereby adding oxygen (O) to a predetermined metal compound of the conductive layer 81 in the p-channel transistor region, resulting in a conductive layer 81′ with a different oxygen concentration compared to the conductive layer 81 in step S222. As a result of step S223, if the conductive layer 81′ is formed by adding a predetermined element such as oxygen to a predetermined metal compound such as titanium nitride (TiN), the conductive layer 81′ changes to have a work function suitable for a p-channel field-effect transistor TR, for example, approximately 4.7 to 5 eV. As shown in FIG. 6 , this work function can be controlled by the concentration of the predetermined element added. Meanwhile, since a mask layer 89 is formed in the n-channel transistor region, oxygen (O) is not added to the conductive layer 81 in the n-channel transistor region, and the conductive layer 81 remains as it was in step S222. After adding oxygen (O) to the p-channel transistor region, the mask layer 89 in the n-channel transistor region is removed. In this manner, the structure CS is formed.

[0060] 8, next, the structure CS formed in step S223 is covered with a metal gate 60 (S224). As a result of performing step S224, the gate electrode GA of the field effect transistor TR can be formed.

[0061] After step S224, the manufacturing method S200 ends.

[0062] In this embodiment, an example has been shown in which the source electrode SO and drain electrode DR of the field effect transistor TR are formed, and then the gate electrode GA of the field effect transistor TR is formed, but this is not limited to this. For example, the source electrode SO and drain electrode DR of the field effect transistor TR may be formed after the gate electrode GA of the field effect transistor TR is formed. In this case, the nanosheet 30 is prepared in advance before forming the gate electrode GA of the field effect transistor TR.

[0063] Furthermore, when the semiconductor device 100 includes either an n-channel field effect transistor TR or a p-channel field effect transistor TR, after step S222, step S223 may be skipped and step S224 may be performed.

[0064] Thus, in the first example of the method for manufacturing the semiconductor device 100, forming the conductive layers 81, 81′ includes adding a predetermined element to a predetermined metal compound of the conductive layer 81. This allows the concentrations of the predetermined element, such as oxygen, to be appropriately adjusted in the conductive layer 81 in the n-channel transistor region and the conductive layer 81′ in the p-channel transistor region, making it possible to easily realize (manufacture) the semiconductor device 100 including the n-channel field-effect transistor TR and the p-channel field-effect transistor TR having different threshold voltages.

[0065] Second Example Next, a second example of the method for manufacturing the semiconductor device 100 will be described. In the manufacturing method S250, which is the second example of the method for manufacturing the semiconductor device 100, steps that are the same as or similar to those in the manufacturing method S200 of the first example are denoted by the same or similar reference numerals, and their description will be omitted as appropriate. Furthermore, similar effects due to similar configurations will not be mentioned sequentially.

[0066] 13 , after step S221, a conductive layer 81 is formed on the gate insulating layer 70, the conductive layer 81 containing a predetermined metal compound as a main component and a predetermined element (S232). Specifically, as in the first example, a predetermined metal compound such as titanium nitride (TiN) is deposited around the gate insulating layer 70 by, for example, atomic layer deposition, chemical vapor deposition, or the like, to form the conductive layer 81. The difference from the first example is that the predetermined metal compound such as titanium nitride (TiN) used in the conductive layer 81 is controlled by the concentration of added oxygen using the relationship shown in FIG. 6 so that the predetermined metal compound has a work function suitable for a p-channel field-effect transistor TR, for example, approximately 4.7 to 5.1 eV.

[0067] Next, an adjustment layer 83 is formed in contact with the conductive layer 81 (S233-1). Specifically, as shown in FIG. 14 , the adjustment layer 83 is formed on the surface of the conductive layer 81 opposite to the surface in contact with the gate insulating film 70. The adjustment layer contains an element that can reduce a metal element in a predetermined metal compound that constitutes the conductive layer 81, specifically, an element whose absolute value of the enthalpy of formation of an oxide is larger than that of the metal element in the predetermined metal compound that constitutes the conductive layer 81.

[0068] 15, a mask layer 89 is formed on the adjustment layer 83 of the conductive layer 81 in the n-channel transistor region. Specifically, when the predetermined element is oxygen (O), a mask layer 89 made of, for example, SiN, which does not contain oxygen and serves as an oxygen barrier, is formed on the adjustment layer 83 on the conductive layer 81 in the n-channel transistor region.

[0069] 16, a predetermined element such as oxygen is added to adjustment layer 83 in the p-channel transistor region by heat treatment in an oxygen atmosphere or by oxidation by wet treatment, to form adjustment layer 83' having a different oxygen concentration compared to adjustment layer 83 in step S233-1. At this time, since mask layer 89 is formed in the n-channel transistor region, the predetermined element is not added to adjustment layer 83 in the n-channel transistor region, and adjustment layer 83 remains as it was in step S233-1.

[0070] Next, as shown in FIG. 17, the mask layer 89 is removed from above the adjustment layer 83 of the conductive layer 81 in the n-channel transistor region.

[0071] Returning to FIG. 13 , next, a portion of the predetermined element in the conductive layer 81 is removed by the adjustment layer 83 (S233-2). Specifically, as shown in FIG. 18 , by performing heat treatment in an atmosphere that does not contain oxygen, such as nitrogen, the predetermined element, such as oxygen, in the conductive layer 81 in the n-channel transistor region migrates into the adjustment layer 83, and a portion of the predetermined element in the conductive layer 81 is removed. This is because the adjustment layer 83 contains an element that can reduce a metal element in the predetermined metal compound that constitutes the conductive layer 81. As a result of the migration of the predetermined element, the conductive layer 81 becomes a conductive layer 81″ in which the concentration of the predetermined element, such as oxygen, is reduced compared to the original conductive layer 81. For example, if the conductive layer 81 is made of titanium nitride (TiN), the conductive layer 81 has a work function, such as 4 to 4.5 eV, that is suitable for an n-channel field-effect transistor TR. Furthermore, as a result of this migration, the adjustment layer 83 before step S233-2 becomes an adjustment layer 83″ in which the concentration of the predetermined element, such as oxygen, is increased.

[0072] On the other hand, in the p-channel transistor region, the migration of predetermined elements, such as oxygen, in the conductive layer 81 into the adjustment layer 83 is inhibited. This is because, in the p-channel transistor region, the adjustment layer 83 formed in step S233-1 is formed as the adjustment layer 83' by adding a predetermined element, such as oxygen. Therefore, the reduction ability of the elements in the adjustment layer 83', which can reduce the metal elements in the predetermined metal compound constituting the conductive layer 81, i.e., their ability to remove oxygen from other elements, is reduced. As a result, even after the heat treatment, the concentration of the predetermined element, such as oxygen, in the conductive layer 81 in the p-channel transistor region remains unchanged from before the heat treatment. When the conductive layer 81 is a predetermined metal compound, such as titanium nitride (TiN), the work function, for example, approximately 4.7 to 5.1 eV, is maintained, which is suitable for a p-channel field-effect transistor TR. When the conductive layer 81 is a predetermined metal compound, such as titanium nitride (TiN), its work function can be controlled by the concentration of the predetermined element added, as shown in FIG. 6 . In this manner, the structure CS is formed.

[0073] 13, next, the structure CS formed in step S233-2 is covered with a metal gate 60 (S224). As a result of performing step S224, the gate electrode GA of the field effect transistor TR can be formed.

[0074] After step S224, the manufacturing method S250 ends.

[0075] In this embodiment, an example has been shown in which the source electrode SO and drain electrode DR of the field effect transistor TR are formed, and then the gate electrode GA of the field effect transistor TR is formed, but this is not limited to this. For example, the source electrode SO and drain electrode DR of the field effect transistor TR may be formed after the gate electrode GA of the field effect transistor TR is formed. In this case, the nanosheet 30 is prepared in advance before forming the gate electrode GA of the field effect transistor TR.

[0076] Furthermore, if the semiconductor device 100 includes either an n-channel field effect transistor TR or a p-channel field effect transistor TR, after step S232, steps S233-1 and S233-2 may be skipped and step S224 may be performed.

[0077] Thus, in the second example of the method for manufacturing the semiconductor device 100, forming the conductive layers 81, 81" includes forming the adjustment layer 83 in contact with the conductive layer 81 and removing a portion of the predetermined element in the conductive layer 81 by the adjustment layer 83. This allows the concentrations of the predetermined element, such as oxygen, to be appropriately adjusted in the conductive layer 81" in the n-channel transistor region and the conductive layer 81 in the p-channel transistor region, making it possible to easily realize (manufacture) the semiconductor device 100 including the n-channel field-effect transistor TR and the p-channel field-effect transistor TR having different threshold voltages.

[0078] The above describes exemplary embodiments of the present invention. In the semiconductor device 100 according to one embodiment of the present invention, the conductive layer 81 is in contact with the gate insulating layer 70, contains a predetermined metal compound as a main component, and includes a predetermined element having an electronegativity that is 0.5 or more greater than the effective electronegativity of the predetermined metal compound. This results in a difference in electronegativity of 0.5 or more between the predetermined metal compound, which is the main component, and the predetermined element contained in the conductive layer 81, making it possible to significantly change the work function of the structure CS of the gate electrode GA. Therefore, by changing the work function of the gate electrode GA, the threshold voltage of the field-effect transistor TR can be controlled and set to an appropriate value. Furthermore, by controlling the threshold voltage without changing the thickness of the gate electrode GA, the semiconductor device 100 can be miniaturized and power consumption can be reduced.

[0079] Furthermore, in the method for manufacturing the semiconductor device 100 according to one embodiment of the present invention, the step of forming the gate electrode GA includes forming a conductive layer 81, 81′, 81″ in contact with the gate insulating layer 70, the conductive layer 81 including a predetermined metal compound as a main component and a predetermined element having an electronegativity 0.5 or more greater than the effective electronegativity of the predetermined metal compound. This results in a difference in electronegativity of 0.5 or more between the predetermined element contained in the conductive layer 81, 81′, 81″ and the predetermined metal compound as a main component, making it possible to significantly change the work function of the structure CS of the gate electrode GA. Therefore, by changing the work function of the gate electrode GA, the threshold voltage of the field-effect transistor TR can be controlled and set to an appropriate value. Furthermore, by controlling the threshold voltage without changing the thickness of the gate electrode GA, the semiconductor device 100 can be miniaturized and its power consumption can be reduced.

[0080] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the scope of the present invention. The present invention may be modified or improved without departing from its spirit, and equivalents are also included within the scope of the present invention. In other words, designs modified by those skilled in the art as appropriate are also encompassed within the scope of the present invention as long as they incorporate the characteristics of the present invention. For example, the elements of the embodiments, their arrangement, materials, conditions, shapes, sizes, etc., are not limited to those illustrated and can be modified as appropriate. Furthermore, the embodiments are merely examples, and partial substitution or combination of the configurations shown in different embodiments is, of course, possible. These are also encompassed within the scope of the present invention as long as they incorporate the characteristics of the present invention.

[0081] 10...semiconductor substrate, 20...insulating layer, 30...nanosheet, 30a...channel layer, 40...spacer, 50...contact, 60...metal gate, 70...gate insulating layer, 81, 81', 81''...conductive layer, 83, 83', 83''...adjustment layer, 89...mask layer, 100...semiconductor device, CS...structure, DR...drain electrode, GA...gate electrode, SO...source electrode, S200...manufacturing method, S250...manufacturing method, TR...field effect transistor.

Claims

1. A semiconductor device comprising a field effect transistor, wherein the gate stack of the field effect transistor has a structure including a channel layer, a gate insulating layer in contact with the channel layer, and a conductive layer in contact with the gate insulating layer and containing a predetermined metal compound as a main component, and the conductive layer further contains a predetermined element having an electronegativity that is 0.5 or more higher than the effective electronegativity of the predetermined metal compound.

2. The semiconductor device according to claim 1, wherein the effective electronegativity of the predetermined metal compound is 2.5 or less.

3. The semiconductor device according to claim 1, wherein the work function of the predetermined metal compound is 4.3 eV or less.

4. The semiconductor device according to claim 1, wherein the predetermined metal compound is any one of titanium nitride, titanium carbide, tantalum carbide, tantalum nitride, hafnium nitride, niobium carbide, niobium nitride, zirconium carbide, and zirconium nitride.

5. The semiconductor device according to claim 1, wherein the electronegativity of the predetermined element is 3 or more.

6. The semiconductor device according to claim 5, wherein the predetermined element is oxygen.

7. The semiconductor device according to claim 1, wherein the field effect transistor is an n-channel field effect transistor, the predetermined metal compound is titanium nitride, the predetermined element is oxygen, and the concentration of oxygen in the conductive layer is greater than 0 at % and not greater than 33 at %.

8. The semiconductor device according to claim 1, wherein the field effect transistor is an n-channel field effect transistor, the predetermined metal compound is titanium nitride, the predetermined element is oxygen, and the concentration of oxygen in the conductive layer is greater than 0 at % and not greater than 25 at %.

9. The semiconductor device according to claim 1, wherein the field effect transistor is an n-channel field effect transistor, the predetermined metal compound is titanium nitride, the predetermined element is oxygen, and the concentration of oxygen in the conductive layer is greater than 0 at % and not more than 20 at %.

10. The semiconductor device according to claim 1, wherein the field effect transistor is a p-channel field effect transistor, the predetermined metal compound is titanium nitride, the predetermined element is oxygen, and the concentration of oxygen in the conductive layer is 45 at % or more and less than 100 at %.

11. The semiconductor device according to claim 1, wherein the field effect transistor is a p-channel field effect transistor, the predetermined metal compound is titanium nitride, the predetermined element is oxygen, and the concentration of oxygen in the conductive layer is equal to or greater than 50 at % and less than 100 at %.

12. The semiconductor device according to claim 1, wherein the field effect transistor is a p-channel field effect transistor, the predetermined metal compound is titanium nitride, the predetermined element is oxygen, and the concentration of oxygen in the conductive layer is 55 at % or more and less than 100 at %.

13. The semiconductor device according to claim 1, wherein the structure further includes an adjustment layer in contact with the conductive layer for adjusting the concentration of the predetermined element in the conductive layer.

14. The semiconductor device according to claim 1, wherein the main component of the gate insulating layer is a compound having a relative dielectric constant of 4 or more.

15. The semiconductor device according to any one of claims 1 to 14, wherein the main component of the gate insulating layer is hafnium oxide.

16. A method for manufacturing a semiconductor device, comprising: a step of forming a source electrode and a drain electrode of a field effect transistor; and a step of forming a gate stack for the field effect transistor, the gate stack having a structure including a channel layer, a gate insulating layer, and a conductive layer, wherein the step of forming the gate stack comprises: forming the gate insulating layer in contact with the channel layer; and forming the conductive layer in contact with the gate insulating layer, the conductive layer containing a predetermined metal compound as a main component and a predetermined element having an electronegativity that is 0.5 or more higher than the effective electronegativity of the predetermined metal compound.

17. The method for manufacturing a semiconductor device according to claim 16, wherein forming the conductive layer includes adding the predetermined element to the predetermined metal compound.

18. The method for manufacturing a semiconductor device according to claim 16, wherein forming the conductive layer includes forming an adjustment layer in contact with the conductive layer, and removing a portion of the predetermined element in the conductive layer by using the adjustment layer.

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