Semiconductor device

Abstract

The present invention enables the switching characteristics of a semiconductor device to be improved. A semiconductor device (1A) comprises: a plurality of transistor chips (3); an electrically conductive plate (41d) having the plurality of transistor chips (3) mounted on one surface side thereof; and a wiring substrate (20) disposed on said one surface side of the electrically conductive plate (41d) so as to be spaced apart from the chips (3). Furthermore: the wiring substrate (20) includes a control electrically conductive portion (23g), a main electrically conductive portion (23s), and a detection electrically conductive portion (21sd); a control electrode (4g) of each of the plurality of chips (3) is electrically connected to the control electrically conductive portion (23g) of the wiring substrate (20) via a control electrode pin (11g), for each chip (3); and a first main electrode (4s) of each of the plurality of chips (3) is electrically connected to the main electrically conductive portion (23s) of the wiring substrate (20) via a main electrode pin (11s), for each chip (3), and is electrically connected to the detection electrically conductive portion (21sd) of the wiring substrate (20) via a detection electrode pin (11sd), for each chip (3). Furthermore, the main electrically conductive portion (23s) and the detection electrically conductive portion (21sd) are electrically separated from each other in the wiring substrate (20).

Description

Semiconductor Devices

[0001] The present technology (technology according to the present disclosure) relates to a semiconductor device, and in particular to a technology that is effective when applied to a semiconductor device having a plurality of transistor chips connected in parallel.

[0002] A semiconductor device includes a switching element such as an IGBT and control wiring such as a gate wiring and a source sense wiring. In such a device, a resistance is sometimes provided in the control wiring to suppress oscillation of the gate voltage (see, for example, Patent Documents 1, 2, and 3).

[0003] JP 2009-130186 A JP 2018-74088 A JP 2019-91850 A

[0004] An object of the present technology is to provide a technology that can improve the switching characteristics of a semiconductor device.

[0005] A semiconductor device according to one aspect of the present technology includes: a plurality of transistor chips, each having a first main electrode, a second main electrode, and a control electrode; a conductive plate on one side of which the plurality of transistor chips are mounted; and a wiring substrate disposed on the transistor chip side of the conductive plate at a distance from the transistor chips. The wiring substrate includes a control conductive portion, a main conductive portion, and a detection conductive portion, and the control electrode of each of the plurality of transistor chips is electrically connected to the control conductive portion of the wiring substrate via a control electrode pin for each transistor chip, and the first main electrode of each of the plurality of transistor chips is electrically connected to the main conductive portion of the wiring substrate via a main electrode pin for each transistor chip and is also electrically connected to the detection conductive portion of the wiring substrate via a detection electrode pin for each transistor chip. The main conductive portion and the detection conductive portion are electrically separated on the wiring substrate.

[0006] According to one aspect of the present technology, it is possible to improve the switching characteristics of a semiconductor device.

[0007] 9A is an equivalent circuit diagram showing an example of a semiconductor device according to a first embodiment of the present technology. FIG. 9B is a plan view schematically showing an external configuration of the semiconductor device according to the first embodiment of the present technology. FIG. 9C is a plan view schematically showing an internal configuration of the semiconductor device according to the first embodiment of the present technology. FIG. 9D is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the IV-IV cutting line of FIG. 3. FIG. 4 is a longitudinal cross-sectional view selectively enlarging the left side of FIG. 4. FIG. 4 is a longitudinal cross-sectional view selectively enlarging the right side of FIG. 4. FIG. 9E is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the VI-VI cutting line of FIG. 3. FIG. 9F is a longitudinal cross-sectional view schematically showing a longitudinal cross-sectional structure taken along the VII-VII cutting line of FIG. 3. FIG. 9G is a plan view schematically showing a configuration of a transistor chip side of a support substrate in a semiconductor device according to a first embodiment of the present technology. FIG. 9H is a plan view schematically showing a conductive portion pattern on a front surface side of a wiring substrate in a semiconductor device according to a first embodiment of the present technology. FIG. 9H is a plan view selectively enlarging a part of FIG. 9A. FIG. 9H is a plan view seen through the conductive portion pattern on a back surface side of the wiring substrate in FIG. 9A from the front surface side. FIG. 1 is a conductive path diagram schematically showing a chip-to-terminal conductive path that electrically connects an electrode of a chip and a terminal pin in a semiconductor device according to a first embodiment of the present technology. FIG. 2 is a conductive path diagram schematically showing an inter-chip conductive path that electrically connects two transistor chips in a semiconductor device according to a first embodiment of the present technology. FIG. 3 is an equivalent circuit diagram when an electrode pin that is the same as a source electrode pin is used as a detection electrode pin in a semiconductor device according to a first embodiment of the present technology. FIG. 4 is an equivalent circuit diagram when an electrode pin having a higher resistance than a source electrode pin is used as a detection electrode pin in a semiconductor device according to a first embodiment of the present technology. FIG. 5 is a plan view showing an enlarged portion of a wiring substrate, according to a modified example 1-1 of the first embodiment of the present technology. FIG. 6 is a plan view showing an enlarged portion of a wiring substrate, according to a modified example 1-2 of the first embodiment of the present technology. FIG. 7 is a plan view showing an enlarged portion of a wiring substrate, according to a modified example 1-3 of the first embodiment of the present technology. FIG. 8 is a longitudinal cross-sectional view showing a schematic portion of a longitudinal cross-sectional structure, according to a modified example 1-4 of the first embodiment of the present technology. FIG. 9 is a longitudinal cross-sectional view showing a schematic portion of a longitudinal cross-sectional structure, according to a modified example 1-5 of the first embodiment of the present technology. FIG. 10 is a longitudinal cross-sectional view schematically illustrating a longitudinal cross-sectional structure of a modified example 1-6 according to the first embodiment of the present technology.

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description.

[0009] Furthermore, it goes without saying that the dimensional relationships and ratios may differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0010] Furthermore, the following embodiments exemplify devices and methods for embodying the technical idea of ​​the present technology, and do not limit the configuration to the following. In other words, the technical idea of ​​the present technology can be modified in various ways within the technical scope described in the claims.

[0011] Furthermore, the definitions of directions such as up and down in the following description are merely for the sake of convenience and do not limit the technical concept of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if an object is rotated 180 degrees and observed, up and down are obviously read as reversed.

[0012] In the following embodiments, among the three mutually orthogonal directions in space, a first direction and a second direction that are mutually orthogonal in the same plane are defined as the X direction and the Y direction, respectively, and a third direction that is orthogonal to each of the first and second directions is defined as the Z direction. In the following embodiments, the stacking direction of a support substrate and a wiring substrate, which will be described later, will be described as the Z direction.

[0013] In this specification, when a transistor mounted on a transistor chip is a field-effect transistor (FET) or a static induction transistor (SIT), a first main electrode refers to either a source electrode or a drain electrode, a second main electrode refers to the other electrode, and a control electrode refers to a gate electrode. When a transistor mounted on a transistor chip is a bipolar junction transistor (BJT), a first main electrode refers to either an emitter electrode or a collector electrode, a second main electrode refers to the other electrode, and a control electrode refers to a base electrode. When a transistor mounted on a transistor chip is an insulated gate bipolar transistor (IGBT), a first main electrode refers to either an emitter electrode or a collector electrode, a second main electrode refers to the other electrode, and a control electrode refers to a gate electrode. In the following embodiments, the description will be focused on a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) as a transistor mounted on a transistor chip, and therefore the first main electrode will be described as a source electrode, the second main electrode as a drain electrode, and the control electrode as a gate electrode.

[0014] First Embodiment In this first embodiment, an example will be described in which the present technology is applied to a one-element package type (1-in-1 type) semiconductor device that includes a set of a switching element and a rectifier element, as a semiconductor power device used in a power conversion device or the like.

[0015] In addition, in the first embodiment, the first main electrode of the transistor chip is described as a source electrode, and the second main electrode is described as a drain electrode.

[0016] <<Overall Configuration of Semiconductor Device>> First, the overall configuration of the semiconductor device 1A will be described.

[0017] As shown in FIG. 1, a semiconductor device 1A according to a first embodiment of the present technology includes a switching element Tr and a rectifying element Di connected in reverse in parallel to the switching element Tr.

[0018] Also, as shown in FIG. 1 , the semiconductor device 1A according to the first embodiment of the present technology has a source terminal S, a drain terminal D, and a gate terminal G, and further has a detection terminal Sd for detecting the voltage on the source terminal S side, etc.

[0019] The source terminal S corresponds to a source terminal pin 51s (see FIG. 2) described later. The drain terminal D corresponds to a drain terminal pin 51d (see FIG. 2) described later. The gate terminal G corresponds to a gate terminal pin 51g (see FIG. 2) described later. The detection terminal Sd corresponds to a detection terminal pin 51sd (see FIG. 2) described later.

[0020] 1, the rectifying element Di has an anode electrode A and a cathode electrode K. The anode electrode A is electrically connected to a source terminal S. The cathode electrode K is electrically connected to a drain terminal D.

[0021] The switching element Tr is configured by connecting multiple transistor chips 3 shown in Fig. 4 in parallel to increase the current capacity, and the rectifying element Di is configured by connecting multiple diode chips 5 shown in Fig. 4 in parallel to increase the rectifying capacity.

[0022] The switching element Tr is preferably a vertical semiconductor element having an insulated gate structure, such as a MIS transistor or an IGBT, in which a main current flows in the depth direction (thickness direction) of the transistor chip 3. The rectifying element Di is preferably a vertical semiconductor element such as a fast recovery diode (FRD) or a Schottky barrier diode (SBD). In this first embodiment, the switching element Tr is a vertical MISFET having an insulated gate structure, which is mainly made of a semiconductor substrate made of, for example, silicon carbide (SiC), and the rectifying element Di is an SBD, which is mainly made of a semiconductor substrate made of, for example, SiC.

[0023] The MIS transistor mounted on the transistor chip 3 is a concept that includes MOSFETs, MISSITs, etc. A silicon oxide film (SiO ２In contrast to a MOS transistor that uses an insulating film other than a silicon oxide film as a gate insulating film, a MIS transistor refers to a more comprehensive insulated gate transistor.

[0024] The gate insulating film of the MIS transistor may be a silicon oxynitride film (SiON film), a strontium oxide film (SrO film), a silicon nitride film (Si ３ N ４ film), aluminum oxide film (Al ２ O ３ Alternatively, a magnesium oxide film (MgO film) or an yttrium oxide film (Y film) can be used. ２ O ３ film), hafnium oxide film (HfO ２ film), zirconium oxide film (ZrO ２ film), tantalum oxide film (Ta ２ O ５ film), bismuth oxide film (BI ２ O ３ Furthermore, composite membranes in which several of these single layer membranes are selected and different types of membranes are laminated may also be used.

[0025] As the semiconductor material, in addition to SiC, semiconductor materials such as silicon (Si), gallium nitride (GaN), diamond, and aluminum nitride (AlN) can be used.

[0026] <Specific Configuration of Semiconductor Device> Next, a specific configuration of the semiconductor device 1A according to the first embodiment of the present technology will be described.

[0027] 2 to 7, the semiconductor device 1A according to the first embodiment includes a substrate stack 2 and a resin sealing body 60 that seals the substrate stack 2. The semiconductor device 1A according to the first embodiment also includes terminal pins that extend from the inside to the outside of the resin sealing body 60, such as a drain terminal pin 51 d, a gate terminal pin 51 g, a source terminal pin 51 s, and a detection terminal pin 51 sd.

[0028] 2 to 7 , the substrate laminate 2 includes a support substrate 40, a plurality of transistor chips 3 and a plurality of diode chips 5 mounted on one surface of the support substrate 40, and a wiring substrate 20 disposed on one surface of the support substrate 40 at a distance from the transistor chips 3 and the diode chips 4. The support substrate 40 and the wiring substrate 20 are stacked in the Z direction.

[0029] The substrate stack 2 also includes, as chip-to-substrate internal pins located between the transistor chip 3 and the diode chip 5 and the wiring substrate 20, a gate electrode pin 11g (see FIG. 6), a source electrode pin 11s (see FIGS. 4 and 5A), a detection electrode pin 11sd (see FIGS. 4 and 5A), an anode electrode pin 12a (see FIGS. 4 and 5B), and the like.

[0030] The substrate laminate 2 also includes, as inter-substrate internal pins located between the support substrate 40 and the wiring substrate 20, gate conductive pins 31g (see Figure 6), source conductive pins 31s (see Figures 4 and 5B), and detection conductive pins 31sd (see Figures 4 and 5A).

[0031] In the first embodiment, the gate electrode pin 11g, the source electrode pin 11s, and the detection electrode pin 11sd correspond to specific examples of a "control electrode pin," a "main electrode pin," and a "detection pin" in the present technology, and the drain terminal pin 51d, the gate terminal pin 51g, the source terminal pin 51s, and the detection terminal pin 51sd correspond to specific examples of a "second main terminal pin," a "control terminal pin," a "first main terminal pin," and a "detection terminal pin" in the present technology.

[0032] 2 and 3, the resin encapsulant 60 has a square, e.g., rectangular, planar shape in plan view. The resin encapsulant 60 has two short sides located opposite each other in the longitudinal direction, which is the X direction, and extending in the lateral direction, which is the Y direction orthogonal to the X direction, and two long sides located opposite each other in the Y direction and extending in the X direction.

[0033] 4 to 7, the resin encapsulant 60 has a thickness in the Z direction perpendicular to the X and Y directions. The resin encapsulant 60 can be molded by, for example, a transfer molding method using an epoxy-based thermosetting insulating resin.

[0034] The resin sealing body 60 has a thickness in the Z direction, and has a main surface portion and a back surface portion located on opposite sides in the Z direction. In the first embodiment, the resin sealing body 60 corresponds to a specific example of a “sealing body” of the present technology.

[0035] <Support Substrate> As shown in Figures 2 and 3, the support substrate 40 has a square, e.g., rectangular, planar shape in a plan view. The support substrate 40 has two short sides located opposite each other in the longitudinal direction, which is the X direction, and extending in the lateral direction, which is the Y direction perpendicular to the X direction, and two long sides located opposite each other in the Y direction and extending in the X direction. As shown in Figures 4 to 7, the support substrate 40 has a thickness in the Z direction, which is perpendicular to the X and Y directions. As shown in Figures 2 and 3, the extension directions of the two short sides of the support substrate 40 coincide with the extension directions of the two short sides of the resin encapsulant 60, and the extension directions of the two long sides of the support substrate 40 coincide with the extension directions of the two long sides of the resin encapsulant 60.

[0036] As shown in Figures 4 to 7, the support substrate 40 has an insulating plate 42 having a main surface portion and a back surface portion located opposite each other in the Z direction, a drain conductive plate 41d, a gate conductive plate 41g, a source conductive plate 41s, and a detection conductive plate 41sd which are conductive plates provided on the main surface side of the insulating plate 42, and a heat sink 43 provided on the back surface side of the insulating plate 42.

[0037] The support substrate 40 may be, for example, a direct copper bonded (DCB) substrate in which a metal is eutectic-bonded to each of the main surface and the back surface of a ceramic substrate, or an active metal brazing (AMB) substrate in which a metal is provided by an active metal brazing (AMB) method to each of the main surface and the back surface of a ceramic substrate. The material of the ceramic substrate may be, for example, silicon nitride (Si ３ N ４ ), aluminum nitride (AlN), alumina (Al２ O ３ The support substrate 40 of the first embodiment uses, for example, an aluminum nitride plate as the insulating plate 42, and uses, for example, copper (Cu) plates, which have excellent electrical and thermal conductivity, as the conductive plates (drain conductive plate 41 d, gate conductive plate 41 g, source conductive plate 41 s, detection conductive plate 41 sd) and the heat dissipation plate 43.

[0038] 8, the insulating plate 42 has a square, e.g., rectangular, planar shape in plan view. The insulating plate 42 has two short sides 42a and 42b located opposite each other in the X direction and extending in the Y direction perpendicular to the X direction, and two long sides 42c and 42d located opposite each other in the Y direction and extending in the X direction.

[0039] The extension direction of the two short sides 42a and 42b of the insulating plate 42 coincides with the extension direction of the two short sides of the resin encapsulant 60, and the extension direction of the two long sides 42c and 42d of the insulating plate 42 coincides with the extension direction of the two long sides of the resin encapsulant 60. In this first embodiment, the two short sides 42a and 42b and the two long sides 42c and 42d of the insulating plate 42 correspond to the two short sides and two long sides of the support substrate 40.

[0040] 8, the drain conductive plate 41d is disposed in the center of the insulating plate 42 in the X direction. The drain conductive plate 41d has, for example, a rectangular shape in a plan view. In the first embodiment, the drain conductive plate 41d corresponds to a specific example of a "conductive plate" of the present technology.

[0041] 8, the gate conductive plate 41g is disposed on the short side 42a side of one of the two short sides 42a and 42b of the insulating plate 42 and on the long side 42c side of one of the two long sides 42c and 42d of the insulating plate 42. The gate conductive plate 41g has a rectangular shape in a plan view.

[0042] 8, the detection conductive plate 41sd is disposed on the side of one of the two short sides 42a and 42b of the insulating plate 42, namely, the short side 42a, and on the side of the other of the two long sides 42c and 42d of the insulating plate 42. The gate conductive plate 41g has a rectangular shape in a plan view.

[0043] The gate conductive plate 41g and the detection conductive plate 41sd are arranged apart from each other in the Y direction in plan view and are electrically isolated from each other. The gate conductive plate 41g and the detection conductive plate 41sd are arranged apart from each other in the X direction in plan view and are electrically isolated from the drain conductive plate 41d.

[0044] 8, the source conductive plate 41s is disposed on the other of the two short sides 42a and 42b of the insulating plate 42, that is, the short side 42b. The source conductive plate 41s has a rectangular shape in a plan view. The source conductive plate 41s is spaced apart from and aligned with the drain conductive plate 41d in the X direction in a plan view, and is electrically isolated from the drain conductive plate 41d.

[0045] 4 to 7, the heat sink 43 has a rectangular planar shape in plan view, similar to the insulating plate 42, and its outer size is slightly smaller than that of the insulating plate 42. The heat sink 43 overlaps the drain conductive plate 41d, the gate conductive plate 41g, the source conductive plate 41s, and the detection conductive plate 41sd in plan view. In the first embodiment, the main surface (front surface (+Z direction surface)) of the heat sink 43 is joined to the back surface of the insulating plate 42, and the back surface (−Z direction surface) of the heat sink 43 opposite to the main surface is exposed from the back surface of the resin sealing body 60 opposite to the main surface. The support substrate 40 of the first embodiment is configured such that a drain conductive plate 41 d, a source conductive plate 41 s, a gate conductive plate 41 g, and a detection conductive plate 41 sd are provided as conductive plates on one insulating plate 42 and one heat dissipation plate 43. However, the insulating plate 42 and the heat dissipation plate 43 may be divided, for example, in accordance with the drain conductive plate 41 d, the source conductive plate 41 s, the gate conductive plate 41 g, and the detection conductive plate 41 sd.

[0046] 3, 4, and 5A, a plurality of transistor chips 3 are mounted on one surface side, which is the main surface side, of the support substrate 40. In this first embodiment, although not limited to this, for example, as shown in FIG. 8, the support substrate 40 has six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) arranged in a 3×2 array adjacent to each other in each of the X and Y directions in a plan view.

[0047] Each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, and 3f) is equipped with, for example, a vertical MISFET as a transistor. The transistors of each of the six transistor chips 3 are connected in parallel to form one switching element Tr shown in FIG.

[0048] Each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) has the same structural configuration. Referring to Figures 4, 5A, and 8, each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) has a first surface S1 and a second surface S2 located on opposite sides in the thickness direction, a source electrode 4s serving as a first main electrode provided on the first surface S1 side, a gate electrode 4g serving as a control electrode provided on the first surface S1 side, and a drain electrode 4d serving as a second main electrode provided on the second surface S2 side.

[0049] 4 and 5A, the drain electrodes 4d of each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, and 3f) are joined to a drain conductive plate 41d of the support substrate 40 with a conductive bonding material (e.g., solder material), and the chips are mounted on the drain conductive plate 41d. That is, the drain electrodes 4d of each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, and 3f) are electrically and mechanically connected to the drain conductive plate 41d and are connected in parallel via the drain conductive plate 41d.

[0050] 8, the source electrode 4s and the gate electrode 4g each have a rectangular shape in plan view that includes four sides. Although not shown in detail, the drain electrode 4d shown in FIG. 4 also has a rectangular shape in plan view that includes four sides.

[0051] 3, 4, and 5B, a plurality of diode chips 5 are mounted on the main surface side, which is one surface side, of the support substrate 40. In this first embodiment, although not limited to this, for example, as shown in FIG. 8, six diode chips 5 (5a, 5b, 5c, 5d, 5e, 5fg) are arranged in a 2×3 array adjacent to each other in each of the X direction and the Y direction in a plan view.

[0052] Each of the six diode chips 5 (5a, 5b, 5c, 5d, 5e, and 5f) is equipped with, for example, an SBD as a diode element. The diode elements of the six diode chips 5 are connected in parallel to form one rectifier element Di shown in FIG. 1.

[0053] Each of the six diode chips 5 (5a, 5b, 5c, 5d, 5e, 5f) has the same structural configuration. Referring to Figures 4, 5B, and 8, each of the six diode chips 5 (5a, 5b, 5c, 5d, 5e, 5f) has a third surface S3 and a fourth surface S4 located on opposite sides in the thickness direction (Z direction), an anode electrode 6a serving as a third main electrode provided on the third surface S3 side, and a cathode electrode 6k serving as a fourth main electrode provided on the fourth surface S4 side.

[0054] 4 and 5B, the cathode electrode 6k of each of the six diode chips 5 (5a, 5b, 5c, 5d, 5e, and 5f) is joined to the drain conductive plate 41d of the support substrate 40 with a conductive bonding material (e.g., solder material), and the chips are mounted on the drain conductive plate 41d. That is, the cathode electrode 6k of each of the six diode chips 5 (5a, 5b, 5c, 5d, 5e, and 5f) is electrically and mechanically connected to the drain conductive plate 41d, and is connected in parallel via the drain conductive plate 41d.

[0055] <Wiring Board> As shown in FIG. 3 , the wiring board 20 has a square, e.g., rectangular, planar shape in a planar view. The wiring board 20 has two short sides located opposite each other in the longitudinal direction, which is the X direction, and extending in the lateral direction, which is the Y direction, perpendicular to the X direction, and two long sides located opposite each other in the Y direction and extending in the X direction. As shown in FIG. 4 , the wiring board 20 has a thickness in the thickness direction, which is the Z direction, which is perpendicular to the X and Y directions. As shown in FIG. 3 , in a planar view, the extension directions of the two short sides of the wiring board 20 coincide with the extension directions of the two short sides of the resin encapsulant 60, and the extension directions of the two long sides of the wiring board 20 coincide with the extension directions of the two long sides of the resin encapsulant 60.

[0056] 3 to 7 , the wiring board 20 is, for example, a normal printed wiring board, but is not limited to, and has a two-layer wiring structure. Specifically, as shown in Fig. 3 to 7 , the wiring board 20 has an insulating plate 22 having a main surface portion and a back surface portion located opposite each other in the Z direction, a detection conductive portion 21sd as a conductive portion provided in a first wiring layer on the main surface side of the insulating plate 22, and a gate conductive portion 23g and a source conductive portion 23s as conductive portions provided in a second wiring layer on the back surface side of the insulating plate 22.

[0057] The detection conductive portion 21sd, the gate conductive portion 23g, and the source conductive portion 23s are each made of, for example, copper foil with a thickness of about 75 μm. The insulating plate 22 is made of, for example, an insulating resin substrate made of glass fiber impregnated with polyimide resin.

[0058] In the first embodiment, the gate conductive portion 23g, the source conductive portion 23s, and the detection conductive portion 21sd correspond to specific examples of the "control conductive portion," "main conductive portion," and "detection conductive portion" of the present technology.

[0059] 9A and 10, the insulating plate 22 has a square, e.g., rectangular, planar shape in plan view. The insulating plate 22 has two short sides 22a and 22b located opposite each other in the X direction and extending in the Y direction perpendicular to the X direction, and two long sides 22c and 22d located opposite each other in the Y direction and extending in the X direction.

[0060] The extension direction of the two short sides 22a and 22b of the insulating plate 22 coincides with the extension direction of the two short sides of the resin encapsulant 60, and the extension direction of the two long sides 22c and 22d of the insulating plate 22 coincides with the extension direction of the two long sides of the resin encapsulant 60. In this first embodiment, the outer periphery of the insulating plate 22 becomes the outer periphery of the wiring board 20 in a plan view, and therefore the two short sides 22a and 22b and the two long sides 22c and 22d of the insulating plate 22 become the two short sides and two long sides of the wiring board 20.

[0061] (Source conductive portion and gate electrode portion) As shown in Figure 10, the source conductive portion 23s of the wiring substrate 20 is configured as a plate-shaped planar pattern that overlaps, in a planar view, the source electrodes 4s of the six transistor chips 3 and the anode electrodes 6a of the six diode chips 5, and is also arranged to overlap the source conductive plate 41s of the support substrate 40.

[0062] As shown in FIG. 10 , the gate conductive portion 23 g of the wiring substrate 20 is configured as a linear planar pattern that overlaps with the gate electrodes 4 g of each of the six transistor chips 3 in a plan view and is routed so as to overlap with the gate conductive plate 41 g of the support substrate 40.

[0063] (Detection conductive portion) As shown in Figure 9A, the detection conductive portion 21sd of the wiring substrate 20 is composed of a linear conductive pattern that overlaps with the source electrodes 4s of each of the six transistor chips 3 in a planar view and is routed so as to overlap with the detection conductive plate 41sd of the support substrate 40.

[0064] The source conductive portion 23s shown in FIG. 10 and the gate conductive portion 23g shown in FIG.

[0065] 9A and the source conductive portion 23s and the gate conductive portion 23g shown in FIG. 10 are electrically separated from each other on the wiring substrate 20. In FIG.

[0066] 3 and 6 , a gate electrode pin 11g is provided for each transistor chip 3. The gate electrode pin 11g extends in the Z direction between the gate electrode 4g of the transistor chip 3 and the gate conductive portion 23g of the wiring substrate 20. The gate electrode pin 11g has two ends positioned opposite to each other, one end being electrically and mechanically connected to the gate conductive portion 23g of the wiring substrate 20, and the other end being electrically and mechanically connected to the gate electrode 4g of the transistor chip 3.

[0067] That is, the gate electrodes 4g of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) are electrically connected to the gate conductive portions 23g of the wiring substrate 20 via the gate electrode pins 11g, and are connected in parallel via the gate electrode pins 11g and the gate conductive portions 23g of the wiring substrate 20.

[0068] One end of the gate electrode pin 11g is press-fitted into a through-hole provided across the gate conductive portion 23g and the insulating plate 22, and is joined to the gate conductive portion 23g by this press-fitting. The other end of the gate electrode pin 11g is joined to the gate electrode 4g of the transistor chip 3 with a joining material (not shown) so as to abut against the gate electrode 4g from above. The joining material may be, for example, a solder material.

[0069] Although not limited to this, for example, one gate electrode pin 11g is provided for each transistor chip 3 (3a, 3b, 3c, 3d, 3e, 3f).

[0070] 3, 4, and 5A, a source electrode pin 11s is provided for each transistor chip 3. The source electrode pin 11s extends in the Z direction between the source electrode 4s of the transistor chip 3 and the source conductive portion 23s of the wiring substrate 20. The source electrode pin 11s has two ends, one of which is electrically and mechanically connected to the source conductive portion 23s of the wiring substrate 20, and the other end of which is electrically and mechanically connected to the source electrode 4s of the transistor chip 3. That is, the source electrodes 4s of each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, and 3f) are electrically connected to the source conductive portion 23s of the wiring substrate 20 via the respective source electrode pins 11s, and are connected in parallel via the respective source electrode pins 11s and the source conductive portions 23s of the wiring substrate 20.

[0071] One end of the source electrode pin 11s is press-fitted into a through-hole provided across the source conductive portion 23s and the insulating plate 22, and is joined to the source conductive portion 23s by this press-fitting. The other end of the source electrode pin 11s is joined to the source conductive portion 23s with a bonding material (not shown) in a state of abutting against the source electrode 4s of the transistor chip 3 from above. As the bonding material, for example, a solder material can be used.

[0072] In order to reduce the surface resistance of the device, a plurality of source electrode pins 11s are provided for each transistor chip 3 (3a, 3b, 3c, 3d, 3e, 3f). In the first embodiment, for example, eight source electrode pins 11s are provided for each transistor chip 3, although this is not limited to this.

[0073] 3, 4, and 5B, an anode electrode pin 12a is provided for each diode chip 5. The anode electrode pin 12a extends in the Z direction between the anode electrode 6a of the diode chip 5 and the source conductive portion 23s of the wiring substrate 20. The anode electrode pin 12a has two ends, one of which is electrically and mechanically connected to the source conductive portion 23s of the wiring substrate 20, and the other end of which is electrically and mechanically connected to the anode electrode 6a of the diode chip 5. That is, the anode electrode 6a of each of the six diode chips 5 (5a, 5b, 5c, 5d, 5e, and 5f) is electrically connected to the source conductive portion 23s of the wiring substrate 20 via the corresponding anode electrode pin 12a, and is connected in parallel via the corresponding anode electrode pin 12a and source conductive portion 23s. The anode electrodes 6a of the six diode chips 5 are electrically connected to the source electrodes 4s of the six transistor chips 3 via the anode electrode pins 12a, the source conductive portions 23s, and the source electrode pins 11s.

[0074] One end of the anode electrode pin 12a is press-fitted into a through-hole provided across the source conductive portion 23s and the insulating plate 22, and is joined to the source conductive portion 23s by this press-fitting. The other end of the anode electrode pin 12a is joined to the anode electrode 6a of the diode chip 5 with a bonding material (not shown) so as to abut against the anode electrode 6a from above. For example, a solder material can be used as the bonding material. To reduce the surface resistance of the device, multiple anode electrode pins 12a are provided for each diode chip 5 (5a, 5b, 5c, 5d, 5e, 5f). In this first embodiment, although not limited thereto, for example, two anode electrode pins 12a are provided for each diode chip 5.

[0075] 3, 4, and 5A, a detection electrode pin 11sd is provided for each transistor chip 3. The detection electrode pin 11sd extends in the Z direction between the source electrode 4s of the transistor chip 3 and the detection conductive portion 21sd of the wiring board 20. One end of the detection electrode pin 11sd is electrically and mechanically connected to the detection conductive portion 21d of the wiring board 20, and the other end is electrically and mechanically connected to the source electrode 4s of the transistor chip 3. That is, the source electrode 4s of each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f, 3g) is electrically connected to the detection conductive portion 21sd of the wiring board 20 via the respective detection electrode pin 11sd, and is connected in parallel via the respective detection electrode pin 11sd and the detection conductive portion 21sd of the wiring board 20.

[0076] One end of the detection electrode pin 11sd is press-fitted into a through-hole provided across the detection conductive portion 21sd and the insulating plate 22, and is joined to the detection conductive portion 21sd by this press-fitting. The other end of the detection electrode pin 11sd is joined to the source electrode 4s of the transistor chip 3 with a bonding material (not shown) in a state where it abuts against the source electrode 4s from above. As the bonding material, for example, a solder material can be used.

[0077] Although not limited to this, for example, one detection electrode pin 11sd is provided for each transistor chip 3 (3a, 3b, 3c, 3d, 3e, 3f).

[0078] 5A , an opening 24a is provided in the source conductive portion 23s of the wiring substrate 20. The detection electrode pin 11sd penetrates the insulating plate 22 from the back surface side toward the main surface side of the wiring substrate 20 through the opening 24a in the source conductive portion 23s, and is electrically isolated from the source conductive portion 23s on the wiring substrate 20. The detection electrode pin 11sd is insulated from the source conductive portion 23s by an insulator 24b provided between the detection electrode pin 11sd and the opening 24a in the source conductive portion 23s.

[0079] 3 and 6 , the gate conductive pin 31g extends in the Z direction between the gate conductive plate 41g of the support substrate 40 and the gate conductive portion 23g of the wiring substrate 20. One end of the gate conductive pin 31g is electrically and mechanically connected to the gate conductive portion 23g of the wiring substrate 20, and the other end is electrically and mechanically connected to the gate conductive plate 41g of the support substrate 40, at one end and the other end located opposite to each other. That is, the gate electrode 4g of each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) is electrically connected to the gate conductive plate 41g of the support substrate 40 via the gate electrode pin 11g, the gate conductive portion 21g of the wiring substrate 20, and the gate conductive pin 31g.

[0080] One end of the gate conductive pin 31g is press-fitted into a through-hole provided across the gate conductive portion 23g and the insulating plate 22, and is joined to the gate conductive portion 23g by this press-fitting.

[0081] 3, 4, and 5B, the source conductive pin 31s extends in the Z direction between the source conductive plate 41s of the support substrate 40 and the source conductive portion 23s of the wiring substrate 20. One end of the source conductive pin 31s is electrically and mechanically connected to the source conductive portion 23s of the wiring substrate 20, and the other end is electrically and mechanically connected to the source conductive plate 41s of the support substrate 40, at one end and the other end located opposite to each other. That is, the source electrode 4s of each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) is electrically connected to the source conductive plate 41s of the support substrate 40 via each of the source electrode pins 11s, the source conductive portion 23s of the wiring substrate 20, and the source conductive pin 31s.

[0082] In addition, the anode electrodes 6a of each of the six diode chips 5 (5a, 5b, 5c, 5d, 5e, 5f) are also electrically connected to the source conductive plate 41s of the support substrate 40 via each anode electrode pin 12a, the source conductive portion 23s of the wiring substrate 20, and the source conductive pin 31s.

[0083] One end of the source conductive pin 31s is press-fitted into a through-hole provided across the source conductive portion 23s and the insulating plate 22, and is joined to the source conductive portion 23s by this press-fitting. The other end of the source conductive pin 31s is joined to the source conductive plate 41s of the support substrate 40 with a bonding material (not shown) in a state where it abuts against the source conductive plate 41s from above. For example, a solder material can be used as the bonding material. Although not limited to this, for example, four source conductive pins 31s are provided.

[0084] 3, 4, and 5A, the detection conductive pin 31sd extends in the Z direction between the detection conductive plate 41sd of the support substrate 40 and the detection conductive portion 21sd of the wiring substrate 20. One end of the detection conductive pin 31sd is electrically and mechanically connected to the detection conductive portion 21sd of the wiring substrate 20, and the other end is electrically and mechanically connected to the detection conductive plate 41sd of the support substrate 40 at one end located on opposite sides. That is, the source electrode 4s of each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) is electrically connected to the detection conductive plate 41sd of the support substrate 40 via the respective detection electrode pins 11sd, the detection conductive portions 21sd of the wiring substrate 20, and the detection conductive pins 31sd.

[0085] One end of the detection conductive pin 31sd is press-fitted into a through-hole provided across the detection conductive portion 21sd and the insulating plate 22, and is joined to the detection conductive portion 21sd by this press-fitting. The other end of the detection conductive pin 31sd is joined to the detection conductive plate 41sd with a joining material (not shown) in a state where it abuts against the detection conductive plate 41sd of the support substrate 40 from above. For example, a solder material can be used as the joining material. The number of detection conductive pins 31sd is not limited to this, but for example, four are provided.

[0086] 3 , 6 , and 7 , the drain terminal pin 51 d extends along the thickness direction (Z direction) of the resin encapsulant 60 and extends from the inside to the outside of the resin encapsulant 60. The drain terminal pin 51 d has an intermediate portion between opposite ends thereof that penetrates the wiring substrate 20 in the thickness direction. One end of the drain terminal pin 51 d is disposed outside the resin encapsulant 60, and the other end is electrically and mechanically connected to the drain conductive plate 41 d of the support substrate 40. That is, the drain electrodes 4 d of the six transistor chips 3 (3 a, 3 b, 3 c, 3 d, 3 e, 3 f) are electrically connected to the drain terminal pin 51 d via the drain conductive plate 41 d of the support substrate 40. In addition, the cathode electrode 6k of each of the six diode chips 5 (5a, 5b, 5c, 5d, 5e, 5f) is also electrically connected to the drain terminal pin 51d via the drain conductive plate 41d of the support substrate 40.

[0087] The other end of the drain terminal pin 51d is joined to the drain conductive plate 41d by a joining material (not shown) in a state where the other end abuts against the drain conductive plate 41d of the support substrate 40 from above. As the joining material, for example, a solder material can be used.

[0088] The drain terminal pin 51d is insulated from each of the gate conductive portion 23g, the source conductive portion 23s, and the detection conductive portion 21sd of the wiring substrate 20. Although not limited thereto, for example, as shown in FIGS. 3 and 8, two drain terminal pins 51d are provided on each of the two long side portions 42c and 42d of the support substrate 40 (insulating plate 42).

[0089] 3 , 6 , and 7 , the source terminal pins 51s extend along the thickness direction (Z direction) of the resin encapsulant 60 and extend both inside and outside the resin encapsulant 60. The source terminal pins 51s have an intermediate portion between opposite ends thereof that penetrates the wiring substrate 20 in the thickness direction. One end of the source terminal pins 51s is disposed outside the resin encapsulant 60, and the other end is electrically and mechanically connected to the source conductive plate 41s of the support substrate 40. That is, the source electrodes 4s of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, and 3f) are electrically connected to the source terminal pins 51s via the respective source electrode pins 11s, the source conductive portions 23s of the wiring substrate 20, the source conductive pins 31s, and the source conductive plate 41s of the support substrate 40. In addition, the anode electrodes 6a of the six diode chips 5 (5a, 5b, 5c, 5d, 5e, 5f) are also electrically connected to the source terminal pins 51s via the respective anode electrode pins 12a, the source conductive portions 23s of the wiring substrate 20, the source conductive pins 31s, and the source conductive plates 41s of the support substrate 40.

[0090] The other end of the source terminal pin 51s is joined to the source conductive plate 41s by a joining material (not shown) in a state where it abuts against the source conductive plate 41s of the support substrate 40 from above. As the joining material, for example, a solder material can be used.

[0091] The source terminal pin 51s is insulated from each of the gate conductive portion 23g, the source conductive portion 23s, and the detection conductive portion 21sd of the wiring substrate 20. Although not limited thereto, for example, as shown in FIGS. 3 and 8 , two source terminal pins 51s are provided on each of the two long side portions 42c and 42d of the support substrate 40 (insulating plate 42).

[0092] 3 and 7 , the detection terminal pin 51sd extends along the thickness direction (Z direction) of the resin sealing body 60 and extends both inside and outside the resin sealing body 60. The detection terminal pin 51sd has an intermediate portion between opposite ends that penetrates the wiring board 20 in the thickness direction. One end of the detection terminal pin 51sd is disposed outside the resin sealing body 60, and the other end is electrically and mechanically connected to the detection conductive plate 41sd of the support substrate 40. That is, the source electrode 4s of each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) is electrically connected to the detection terminal pin 51sd via the respective detection electrode pins 11sd, the detection conductive portions 21sd of the wiring board 20, the detection conductive pins 31sd, and the detection conductive plate 41sd of the support substrate 40.

[0093] The other end of the detection terminal pin 51sd is joined to the source conductive plate 41s by a joining material (not shown) in a state where it abuts against the source conductive plate 41s of the support substrate 40 from above. As the joining material, for example, a solder material can be used.

[0094] The detection terminal pin 51sd is insulated from each of the gate conductive portion 23g and the source conductive portion 23s of the wiring substrate 20. Although not limited thereto, for example, as shown in FIGS. 3 and 8 , two detection terminal pins 51sd are provided closer to the long side portion 42d of the support substrate 40 (insulating plate 42) than the detection conductive pin 31sd in a plan view.

[0095] (Gate Terminal Pin) Although not shown in detail, the gate terminal pin 51g shown in FIGS. 3 and 8 extends along the thickness direction (Z direction) of the resin encapsulant 60, similar to the drain terminal pin 51d, source terminal pin 51s, and detection terminal pin 51sd described above, and extends from the inside to the outside of the resin encapsulant 60. The gate terminal pin 51g also has an intermediate portion between opposite ends that penetrates the wiring substrate 20 in the thickness direction. One end of the gate terminal pin 51g is also disposed outside the resin encapsulant 60, and the other end is electrically and mechanically connected to the gate conductive plate 41g of the support substrate 40. That is, the gate electrodes 4g of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) are electrically connected to the gate terminal pin 51g via the gate electrode pins 11g, the gate conductive portions 23g of the wiring substrate 20, the gate conductive pins 31g, and the gate conductive plate 41g of the support substrate 40.

[0096] The other end of the source terminal pin 51g is joined to the gate conductive plate 41g with a joining material (not shown) in a state where the other end abuts against the gate conductive plate 41g of the support substrate 40 from above. As the joining material, for example, a solder material can be used.

[0097] The gate terminal pin 51g is insulated from each of the source conductive portion 23s and the detection conductive portion 21sd of the wiring substrate 20. Although not limited thereto, for example, as shown in FIGS. 3 and 8 , two gate terminal pins 51g are provided closer to the long side portion 42c of the support substrate 40 (insulating plate 42) than the gate conductive pin 31g in a plan view.

[0098] <Chip / Terminal Conductive Path> Next, a chip / terminal conductive path included in the semiconductor device 1A according to the first embodiment of the present technology will be described with reference to FIG.

[0099] As shown in FIG. 11, the semiconductor device 1A according to the first embodiment includes, as chip-to-terminal conductive paths, a chip-to-terminal drain conductive path 55d, a chip-to-terminal gate conductive path 55g, a chip-to-terminal source conductive path 55s, and a chip-to-terminal detection conductive path 55sd.

[0100] 11 , the chip-to-terminal drain conductive path 55d electrically connects the drain electrode 4d provided on the second surface S2 side of the transistor chip 3 to the drain terminal pin 51d extending from the inside to the outside of the resin sealing body 60. This chip-to-terminal drain conductive path 55d includes the drain conductive plate 41d of the support substrate 40 described above. The drain conductive plate 41d of this chip-to-terminal drain conductive path 55d is electrically connected to the cathode electrode 6k provided on the fourth surface S4 side of the diode chip 5.

[0101] 11 , the chip-to-terminal gate conductive path 55g electrically connects the gate electrode 4g provided on the first surface S1 of the transistor chip 3 to the gate terminal pin 51g extending from the inside to the outside of the resin encapsulant 60. This chip-to-terminal gate conductive path 55g includes the gate electrode pin 11g, the gate conductive portion 23g of the wiring substrate 20, the gate conductive pin 31g, and the gate conductive plate 41g of the support substrate 40, all of which are described above.

[0102] 11 , the chip-to-terminal source conductive path 55s electrically connects the source electrode 4s provided on the first surface S1 of the transistor chip 3 to the source terminal pin 51s extending from the inside to the outside of the resin sealing body 60. This chip-to-terminal source conductive path 55s includes the above-mentioned source electrode pin 11s, the source conductive portion 23s of the wiring substrate 20, the source conductive pin 31s, and the source conductive plate 41s of the support substrate 40. The anode electrode 6a provided on the third surface S3 of the diode chip 5 is electrically connected to the source conductive portion 23s of this chip-to-terminal source conductive path 55s via the anode electrode pin 12a.

[0103] 11 , the chip-to-terminal detection conductive path 55sd electrically connects the source electrode 4s of the transistor chip 3 to the detection terminal pin 51s extending from the inside to the outside of the resin encapsulant 60. The chip-to-terminal detection conductive path 55sd includes the detection electrode pin 11sd, the detection conductive portion 21sd of the wiring substrate 20, the detection conductive pin 31sd, and the detection conductive plate 41sd of the support substrate 40. The chip-to-terminal detection conductive path 55sd is electrically connected to the chip-to-terminal source conductive path 55s via the source electrode 4s of the transistor chip 3, but is electrically isolated from the chip-to-terminal source conductive path 55s on the wiring substrate 20. That is, the chip-to-terminal source conductive path 55s and the chip-to-terminal detection conductive path 55sd are electrically connected to the source electrode 4s of the transistor chip 3 as electrically isolated conductive paths.

[0104] 11 illustrates one transistor chip 3 and one diode chip 5 for the sake of simplicity, but in reality, six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) and six diode chips 5 (5a, 5b, 5c, 5d, 5e, 5f) are provided. A gate electrode pin 11g included in the chip-to-terminal gate conductive path 55g, a source electrode pin 11s included in the chip-to-terminal source conductive path 55s, and a detection electrode pin 11sd included in the chip-to-terminal detection conductive path 55sd are provided for each transistor chip 3 and are connected to corresponding conductive portions (gate conductive portion 23g, source conductive portion 23s, detection conductive portion 21sd) of the wiring substrate 20.

[0105] <Inter-chip conductive paths> Next, the inter-chip conductive paths included in the semiconductor device 1A according to the first embodiment of the present technology will be described with reference to FIG. 12 . Here, the inter-chip conductive paths will be described focusing on two transistor chips 3a and 3b as an example among the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f). Because each of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) is connected in parallel, the inter-chip conductive paths are not limited to the two transistor chips 3a and 3b, and all of the inter-chip conductive paths of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) have the same configuration.

[0106] As shown in FIG. 12, the semiconductor device 1A according to the first embodiment includes, as inter-chip conductive paths, an inter-chip drain conductive path 58d, an inter-chip gate conductive path 58g, an inter-chip source conductive path 58s, and an inter-chip detection conductive path 58sd.

[0107] 12 , the inter-chip drain conductive path 58d electrically connects the drain electrode 4d of one transistor chip 3 (3a) to the drain electrode 4d of the other transistor chip 3 (3b) between two transistor chips 3 (3a and 3b in this embodiment). This inter-chip drain conductive path 58d includes the drain conductive plate 41d of the support substrate 40 described above. The drain conductive plate 41d is electrically connected to the drain terminal pin 51d.

[0108] 12 shares the drain conductive plate 41d with another inter-chip drain conductive path 58d that electrically connects four other transistor chips 3. That is, the drain electrodes 4d of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, and 3f) are connected in parallel via the inter-chip drain conductive path 58d.

[0109] 12 , an inter-chip gate conductive path 58g electrically connects the gate electrode 4g of one transistor chip 3 (3a) to the gate electrode 4g of the other transistor chip 3 (3b) between two transistor chips 3 (3a and 3b in this embodiment). This inter-chip gate conductive path 58g includes a gate electrode pin 11g on the one transistor chip 3 (3a), a gate conductive portion 23g of the wiring substrate 20, and a gate electrode pin 11g on the other transistor chip 3 (3b). The gate conductive portion 23g of this inter-chip gate conductive path 58g is electrically connected to a gate conductive pin 31g.

[0110] 12 shares the gate conductive portion 23g of the wiring substrate 20 with another inter-chip gate conductive path 58g that electrically connects the other four transistor chips 3. That is, the gate electrodes 4g of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, and 3f) are connected in parallel via the respective inter-chip gate conductive paths 58g.

[0111] 12 , an inter-chip source conductive path 58s electrically connects the source electrode 4s of one transistor chip 3 (3a) to the source electrode 4s of the other transistor chip 3 (3b) between two transistor chips 3 (3a and 3b in this embodiment). This inter-chip source conductive path 58s includes a source electrode pin 11s on the one transistor chip 3 (3a), a source conductive portion 23s on the wiring substrate 20, and a source electrode pin 11s on the other transistor chip 3 (3b). The source conductive portion 23s of this inter-chip source conductive path 58s is electrically connected to the gate conductive pin 31g.

[0112] 12 shares the source conductive portion 23s of the wiring substrate 20 with other inter-chip source conductive paths 58s that electrically connect four other transistor chips 3. That is, the source electrodes 4s of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, and 3f) are connected in parallel via the inter-chip source conductive paths 58s.

[0113] 12 , the inter-chip detection conductive path 58sd electrically connects the source electrode 4s of one transistor chip 3 (3a) to the source electrode 4s of the other transistor chip 3 (3b) between two transistor chips 3 (3a and 3b in this embodiment). This inter-chip detection conductive path 58sd includes a detection electrode pin 11sd on the one transistor chip 3 (3a), a detection conductive portion 21sd on the wiring substrate 20, and a detection electrode pin 11sd on the other transistor chip 3 (3b). The detection conductive portion 21sd of this inter-chip detection conductive path 58sd is electrically connected to the detection conductive pin 31sd.

[0114] 12 shares the detection conductive portion 21sd of the wiring substrate 20 with another inter-chip detection conductive path 58sd that electrically connects four other transistor chips 3. That is, the source electrodes 4s of the six transistor chips 3 (3a, 3b, 3c, 3d, 3e, and 3f) are connected in parallel via the detection conductive portion 21sd of the wiring substrate 20.

[0115] 12 , the inter-chip detection conductive path 58sd and the inter-chip source conductive path 58s are electrically separated from each other except for the area above the source electrode 4s of the chip. The detection conductive portion 21sd included in the inter-chip detection conductive path 58sd and the source conductive portion 23s included in the inter-chip source conductive path 58s are electrically separated on the wiring substrate 20.

[0116] Between two transistor chips 3 (described as 3a and 3b in this embodiment), the resistance value of an inter-chip detection conductive path 58sd that electrically connects the source electrode 4s of one transistor chip 3a to the source electrode 4s of the other transistor chip 3b via the detection electrode pin 11sd and the detection conductive portion 21sd is greater than the resistance value of an inter-chip source conductive path 58s that electrically connects the source electrode 4s of one transistor chip 3a to the source electrode 4s of the other transistor chip 3b via the source electrode pin 11s and the source conductive portion 23s.

[0117] The resistance of the detection electrode pin 11sd is greater than the resistance of the source electrode pin 11s. In the first embodiment, the resistance of the detection electrode pin 11sd is made "larger" than the resistance of the source electrode pin 11s by using materials with different resistivities. Specifically, the detection electrode pin 11sd is made of a material with a higher resistivity than the source electrode pin 11s. For example, when the source electrode pin 11s is made of copper as the conductive material, the resistance of the inter-chip detection conductive path 58sd can be made higher than the resistance of the inter-chip source conductive path 58s by using a detection electrode pin made of a conductive material with a higher resistivity than copper. Examples of conductive materials with a higher resistivity than copper include nickel (Ni), titanium (Ti), and tungsten (W).

[0118] 9A and 9B , in this first embodiment, an electrode pin group 15 (see FIG. 9B ) including, for example, eight source electrode pins 11s and one detection electrode pin 11sd is provided for each transistor chip 3, although this is not limited thereto. As shown in FIG. 9B , the eight source electrode pins 11s and one detection electrode pin 11sd included in the electrode pin group 15 are arranged in a 3×3 matrix. To facilitate connection with the detection conductive portion 21sd, the one detection electrode pin 11sd is arranged on the outer periphery side including four sides of the source electrode 4s in a plan view, in other words, on the outer periphery of the electrode pin group 15. In this first embodiment, the detection conductive portion 21sd extends in the X direction between two rows of transistor chips 3 aligned in the X direction in a plan view. Therefore, the detection electrode pin 11sd is provided at a corner of one of the four sides of the source electrode 4s in a plan view, the corner being adjacent to the detection conductive portion 21sd extending in the X direction.

[0119] <<Main Effects of the First Embodiment>> Next, the main effects of the first embodiment will be described. In the semiconductor device 1A according to the first embodiment, as shown in FIG. 12 , the inter-chip source conductive path 58s and the inter-chip detection conductive path 58sd are electrically isolated from each other except for the area over the source electrode 4s of the chip. The source conductive portion 23s included in the inter-chip source conductive path 58s and the detection conductive portion 21sd included in the inter-chip detection conductive path 58sd are electrically isolated from each other on the wiring substrate 20. This allows the resistance of the inter-chip detection conductive path 58sd to be greater than the resistance of the inter-chip source conductive path 58s.

[0120] Furthermore, in the inter-chip source conductive path 58s, the source electrodes 4s of the transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) are electrically connected to the source conductive portions 23s of the wiring substrate 20 by the source electrode pins 11s, and in the inter-chip detection conductive path 58sd, the source electrodes 4s of the transistor chips 3 (3a, 3b, 3c, 3d, 3e, 3f) are electrically connected to the detection conductive portions 21sd of the wiring substrate 20 by the detection electrode pins 11sd. Therefore, it is possible to easily select detection electrode pins 11sd having a higher resistance than the source electrode pins 11s, and it is also possible to easily make the resistance of the inter-chip detection conductive path 58sd larger than the resistance of the inter-chip source conductive path 58s.

[0121] Furthermore, in the semiconductor device 1A according to the first embodiment, the resistance of the detection electrode pin 11sd included in the inter-chip detection conductive path 58sd is greater than the resistance of the source electrode pin 11s included in the inter-chip source conductive path 58s. Therefore, the presence of a resistive pin (detection electrode pin 11sd) between the transistor chips 3 connected in parallel can reduce loop current and suppress vibration between the transistor chips 3. As a result, Vgs vibration during switching operation of the semiconductor device 1A can be suppressed, and the switching characteristics of the semiconductor device 1A can be improved.

[0122] Here, the inter-chip detection conductive path 58sd will be described with reference to FIGS. 13 and 14 . FIG. 13 is an equivalent circuit diagram when a conductive pin the same as a source conductive pin is used as a detection electrode pin in a semiconductor device 1A according to a first embodiment of the present technology. FIG. 14 is an equivalent circuit diagram when a conductive pin having a higher resistance than the source conductive pin is used as a detection electrode pin in a semiconductor device 1A according to a first embodiment of the present technology. In FIGS. 13 and 14 , for simplicity of description, two transistor chips connected in parallel are illustrated as an example.

[0123] In FIG. 13, if there is no gate resistor, a potential difference between the transistor chips 3 connected in parallel will cause a current loop Lp to be formed between the transistor chips 3, resulting in Vgs oscillation between the transistor chips 3.

[0124] In response to this, as shown in FIG. 14, by inserting a resistive pin (detection electrode pin 11sd) between the transistor chips 3 connected in parallel, it is possible to suppress the Vgs oscillation caused by the current loop Lp.

[0125] Therefore, according to the semiconductor device 1A of the first embodiment, it is possible to suppress Vgs oscillation during switching operations, and to improve switching characteristics.

[0126] 9B , in the semiconductor device 1A according to the first embodiment, the detection electrode pin 11sd is disposed on the outer peripheral edge side of the source electrode 4s in a plan view, which makes it easier to connect the detection electrode pin 11sd to the detection conductive portion 21sd of the wiring substrate 20 compared to when the detection electrode pin 11sd is disposed in the center of the source electrode 4s in a plan view.

[0127] Furthermore, according to the semiconductor device 1A of the first embodiment, by using the detection electrode pin 11sd having a resistance greater than that of the source electrode pin 11s, it is possible to suppress Vgs oscillations during the switching operation of the semiconductor device 1A, and therefore it is possible to suppress an increase in costs compared to the case where passive components such as resistive elements and capacitive elements are newly used to suppress Vgs oscillations during the switching operation of the semiconductor device 1A.

[0128] Note that none of the above-mentioned Patent Documents 1 to 3 disclose a configuration in which the inter-chip source conductive path 58s and the inter-chip detection conductive path 58sd are electrically isolated from each other except on the source electrodes of the chips, nor do they disclose a configuration in which the source conductive portion 23s included in the inter-chip source conductive path 58s and the detection conductive portion 21sd included in the inter-chip detection conductive path 58sd are electrically isolated from each other on the wiring substrate 20.

[0129] <Modifications of First Embodiment> <Modifications 1-1 and 1-2> Fig. 15 is a plan view showing an enlarged portion of a wiring substrate according to Modification 1-1 of the first embodiment of the present technology. Fig. 16 is a plan view showing an enlarged portion of a wiring substrate according to Modification 1-2 of the first embodiment of the present technology. In Figs. 15 and 16, the arrangement of the detection electrode pins 11sd is indicated by diagonal lines.

[0130] In the above-described first embodiment, as shown in FIG. 9B , the case where the detection electrode pin 11sd is arranged at the corner of the outer peripheral edge of the source electrode 4s of the transistor chip 3 on the side of the detection conductive portion 21sd extending in the X direction in plan view has been described. However, the arrangement of the detection electrode pin 11sd is not limited to the above-described first embodiment.

[0131] That is, the detection electrode pin 11sd may be located anywhere on the outer peripheral edge side of the source electrode 4s, as shown by the hatched area in FIG. 15 of Modification 1-1.

[0132] However, when the distance between the source electrode 4s and the gate electrode 4g of the transistor chip 3 is narrow, it is preferable to position the detection electrode pin 11sd at a position on the outer edge of the source electrode 4s that avoids the area adjacent to the gate electrode 4g in a planar view, as shown by the diagonal lines in Figure 16.

[0133] In either of the modified examples 1-1 and 1-2, the connection to the detecting conductive portion 21sd of the wiring board 20 can be facilitated.

[0134] <Modifications 1-3 and 1-4> Fig. 17 is a longitudinal cross-sectional view schematically showing a part of a longitudinal cross-sectional structure of Modification 1-3 according to the first embodiment of the present technology. Fig. 18 is a longitudinal cross-sectional view schematically showing a part of a longitudinal cross-sectional structure of Modification 1-4 according to the first embodiment of the present technology.

[0135] In the above-described first embodiment, a method for making the resistance of the detection electrode pin 11sd "larger" than the resistance of the source electrode pin 11s has been described in which the detection electrode pin 11sd is made of a material with a higher resistivity than the source electrode pin 11s. However, the method for making the resistance of the detection electrode pin 11sd "larger" than the resistance of the source electrode pin 11s is not limited to the above-described first embodiment.

[0136] For example, at least a portion of the detection electrode pin 11sd may be made thinner than the source electrode pin 11s, so that the resistance of the detection electrode pin 11sd is "larger" than the resistance of the source electrode pin 11s. In Modification 1-3 of Fig. 17, the entire detection electrode pin 11sd from one end to the other end is thinner than the source electrode pin 11s. In Modification 1-4 of Fig. 18, the intermediate portion between one end and the other end of the detection electrode pin 11sd is thinner than the source electrode pin 11s.

[0137] In either of the modified examples 1-3 and 1-4, the same effects as those of the first embodiment can be obtained.

[0138] <Modification 1-5> FIG. 19 is a longitudinal cross-sectional view schematically showing a part of a longitudinal cross-sectional structure according to Modification 1-5 of the first embodiment of the present technology.

[0139] 19, in this modification 1-5, the length of the detection electrode pin 11sd is made longer than the length of the source electrode pin 11s as a method for making the resistance of the detection electrode pin 11sd "larger" than the resistance of the source electrode pin 11s. In this modification 1-5, the intermediate portion between one end and the other end of the detection electrode pin 11sd is bent or curved so that the extension length of the detection electrode pin 11sd is longer than the extension length of the source electrode pin 11s.

[0140] In this modified example 1-5, the same effects as those of the first embodiment can be obtained.

[0141] <Modification 1-6> FIG. 20 is a longitudinal sectional view schematically showing a longitudinal sectional structure of Modification 1-6 according to the first embodiment of the present technology.

[0142] 20, in this modified example 1-6, the insulating plate 42 and the heat sink 43 are divided. That is, the insulating plate 42 and the heat sink 43 are divided corresponding to the drain conductive plate 41d, the source conductive plate 41s, the gate conductive plate 41g, and the detection conductive plate 41sd.

[0143] The present technology can also be applied to this modified example 1-6, and the same effects as those of the first embodiment described above can be obtained.

[0144] [Other Embodiments] In the above-described first embodiment, an example has been described in which the present technology is applied to a semiconductor device of a single-element package type (1-in-1 type) that includes a pair of a switching element and a rectifier element, as a semiconductor power device used in a power conversion device, etc. However, the present technology is not limited to semiconductor devices of a single-element package type, and can also be applied to semiconductor devices of a two-element package type (2-in-1 type) and semiconductor devices of a multi-element package type.

[0145] Furthermore, although the transistor mounted on the transistor chip 3 has been described as a vertical structure MISFET, the present technology can also be applied to the case where an IGBT is used as the transistor mounted on the transistor chip 3.

[0146] The present technology has been specifically described above based on the above-described embodiment and its modified examples. However, the present technology is not limited to the above-described embodiment and its modified examples, and it goes without saying that various modifications are possible within the scope of the gist of the technology.

[0147] 1A...Semiconductor device 2...Substrate laminate 3 (3a, 3b, 3c, 3d, 3e, 3f)...Transistor chip 4d...Drain electrode (second main electrode) 4g...Gate electrode (control electrode) 4s...Source electrode (first main electrode) 5...Diode chip 6a...Anode electrode 6k...Cathode electrode 7...Resistor chip 7a...First electrode 7b...Second electrode 11d...Drain electrode pin 11g...Gate electrode pin (control electrode pin) 11s...Source electrode pin (main electrode pin) 11sd...Detection electrode pin (detection electrode pin) 12k...Anode electrode pin 20...Wiring substrate 21sd...Detection conductive portion 22...Insulating plate 23g...Gate conductive portion 23s...Source conductive portion (main conductive portion) 31g...Gate conductive pin 31s...Source conductive pin 31sd...Detection conductive pin 40...Support substrate DESCRIPTION OF TERMINAL NUMERALS 41d...Drain conductive plate (conductive plate) 41g...Gate conductive plate 41s...Source conductive plate 41sd...Detection conductive plate 42...Insulating plate 43...Heat sink 51d...Drain terminal pin (second main terminal pin) 51g...Gate terminal pin (control terminal pin) 51s...Source terminal pin (first main terminal pin) 51sd...Detection terminal pin 55d...Chip / terminal drain conductive path 55g...Chip / terminal gate conductive path 55s...Chip / terminal source conductive path 55sd...Chip / terminal detection conductive path 58g...Chip-to-terminal drain conductive path 58g...Chip-to-chip gate conductive path 58s...Chip-to-chip source conductive path (main conductive path) 58sd...Chip-to-chip detection conductive path (detection conductive path) 60...Resin sealing body (sealing body)

Claims

1. A semiconductor device comprising: a plurality of transistor chips, each having a first main electrode, a second main electrode, and a control electrode; a conductive plate on one side of which the plurality of transistor chips are mounted; and a wiring substrate arranged on the transistor chip side of the conductive plate at a distance from the transistor chips, wherein the wiring substrate includes a control conductive portion, a main conductive portion, and a detection conductive portion, and the control electrode of each of the plurality of transistor chips is electrically connected to the control conductive portion of the wiring substrate via a control electrode pin for each transistor chip, and the first main electrode of each of the plurality of transistor chips is electrically connected to the main conductive portion of the wiring substrate via a main electrode pin for each transistor chip, and is also electrically connected to the detection conductive portion of the wiring substrate via a detection electrode pin for each transistor chip, and the main conductive portion and the detection conductive portion are electrically separated on the wiring substrate.

2. The semiconductor device described in claim 1, wherein, between two of the transistor chips, the resistance of a detection conductive path electrically connecting the first main electrode of one of the transistor chips to the first main electrode of the other of the transistor chips via the detection electrode pin and the detection conductive portion is greater than the resistance of a main conductive path electrically connecting the first main electrode of one of the transistor chips to the first main electrode of the other of the transistor chips via the main electrode pin and the main conductive portion.

3. The semiconductor device according to claim 1 or 2, wherein the detection electrode pin has a resistance greater than that of the main electrode pin.

4. The semiconductor device according to claim 3, wherein at least a portion of said detection electrode pin is thinner than said main electrode pin.

5. The semiconductor device according to claim 3, wherein the detection electrode pin is longer than the main electrode pin.

6. The semiconductor device according to claim 3, wherein the detection electrode pin is made of a material having a higher resistivity than the main electrode pin.

7. The semiconductor device according to claim 1, wherein the detection electrode pin is disposed on the outer peripheral edge side of the first main electrode in a plan view.

8. The semiconductor device according to claim 7, wherein the control electrode is disposed in the vicinity of the first main electrode, and the detection conductive pin is disposed at a position that avoids an area adjacent to the control electrode in a plan view.

9. The semiconductor device according to claim 1, wherein each of the plurality of transistor chips has a first surface and a second surface located opposite each other, the first main electrode and control electrode are disposed on the first surface of the semiconductor chip, and the second main electrode is disposed on the second surface of the semiconductor chip and is electrically and mechanically connected to the conductive plate.

10. The semiconductor device according to claim 9, further comprising: a sealing body that seals the plurality of transistor chips, the conductive plate, the wiring board, the main electrode pins, the inspection electrode pins, and the control electrode pins; a first main terminal pin that extends from the inside to the outside of the sealing body and is electrically connected to the main conductive portion of the wiring board; a detection terminal pin that extends from the inside to the outside of the sealing body and is electrically connected to the detection conductive portion of the wiring board; a control terminal pin that extends from the inside to the outside of the sealing body and is electrically connected to the control conductive portion of the wiring board; and a second main terminal pin that extends from the inside to the outside of the sealing body and is electrically connected to the conductive plate.

11. The semiconductor device according to claim 1, further comprising a plurality of diode chips each having a first electrode and a second electrode located opposite each other, wherein the first electrode of each of the plurality of diode chips is electrically connected to the main conductive portion of the wiring substrate via a diode pin for each of the diode chips, and the second electrode of each of the plurality of diode chips is electrically and mechanically connected to the conductive plate.

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