Silicon carbide semiconductor device

Abstract

The present invention comprises: a substrate (1) that is made of SiC; and an epitaxial layer (2) that is disposed on the substrate (1) and that is made of SiC. The epitaxial layer (2) has: a buffer layer (11) that is disposed on the substrate (1) side thereof, and that has an impurity concentration lower than that of the substrate (1); and a drift layer (14) that is disposed on the buffer layer (11) and that has an impurity concentration lower than that of the buffer layer (11). The buffer layer (11) has a thickness of greater than 1 μm. The relative intensity of DAP light emission with respect to band edge light emission is configured so as to have a minimum value within the buffer layer (11).

Description

Silicon carbide semiconductor device CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2024-126115, filed on August 1, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a silicon carbide (hereinafter also referred to as SiC) semiconductor device made of SiC.

[0003] Substrates made of SiC single crystals have been attracting attention as materials for various semiconductor devices, including power devices for vehicles, due to their excellent semiconductor properties. However, it has been reported that current substrates made of SiC single crystals contain basal plane dislocations.

[0004] When an SiC semiconductor device is constructed by growing an epitaxial layer on such a substrate and forming a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or the like, a parasitic diode is formed. In this case, it has been reported that when the parasitic diode operates as a diode, holes passing near the basal plane dislocations may expand the basal plane dislocations into stacking faults. Stacking faults are defects that are more likely to degrade the electrical characteristics of SiC semiconductor devices than basal plane dislocations.

[0005] For this reason, for example, Patent Document 1 discloses that by disposing an impurity element in a substrate, the expansion of basal plane dislocations into stacking faults is suppressed. Specifically, by disposing an impurity element in a substrate, the impurity element can easily terminate carbon vacancies that constitute basal plane dislocations, thereby suppressing the expansion of basal plane dislocations into stacking faults. Furthermore, by disposing an impurity element in a substrate, the impurity element functions as a lifetime killer, thereby reducing the number of holes that pass near basal plane dislocations. Therefore, in this SiC semiconductor device, the expansion of basal plane dislocations into stacking faults can be suppressed.

[0006] Japanese Patent Application Laid-Open No. 2021-57381

[0007] The present inventors have been studying the construction of a SiC semiconductor device by disposing an epitaxial layer on a substrate having impurity elements disposed thereon as described above, the epitaxial layer including a buffer layer having an impurity concentration lower than that of the substrate and a drift layer having an impurity concentration lower than that of the buffer layer. The inventors' study of such a SiC semiconductor device has confirmed that point defects are formed in the epitaxial layer due to the diffusion of impurity elements contained in the substrate toward the epitaxial layer. Furthermore, the inventors' study has confirmed that point defects also affect the electrical characteristics of the SiC semiconductor device, and that point defects may cause variations in the electrical characteristics of the SiC semiconductor device.

[0008] An object of the present disclosure is to provide a SiC semiconductor device that can suppress variations in electrical characteristics.

[0009] According to one aspect of the present disclosure, a SiC semiconductor device includes a substrate made of SiC and an epitaxial layer made of SiC and disposed on the substrate, the epitaxial layer having a buffer layer disposed on the substrate side and having a lower impurity concentration than the substrate, and a drift layer disposed on the buffer layer and having a lower impurity concentration than the buffer layer, the buffer layer having a thickness greater than 1 μm, and the relative intensity of the DAP emission to the band-edge emission has a minimum value within the buffer layer.

[0010] According to this, since the thickness of the buffer layer is made thicker than 1 μm, the variation in point defects contained in the drift layer can be reduced, and the variation in electrical characteristics including the on-voltage fluctuation can be suppressed.

[0011] Fig. 1 is a perspective cross-sectional view of a SiC semiconductor device according to a first embodiment; Fig. 2 is a diagram showing the relationship between the depth of a semiconductor substrate, the relative intensity of DAP luminescence to band-edge luminescence, and the amount of defects contained in the substrate; Fig. 3 is a diagram showing the relationship between the depth of a semiconductor substrate, the relative intensity of DAP luminescence to band-edge luminescence, and the thickness of a buffer layer; Fig. 4 is a diagram showing the relationship between the thickness of a buffer layer, the minimum value of the relative intensity, the relative intensity at the interface between a drift layer and a buffer layer, and the ratio of the minimum value of the relative intensity to the relative intensity at the interface; Fig. 5 is a diagram showing the relationship between the thickness of a buffer layer and on-voltage fluctuations due to degradation due to electrical conduction;

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0013] First Embodiment A first embodiment will be described with reference to the drawings. In this embodiment, a SiC semiconductor device in which a MOSFET with a trench gate structure is formed as a semiconductor element will be described as an example. Note that, although the configuration of a cell region in the SiC semiconductor device in which the MOSFET is formed will be described below, an actual SiC semiconductor device will have an outer periphery region in which a FLR (abbreviation for Field Limiting Ring) structure or the like is formed so as to surround the cell region.

[0014] In the following description, one direction in the surface direction of the semiconductor substrate 10 (described later) is referred to as the X-axis direction, a direction intersecting the one direction in the surface direction of the semiconductor substrate 10 is referred to as the Y-axis direction, and a direction perpendicular to the X-axis direction and the Y-axis direction is referred to as the Z-axis direction. In this embodiment, the X-axis direction and the Y-axis direction are perpendicular to each other. In addition, the Z-axis direction in this embodiment corresponds to the thickness (i.e., depth) direction of the semiconductor substrate 10 (described later), and can also be said to be the stacking direction of the substrate 1 and the buffer layer 11 (described later).

[0015] As shown in Fig. 1, the SiC semiconductor device is configured using a semiconductor substrate 10 having one surface 10a and another surface 10b. Specifically, the semiconductor substrate 10 is a n-type semiconductor substrate made of SiC. ＋ The semiconductor device includes a substrate 1 and an epitaxial layer 2 made of SiC disposed on the substrate 1. In this embodiment, the substrate 1 has an off-angle of 0 to 8° with respect to the (0001) Si plane, and an n-type impurity concentration of nitrogen, phosphorus, or the like of 1.0×10 １９ cm －３ The substrate 1 has a thickness of about 300 μm. In this embodiment, the substrate 1 constitutes the drain region and can also be said to be a first impurity region. The substrate 1 in this embodiment is prepared by cutting a general SiC ingot, and contains basal plane dislocations, point defects, impurity elements, and the like.

[0016] The epitaxial layer 2 is disposed on the surface of the substrate 1 to a thickness of more than 1 μm and includes an n-type buffer layer 11 having a lower impurity concentration than the substrate 1. The buffer layer 11 has an n-type impurity concentration of 0.45×10 １８ cm －３ or more than 5.0 × 10 １８ cm －３ The reason why the thickness of the buffer layer 11 is greater than 1 μm will be specifically described later.

[0017] The epitaxial layer 2 is disposed on the buffer layer 11 and has a thickness of, for example, about 10 to 15 μm. The epitaxial layer 2 is made of SiC and has a lower impurity concentration than the buffer layer 11. － The low concentration layer 12 has an n-type impurity concentration of, for example, 5.0 to 20.0×10 １５ cm －３ It is said that...

[0018] The epitaxial layer 2 has a JFET layer 13 and a deep layer 15 disposed on the low-concentration layer 12. The JFET layer 13 and the deep layer 15 each extend along the X-axis direction and have linear portions arranged alternately and repeatedly in the Y-axis direction. That is, the JFET layer 13 and the deep layer 15 are configured as stripes extending along the X-axis direction in the normal direction to the surface of the substrate 1, and are arranged alternately along the Y-axis direction. Note that while only one deep layer 15 is shown in FIG. 1 , in reality, the deep layers 15 are arranged alternately and repeatedly in the Y-axis direction. In addition, "in the normal direction to the surface of the substrate 1" can be rephrased as when viewed from the normal direction to the surface of the substrate 1 or when viewed from the Z-axis direction.

[0019] In this embodiment, the JFET layer 13 is of n-type and is configured by stacking a first JFET layer 13a and a second JFET layer 13b having a higher n-type impurity concentration than the first JFET layer 13a. The JFET layer 13 has a thickness of 0.3 to 1.5 μm and an n-type impurity concentration of 5.0×10 １６ ~1.0 x 10１７ cm －３ The deep layer 15 is p-type, and the p-type impurity concentration is about 2.0×10 １７ ~2.0 x 10 １８ cm －３ In this embodiment, as will be described later, electrons flow in the low-concentration layer 12 and the JFET layer 13. Therefore, in this embodiment, it can be said that the drift layer 14 is configured to include the low-concentration layer 12 and the JFET layer 13. In this embodiment, the n-type impurity concentration is adjusted as described above, and the low-concentration layer 12 and the JFET layer 13 that configure the drift layer 14 both have lower n-type impurity concentrations than the buffer layer 11. Therefore, with regard to the n-type impurity concentrations of the substrate 1, buffer layer 11, and drift layer 14 in this embodiment, the n-type impurity concentration of the substrate 1 is the highest, and the impurity concentration of the drift layer 14 is the lowest.

[0020] The deep layer 15 in this embodiment is formed shallower than the JFET layer 13. That is, the deep layer 15 is formed so that its lower surface is located within the JFET layer 13. In other words, the deep layer 15 is formed so that the JFET layer 13 is located between the deep layer 15 and the low concentration layer 12.

[0021] The epitaxial layer 2 has a p-type base layer 16 disposed on the JFET layer 13 and the deep layer 15. The p-type deep layer 15 is formed so as to be connected to the lower surface of the p-type base layer 16. As a result, the deep layer 15 is electrically connected to the base layer 16. The base layer 16 has a p-type impurity concentration of, for example, 5.0×10 １６ ~2.0 x 10 １９ cm －３ The thickness is about 2.0 μm.

[0022] The epitaxial layer 2 is formed by n-type GaN layer disposed on the surface of the base layer 16. ＋ type source region 17 and p ＋The source region 17 has an n-type contact region 18. Specifically, the source region 17 is formed so as to contact the side surface of a trench 20, which will be described later, and the contact region 18 is formed on the opposite side of the source region 17 from the trench 20, which will be described later. In this embodiment, the source region 17 has an n-type impurity concentration in the surface layer (i.e., surface concentration) of, for example, 1.0×10 ２１ cm －３ The contact region 18 has a p-type impurity concentration in the surface layer (i.e., surface concentration) of, for example, 1.0×10 ２１ cm －３ The source region 17 has a thickness of about 0.3 μm. In this embodiment, the source region 17 can also be considered as a second impurity region. One surface 10 a of the semiconductor substrate 10 is composed of the source region 17 and the contact region 18, and the other surface 10 b is composed of the substrate 1.

[0023] Trenches 20 having a width of, for example, 1.4 to 2.0 μm are formed in the semiconductor substrate 10, penetrating the source region 17, the base layer 16, etc., from the one surface 10a side to the JFET layer 13, and with their lower surfaces located within the JFET layer 13. The trenches 20 extend with their longitudinal direction in the Y-axis direction. That is, the trenches 20 are formed so that their longitudinal direction is perpendicular to the longitudinal direction of the deep layer 15. Note that although only two trenches 20 are shown in FIG. 1 , in reality, a plurality of trenches 20 extend along the Y-axis direction and are arranged at equal intervals in the X-axis direction to form a stripe pattern.

[0024] A gate insulating film 21 is formed on the inner wall surface of the trench 20, and a gate electrode 22 made of doped poly-Si or the like is formed on the gate insulating film 21. This forms a trench gate structure. Although not particularly limited, the gate insulating film 21 is formed by thermally oxidizing the inner wall surface of the trench 20 or by performing a CVD (short for chemical vapor deposition) method. The gate insulating film 21 has a thickness of about 100 nm on both the side and bottom surfaces of the trench 20.

[0025] A p-type trench lower layer 24 is formed in the semiconductor substrate 10 so as to face the lower surface of the trench 20 and extend along the Y-axis direction, which is the longitudinal direction of the trench 20. The trench lower layer 24 is formed so as to intersect with the p-type deep layer 15, and is connected to the deep layer 15, thereby electrically connecting to the base layer 16. The trench lower layer 24 has an impurity concentration of 2.0×10 １７ ~2.0 x 10 １８ cm －３ The trench lower layer 24 has a depth of about 1000 nm, and is formed so that its lower surface is substantially flush with the lower surface of the deep layer 15. In other words, the trench lower layer 24 is formed shallower than the JFET layer 13, and is formed so that its lower surface is located within the JFET layer 13. That is, the trench lower layer 24 is formed so that the JFET layer 13 is located between the trench lower layer 24 and the low-concentration layer 12. Note that, although the trench lower layer 24 is formed so as to be in contact with the lower surface of the trench 20 in this embodiment, it may be formed at a position slightly separated from the lower surface of the trench 20.

[0026] An interlayer insulating film 25 is formed on one surface 10a of the semiconductor substrate 10 to cover the gate electrode 22, the gate insulating film 21, and the like. The interlayer insulating film 25 is made of BPSG (Borophosphosilicate Glass) or the like. Contact holes 25a are formed in the interlayer insulating film 25 to expose the source region 17 and the contact region 18. The contact holes 25a may have any pattern, such as an array of multiple squares, an array of rectangular lines, or an array of lines. In this embodiment, the contact holes 25a are linear along the longitudinal direction of the trench 20.

[0027] An upper electrode 26 electrically connected to the source region 17 and the contact region 18 through the contact hole 25a is formed on the interlayer insulating film 25. In this embodiment, the upper electrode 26 can also be called a first electrode.

[0028] The upper electrode 26 of this embodiment is made of a plurality of metals, such as Ni / Al. The portion of the plurality of metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 17) is made of a metal that can make ohmic contact with the n-type SiC. Furthermore, the portion of the plurality of metals that contacts at least the p-type SiC (i.e., the base layer 16) is made of a metal that can make ohmic contact with the p-type SiC.

[0029] A lower electrode 27 is formed on the other surface 10b of the semiconductor substrate 10 and is electrically connected to the substrate 1. In this embodiment, the lower electrode 27 can also be called a second electrode.

[0030] In the SiC semiconductor device of this embodiment, such a structure constitutes an n-channel inversion trench gate MOSFET. In this embodiment, as described above, the semiconductor substrate 10 is constituted by including the substrate 1, buffer layer 11, low concentration layer 12, JFET layer 13, deep layer 15, base layer 16, source region 17, contact region 18, trench lower layer 24, etc. The epitaxial layer 2 is constituted by including the buffer layer 11, low concentration layer 12, JFET layer 13, deep layer 15, base layer 16, source region 17, contact region 18, trench lower layer 24, etc. In this embodiment, the n － type, n type, n ＋ The type can also be called the first conductivity type, and p-type, p ＋ In addition, in such a SiC semiconductor device, a parasitic diode including a pn junction formed at the interface between the drift layer 14 and the base layer 16, etc., is formed.

[0031] The above is the configuration of the SiC semiconductor device according to this embodiment. Next, the operation and effects of the SiC semiconductor device will be described.

[0032] In the SiC semiconductor device, in an off state before a gate voltage equal to or greater than the threshold voltage is applied to gate electrode 22, no inversion layer is formed in base layer 16. Therefore, even if a positive voltage, for example, 1600 V, is applied to lower electrode 27, electrons do not flow from source region 17 into base layer 16, and the SiC semiconductor device enters an off state in which no current flows between upper electrode 26 and lower electrode 27.

[0033] When the SiC semiconductor device is in an off state, an electric field is applied between the gate and drain, which can cause electric field concentration at the bottom of the gate insulating film 21. However, the SiC semiconductor device of this embodiment is provided with a p-type deep layer 15, a trench lower layer 24, and an n-type JFET layer 13. Therefore, a depletion layer formed between the deep layer 15, the trench lower layer 24, and the JFET layer 13 suppresses the rise of equipotential lines due to the influence of the drain voltage, making it difficult for a high electric field to penetrate into the gate insulating film 21. Therefore, in this embodiment, it is possible to suppress breakdown of the gate insulating film 21 and improve the breakdown voltage.

[0034] When a gate voltage equal to or higher than the threshold voltage, for example, 20 V, is applied to the gate electrode 22, an inversion layer is formed on the surface of the base layer 16 that contacts the trench 20. This causes a current to flow between the upper electrode 26 and the lower electrode 27, turning the SiC semiconductor device on. In this embodiment, the JFET layer 13 is configured such that a second JFET layer 13b having a higher impurity concentration than the first JFET layer 13a is disposed on the first JFET layer 13a, and the second JFET layer 13b is in contact with the base layer 16. This reduces the resistance when a current flows from the inversion layer to the JFET layer 13 (i.e., the second JFET layer 13b), thereby preventing an increase in on-resistance. In this embodiment, electrons that pass through the inversion layer pass through the JFET layer 13 and the low-concentration layer 12 and flow to the substrate 1. Therefore, it can be said that the drift layer 14 includes the JFET layer 13 and the low-concentration layer 12.

[0035] The SiC semiconductor device described above is used, for example, to configure an inverter circuit, in which the voltage applied to the upper electrode 26 and the voltage applied to the lower electrode 27 change periodically. In the SiC semiconductor device described above, when a voltage higher than that of the lower electrode 27 is applied to the upper electrode 26, the parasitic diode operates as a diode. In this case, when holes pass near basal plane dislocations that may be included in the substrate 1, the basal plane dislocations may expand into stacking faults. When the basal plane dislocations expand into stacking faults, electrical degradation occurs, resulting in an increase in the on-state voltage of the SiC semiconductor device.

[0036] Here, the SiC semiconductor device of this embodiment is configured using a semiconductor substrate 10 in which an epitaxial layer 2 is grown on a substrate 1. According to studies by the present inventors, it has been confirmed that, when the epitaxial layer 2 is grown on the substrate 1, impurity elements contained in the substrate 1 diffuse into the epitaxial layer 2, thereby forming point defects in the epitaxial layer 2. For this reason, the present inventors first studied the amount of point defects.

[0037] It is difficult to directly measure the amount of point defects formed in the epitaxial layer 2. Therefore, the following discussion will be directed to Figure 2 , which shows the relative intensity of DAP luminescence (hereinafter simply referred to as relative intensity) relative to band-edge luminescence, which correlates with the amount of point defects and increases as the amount of point defects increases. DAP stands for donor-acceptor pair recombination luminescence. Figure 2 shows the results of relative intensity measurements using cathodoluminescence at wavelengths of 585 to 595 nm under a temperature condition of 300°C. In Figure 2 , Sample 1 has a higher amount of point defects and impurities in the substrate 1 than Sample 2. In Figure 2 , the direction from one surface 10a to the other surface 10b of the semiconductor substrate 10 is the depth direction, and the thickness of the epitaxial layer 2 is 9 μm and the thickness of the buffer layer 11 is 1 μm. That is, in FIG. 2, the position at a depth of 8 μm is the interface between drift layer 14 and buffer layer 11, and the position at a depth of 9 μm is the interface between buffer layer 11 and substrate 1.

[0038] As shown in FIG. 2 , it is confirmed that the relative intensity decreases from the substrate 1 toward the buffer layer 11 (i.e., from a position deeper than 9 μm toward a position 8-9 μm). It is also confirmed that the relative intensity has a minimum value (i.e., a minimum value) in the buffer layer 11. It is also confirmed that the relative intensity is higher in Sample 1, which has a higher amount of point defects and impurities, than in Sample 2 in the buffer layer 11 and in the portion of the drift layer 14 closer to the buffer layer 11. In other words, it is confirmed that the greater the amount of point defects and impurity elements contained in the substrate 1, the higher the relative intensity in the portion of the epitaxial layer 2 closer to the buffer layer 11. Furthermore, although the exact mechanism is not clear, it is confirmed that the relative intensity increases with decreasing depth. In this embodiment, it can be said that Sample 1 uses a substrate 1 with a large amount of point defects, and Sample 2 uses a substrate 1 with a small amount of point defects. It can also be said that a substrate 1 with a large amount of point defects has a lower relative intensity at the interface between drift layer 14 and buffer layer 11 (i.e., a depth of 8 μm) than the relative intensity at the interface between buffer layer 11 and substrate 1 (i.e., a depth of 9 μm). It can also be said that a substrate 1 with a small amount of point defects has a higher relative intensity at the interface between drift layer 14 and buffer layer 11 (i.e., a depth of 8 μm) than the relative intensity at the interface between buffer layer 11 and substrate 1 (i.e., a depth of 9 μm).

[0039] The inventors then investigated the relative intensity by changing the thickness of buffer layer 11, and obtained the results shown in FIGS. 3 and 4 . Note that FIG. 3 shows the results when substrate 1 of sample 1 in FIG. 2 was used. Also, FIG. 3 shows the results when the depth of 10 μm was fixed as the interface between drift layer 14 and buffer layer 11 and the thickness of buffer layer 11 was changed. That is, in FIG. 3 , when the thickness of buffer layer 11 is 1 μm, the interface between buffer layer 11 and substrate 1 is at a depth of 11 μm; when the thickness of buffer layer 11 is 3 μm, the interface between buffer layer 11 and substrate 1 is at a depth of 13 μm; and when the thickness of buffer layer 11 is 5 μm, the interface between buffer layer 11 and substrate 1 is at a depth of 15 μm. The depths in FIG. 4 indicate the depths in semiconductor substrate 10 at which the relative intensities shown in FIG. 4 are obtained.

[0040] 3 and 4, it has been confirmed that increasing the thickness of the buffer layer 11 reduces the minimum value of the relative intensity in the buffer layer 11. Specifically, it has been confirmed that the minimum value of the relative intensity decreases as the thickness of the buffer layer 11 increases within the range of 1 to 3 μm. It has also been confirmed that when the thickness of the buffer layer 11 is 3 μm or greater, the minimum value of the relative intensity in the buffer layer 11 remains almost unchanged.

[0041] Specifically, it was confirmed that when the thickness of the buffer layer 11 was 1 μm, the minimum value of the relative intensity was 0.94. On the other hand, when the thickness of the buffer layer 11 was 3 μm, the minimum value of the relative intensity was 0.14, and when the thickness of the buffer layer 11 was 5 μm, the minimum value of the relative intensity was 0.12. In other words, it was confirmed that, within the thickness range of the buffer layer 11 from 1 to 3 μm, the minimum value of the relative intensity decreases as the thickness of the buffer layer 11 increases. It was also confirmed that by increasing the thickness of the buffer layer 11 to 3 μm or more, the minimum value of the relative intensity remains almost unchanged at 0.2 or less.

[0042] Furthermore, when the thickness of buffer layer 11 is 1 μm, the relative intensity at the interface between drift layer 14 and buffer layer 11 was confirmed to be 1.98. On the other hand, when the thickness of buffer layer 11 is 3 μm, the relative intensity at the interface between drift layer 14 and buffer layer 11 was confirmed to be 0.95. When the thickness of buffer layer 11 is 5 μm, the relative intensity at the interface between drift layer 14 and buffer layer 11 was confirmed to be 1.17.

[0043] It was confirmed that the ratio of the minimum value of the relative intensity to the relative intensity at the interface between the drift layer 14 and the buffer layer 11 was 0.48 when the thickness of the buffer layer 11 was 1 μm. In contrast, it was confirmed that the ratio of the minimum value of the relative intensity to the relative intensity at the interface between the drift layer 14 and the buffer layer 11 was 0.15 when the thickness of the buffer layer 11 was 3 μm, and 0.10 when the thickness of the buffer layer 11 was 5 μm. In other words, it was confirmed that the ratio of the minimum value of the relative intensity to the relative intensity at the interface between the drift layer 14 and the buffer layer 11 decreased as the thickness of the buffer layer 11 increased within the range of 1 to 3 μm. It was also confirmed that by setting the thickness of the buffer layer 11 to 3 μm or more, the ratio of the minimum value of the relative intensity to the relative intensity at the interface between the drift layer 14 and the buffer layer 11 remained almost unchanged at 0.15 or less.

[0044] The inventors then conducted extensive research into the relationship between the thickness of buffer layer 11 and the on-state voltage variation ΔVon due to degradation due to electrical conduction, and obtained the results shown in Fig. 5. As described above, the on-state voltage variation ΔVon due to degradation due to degradation occurs when, when the parasitic diode operates as a diode, holes pass near basal plane dislocations that may be contained in substrate 1, causing the basal plane dislocations to expand into stacking faults.

[0045] 5, it is confirmed that the on-state voltage fluctuation ΔVon due to degradation due to current flow decreases as the thickness of buffer layer 11 increases. This is because the thicker buffer layer 11 increases the number of electrons in buffer layer 11, making it easier for holes to recombine with electrons when the parasitic diode operates as a diode, and making it more difficult for holes to reach substrate 1, thereby reducing the number of holes flowing near basal plane dislocations.

[0046] It has also been confirmed that the more point defects there are in the substrate 1, the smaller the on-state voltage fluctuation ΔVon due to degradation due to electrical conduction. This is because the more point defects there are in the substrate 1, the more impurity elements there are in the substrate 1, and the more point defects can be formed in the epitaxial layer 2 when the epitaxial layer 2 is grown. Furthermore, when the parasitic diode operates as a diode, holes are more likely to recombine with electrons, making it more difficult for the holes to reach the substrate 1, which reduces the number of holes flowing near the basal plane dislocations.

[0047] Furthermore, according to the investigations of the present inventors, it has been confirmed that the on-state voltage fluctuation ΔVon due to degradation due to electrical conduction can be made smaller than the value of the on-state voltage fluctuation ΔVon currently required, without being affected by the amount of point defects that may be contained in the substrate 1, by making the thickness of the buffer layer 11 3 μm or more.

[0048] Furthermore, it has been confirmed that when the thickness of the buffer layer 11 is 1 μm, the on-voltage fluctuation ΔVon tends to vary more than when the thickness of the buffer layer 11 is 3 μm or greater, particularly when a substrate 1 with many point defects is used. This is because the thin buffer layer 11 increases the variation in point defects that may be formed in the drift layer 14 when the epitaxial layer 2 is grown. Therefore, by making the buffer layer 11 thicker than 1 μm, the variation in point defects that may be formed in the drift layer 14 can be suppressed, and the variation in the on-voltage fluctuation ΔVon can be reduced. In this case, by making the thickness of the buffer layer 11 3 μm or greater, the variation in the on-voltage fluctuation ΔVon can be further reduced.

[0049] For the above reasons, it is preferable that the thickness of the buffer layer 11 is greater than 1 μm. This can suppress the variation in point defects that may be formed in the drift layer 14, and can suppress the variation in electrical characteristics, including the on-voltage variation ΔVon. In this case, by setting the thickness of the buffer layer 11 to 3 μm or greater, the variation in electrical characteristics, including the on-voltage variation ΔVon, can be further suppressed. This also makes it possible to satisfy the currently required on-voltage variation ΔVon.

[0050] According to the present embodiment described above, the thickness of the buffer layer 11 is set to be greater than 1 μm, and the relative intensity has a minimum value within the buffer layer 11. This makes it possible to suppress variations in point defects that may be formed in the drift layer 14, and to suppress variations in electrical characteristics including the on-voltage fluctuation ΔVon.

[0051] (1) In this embodiment, the thickness of the buffer layer 11 is set to 3 μm or more. This further reduces variations in electrical characteristics, including the on-state voltage fluctuation ΔVon. Furthermore, the currently required electrical characteristics, including the on-state voltage fluctuation ΔVon, can be satisfied.

[0052] (2) When configuring a SiC semiconductor device such as that of this embodiment, the ratio of the minimum value of the relative intensity to the relative intensity at the interface between the drift layer 14 and the buffer layer 11 is set to 0.15 or less, whereby the currently required electrical characteristics, including the on-voltage fluctuation ΔVon, can be satisfied, as described above.

[0053] (3) When configuring a SiC semiconductor device such as that of this embodiment, the minimum value of the relative intensity is set to 0.2 or less, so that the currently required electrical characteristics, including the on-state voltage fluctuation ΔVon, can be satisfied, as described above.

[0054] (Modification of First Embodiment) A modification of the first embodiment will be described. In the first embodiment, an impurity element may be further added to the substrate 1. For example, at least one impurity element selected from boron, hydrogen, helium, titanium, vanadium, and aluminum may be implanted into the substrate 1 by ion implantation. Furthermore, the substrate 1 may contain a large amount of impurity elements when preparing a SiC ingot for the substrate 1 by sublimation recrystallization. In this case, for example, a sublimation furnace may be set to an atmosphere containing impurity elements such as boron. Then, when growing SiC crystals by sublimation recrystallization, a SiC ingot containing the impurity element throughout may be manufactured, and the SiC ingot may be cut to obtain the substrate 1. Increasing the amount of impurity contained in the substrate 1 in this way facilitates suppression of the on-state voltage fluctuation ΔVon.

[0055] (Other Embodiments) While the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0056] In the first embodiment, a SiC semiconductor device has been described in which an n-channel type trench gate MOSFET is formed, with the first conductivity type being n-type and the second conductivity type being p-type. However, the SiC semiconductor device may be configured with a semiconductor switching element of another structure, for example, a p-channel type trench gate MOSFET in which the conductivity types of each component are inverted relative to the n-channel type. Furthermore, the SiC semiconductor device may be configured with a planar gate structure instead of a semiconductor device with a trench gate structure. In addition to the MOSFET, the SiC semiconductor device may also be configured with an IGBT of a similar structure formed therein. In the case of an IGBT, the n-channel MOSFET in the first embodiment may be configured with a planar gate structure instead of a trench gate structure. ＋ The substrate 1 is ＋Except for the change to the substrate 1 of the same type, the vertical MOSFET is the same as that described in the first embodiment.

[0057] [Disclosure of the Present Invention] The above-described present disclosure can be understood from the following perspectives, for example. [First Aspect] A silicon carbide semiconductor device comprising: a substrate (1) made of silicon carbide; and an epitaxial layer (2) arranged on the substrate and made of silicon carbide, the epitaxial layer having: a buffer layer (11) arranged on the substrate side and having a lower impurity concentration than the substrate; and a drift layer (14) arranged on the buffer layer and having a lower impurity concentration than the buffer layer, the buffer layer having a thickness of more than 1 μm, and the relative intensity of DAP emission to band-edge emission has a minimum value in the buffer layer. "Second Aspect" A silicon carbide semiconductor device according to the first aspect, wherein the buffer layer has a thickness of 3 μm or more. [Third Aspect] The silicon carbide semiconductor device according to the first or second aspect, wherein a ratio of a minimum value of the relative intensity in the buffer layer to the relative intensity at the interface between the buffer layer and the drift layer is 0.15 or less. [Fourth Aspect] The silicon carbide semiconductor device according to any one of the first to third aspects, wherein the minimum value of the relative intensity is 0.2 or less. [Fifth Aspect] The buffer layer has an impurity concentration of 0.45×10 １８ cm －３ or more than 5.0 × 10 １８ cm －３a trench gate structure in which a gate insulating film (21) is formed on an inner wall surface of a trench (20) formed from the one surface side of the semiconductor substrate with one direction in a surface direction of the semiconductor substrate as a longitudinal direction, the trench having a gate insulating film (21) formed on an inner wall surface of the trench, the gate insulating film (21) being a first conductivity type or a second conductivity type, the buffer layer and the drift layer being the first conductivity type, a first conductivity type impurity region (17) formed on the one surface side and in contact with the gate insulating film on a side surface of the trench; a second conductivity type base layer (16) in contact with the gate insulating film on a side surface of the trench located below the impurity region; a second conductivity type trench lower layer (24) formed so as to face a lower surface of the trench; a plurality of second conductivity type deep layers (15) extending along an intersecting direction intersecting a longitudinal direction of the trench and connected to the trench lower layer; and a first conductivity type JFET layer (13) disposed between the deep layers adjacent to each other in the longitudinal direction of the trench and in contact with the base layer, having a portion extending along the intersecting direction and on which the lower surface of the trench is disposed.

Claims

1. A silicon carbide semiconductor device comprising: a substrate (1) made of silicon carbide; and an epitaxial layer (2) arranged on the substrate and made of silicon carbide; the epitaxial layer having a buffer layer (11) arranged on the substrate side and having a lower impurity concentration than the substrate; and a drift layer (14) arranged on the buffer layer and having a lower impurity concentration than the buffer layer; the buffer layer having a thickness of more than 1 μm; and the relative intensity of DAP emission to band-edge emission has a minimum value within the buffer layer.

2. The silicon carbide semiconductor device according to claim 1, wherein the buffer layer has a thickness of 3 μm or more.

3. The silicon carbide semiconductor device according to claim 1, wherein a ratio of the minimum value of the relative intensity in the buffer layer to the relative intensity at the interface between the buffer layer and the drift layer is 0.15 or less.

4. The silicon carbide semiconductor device according to claim 1, wherein the relative intensity has a minimum value of 0.2 or less.

5. The buffer layer has an impurity concentration of 0.45×10 １８ cm －３ or more than 5.0 × 10 １８ cm －３ 2. The silicon carbide semiconductor device according to claim 1, wherein:

6. A semiconductor substrate (10) including the substrate and the epitaxial layer, with the surface facing the substrate being the other surface (10b) and the surface opposite to the other surface being one surface (10a); and a trench gate structure in which a gate insulating film (21) is formed on the inner wall surface of a trench (20) formed from the one surface side of the semiconductor substrate with one direction in the surface direction of the semiconductor substrate as the longitudinal direction, and a gate electrode (22) is arranged on the gate insulating film, wherein the substrate is of a first conductivity type or a second conductivity type, the buffer layer and the drift layer are of the first conductivity type, 6. The silicon carbide semiconductor device according to claim 1, wherein the semiconductor substrate includes: an impurity region (17) of a first conductivity type formed on the one surface and in contact with the gate insulating film on a side surface of the trench; a base layer (16) of a second conductivity type in contact with the gate insulating film on a side surface of the trench located below the impurity region; a trench lower layer (24) of the second conductivity type formed so as to face a lower surface of the trench; a plurality of deep layers (15) of the second conductivity type extending along an intersecting direction intersecting a longitudinal direction of the trench and connected to the trench lower layer; and a JFET layer (13) of the first conductivity type disposed between the deep layers adjacent to each other in the longitudinal direction of the trench and in contact with the base layer, having a portion extending along the intersecting direction and on which the lower surface of the trench is disposed.

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