Embedding frame, embedded substrate and preparation method therefor, power supply apparatus, and electronic device

Abstract

An embedding frame, an embedded substrate, a power supply apparatus, an electronic device, and a preparation method for an embedded substrate. The embedding frame comprises a core retainer, a first wiring layer and a first insulating layer, wherein the core retainer comprises two oppositely arranged side plate surfaces, the first wiring layer is arranged on one side plate surface of the core retainer, and the first insulating layer covers the outside of the first wiring layer. The embedding frame is provided with an embedding groove in which electronic components can be embedded, wherein the embedding groove runs through the core retainer, the first wiring layer and the first insulating layer. In this way, on the basis of the insulating layer arranged on the outside of the wiring layer, insulation protection can be constructed for the wiring layer; there is no copper on the surface of the embedding frame, and when a build-up layer is further laminated after component mounting, the insulating layer can effectively block foreign objects from coming into contact with the wiring layer, thereby effectively avoiding the risk of interlayer short circuiting, and also achieving the effect of mitigating the warpage of an embedded substrate. Overall, the present invention exhibits high reliability to meet application requirements of various high-integration and high-density scenarios.

Description

Embedded frame, embedded substrate and preparation method, power supply device and electronic equipment

[0001] The present application claims priority from the Chinese patent application No. 202411069417.3 filed on August 5, 2024, and entitled "Embedded frame, embedded substrate and preparation method, power supply device and electronic equipment", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of electronic component packaging, in particular to an embedded frame, an embedded substrate, a power supply device, an electronic equipment and a preparation method of the embedded substrate. BACKGROUND

[0003] The embedded substrate technology can embed electronic components such as but not limited to chips, resistors, capacitors, inductors, etc. in the embedded frame of the substrate, and realize interconnection through peripheral circuits to form a high-integration and high-density functional module. In the general embedded substrate process, an embedded groove is first formed on the embedded frame of the surface wiring, and then the component mounting and subsequent processes such as substrate build-up pressing are performed. Between the component mounting and the substrate build-up pressing station, if the environment or device foreign matter falls on the embedded frame of the surface wiring, it is easy to cause interlayer short circuit after laminating and building up, that is, based on the existence of foreign matter, the short circuit between the surface wiring of the embedded frame and the outer layer build-up wiring is caused. In particular, the small foreign matter cannot be effectively detected during product electrical measurement, which causes hidden dangers of reliability in the terminal product and has a great impact. SUMMARY

[0004] Embodiments of the present application provide an embedded frame, an embedded substrate, a preparation method of the embedded substrate, a power supply device and an electronic equipment. By optimizing the structure of the embedded frame, the short circuit risk of the embedded substrate is avoided, and the reliability is improved.

[0005] In a first aspect, an embodiment of the present application provides an embedded frame for embedding electronic components, specifically comprising a core retaining body, a first wiring layer and a first insulating layer; wherein the core retaining body comprises two side plate surfaces arranged oppositely, the first wiring layer is arranged on one side plate surface of the core retaining body, and the first insulating layer is arranged outside the first wiring layer; the embedded frame is provided with an embedded groove for embedding electronic components, and the embedded groove penetrates through the core retaining body, the first wiring layer and the first insulating layer. In this way, based on the insulating layer arranged outside the wiring layer, the insulating protection of the wiring layer can be constructed, that is, there is no copper on the surface of the embedded frame. After mounting the component and further pressing the build-up layer, the insulating layer can effectively prevent the foreign matter from contacting the wiring layer, and the interlayer short circuit risk is effectively avoided. Overall, it has good reliability to meet the application requirements of different high-integration and high-density scenes.

[0006] In addition, the insulating layer arranged outside the embedded frame can improve the warping of the embedded substrate.

[0007] The core holding body is exemplarily a core plate. In actual applications, the core plate can be made of an organic material or a glass material.

[0008] The core holding body is exemplarily a core plate. In actual applications, the core plate can be made of an organic material or a glass material.

[0009] Based on the first aspect, the embodiments of the present application further provide a first implementation of the first aspect: the embedded frame further comprises a second wiring layer and a second insulating layer, wherein the second wiring layer is arranged on the other side plate surface of the core holding body, the second insulating layer is arranged outside the second wiring layer, and the embedded groove penetrates through the second wiring layer and the second insulating layer. In this way, the needs of different application scenarios can be met, and good adaptability is achieved.

[0010] For example, in actual applications, for electronic components with PINs on both sides, the interconnection wiring on the corresponding side can be conveniently constructed.

[0011] Exemplarily, the first insulating layer and the second insulating layer can be made of Ajinomoto Build-up Film (ABF) or Prepreg (PP) material.

[0012] Based on the first implementation of the first aspect, the embodiments of the present application further provide a second implementation of the first aspect: the thickness of the first insulating layer and the thickness of the second insulating layer are the same or different. In this way, the warping of the embedded substrate can be further improved.

[0013] In actual applications, for application scenarios with asymmetric product structures, the thickness of the first insulating layer and / or the second insulating layer can be adjusted for processing. For example, the asymmetric arrangement of the embedded substrate surface-mounted device can limit the warping trend by reducing or increasing the thickness of the first insulating layer and the second insulating layer. In this way, on the basis of effectively preventing foreign matter from contacting the wiring layer, the warping problem of the embedded substrate product can be flexibly improved. Overall, the application reliability and good adaptability are taken into account.

[0014] Based on the first implementation of the first aspect or the second implementation of the first aspect, the embodiments of the present application further provide a third implementation of the first aspect: the core holding body is provided with a through structure, and the first wiring layer and the second wiring layer are interconnected through the through structure. In this way, the line interconnection of the corresponding double-layer wiring layer can be realized as needed, and a functional circuit that meets different needs can be constructed.

[0015] Exemplarily, the conductive structure includes a via hole with copper plating on the end face, a via hole without copper plating on the end face, or an X-shaped hole.

[0016] In actual applications, the number and the position of the conductive structures can be configured according to the functional requirements of the product to establish the corresponding interconnection relationship between the first wiring layer and the second wiring layer.

[0017] For the case that multiple conductive structures are arranged on the embedded frame, a combination of different structural forms of the conductive structures can be used, such as, but not limited to, any combination of the PTH hole without Cap copper, the PTH hole with Cap copper, and the X-shaped hole.

[0018] Based on the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, the embodiments of the present application further provide a fourth implementation of the first aspect: the first insulating layer is arranged as one layer or multiple layers, and the second insulating layer is arranged as one layer or multiple layers. In actual applications, the actual process conditions can be determined to have better processability.

[0019] The second aspect of the embodiments of the present application provides an embedded substrate, which includes an embedded frame, a build-up layer, and an electronic component. The embedded frame is as described above, the electronic component is embedded in the embedded groove of the embedded frame, the build-up layer is arranged on the embedded frame, and the wiring layer of the build-up layer is electrically connected with the pin of the electronic component. Based on the embedded frame without copper on the surface, technical support is provided to avoid the risk of short circuit of the embedded substrate. In actual applications, for smaller foreign matter that cannot be effectively detected during product electrical measurement, the hidden danger of the reliability of the terminal product can also be avoided, and the product reliability can be effectively improved.

[0020] Based on the second aspect, the embodiments of the present application further provide a first implementation of the second aspect: the thickness of the embedded frame is greater than or equal to the thickness of the electronic component. In this way, the electronic component embedded in the embedded groove will not be exposed to the embedded frame, that is, it can be completely placed in the corresponding embedded groove, and the risk of subsequent lamination process can be further avoided.

[0021] The third aspect of the embodiments of the present application provides a power supply device, which includes a chip and an inductor. The chip forms an embedded package by using the embedded substrate as described above, and the inductor is surface-mounted on the embedded substrate. Exemplarily, the inductor can be surface-mounted on the front surface of the embedded substrate, or surface-mounted on the back surface of the embedded substrate.

[0022] Based on the third aspect, the embodiments of the present application further provide a first implementation of the third aspect: the power supply device further comprises a plurality of electronic elements, a part of the plurality of electronic elements and the chip form a buried package by using the embedded substrate, and another part of the plurality of electronic elements and the inductor element are attached to the embedded substrate. In this way, the product function can be flexibly configured according to the needs, and the designability is good.

[0023] The fourth aspect of the embodiments of the present application provides an electronic device, which comprises a circuit board and a power supply device, the power supply device is arranged on the circuit board, and the power supply device is the power supply device as described above.

[0024] In actual application, the electronic device can be a server, a computer or a high-performance computing cluster, for a high-power, high-integration and super-large data center server. In addition, the electronic device can also be a switch, a router or an edge device, etc.

[0025] The fifth aspect of the embodiments of the present application provides a preparation method of the embedded substrate, which comprises: providing the buried embedding frame as described above; attaching the electronic element so that the electronic element is arranged in the embedded groove of the buried embedding frame; filling and pressing by using the embedded filling material to fix the electronic element and the buried embedding frame; and manufacturing the increment layer outside the embedded substrate.

[0026] In actual application, the adhesive film can be attached to one side surface of the buried embedding frame to embed the electronic element in the embedded groove and attach and fix the electronic element to the adhesive film. Further, the adhesive film can be removed after the electronic element and the buried embedding frame are fixed by pressing and filling of the embedded filling material.

[0027] Based on the fifth aspect, the embodiments of the present application further provide a first implementation of the fifth aspect: the preparation of the buried embedding frame comprises: preparing a core holding body, and forming a surface copper layer on the plate surface of the core holding body; patterning the surface copper layer to form a wiring layer of the buried embedding frame; laminating an insulating layer outside the wiring layer; and opening an embedded groove, and the embedded groove penetrates through the core holding body, the wiring layer and the insulating layer.

[0028] Based on the first implementation of the fifth aspect, the embodiments of the present application further provide a second implementation of the fifth aspect: the patterning of the surface copper layer to form the wiring layer of the buried embedding frame comprises: patterning the surface copper layer on both sides of the plate surface of the core holding body to form a first wiring layer and a second wiring layer of the buried embedding frame, respectively, and preparing a conductive structure electrically connected to the first wiring layer and the second wiring layer.

[0029] Based on the first implementation of the fifth aspect, the embodiments of the present application further provide a second implementation of the fifth aspect: the conductive structure comprises a via hole with a copper-plated end face, a via hole without a copper-plated end face or an X-shaped hole. BRIEF DESCRIPTION OF DRAWINGS

[0030] FIG. 1 is a schematic diagram of a cross section of an embedded frame according to an embodiment of the present application;

[0031] FIG. 2 is a schematic diagram of a process flow of the embedded frame shown in FIG. 1 according to an embodiment of the present application;

[0032] FIG. 3 is a schematic diagram of a cross section of an embedded substrate according to an embodiment of the present application;

[0033] FIG. 4 is a schematic diagram of a cross section of another embedded frame according to an embodiment of the present application;

[0034] FIG. 5 is a schematic diagram of a process flow of the embedded frame shown in FIG. 4 according to an embodiment of the present application;

[0035] FIG. 6 is a schematic diagram of a cross section of another embedded substrate according to an embodiment of the present application;

[0036] FIG. 7 is a schematic diagram of a cross section of another embedded substrate according to an embodiment of the present application;

[0037] FIG. 8 is a schematic diagram of a cross section of another embedded frame according to an embodiment of the present application;

[0038] FIG. 9 is a schematic diagram of a process flow of the embedded frame shown in FIG. 8 according to an embodiment of the present application;

[0039] FIG. 10 is a schematic diagram of a cross section of another embedded frame according to an embodiment of the present application;

[0040] FIG. 11 is a flow chart of a method for manufacturing an embedded substrate according to an embodiment of the present application;

[0041] FIG. 12 is a schematic diagram of a power supply device according to an embodiment of the present application;

[0042] FIG. 13 is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] The present application provides an embedded substrate implementation scheme that can improve reliability, which can be applied to different high-integration and high-density application scenarios.

[0044] The embedded substrate technology is used to embed electronic components in the embedded frame of the substrate, which can shorten the link path between components, reduce transmission loss, improve product integration, and reduce module size. For example, an embedded substrate for a power chip packaging module, a typical embedded substrate architecture, the chip, capacitor and / or resistor components can be embedded in the embedded frame, and the surface of the embedded frame is stacked with an increase layer, which can be used to realize the interconnection between electronic components and the connection with external circuits. Generally, the process of the embedded substrate opens the embedded groove on the embedded frame, the surface of the embedded frame has a wiring, and then the components are attached and the increase layer is compressed. Between the component attachment and the compression increase layer station, if the environment or equipment foreign matter falls on the surface wiring of the embedded frame, based on the existence of foreign matter, it is easy to cause interlayer short circuit after laminating the increase layer. For smaller foreign matter, it is often not effectively detected during product electrical measurement, resulting in potential reliability risks in the end product, thereby causing greater impact.

[0045] Based on this, the embedded frame of the embedded substrate provided by the embodiments of the present application is used to embed electronic components, which includes a core holding body, a first wiring layer and a first insulation layer. The core holding body includes two oppositely arranged side plate surfaces, the first wiring layer is arranged on one side plate surface of the core holding body, and the first insulation layer is arranged outside the first wiring layer. The embedded groove of the embedded frame penetrates the core holding body, the first wiring layer and the first insulation layer. In this way, based on the insulation layer arranged outside the wiring layer, insulation protection of the wiring layer can be constructed. After attaching the components and further compressing the increase layer, the insulation layer can effectively prevent foreign matter from contacting the wiring layer, effectively avoiding the risk of interlayer short circuit. Overall, it has good reliability to meet the application requirements of different high integration and high density scenarios.

[0046] In order not to lose generality, the specific embodiments will be described in detail in combination with the drawings. Please refer to FIG. 1, which is a cross-sectional schematic view of an embedded frame provided by the embodiments of the present application.

[0047] As shown in FIG. 1, the core holding body 11 of the embedded frame 10 can be made of a core plate, for example but not limited to, a core plate made of organic material or glass material.

[0048] In this embodiment, the two side plate surfaces of the core holding body 11 are respectively provided with a wiring layer 12: a first wiring layer 121 and a second wiring layer 122. Specifically, the first wiring layer 121 is arranged on one side plate surface of the core holding body 11, and the second wiring layer 122 is arranged on the other side plate surface of the core holding body 11.

[0049] In a specific implementation, the first wiring layer 121 and the second wiring layer 122 can be respectively used to electrically connect with the corresponding side of the build-up wiring layer, to realize the interconnection between the electronic components (not shown in the figure) embedded in the embedded groove 15 and the external circuit, and to construct the corresponding functional circuit. In other specific implementations, the first wiring layer 121 and the second wiring layer 122 can also be used for interconnection between the electronic components (not shown in the figure).

[0050] The outer part of the wiring layer 12 is covered with an insulating layer 13: a first insulating layer 131 and a second insulating layer 132. Specifically, the first insulating layer 131 covers the outer part of the first wiring layer 121, and the second insulating layer 132 covers the outer part of the second wiring layer 122. In this way, the corresponding side of the wiring layer 12 can be protected from foreign matter; that is, compared with the traditional embedded frame, the surface of the embedded frame 10 provided by the present application is copper-free, which can effectively avoid the risk of interlayer short circuit caused by foreign matter.

[0051] In a specific implementation, the insulating layer 13 can be made of ABF material or PP material. It can be understood that the material selection of the insulating layer can be determined according to the overall design requirements of the product, as long as it can effectively block the influence of foreign matter and effectively avoid the risk of interlayer short circuit.

[0052] In other specific implementations, the first insulating layer 131 covering the outer part of the first wiring layer 121 can be set to one layer or multiple layers as needed. Similarly, the second insulating layer 132 covering the outer part of the second wiring layer 122 can also be set to one layer or multiple layers as needed. The present application does not make any limitation.

[0053] The first wiring layer 121 and the second wiring layer 122 can be interconnected through the conductive structure 14 penetrating the core retaining body 11. In FIG. 1, a through-hole (Plating Through Hole, PTH) with a copper-plated end face (Cap copper) is used as a kind of conductive structure 14. A copper layer is plated on the side wall of the hole, so that the hole wall of the PTH hole has conductivity, and the end face of the through-hole has a copper-plated end face structure, forming a conductive structure 14 for interconnecting the first wiring layer 121 and the second wiring layer 122, and respectively forming an electrical connection with the first wiring layer 121 and the second wiring layer 122 on both sides of the embedded frame 10.

[0054] In actual application, based on the PTH hole with Cap copper as the conductive structure, the welding performance can be further enhanced while improving the current-carrying capacity.

[0055] For the sake of clarity, the conductive structure 14 is exemplarily shown as a PTH hole with CAP copper in FIG. 1. Of course, the number of the conductive structures 14 is not limited to one as shown in the figure, and can be configured according to the functional requirements of the product to establish the corresponding interconnection relationship between the first wiring layer 121 and the second wiring layer 122. The embodiments of the present application are not limited.

[0056] The embedding groove 15 for embedding the electronic component is provided through the embedding frame. In other words, the embedding groove 15 is provided through the first insulating layer 131, the first wiring layer 121, the core holding body 11, the second wiring layer 122, and the second insulating layer 132. Before the electronic component is mounted, the surface of the embedding frame 10 is free of copper, and the embedding frame 10 is an intermediate product of the embedding frame process. The embedding frame 10 is protected by the two insulating layers 13 and is not affected by foreign matter that may be generated during use of the environment or equipment.

[0057] For the sake of clarity, only one embedding groove 15 is exemplarily shown in FIG. 1. It should be noted that in different application scenarios, the position, number, and size of the embedding groove can be configured according to the functional requirements of the product to embed one or more electronic components in one embedding frame and establish the corresponding interconnection relationship between the first wiring layer 121 and the second wiring layer 122. The embodiments of the present application are not limited.

[0058] The process of the embedding frame 10 described in FIG. 1 will be briefly described below with reference to FIG. 2.

[0059] In step S201, a core plate is prepared as the core holding body 11. In a specific implementation, based on the incoming core plate, a copper layer can be prepared on the two side surfaces of the core holding body 11 to form the wiring layer 12.

[0060] In step S202, the wiring layer is patterned, and the conductive structure 14 is prepared. In a specific implementation, the first wiring layer 121 and the second wiring layer 122 on the two sides of the core holding body 11 can be formed. Here, the conductive structure 14 is a PTH hole with CAP copper, which is electrically connected to the first wiring layer 121 and the second wiring layer 122 through the PTH hole with CAP copper to achieve interconnection between the two.

[0061] In step S203, the insulating layer is laminated. In a specific implementation, the first insulating layer 131 and the second insulating layer 132 can be laminated outside the first wiring layer 121 and the second wiring layer 122. Here, the material of the insulating layer can be ABF or PP.

[0062] Step S204, opening the embedded groove 15. In a specific implementation, a UV Laser, a CO2 laser or other mechanical processing technology can be used to open the groove on the embedded frame 10. Thus, the embedded frame 10 without copper on the surface is made.

[0063] Based on the insulating layer arranged outside the embedded frame, in the subsequent process of embedding the substrate, in addition to effectively blocking the contact between foreign matter and the wiring layer, it also has the effect of improving the warping of the embedded substrate. Please refer to Figure 3, which is a schematic cross-sectional view of an embedded substrate according to an embodiment of the present application. The embedded substrate 100 shown in Figure 3 is constructed based on the embedded frame 10 shown in Figure 1.

[0064] The embedded substrate 100 includes the embedded frame 10, the build-up layer 20 and the electronic component 30, wherein the electronic component 30 is embedded in the embedded groove 15 of the embedded frame 10, for example, the electronic component 30 can be a chip of a power module, or can be a resistor or a capacitor or other components. The build-up layer 20 includes a build-up wiring layer 21 and a dielectric layer 22 which are laminated. The pin of the electronic component 30 can be electrically connected to the build-up wiring layer 21 through the blind hole 211 provided in the corresponding side build-up layer 20.

[0065] In the present embodiment, the first build-up layer 201 is laminated on one side of the first insulating layer 131, and the second build-up layer 202 is laminated on one side of the second insulating layer 132. For the embedded substrate 100, based on the arrangement of the insulating layer 12 outside the embedded frame 10, the overall rigidity of the structure is enhanced, which can improve the warping problem of the embedded substrate 100 to a certain extent, for example, but not limited to, the deformation caused by the operation of the component or the assembly process, etc., reduces the influence of warping stress, and further improves the application reliability.

[0066] As shown in Figure 1, the thickness of the first insulating layer 131 is t1, and the thickness of the second insulating layer 132 is t2. In a specific implementation, the thickness t1 of the first insulating layer 131 and the thickness t2 of the second insulating layer 132 can be the same or different, in order to further improve the warping of the embedded substrate 100. In particular, for the application scenarios of asymmetric structure of the product, the thickness of the first insulating layer 131 and / or the second insulating layer 132 can be adjusted for processing. For example, the asymmetric arrangement of the embedded substrate surface-mounted device, etc., so that the embedded substrate 100 as a whole has a warping of the upper middle part, which can be limited in the reverse direction by reducing the thickness t1 of the first insulating layer 131 or increasing the thickness t2 of the second insulating layer 132. On the basis of effectively blocking the contact between foreign matter and the wiring layer, the warping problem of the embedded substrate product can be flexibly improved. Overall, the application reliability and good adaptability are taken into account.

[0067] In a specific implementation, the material of the dielectric layer 22 of the build-up layer 20 can be the same as or different from the material of the insulating layer 12. The material can be determined according to the overall design requirement of the product, which is not limited in the embodiments of the present application.

[0068] Specifically, the electronic component 30 shown in FIG. 3 is a single-sided pin component, and the pin thereof can be electrically connected to the build-up wiring layer 21 of the second build-up layer 202 through the blind via hole 211.

[0069] In other specific implementations, the electronic component can also be a double-sided pin component (not shown in the figure), which is electrically connected to the build-up wiring layers 21 of the build-up layers on both sides of the embedded frame 10. The specific implementation can be selected according to the overall design requirement of the product.

[0070] Optionally, the thickness of the embedded frame 10 is not less than the thickness of the electronic component 30, that is, the thickness of the embedded frame 10 is greater than or equal to the thickness of the electronic component 30. In this way, it can be ensured that the electronic component 30 embedded in the corresponding embedded groove 15 is not exposed, that is, it is completely embedded in the embedded groove 15. In this way, the risk of subsequent lamination process can be further avoided.

[0071] In addition, the build-up wiring layer 21 of the first build-up layer 201 and the build-up wiring layer 21 of the second build-up layer 202 can be electrically connected to the first wiring layer 121 and the second wiring layer 122 of the embedded frame 10 on the corresponding side through the interlayer conductive structure such as the blind hole 212. It should be understood that the interlayer conductive structure shown in the figure is only an exemplary schematic, and in different product application scenarios, the interlayer conductive structure can be configured according to actual functional needs. The embodiments of the present application are not limited.

[0072] For the embedded frame 10 with the wiring layer 12 arranged on both sides, the conductive structure for realizing the interconnection of the first wiring layer 121 and the second wiring layer 122 can also adopt other structural forms.

[0073] Please refer to FIG. 4, which is a cross-sectional view of another embedded frame provided by the embodiments of the present application. In order to clearly show the difference and connection between the embedded frame of the present embodiment and the embedded frame described in FIG. 1, the same functional components or structures are shown with the same reference numerals in the figure.

[0074] As shown in FIG. 4, the embedded frame 10 uses a PTH hole without Cap copper as another conductive structure 14a, and a copper layer is plated on the sidewall of the hole, so that the hole wall of the PTH hole has conductivity, forming a conductive structure 14a for realizing the interconnection of the first wiring layer 121 and the second wiring layer 122.

[0075] Other functional components and connection relationships can be consistent with the embedded frame described in FIG. 1. Here, no further description is given.

[0076] The process of manufacturing the embedded frame 10 described in FIG. 4 is briefly explained below in connection with FIG. 5.

[0077] In step S501, a core plate is prepared as the core holding body 11.

[0078] In step S502, a wiring layer is patterned to form the interlayer conductive structure 14a. Here, the conductive structure 14a is a CAP-free PTH hole.

[0079] In step S503, an insulating layer is laminated.

[0080] In step S504, an embedded groove 15 is opened. Thus, the surface-CAP-free embedded frame 10 is manufactured.

[0081] The above steps S501, S503 and S504 can be the same as steps S201, S203 and S204 in FIG. 2.

[0082] In addition, please refer to FIG. 6 and FIG. 7, the embedded substrate 100 shown in FIG. 6 and FIG. 7 are both based on the embedded frame 10 shown in FIG. 4. In order to clearly show the difference and connection between each embodiment and the embedded substrate described in FIG. 3, the same functional components or structures are shown with the same reference signs in the figures.

[0083] Please refer to FIG. 6, the embedded substrate 100 includes the embedded frame 10, the build-up layer 20 and the electronic component 30 shown in FIG. 4. The electronic component 30 is embedded in the embedded groove 15 of the embedded frame 10. The build-up layer 20 includes the build-up wiring layer 21 and the dielectric layer 22 which are laminated together. The first build-up layer 201 is laminated on one side of the first insulating layer 131, and the second build-up layer 202 is laminated on one side of the second insulating layer 132.

[0084] In this embodiment, the build-up wiring layer 21 of the first build-up layer 201 and the build-up wiring layer 21 of the second build-up layer 202 can be electrically connected through the via 212a. In a specific implementation, the via 212a can be connected with the conductive structure on the embedded frame 10, such as but not limited to the vertical interconnection shown in the figure, or the electrical connection between the two can be established through an independently formed via. The embodiments of the present application are not limited.

[0085] In other possible implementations, the build-up wiring layer 21 of the first build-up layer 201 and the build-up wiring layer 21 of the second build-up layer 202 can also be electrically connected with the first wiring layer 121 and the second wiring layer 122 of the embedded frame 10 on the corresponding side through the interlayer conductive structure such as the blind via (not shown in the figure). In different product application scenarios, the configuration can be made according to the actual functional needs. The embodiments of the present application are not limited.

[0086] The via 212a shown in FIG. 6 is a Capless copper PTH hole. In other embodiments, please refer to FIG. 7, the via 212b is a Cap copper PTH hole, which electrically connects the build-up wiring layer 21 of the first build-up layer 201 and the build-up wiring layer 21 of the second build-up layer 202 of the embedded substrate 100.

[0087] It should be understood that the interconnection structure of the build-up wiring layer 21 can be selected according to product design and process conditions, such as but not limited to any combination of Capless copper PTH hole, Capless copper PTH hole and X-shaped hole (not shown in the figure) and the like, which is not limited in the embodiments of the present application.

[0088] For the embedded substrate shown in FIGS. 6 and 7, other functional components and connection relationships can be consistent with the embedded substrate described in FIG. 3. Here, no longer described in detail.

[0089] For the embedded frame 10 with the wiring layer 12 arranged on both sides, please also refer to FIG. 8, which is another cross-sectional view of the embedded frame provided by the embodiments of the present application. In order to clearly show the difference and relationship between the implementation and the embedded frame described in FIG. 1, the same functional components or structures are shown with the same marks in the figure.

[0090] As shown in FIG. 8, the embedded frame 10 takes the X-shaped hole as another through structure 14b, and the through structure 14b is formed by filling copper in the X-shaped opening to realize the interconnection between the first wiring layer 121 and the second wiring layer 122. The interlayer large current carrying capacity and high thermal conductivity can be further improved, and the architecture design is more flexible.

[0091] Other functional components and connection relationships can be consistent with the embedded frame described in FIG. 1. Here, no longer described in detail.

[0092] The process of the embedded frame 10 described in FIG. 8 will be briefly described below in combination with FIG. 9.

[0093] In step S901, a core plate is prepared as a core holding body 11.

[0094] In step S902, a wiring layer is patterned, and an interlayer through structure 14b is prepared. Here, the through structure 14b is an X-shaped hole.

[0095] In step S903, an insulating layer is laminated.

[0096] In step S904, an embedded groove 15 is formed. Thus, a surface copper-free embedded frame 10 is made.

[0097] The above steps S901, S903 and S904 can refer to the same steps S201, S203 and S204 in FIG. 2.

[0098] It can be understood that, for the sake of clarity, the via with Cap copper is exemplarily shown in FIG. 4, and the X-shaped hole is exemplarily shown in FIG. 8. The number of the via structures can be configured according to the functional requirements of the product, so as to establish the corresponding interconnection relationship between the first wiring layer 121 and the second wiring layer 122. The embodiments of the present application are not limited.

[0099] In addition, for the case that the embedded frame 10 is provided with a plurality of via structures, in other possible specific implementations, a combination of different structure forms of the via structures can be used, for example, but not limited to, any combination of the via structures such as the via without Cap copper, the via with Cap copper, and the X-shaped hole (not shown in the figure).

[0100] In the foregoing embodiments, the embedded frame is provided with the wiring layer 12 on both sides. In other implementations, the embedded frame can be provided with the wiring layer on one side surface of the core holding body 11, and the corresponding insulating layer on the other side surface. Please refer to FIG. 10, which is a schematic cross-sectional view of another embedded frame provided by the embodiments of the present application. In order to clearly show the differences and connections between the present embodiment and the embedded frame described in FIG. 1, the same functional components or structures are shown with the same reference numerals in the figure.

[0101] As shown in FIG. 10, the embedded frame 10 includes the core holding body 11 made of a core plate, and is provided with the wiring layer 12 (121) and the insulating layer 13 (131) on one side surface of the core holding body 11. Similarly, based on the provision of the insulating layer, the contact of foreign matters with the wiring layer can be blocked, and the risk of short circuit can be avoided.

[0102] Other functional components and connection relationships can be consistent with those of the embedded frame described in FIG. 1. Here, no further description is given.

[0103] The foregoing embodiments all use the core plate as the core holding body 11. In other specific implementations, the core holding body can also be formed by filling materials. That is, the frame structure without core plate, which is simple in process and can reasonably control the manufacturing cost.

[0104] For the embedded substrate described in the foregoing embodiments, the preparation method thereof will be briefly described below with reference to FIG. 11.

[0105] Step S1101, providing the embedded frame 10 described in the foregoing figures 1, 4, 8 or 10. In a specific implementation, for the embedded frame 10 described in figure 1, for example but not limited to, prepared by the process described in figure 2; for the embedded frame 10 described in figure 4, for example but not limited to, prepared by the process described in figure 5; for the embedded frame 10 described in figure 8, for example but not limited to, prepared by the process described in figure 9; for the embedded frame 10 described in figure 10, please refer to the corresponding process steps in figures 2, 5 or 9.

[0106] Step S1102, attaching the electronic component 30. Specifically, an adhesive film can be attached to one side surface of the embedded frame 10 to embed the electronic component in the embedded groove and attach and fix it to the adhesive film.

[0107] Step S1103, filling and pressing. In a specific implementation, an embedded filling material can be used to press and fill the gap between the electronic component and the embedded groove. The adhesive film can be removed after the electronic component is fixed to the embedded frame 10. Here, the embedded filling material can be ABF, or selected according to actual process conditions.

[0108] Step S1104, making the build-up layer. In a specific implementation, the aforementioned embedded filling material can form a dielectric layer of the build-up layer in conjunction with the insulating layer of the embedded frame 10 while filling the gap. On this basis, the surface copper of the build-up wiring layer is prepared, and the build-up wiring layer is made by surface patterning.

[0109] In addition, for the case of having multiple outer build-up layers, they can be sequentially pressed and formed according to specific process conditions. At the same time, a solder resist layer is formed on the surface of the wiring layer of the outermost build-up layer, and the surface of the outermost metal is processed. In other possible implementation schemes, the number of build-up layers of each outer build-up layer can be determined according to the overall design requirements of the product, and the corresponding process procedures are formulated. The embodiments of the present application are not limited.

[0110] The embedded substrate architecture scheme described in the foregoing embodiments can be widely applied to the packaging structure of different functional modules. In actual application, the above technical advantages are particularly significant in the power module architecture scenario. Please refer to figure 12, which is a schematic diagram of a power device provided by an embodiment of the present application.

[0111] As shown in figure 12, the power device 1000 includes an inductor 200 and a chip, and also includes a capacitor element and a resistor element (not shown in the figure) to construct a corresponding functional circuit. Among them, the chip can form an embedded package by using the embedded substrate 100 architecture described in figures 3, 6 or 7, and the inductor 200 can be surface-mounted on the surface of the embedded substrate 100.

[0112] In a specific implementation, the capacitive element and the resistive element can be embedded in the embedded substrate 100 together with the chip, or can be surface-mounted on the embedded substrate 100 (not shown in the figure) together with the inductor 200. The embodiments of the present application are not limited in this regard. In a use state, the reliability of the embedded substrate can meet the performance requirements of the power supply device.

[0113] It should be understood that other functions of the power supply device are not the core of the present application, and those skilled in the art can implement them according to the prior art, so they will not be described here.

[0114] In addition to the aforementioned embedded substrate, the present embodiment also provides an electronic device, please refer to FIG. 13, which is a structural schematic diagram of an electronic device provided by the embodiments of the present application.

[0115] As shown in FIG. 13, the electronic device 10000 includes a housing 3000 and a circuit board 2000 disposed in the housing 3000, and the circuit board 2000 is provided with the power supply device 1000 as described in the foregoing embodiments. Based on the high reliability of the power supply device 1000, it can be widely used in different high-density application scenarios.

[0116] In a specific implementation, the electronic device can be a server, a computer, or a high-performance computing cluster, for a high-power, high-integration, and ultra-large-scale data center server. In addition, the electronic device can also be a switch, a router, or an edge device, and the embodiments of the present application are not limited in this regard.

[0117] It should be understood that other functions of the electronic device are not the core of the present application, and those skilled in the art can implement them according to the prior art, so they will not be described here.

[0118] The above is only the preferred embodiment of the present application, it should be pointed out that, for those skilled in the art, without departing from the principles of the present application, can make a number of improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. An embedded frame for embedding electronic components, characterized in that, The embedded frame comprises a core holding body, a first wiring layer and a first insulating layer; the core holding body comprises two oppositely arranged side plate surfaces, the first wiring layer is arranged on one side plate surface of the core holding body, and the first insulating layer is arranged outside the first wiring layer; the embedded frame is provided with an embedded groove, and the embedded groove penetrates through the core holding body, the first wiring layer and the first insulating layer.

2. The flush frame of claim 1, wherein, The embedded frame further comprises a second wiring layer and a second insulating layer, the second wiring layer is arranged on the other side plate surface of the core holding body, the second insulating layer is arranged outside the second wiring layer, and the embedded groove further penetrates through the second wiring layer and the second insulating layer.

3. The flush frame of claim 2, wherein, The thickness of the first insulating layer and the thickness of the second insulating layer are the same or different.

4. The flush frame of claim 2 or 3, wherein, The core holding body is provided with a conductive structure, and the first wiring layer and the second wiring layer are interconnected through the conductive structure.

5. The flush frame of claim 4, wherein, The conductive structure comprises a through hole with copper plating on an end surface, a through hole without copper plating on an end surface or an X-shaped hole.

6. The flush-mount frame of any of claims 2-5, wherein, The first insulating layer is arranged as one layer or multiple layers, and the second insulating layer is arranged as one layer or multiple layers.

7. The flush-mount frame of any of claims 1-6, wherein, The core holding body is a core plate.

8. An embedded substrate, characterized by, The embedded frame comprises an embedded frame, a build-up layer and an electronic component, the embedded frame is the embedded frame according to any one of claims 1 to 7, the electronic component is embedded in the embedded groove of the embedded frame, the build-up layer is arranged on the embedded frame, and a circuit layer of the build-up layer is electrically connected with a pin of the electronic component.

9. The embedded substrate of claim 8, wherein, The thickness of the embedded frame is greater than or equal to the thickness of the electronic component.

10. A power supply device characterized by comprising: The embedded frame comprises a chip and an inductor, the chip forms an embedded package by using the embedded substrate according to claim 8 or 9, and the inductor is attached to the embedded substrate.

11. The power supply device according to claim 10, wherein The power supply device further comprises a plurality of electronic components, a part of the plurality of electronic components and the chip form an embedded package by using the embedded substrate, and another part of the plurality of electronic components and the inductor are attached to the embedded substrate.

12. An electronic device, comprising: The power supply device comprises a circuit board and a power supply device, the power supply device is arranged on the circuit board, and the power supply device is the power supply device according to claim 10 or 11.

13. A method of manufacturing a buried substrate, characterized by, The embedded frame comprises: The embedded frame comprises: The embedded frame comprises: The embedded frame comprises: The embedded frame comprises:

14. The method of claim 13, wherein The embedded frame comprises: The embedded frame comprises: The embedded frame comprises: The embedded frame comprises: The embedded frame comprises:

15. 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The method of claim 15, wherein The conductive structure includes a via plated with copper on an end face, a via not plated with copper on an end face, or an X-shaped hole.

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