Processing method for substrate having support structure, and chip packaging structure

Abstract

The present application relates to the technical field of chip packaging, in particular to a processing method for a substrate having a support structure, and a chip packaging structure. In the chip packaging structure of the present application, a support structure is provided on a substrate, and a barrier film is supported by means of the support structure, such that the barrier film is prevented from being in contact with chip pins under pressure, and contamination caused by effective resonance regions is avoided, thereby ensuring the integrity of cavities, and greatly improving the performance of chips.

Description

A substrate processing method with a support structure and a chip packaging structure

[0001] The present application is based on the Chinese patent application No. 202411087565.8 entitled "A substrate processing method with a support structure and a chip packaging structure" filed on August 8, 2024, and claims priority thereto. TECHNICAL FIELD

[0002] The present application relates to the field of chip packaging technology, and in particular to a substrate processing method with a support structure and a chip packaging structure. BACKGROUND

[0003] Chip packaging structure is one of the key steps in the integrated circuit (IC) manufacturing process, aiming to protect the fragile silicon chip from physical damage, chemical corrosion and environmental impact, and provide a way to electrically connect to the external circuit board.

[0004] At present, the packaging of chips adopts a plastic encapsulation layer covering the chip on the substrate, which encloses a sealed cavity with the plastic encapsulation layer and the substrate and the chip to avoid pollution of the effective resonance area of the chip by the outside world. In order to prevent the overflow of resin into the cavity and pollute the effective resonance area of the chip when the resin and the surface of the substrate are pressed together, a barrier film is usually arranged between the chip and the plastic encapsulation layer, and the edge of the barrier film is adhesively connected with the substrate. However, during the resin pressing process, the barrier film will extend downward under the influence of pressure, and even contact the pins of the chip, thereby destroying the integrity of the cavity and seriously reducing the performance of the chip. SUMMARY

[0005] The embodiments of the present application provide a substrate processing method with a support structure and a chip packaging structure to solve the problem that in the prior art, the barrier film will extend downward under the influence of pressure during the resin pressing process, and even contact the pins of the chip, thereby destroying the integrity of the cavity and seriously reducing the performance of the chip.

[0006] A chip packaging structure, comprising: a substrate, a chip, a barrier film and a plastic encapsulation layer, the conductive pins of the chip are electrically interconnected with the substrate, the barrier film is arranged on the substrate, the barrier film and the substrate form a cavity, the chip is arranged in the cavity, the barrier film and the substrate form a plastic encapsulation layer, and a support structure is arranged on the substrate in the cavity, the support structure is used to support the barrier film when the plastic encapsulation layer is pressed.

[0007] A substrate processing method with a support structure, the processing method comprising:

[0008] providing a substrate with a prepared circuit pattern;

[0009] coating the ink on the substrate for the first time to obtain the substrate after the ink is coated for the first time;

[0010] exposing the substrate for the first time by using the exposure device to obtain the substrate after the first exposure;

[0011] coating the ink on the substrate after the first exposure for the second time to obtain the substrate after the ink is coated for the second time;

[0012] exposing the substrate for the second time by using the exposure device to obtain the substrate after the second exposure;

[0013] developing and cleaning the substrate after the second exposure to obtain the substrate with the support structure.

[0014] The substrate processing method with the support structure and the chip packaging structure provided by the embodiments of the present application set the support structure on the substrate, support the blocking film through the support structure, avoid the blocking film from being in contact with the chip pins under the pressure, avoid the effective resonance area from being polluted, and ensure the integrity of the cavity, which greatly improves the performance of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative labor under the premise of the drawings.

[0016] FIG. 1 is a schematic diagram of the cross-sectional structure of the chip packaging structure provided by an embodiment of the present application;

[0017] FIG. 2 is a schematic diagram of the top view structure of the chip packaging structure provided by an embodiment of the present application;

[0018] FIG. 3 is a schematic diagram of the flow of the substrate processing method with the support structure provided by an embodiment of the present application;

[0019] FIG. 4 is a schematic diagram of the flow of the substrate processing method with the support structure provided by an embodiment of the present application;

[0020] FIG. 5 is a schematic diagram of the flow of the substrate processing method with the support structure provided by an embodiment of the present application;

[0021] FIG. 6 is a schematic diagram of the flow of the substrate processing method with the support structure provided by an embodiment of the present application;

[0022] In the drawings, 1 is a chip, 2 is a blocking film, 3 is a plastic encapsulation layer, 4 is a substrate, 5 is a support structure, 6 is a pin of the chip packaging structure, 51 is a first solder resist layer, and 52 is a second solder resist layer. DETAILED DESCRIPTION

[0023] In order to make the technical problems, technical solutions and beneficial effects solved by the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0024] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "longitudinal", "radial", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like in the description of the present application is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0025] In the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0026] In order to thoroughly understand the present application, detailed structures and steps will be proposed in the following description in order to explain the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail as follows, however, in addition to these detailed descriptions, the present application can also have other implementation manners.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0028] As shown in FIG. 1, a cross-sectional structure schematic diagram of a chip 1 packaging structure is provided, as shown in FIG. 2, a top view structure schematic diagram of a chip 1 packaging structure is provided.

[0029] In an embodiment, as shown in FIG. 1 and FIG. 2, a chip 1 package structure includes a substrate 4, the chip 1, a barrier film 2 and a plastic sealing layer 3, the conductive pins of the chip 1 are electrically interconnected with the substrate 4, the barrier film 2 is arranged on the substrate 4, the barrier film 2 and the substrate 4 form a cavity, the chip 1 is arranged in the cavity, the barrier film 2 and the substrate 4 form the plastic sealing layer 3, the substrate 4 in the cavity is provided with a support structure 5, and the support structure 5 is used to support the barrier film 2 when the plastic sealing layer 3 is pressed.

[0030] The support structure 5 can be of any material, and can be of metal, ink or plastic. The height of the support structure 5 can be set according to actual application, and is preferably not greater than the height of the chip 1 on the substrate 4, and is greater than the height of the pins of the chip 1 on the substrate 4.

[0031] The support structure 5 can be separately arranged, or can be a metal column arranged on a circuit to form a support structure 5 together with the circuit, or can be a metal column arranged on a pad to form a support structure 5 together with the pad, or can be a solder resist ink arranged on a solder resist ink layer to form a support structure 5.

[0032] The support structure 5 can be single-layered or multi-layered, and the number of layers can be set according to actual application. The support structure 5 can be circular, rectangular or of any other shape.

[0033] It is understood that the pin side of the substrate 4 is provided with a chip package structure and a pin 6 of a chip package structure connected to the outside.

[0034] The position of the support structure 5 can be set according to actual application, and the support structure 5 can be arranged on one side of the chip 1, on both sides of the chip 1, on both front and back sides of the chip 1, or on all of the front, back, left and right sides of the chip 1. The support structures 5 can be connected together, or can be independently arranged.

[0035] The chip 1 package structure of the embodiment supports the barrier film 2 through the support structure 5 arranged on the substrate 4, avoids the barrier film 2 from being in contact with the pins of the chip 1 under pressure, avoids pollution of the effective resonance area, and ensures the integrity of the cavity and greatly improves the performance of the chip 1.

[0036] In an embodiment, as shown in FIG. 1 and FIG. 2, on the basis of the above embodiment, the height of the support structure 5 is half of the height of the chip 1 on the substrate 4.

[0037] The chip 1 packaging structure of the embodiment, the height of the support structure 5 is set to half of the height of the chip 1 on the substrate 4, can better support the barrier film 2, so that the barrier film 2 is more stable, and the reliability of the chip 1 packaging structure is improved.

[0038] In an embodiment, as shown in FIG. 1 and FIG. 2, on the basis of the above-mentioned embodiment, the support structure 5 includes a first solder resist layer 51 and a second solder resist layer 52, and the second solder resist layer 52 is arranged above the first solder resist layer 51.

[0039] The support structure 5 is formed by arranging two layers of solder resist layers in the embodiment, the first solder resist layer 51 can be the original solder resist layer on the substrate 4, or the first solder resist layer 51 can be a specially arranged solder resist layer. Preferably, the first solder resist layer 51 is the original solder resist layer on the substrate 4. The width of the first solder resist layer 51 and the width of the second solder resist layer 52 can be set according to actual application conditions. The width of the first solder resist layer 51 and the width of the second solder resist layer 52 can be set to be the same, or the width of the first solder resist layer 51 and the width of the second solder resist layer 52 can be set to be different. Preferably, the width of the second solder resist layer 52 is greater than the width of the second solder resist layer 52.

[0040] The thickness of the first solder resist layer 51 and the second solder resist layer 52 can be set according to actual application conditions. The thickness of the first solder resist layer 51 and the second solder resist layer 52 can be the same, or the thickness of the first solder resist layer 51 and the thickness of the second solder resist layer 52 can be different. As another embodiment, the support structure 5 can include the first solder resist layer 51, the second solder resist layer 52, and a third solder resist layer.

[0041] The chip 1 packaging structure of the embodiment sets two layers of solder resist layers, avoids the difficulty in preparing a support structure 5 that is too high, and uses the original solder resist layer on the substrate 4 as the first solder resist layer 51, so that the second solder resist layer 52 is easier to prepare. The height that the support structure 5 can support can also be increased.

[0042] In an embodiment, as shown in FIG. 1 and FIG. 2, on the basis of the above-mentioned embodiment, the support structure 5 is a stepped structure, and the width of the second solder resist layer 52 is less than the width of the first solder resist layer 51.

[0043] The chip 1 packaging structure of the embodiment sets the support structure 5 as a stepped type, so that the support structure 5 can be more stable, and the stability of the chip 1 packaging structure is further ensured.

[0044] In an embodiment, as shown in FIG. 1 and FIG. 2, on the basis of the above-mentioned embodiment, the front side, the back side, the left side, and the right side of the chip 1 are respectively provided with the support structure 5.

[0045] Preferably, the support structure 5 of the front side, the back side, the left side and the right side of the chip 1 is rectangular, and the length of the support structure 5 of each side of the chip 1 can be set according to actual application.

[0046] The chip 1 packaging structure of the embodiment can reduce the stress of the compression plastic packaging layer 3, and avoid damage of the connected support structure 5 under the stress during compression, thereby affecting the support of the support structure 5 to the blocking film 2.

[0047] In an embodiment, as shown in FIG. 3, a flowchart of a substrate 4 processing method with a metal support structure 5 is provided, and the processing method comprises the following steps:

[0048] Step S101: providing a substrate 4 with prepared circuit pattern.

[0049] The substrate 4 is a board made of glass cloth and epoxy resin, and blind holes and / or through holes are prepared on the substrate 4. A copper layer is provided on the substrate 4 with prepared holes, and a circuit pattern is formed according to actual conditions by using the copper layer.

[0050] Step S102: coating ink on the substrate 4 for the first time to obtain the substrate 4 after the first coating of ink.

[0051] The pattern is set on the screen printing screen according to actual application, and the ink is screen printed on the substrate 4.

[0052] Step S103: performing first exposure on the substrate 4 by using the exposure equipment to obtain the substrate 4 after the first exposure.

[0053] The substrate 4 is exposed by using the exposure machine, the ink undergoes chemical change under the action of light, the exposed part is more easily dissolved by the developing solution, and the unexposed part is the first solder resist layer 51.

[0054] Step S104: coating ink on the substrate 4 after the first exposure for the second time to obtain the substrate 4 after the second coating of ink.

[0055] The pattern is set on the screen printing screen according to actual application, and the ink is screen printed on the substrate 4.

[0056] Step S105: performing second exposure on the substrate 4 by using the exposure equipment to obtain the substrate 4 after the second exposure.

[0057] The substrate 4 is exposed by using the exposure machine, the ink undergoes chemical change under the action of light, the exposed part is more easily dissolved by the developing solution, and the unexposed part is the second solder resist layer 52.

[0058] Step S106: Perform a developing cleaning on the substrate 4 after the second exposure, to obtain the substrate 4 with the support structure 5.

[0059] The non-hardened ink part is washed away by the developing liquid, leaving the support structure 5 formed by the first solder resist layer 51 and the second solder resist layer 52.

[0060] In this embodiment, a solder resist process is added to the conventional manufacturing process of the substrate 4, and the original ink layer is partially thickened through the two solder resist processes. The thickened ink layer and the original ink layer thereunder form the support structure 5, which supports the barrier film 2, avoids the barrier film 2 from being in contact with the pins of the chip 1 due to pressure, avoids the effective resonance area from being polluted, and guarantees the integrity of the cavity, greatly improving the performance of the chip 1.

[0061] In an embodiment, as shown in FIG. 4, a flowchart of a processing method of the substrate 4 with the metal support structure 5 is provided. Based on the embodiment of FIG. 3, after step S106, the processing method includes:

[0062] Step S201: Perform a curing treatment on the substrate 4 with the support structure 5, to obtain the cured substrate 4.

[0063] The solder resist layer is completely hardened through heat curing, ultraviolet (UV) curing, infrared (IR) curing, or the like, to form the support structure 5.

[0064] In this embodiment, the support structure 5 is cured, so that the support structure 5 has good heat resistance and corrosion resistance, and the support structure 5 is more stable.

[0065] In an embodiment, as shown in FIG. 5, a flowchart of a processing method of the substrate 4 with the metal support structure 5 is provided. Based on the embodiment of FIG. 3, after step S102 and before step S103, the processing method further includes:

[0066] Step S301: Perform a first pre-curing on the substrate 4 after the first ink coating, to obtain the substrate 4 after the first pre-curing.

[0067] After the first ink printing, the substrate 4 is placed in an oven for pre-curing, to evaporate the solvent in the ink and preliminarily fix the position of the first ink printing.

[0068] After step S104 and before step S105, the processing method further includes:

[0069] Step S302: Perform a second pre-curing on the substrate 4 after the second ink coating, to obtain the substrate 4 after the second pre-curing.

[0070] After the second printing ink, the substrate 4 is put into the oven for pre-curing, evaporating the solvent in the ink and preliminarily fixing the position of the second printing ink.

[0071] In this embodiment, the substrate 4 after printing ink is pre-cured, which can evaporate the solvent in the ink and preliminarily fix the position of the ink, avoiding displacement in subsequent processing.

[0072] In an embodiment, as shown in FIG. 6, a flowchart of a substrate 4 processing method with a metal support structure 5 is provided, which further includes, after step S201 in the embodiment of FIG. 4:

[0073] Step S401: surface treatment is performed on the substrate 4 to obtain a surface-treated substrate 4.

[0074] The surface treatment can be cleaning and impurity removal treatment on the substrate 4, the surface treatment can also be mechanical treatment on the substrate 4, and the surface treatment can also be chemical treatment on the substrate 4.

[0075] Step S402: detection treatment is performed on the surface-treated substrate 4 to obtain a detection-treated substrate 4.

[0076] The detection can include appearance detection treatment, and the detection can also include function test, performance test and mechanical strength test.

[0077] In this embodiment, after the support structure 5 is prepared, the surface treatment and detection are performed on the substrate 4 to comprehensively verify the comprehensive quality of the substrate 4, and to ensure the quality and reliability of the substrate 4.

[0078] In an embodiment, on the basis of the embodiment of FIG. 3, step S101 includes:

[0079] A substrate 4 is provided, and the substrate 4 is subjected to copper cladding treatment, film pasting treatment, exposure treatment, development treatment and etching treatment to prepare a circuit pattern.

[0080] A substrate 4 is provided, a uniform copper foil is first coated on the substrate 4, a layer of photosensitive dry film or liquid photoresist is coated on the surface of the copper foil, and curing is performed by using a hot press or UV light, and the cured substrate 4 is exposed by using an exposure machine.

[0081] The unexposed dry film is removed by using a developing solution, and the copper is etched by using an etching solution to remove the copper layer not protected by the dry film or photoresist, and only the circuit pattern is reserved.

[0082] In the embodiment, the substrate 4 is subjected to copper coating, film pasting, exposure, development and etching to prepare a circuit pattern, so that the circuit can be highly integrated, signal interference and delay can be reduced, and the signal transmission quality of the circuit can be improved.

[0083] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalent ones; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A chip package structure, wherein, The method comprises the following steps: A substrate, a chip, a barrier film and a plastic sealing layer, the conductive pins of the chip are electrically interconnected with the substrate, the barrier film is arranged on the substrate, the barrier film and the substrate form a cavity, the chip is arranged in the cavity, the barrier film and the substrate form a plastic sealing layer, and the substrate in the cavity is provided with a support structure for supporting the barrier film when the plastic sealing layer is pressed.

2. The chip package structure of claim 1, wherein, The height of the support structure is half of the height of the chip on the substrate.

3. The chip package structure of claim 1 or 2, wherein, The support structure comprises a first solder resist layer and a second solder resist layer, and the second solder resist layer is arranged above the first solder resist layer.

4. The chip package structure of claim 3, wherein, The support structure is a stepped structure, and the width of the second solder resist layer is smaller than that of the first solder resist layer.

5. The chip package structure of claim 4, wherein, The front side, back side, left side and right side of the chip are respectively provided with the support structure.

6. A substrate processing method having a support structure, wherein, The method comprises the following steps: A substrate with a prepared circuit pattern is provided; An ink is coated on the substrate for the first time to obtain a substrate after the ink is coated for the first time; The substrate is exposed for the first time by using an exposure device to obtain a substrate after the first exposure; An ink is coated on the substrate for the second time to obtain a substrate after the ink is coated for the second time; The substrate is exposed for the second time by using the exposure device to obtain a substrate after the second exposure; The substrate after the second exposure is developed and cleaned to obtain a substrate with a support structure.

7. The substrate processing method with a support structure of claim 6, wherein, After obtaining the substrate with the support structure, the method further comprises the following steps: The substrate with the support structure is subjected to a curing treatment to obtain a cured substrate.

8. The substrate processing method with a support structure according to claim 6, wherein, After obtaining the substrate after the ink is coated for the first time, before the substrate is exposed for the first time by using the exposure device, the method further comprises the following steps: The substrate after the ink is coated for the first time is subjected to a first pre-curing treatment to obtain a substrate after the first pre-curing treatment; After obtaining the substrate after the ink is coated for the second time, before the substrate is exposed for the second time by using the exposure device, the method further comprises the following steps: The substrate after the ink is coated for the second time is subjected to a second pre-curing treatment to obtain a substrate after the second pre-curing treatment.

9. The substrate processing method with a support structure according to claim 7, wherein, After obtaining the cured substrate, the method further comprises the following steps: The substrate is subjected to a surface treatment to obtain a substrate after the surface treatment; The substrate after the surface treatment is subjected to a detection treatment to obtain a substrate after the detection treatment.

10. The substrate processing method with a support structure according to claim 6, wherein, The method comprises the following steps: A substrate is provided, and the substrate is subjected to a copper coating treatment, a film pasting treatment, an exposure treatment, a development treatment and an etching treatment to prepare a circuit pattern.

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